1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Ingenic SoCs pinctrl driver 4 * 5 * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net> 6 * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> 7 * Copyright (c) 2017, 2019 Paul Boddie <paul@boddie.org.uk> 8 */ 9 10 #include <linux/compiler.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/of_device.h> 15 #include <linux/of_irq.h> 16 #include <linux/of_platform.h> 17 #include <linux/pinctrl/pinctrl.h> 18 #include <linux/pinctrl/pinmux.h> 19 #include <linux/pinctrl/pinconf.h> 20 #include <linux/pinctrl/pinconf-generic.h> 21 #include <linux/platform_device.h> 22 #include <linux/regmap.h> 23 #include <linux/slab.h> 24 25 #include "core.h" 26 #include "pinconf.h" 27 #include "pinmux.h" 28 29 #define GPIO_PIN 0x00 30 #define GPIO_MSK 0x20 31 32 #define JZ4740_GPIO_DATA 0x10 33 #define JZ4740_GPIO_PULL_DIS 0x30 34 #define JZ4740_GPIO_FUNC 0x40 35 #define JZ4740_GPIO_SELECT 0x50 36 #define JZ4740_GPIO_DIR 0x60 37 #define JZ4740_GPIO_TRIG 0x70 38 #define JZ4740_GPIO_FLAG 0x80 39 40 #define JZ4760_GPIO_INT 0x10 41 #define JZ4760_GPIO_PAT1 0x30 42 #define JZ4760_GPIO_PAT0 0x40 43 #define JZ4760_GPIO_FLAG 0x50 44 #define JZ4760_GPIO_PEN 0x70 45 46 #define X1830_GPIO_PEL 0x110 47 #define X1830_GPIO_PEH 0x120 48 49 #define REG_SET(x) ((x) + 0x4) 50 #define REG_CLEAR(x) ((x) + 0x8) 51 52 #define REG_PZ_BASE(x) ((x) * 7) 53 #define REG_PZ_GID2LD(x) ((x) * 7 + 0xf0) 54 55 #define GPIO_PULL_DIS 0 56 #define GPIO_PULL_UP 1 57 #define GPIO_PULL_DOWN 2 58 59 #define PINS_PER_GPIO_CHIP 32 60 61 enum jz_version { 62 ID_JZ4740, 63 ID_JZ4725B, 64 ID_JZ4760, 65 ID_JZ4770, 66 ID_JZ4780, 67 ID_X1000, 68 ID_X1500, 69 ID_X1830, 70 }; 71 72 struct ingenic_chip_info { 73 unsigned int num_chips; 74 unsigned int reg_offset; 75 enum jz_version version; 76 77 const struct group_desc *groups; 78 unsigned int num_groups; 79 80 const struct function_desc *functions; 81 unsigned int num_functions; 82 83 const u32 *pull_ups, *pull_downs; 84 }; 85 86 struct ingenic_pinctrl { 87 struct device *dev; 88 struct regmap *map; 89 struct pinctrl_dev *pctl; 90 struct pinctrl_pin_desc *pdesc; 91 92 const struct ingenic_chip_info *info; 93 }; 94 95 struct ingenic_gpio_chip { 96 struct ingenic_pinctrl *jzpc; 97 struct gpio_chip gc; 98 struct irq_chip irq_chip; 99 unsigned int irq, reg_base; 100 }; 101 102 static const u32 jz4740_pull_ups[4] = { 103 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 104 }; 105 106 static const u32 jz4740_pull_downs[4] = { 107 0x00000000, 0x00000000, 0x00000000, 0x00000000, 108 }; 109 110 static int jz4740_mmc_1bit_pins[] = { 0x69, 0x68, 0x6a, }; 111 static int jz4740_mmc_4bit_pins[] = { 0x6b, 0x6c, 0x6d, }; 112 static int jz4740_uart0_data_pins[] = { 0x7a, 0x79, }; 113 static int jz4740_uart0_hwflow_pins[] = { 0x7e, 0x7f, }; 114 static int jz4740_uart1_data_pins[] = { 0x7e, 0x7f, }; 115 static int jz4740_lcd_8bit_pins[] = { 116 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x52, 0x53, 0x54, 117 }; 118 static int jz4740_lcd_16bit_pins[] = { 119 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x55, 120 }; 121 static int jz4740_lcd_18bit_pins[] = { 0x50, 0x51, }; 122 static int jz4740_lcd_18bit_tft_pins[] = { 0x56, 0x57, 0x31, 0x32, }; 123 static int jz4740_nand_cs1_pins[] = { 0x39, }; 124 static int jz4740_nand_cs2_pins[] = { 0x3a, }; 125 static int jz4740_nand_cs3_pins[] = { 0x3b, }; 126 static int jz4740_nand_cs4_pins[] = { 0x3c, }; 127 static int jz4740_nand_fre_fwe_pins[] = { 0x5c, 0x5d, }; 128 static int jz4740_pwm_pwm0_pins[] = { 0x77, }; 129 static int jz4740_pwm_pwm1_pins[] = { 0x78, }; 130 static int jz4740_pwm_pwm2_pins[] = { 0x79, }; 131 static int jz4740_pwm_pwm3_pins[] = { 0x7a, }; 132 static int jz4740_pwm_pwm4_pins[] = { 0x7b, }; 133 static int jz4740_pwm_pwm5_pins[] = { 0x7c, }; 134 static int jz4740_pwm_pwm6_pins[] = { 0x7e, }; 135 static int jz4740_pwm_pwm7_pins[] = { 0x7f, }; 136 137 static int jz4740_mmc_1bit_funcs[] = { 0, 0, 0, }; 138 static int jz4740_mmc_4bit_funcs[] = { 0, 0, 0, }; 139 static int jz4740_uart0_data_funcs[] = { 1, 1, }; 140 static int jz4740_uart0_hwflow_funcs[] = { 1, 1, }; 141 static int jz4740_uart1_data_funcs[] = { 2, 2, }; 142 static int jz4740_lcd_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 143 static int jz4740_lcd_16bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 144 static int jz4740_lcd_18bit_funcs[] = { 0, 0, }; 145 static int jz4740_lcd_18bit_tft_funcs[] = { 0, 0, 0, 0, }; 146 static int jz4740_nand_cs1_funcs[] = { 0, }; 147 static int jz4740_nand_cs2_funcs[] = { 0, }; 148 static int jz4740_nand_cs3_funcs[] = { 0, }; 149 static int jz4740_nand_cs4_funcs[] = { 0, }; 150 static int jz4740_nand_fre_fwe_funcs[] = { 0, 0, }; 151 static int jz4740_pwm_pwm0_funcs[] = { 0, }; 152 static int jz4740_pwm_pwm1_funcs[] = { 0, }; 153 static int jz4740_pwm_pwm2_funcs[] = { 0, }; 154 static int jz4740_pwm_pwm3_funcs[] = { 0, }; 155 static int jz4740_pwm_pwm4_funcs[] = { 0, }; 156 static int jz4740_pwm_pwm5_funcs[] = { 0, }; 157 static int jz4740_pwm_pwm6_funcs[] = { 0, }; 158 static int jz4740_pwm_pwm7_funcs[] = { 0, }; 159 160 #define INGENIC_PIN_GROUP(name, id) \ 161 { \ 162 name, \ 163 id##_pins, \ 164 ARRAY_SIZE(id##_pins), \ 165 id##_funcs, \ 166 } 167 168 static const struct group_desc jz4740_groups[] = { 169 INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit), 170 INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit), 171 INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data), 172 INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow), 173 INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data), 174 INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit), 175 INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit), 176 INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit), 177 INGENIC_PIN_GROUP("lcd-18bit-tft", jz4740_lcd_18bit_tft), 178 { "lcd-no-pins", }, 179 INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1), 180 INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2), 181 INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3), 182 INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4), 183 INGENIC_PIN_GROUP("nand-fre-fwe", jz4740_nand_fre_fwe), 184 INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0), 185 INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1), 186 INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2), 187 INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3), 188 INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4), 189 INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5), 190 INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6), 191 INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7), 192 }; 193 194 static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; 195 static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 196 static const char *jz4740_uart1_groups[] = { "uart1-data", }; 197 static const char *jz4740_lcd_groups[] = { 198 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-18bit-tft", "lcd-no-pins", 199 }; 200 static const char *jz4740_nand_groups[] = { 201 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe", 202 }; 203 static const char *jz4740_pwm0_groups[] = { "pwm0", }; 204 static const char *jz4740_pwm1_groups[] = { "pwm1", }; 205 static const char *jz4740_pwm2_groups[] = { "pwm2", }; 206 static const char *jz4740_pwm3_groups[] = { "pwm3", }; 207 static const char *jz4740_pwm4_groups[] = { "pwm4", }; 208 static const char *jz4740_pwm5_groups[] = { "pwm5", }; 209 static const char *jz4740_pwm6_groups[] = { "pwm6", }; 210 static const char *jz4740_pwm7_groups[] = { "pwm7", }; 211 212 static const struct function_desc jz4740_functions[] = { 213 { "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), }, 214 { "uart0", jz4740_uart0_groups, ARRAY_SIZE(jz4740_uart0_groups), }, 215 { "uart1", jz4740_uart1_groups, ARRAY_SIZE(jz4740_uart1_groups), }, 216 { "lcd", jz4740_lcd_groups, ARRAY_SIZE(jz4740_lcd_groups), }, 217 { "nand", jz4740_nand_groups, ARRAY_SIZE(jz4740_nand_groups), }, 218 { "pwm0", jz4740_pwm0_groups, ARRAY_SIZE(jz4740_pwm0_groups), }, 219 { "pwm1", jz4740_pwm1_groups, ARRAY_SIZE(jz4740_pwm1_groups), }, 220 { "pwm2", jz4740_pwm2_groups, ARRAY_SIZE(jz4740_pwm2_groups), }, 221 { "pwm3", jz4740_pwm3_groups, ARRAY_SIZE(jz4740_pwm3_groups), }, 222 { "pwm4", jz4740_pwm4_groups, ARRAY_SIZE(jz4740_pwm4_groups), }, 223 { "pwm5", jz4740_pwm5_groups, ARRAY_SIZE(jz4740_pwm5_groups), }, 224 { "pwm6", jz4740_pwm6_groups, ARRAY_SIZE(jz4740_pwm6_groups), }, 225 { "pwm7", jz4740_pwm7_groups, ARRAY_SIZE(jz4740_pwm7_groups), }, 226 }; 227 228 static const struct ingenic_chip_info jz4740_chip_info = { 229 .num_chips = 4, 230 .reg_offset = 0x100, 231 .version = ID_JZ4740, 232 .groups = jz4740_groups, 233 .num_groups = ARRAY_SIZE(jz4740_groups), 234 .functions = jz4740_functions, 235 .num_functions = ARRAY_SIZE(jz4740_functions), 236 .pull_ups = jz4740_pull_ups, 237 .pull_downs = jz4740_pull_downs, 238 }; 239 240 static int jz4725b_mmc0_1bit_pins[] = { 0x48, 0x49, 0x5c, }; 241 static int jz4725b_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x56, }; 242 static int jz4725b_mmc1_1bit_pins[] = { 0x7a, 0x7b, 0x7c, }; 243 static int jz4725b_mmc1_4bit_pins[] = { 0x7d, 0x7e, 0x7f, }; 244 static int jz4725b_uart_data_pins[] = { 0x4c, 0x4d, }; 245 static int jz4725b_nand_cs1_pins[] = { 0x55, }; 246 static int jz4725b_nand_cs2_pins[] = { 0x56, }; 247 static int jz4725b_nand_cs3_pins[] = { 0x57, }; 248 static int jz4725b_nand_cs4_pins[] = { 0x58, }; 249 static int jz4725b_nand_cle_ale_pins[] = { 0x48, 0x49 }; 250 static int jz4725b_nand_fre_fwe_pins[] = { 0x5c, 0x5d }; 251 static int jz4725b_pwm_pwm0_pins[] = { 0x4a, }; 252 static int jz4725b_pwm_pwm1_pins[] = { 0x4b, }; 253 static int jz4725b_pwm_pwm2_pins[] = { 0x4c, }; 254 static int jz4725b_pwm_pwm3_pins[] = { 0x4d, }; 255 static int jz4725b_pwm_pwm4_pins[] = { 0x4e, }; 256 static int jz4725b_pwm_pwm5_pins[] = { 0x4f, }; 257 static int jz4725b_lcd_8bit_pins[] = { 258 0x72, 0x73, 0x74, 259 0x60, 0x61, 0x62, 0x63, 260 0x64, 0x65, 0x66, 0x67, 261 }; 262 static int jz4725b_lcd_16bit_pins[] = { 263 0x68, 0x69, 0x6a, 0x6b, 264 0x6c, 0x6d, 0x6e, 0x6f, 265 }; 266 static int jz4725b_lcd_18bit_pins[] = { 0x70, 0x71, }; 267 static int jz4725b_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 268 static int jz4725b_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 269 static int jz4725b_lcd_generic_pins[] = { 0x75, }; 270 271 static int jz4725b_mmc0_1bit_funcs[] = { 1, 1, 1, }; 272 static int jz4725b_mmc0_4bit_funcs[] = { 1, 0, 1, }; 273 static int jz4725b_mmc1_1bit_funcs[] = { 0, 0, 0, }; 274 static int jz4725b_mmc1_4bit_funcs[] = { 0, 0, 0, }; 275 static int jz4725b_uart_data_funcs[] = { 1, 1, }; 276 static int jz4725b_nand_cs1_funcs[] = { 0, }; 277 static int jz4725b_nand_cs2_funcs[] = { 0, }; 278 static int jz4725b_nand_cs3_funcs[] = { 0, }; 279 static int jz4725b_nand_cs4_funcs[] = { 0, }; 280 static int jz4725b_nand_cle_ale_funcs[] = { 0, 0, }; 281 static int jz4725b_nand_fre_fwe_funcs[] = { 0, 0, }; 282 static int jz4725b_pwm_pwm0_funcs[] = { 0, }; 283 static int jz4725b_pwm_pwm1_funcs[] = { 0, }; 284 static int jz4725b_pwm_pwm2_funcs[] = { 0, }; 285 static int jz4725b_pwm_pwm3_funcs[] = { 0, }; 286 static int jz4725b_pwm_pwm4_funcs[] = { 0, }; 287 static int jz4725b_pwm_pwm5_funcs[] = { 0, }; 288 static int jz4725b_lcd_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 289 static int jz4725b_lcd_16bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 290 static int jz4725b_lcd_18bit_funcs[] = { 0, 0, }; 291 static int jz4725b_lcd_24bit_funcs[] = { 1, 1, 1, 1, }; 292 static int jz4725b_lcd_special_funcs[] = { 0, 0, 0, 0, }; 293 static int jz4725b_lcd_generic_funcs[] = { 0, }; 294 295 static const struct group_desc jz4725b_groups[] = { 296 INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit), 297 INGENIC_PIN_GROUP("mmc0-4bit", jz4725b_mmc0_4bit), 298 INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit), 299 INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit), 300 INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data), 301 INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1), 302 INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2), 303 INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3), 304 INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4), 305 INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale), 306 INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe), 307 INGENIC_PIN_GROUP("pwm0", jz4725b_pwm_pwm0), 308 INGENIC_PIN_GROUP("pwm1", jz4725b_pwm_pwm1), 309 INGENIC_PIN_GROUP("pwm2", jz4725b_pwm_pwm2), 310 INGENIC_PIN_GROUP("pwm3", jz4725b_pwm_pwm3), 311 INGENIC_PIN_GROUP("pwm4", jz4725b_pwm_pwm4), 312 INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5), 313 INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit), 314 INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit), 315 INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit), 316 INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit), 317 INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special), 318 INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic), 319 }; 320 321 static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 322 static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 323 static const char *jz4725b_uart_groups[] = { "uart-data", }; 324 static const char *jz4725b_nand_groups[] = { 325 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", 326 "nand-cle-ale", "nand-fre-fwe", 327 }; 328 static const char *jz4725b_pwm0_groups[] = { "pwm0", }; 329 static const char *jz4725b_pwm1_groups[] = { "pwm1", }; 330 static const char *jz4725b_pwm2_groups[] = { "pwm2", }; 331 static const char *jz4725b_pwm3_groups[] = { "pwm3", }; 332 static const char *jz4725b_pwm4_groups[] = { "pwm4", }; 333 static const char *jz4725b_pwm5_groups[] = { "pwm5", }; 334 static const char *jz4725b_lcd_groups[] = { 335 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 336 "lcd-special", "lcd-generic", 337 }; 338 339 static const struct function_desc jz4725b_functions[] = { 340 { "mmc0", jz4725b_mmc0_groups, ARRAY_SIZE(jz4725b_mmc0_groups), }, 341 { "mmc1", jz4725b_mmc1_groups, ARRAY_SIZE(jz4725b_mmc1_groups), }, 342 { "uart", jz4725b_uart_groups, ARRAY_SIZE(jz4725b_uart_groups), }, 343 { "nand", jz4725b_nand_groups, ARRAY_SIZE(jz4725b_nand_groups), }, 344 { "pwm0", jz4725b_pwm0_groups, ARRAY_SIZE(jz4725b_pwm0_groups), }, 345 { "pwm1", jz4725b_pwm1_groups, ARRAY_SIZE(jz4725b_pwm1_groups), }, 346 { "pwm2", jz4725b_pwm2_groups, ARRAY_SIZE(jz4725b_pwm2_groups), }, 347 { "pwm3", jz4725b_pwm3_groups, ARRAY_SIZE(jz4725b_pwm3_groups), }, 348 { "pwm4", jz4725b_pwm4_groups, ARRAY_SIZE(jz4725b_pwm4_groups), }, 349 { "pwm5", jz4725b_pwm5_groups, ARRAY_SIZE(jz4725b_pwm5_groups), }, 350 { "lcd", jz4725b_lcd_groups, ARRAY_SIZE(jz4725b_lcd_groups), }, 351 }; 352 353 static const struct ingenic_chip_info jz4725b_chip_info = { 354 .num_chips = 4, 355 .reg_offset = 0x100, 356 .version = ID_JZ4725B, 357 .groups = jz4725b_groups, 358 .num_groups = ARRAY_SIZE(jz4725b_groups), 359 .functions = jz4725b_functions, 360 .num_functions = ARRAY_SIZE(jz4725b_functions), 361 .pull_ups = jz4740_pull_ups, 362 .pull_downs = jz4740_pull_downs, 363 }; 364 365 static const u32 jz4760_pull_ups[6] = { 366 0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0xfffff00f, 367 }; 368 369 static const u32 jz4760_pull_downs[6] = { 370 0x00000000, 0x00030c00, 0x00000000, 0x00003000, 0x00000483, 0x00000ff0, 371 }; 372 373 static int jz4760_uart0_data_pins[] = { 0xa0, 0xa3, }; 374 static int jz4760_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; 375 static int jz4760_uart1_data_pins[] = { 0x7a, 0x7c, }; 376 static int jz4760_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; 377 static int jz4760_uart2_data_pins[] = { 0x5c, 0x5e, }; 378 static int jz4760_uart2_hwflow_pins[] = { 0x5d, 0x5f, }; 379 static int jz4760_uart3_data_pins[] = { 0x6c, 0x85, }; 380 static int jz4760_uart3_hwflow_pins[] = { 0x88, 0x89, }; 381 static int jz4760_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; 382 static int jz4760_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; 383 static int jz4760_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 384 static int jz4760_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 385 static int jz4760_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 386 static int jz4760_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; 387 static int jz4760_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; 388 static int jz4760_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 389 static int jz4760_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 390 static int jz4760_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 391 static int jz4760_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, }; 392 static int jz4760_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, }; 393 static int jz4760_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 394 static int jz4760_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 395 static int jz4760_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 396 static int jz4760_nemc_8bit_data_pins[] = { 397 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 398 }; 399 static int jz4760_nemc_16bit_data_pins[] = { 400 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 401 }; 402 static int jz4760_nemc_cle_ale_pins[] = { 0x20, 0x21, }; 403 static int jz4760_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; 404 static int jz4760_nemc_rd_we_pins[] = { 0x10, 0x11, }; 405 static int jz4760_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; 406 static int jz4760_nemc_wait_pins[] = { 0x1b, }; 407 static int jz4760_nemc_cs1_pins[] = { 0x15, }; 408 static int jz4760_nemc_cs2_pins[] = { 0x16, }; 409 static int jz4760_nemc_cs3_pins[] = { 0x17, }; 410 static int jz4760_nemc_cs4_pins[] = { 0x18, }; 411 static int jz4760_nemc_cs5_pins[] = { 0x19, }; 412 static int jz4760_nemc_cs6_pins[] = { 0x1a, }; 413 static int jz4760_i2c0_pins[] = { 0x7e, 0x7f, }; 414 static int jz4760_i2c1_pins[] = { 0x9e, 0x9f, }; 415 static int jz4760_cim_pins[] = { 416 0x26, 0x27, 0x28, 0x29, 417 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 418 }; 419 static int jz4760_lcd_24bit_pins[] = { 420 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 421 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 422 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 423 0x58, 0x59, 0x5a, 0x5b, 424 }; 425 static int jz4760_pwm_pwm0_pins[] = { 0x80, }; 426 static int jz4760_pwm_pwm1_pins[] = { 0x81, }; 427 static int jz4760_pwm_pwm2_pins[] = { 0x82, }; 428 static int jz4760_pwm_pwm3_pins[] = { 0x83, }; 429 static int jz4760_pwm_pwm4_pins[] = { 0x84, }; 430 static int jz4760_pwm_pwm5_pins[] = { 0x85, }; 431 static int jz4760_pwm_pwm6_pins[] = { 0x6a, }; 432 static int jz4760_pwm_pwm7_pins[] = { 0x6b, }; 433 434 static int jz4760_uart0_data_funcs[] = { 0, 0, }; 435 static int jz4760_uart0_hwflow_funcs[] = { 0, 0, }; 436 static int jz4760_uart1_data_funcs[] = { 0, 0, }; 437 static int jz4760_uart1_hwflow_funcs[] = { 0, 0, }; 438 static int jz4760_uart2_data_funcs[] = { 0, 0, }; 439 static int jz4760_uart2_hwflow_funcs[] = { 0, 0, }; 440 static int jz4760_uart3_data_funcs[] = { 0, 1, }; 441 static int jz4760_uart3_hwflow_funcs[] = { 0, 0, }; 442 static int jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, }; 443 static int jz4760_mmc0_4bit_a_funcs[] = { 1, 1, 1, }; 444 static int jz4760_mmc0_1bit_e_funcs[] = { 0, 0, 0, }; 445 static int jz4760_mmc0_4bit_e_funcs[] = { 0, 0, 0, }; 446 static int jz4760_mmc0_8bit_e_funcs[] = { 0, 0, 0, 0, }; 447 static int jz4760_mmc1_1bit_d_funcs[] = { 0, 0, 0, }; 448 static int jz4760_mmc1_4bit_d_funcs[] = { 0, 0, 0, }; 449 static int jz4760_mmc1_1bit_e_funcs[] = { 1, 1, 1, }; 450 static int jz4760_mmc1_4bit_e_funcs[] = { 1, 1, 1, }; 451 static int jz4760_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, }; 452 static int jz4760_mmc2_1bit_b_funcs[] = { 0, 0, 0, }; 453 static int jz4760_mmc2_4bit_b_funcs[] = { 0, 0, 0, }; 454 static int jz4760_mmc2_1bit_e_funcs[] = { 2, 2, 2, }; 455 static int jz4760_mmc2_4bit_e_funcs[] = { 2, 2, 2, }; 456 static int jz4760_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, }; 457 static int jz4760_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 458 static int jz4760_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 459 static int jz4760_nemc_cle_ale_funcs[] = { 0, 0, }; 460 static int jz4760_nemc_addr_funcs[] = { 0, 0, 0, 0, }; 461 static int jz4760_nemc_rd_we_funcs[] = { 0, 0, }; 462 static int jz4760_nemc_frd_fwe_funcs[] = { 0, 0, }; 463 static int jz4760_nemc_wait_funcs[] = { 0, }; 464 static int jz4760_nemc_cs1_funcs[] = { 0, }; 465 static int jz4760_nemc_cs2_funcs[] = { 0, }; 466 static int jz4760_nemc_cs3_funcs[] = { 0, }; 467 static int jz4760_nemc_cs4_funcs[] = { 0, }; 468 static int jz4760_nemc_cs5_funcs[] = { 0, }; 469 static int jz4760_nemc_cs6_funcs[] = { 0, }; 470 static int jz4760_i2c0_funcs[] = { 0, 0, }; 471 static int jz4760_i2c1_funcs[] = { 0, 0, }; 472 static int jz4760_cim_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 473 static int jz4760_lcd_24bit_funcs[] = { 474 0, 0, 0, 0, 0, 0, 0, 0, 475 0, 0, 0, 0, 0, 0, 0, 0, 476 0, 0, 0, 0, 0, 0, 0, 0, 477 0, 0, 0, 0, 478 }; 479 static int jz4760_pwm_pwm0_funcs[] = { 0, }; 480 static int jz4760_pwm_pwm1_funcs[] = { 0, }; 481 static int jz4760_pwm_pwm2_funcs[] = { 0, }; 482 static int jz4760_pwm_pwm3_funcs[] = { 0, }; 483 static int jz4760_pwm_pwm4_funcs[] = { 0, }; 484 static int jz4760_pwm_pwm5_funcs[] = { 0, }; 485 static int jz4760_pwm_pwm6_funcs[] = { 0, }; 486 static int jz4760_pwm_pwm7_funcs[] = { 0, }; 487 488 static const struct group_desc jz4760_groups[] = { 489 INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data), 490 INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow), 491 INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data), 492 INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow), 493 INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data), 494 INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow), 495 INGENIC_PIN_GROUP("uart3-data", jz4760_uart3_data), 496 INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow), 497 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4760_mmc0_1bit_a), 498 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a), 499 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e), 500 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e), 501 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e), 502 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d), 503 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d), 504 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e), 505 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e), 506 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e), 507 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b), 508 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b), 509 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e), 510 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e), 511 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e), 512 INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data), 513 INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data), 514 INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale), 515 INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr), 516 INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we), 517 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe), 518 INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait), 519 INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1), 520 INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2), 521 INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3), 522 INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4), 523 INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5), 524 INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6), 525 INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0), 526 INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1), 527 INGENIC_PIN_GROUP("cim-data", jz4760_cim), 528 INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit), 529 { "lcd-no-pins", }, 530 INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0), 531 INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1), 532 INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2), 533 INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3), 534 INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4), 535 INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5), 536 INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6), 537 INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7), 538 }; 539 540 static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 541 static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 542 static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 543 static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 544 static const char *jz4760_mmc0_groups[] = { 545 "mmc0-1bit-a", "mmc0-4bit-a", 546 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e", 547 }; 548 static const char *jz4760_mmc1_groups[] = { 549 "mmc1-1bit-d", "mmc1-4bit-d", 550 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e", 551 }; 552 static const char *jz4760_mmc2_groups[] = { 553 "mmc2-1bit-b", "mmc2-4bit-b", 554 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e", 555 }; 556 static const char *jz4760_nemc_groups[] = { 557 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale", 558 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 559 }; 560 static const char *jz4760_cs1_groups[] = { "nemc-cs1", }; 561 static const char *jz4760_cs2_groups[] = { "nemc-cs2", }; 562 static const char *jz4760_cs3_groups[] = { "nemc-cs3", }; 563 static const char *jz4760_cs4_groups[] = { "nemc-cs4", }; 564 static const char *jz4760_cs5_groups[] = { "nemc-cs5", }; 565 static const char *jz4760_cs6_groups[] = { "nemc-cs6", }; 566 static const char *jz4760_i2c0_groups[] = { "i2c0-data", }; 567 static const char *jz4760_i2c1_groups[] = { "i2c1-data", }; 568 static const char *jz4760_cim_groups[] = { "cim-data", }; 569 static const char *jz4760_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", }; 570 static const char *jz4760_pwm0_groups[] = { "pwm0", }; 571 static const char *jz4760_pwm1_groups[] = { "pwm1", }; 572 static const char *jz4760_pwm2_groups[] = { "pwm2", }; 573 static const char *jz4760_pwm3_groups[] = { "pwm3", }; 574 static const char *jz4760_pwm4_groups[] = { "pwm4", }; 575 static const char *jz4760_pwm5_groups[] = { "pwm5", }; 576 static const char *jz4760_pwm6_groups[] = { "pwm6", }; 577 static const char *jz4760_pwm7_groups[] = { "pwm7", }; 578 579 static const struct function_desc jz4760_functions[] = { 580 { "uart0", jz4760_uart0_groups, ARRAY_SIZE(jz4760_uart0_groups), }, 581 { "uart1", jz4760_uart1_groups, ARRAY_SIZE(jz4760_uart1_groups), }, 582 { "uart2", jz4760_uart2_groups, ARRAY_SIZE(jz4760_uart2_groups), }, 583 { "uart3", jz4760_uart3_groups, ARRAY_SIZE(jz4760_uart3_groups), }, 584 { "mmc0", jz4760_mmc0_groups, ARRAY_SIZE(jz4760_mmc0_groups), }, 585 { "mmc1", jz4760_mmc1_groups, ARRAY_SIZE(jz4760_mmc1_groups), }, 586 { "mmc2", jz4760_mmc2_groups, ARRAY_SIZE(jz4760_mmc2_groups), }, 587 { "nemc", jz4760_nemc_groups, ARRAY_SIZE(jz4760_nemc_groups), }, 588 { "nemc-cs1", jz4760_cs1_groups, ARRAY_SIZE(jz4760_cs1_groups), }, 589 { "nemc-cs2", jz4760_cs2_groups, ARRAY_SIZE(jz4760_cs2_groups), }, 590 { "nemc-cs3", jz4760_cs3_groups, ARRAY_SIZE(jz4760_cs3_groups), }, 591 { "nemc-cs4", jz4760_cs4_groups, ARRAY_SIZE(jz4760_cs4_groups), }, 592 { "nemc-cs5", jz4760_cs5_groups, ARRAY_SIZE(jz4760_cs5_groups), }, 593 { "nemc-cs6", jz4760_cs6_groups, ARRAY_SIZE(jz4760_cs6_groups), }, 594 { "i2c0", jz4760_i2c0_groups, ARRAY_SIZE(jz4760_i2c0_groups), }, 595 { "i2c1", jz4760_i2c1_groups, ARRAY_SIZE(jz4760_i2c1_groups), }, 596 { "cim", jz4760_cim_groups, ARRAY_SIZE(jz4760_cim_groups), }, 597 { "lcd", jz4760_lcd_groups, ARRAY_SIZE(jz4760_lcd_groups), }, 598 { "pwm0", jz4760_pwm0_groups, ARRAY_SIZE(jz4760_pwm0_groups), }, 599 { "pwm1", jz4760_pwm1_groups, ARRAY_SIZE(jz4760_pwm1_groups), }, 600 { "pwm2", jz4760_pwm2_groups, ARRAY_SIZE(jz4760_pwm2_groups), }, 601 { "pwm3", jz4760_pwm3_groups, ARRAY_SIZE(jz4760_pwm3_groups), }, 602 { "pwm4", jz4760_pwm4_groups, ARRAY_SIZE(jz4760_pwm4_groups), }, 603 { "pwm5", jz4760_pwm5_groups, ARRAY_SIZE(jz4760_pwm5_groups), }, 604 { "pwm6", jz4760_pwm6_groups, ARRAY_SIZE(jz4760_pwm6_groups), }, 605 { "pwm7", jz4760_pwm7_groups, ARRAY_SIZE(jz4760_pwm7_groups), }, 606 }; 607 608 static const struct ingenic_chip_info jz4760_chip_info = { 609 .num_chips = 6, 610 .reg_offset = 0x100, 611 .version = ID_JZ4760, 612 .groups = jz4760_groups, 613 .num_groups = ARRAY_SIZE(jz4760_groups), 614 .functions = jz4760_functions, 615 .num_functions = ARRAY_SIZE(jz4760_functions), 616 .pull_ups = jz4760_pull_ups, 617 .pull_downs = jz4760_pull_downs, 618 }; 619 620 static const u32 jz4770_pull_ups[6] = { 621 0x3fffffff, 0xfff0030c, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0xffa7f00f, 622 }; 623 624 static const u32 jz4770_pull_downs[6] = { 625 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0, 626 }; 627 628 static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, }; 629 static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; 630 static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, }; 631 static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; 632 static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, }; 633 static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, }; 634 static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, }; 635 static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, }; 636 static int jz4770_ssi0_dt_a_pins[] = { 0x15, }; 637 static int jz4770_ssi0_dt_b_pins[] = { 0x35, }; 638 static int jz4770_ssi0_dt_d_pins[] = { 0x75, }; 639 static int jz4770_ssi0_dt_e_pins[] = { 0x91, }; 640 static int jz4770_ssi0_dr_a_pins[] = { 0x14, }; 641 static int jz4770_ssi0_dr_b_pins[] = { 0x34, }; 642 static int jz4770_ssi0_dr_d_pins[] = { 0x74, }; 643 static int jz4770_ssi0_dr_e_pins[] = { 0x8e, }; 644 static int jz4770_ssi0_clk_a_pins[] = { 0x12, }; 645 static int jz4770_ssi0_clk_b_pins[] = { 0x3c, }; 646 static int jz4770_ssi0_clk_d_pins[] = { 0x78, }; 647 static int jz4770_ssi0_clk_e_pins[] = { 0x8f, }; 648 static int jz4770_ssi0_gpc_b_pins[] = { 0x3e, }; 649 static int jz4770_ssi0_gpc_d_pins[] = { 0x76, }; 650 static int jz4770_ssi0_gpc_e_pins[] = { 0x93, }; 651 static int jz4770_ssi0_ce0_a_pins[] = { 0x13, }; 652 static int jz4770_ssi0_ce0_b_pins[] = { 0x3d, }; 653 static int jz4770_ssi0_ce0_d_pins[] = { 0x79, }; 654 static int jz4770_ssi0_ce0_e_pins[] = { 0x90, }; 655 static int jz4770_ssi0_ce1_b_pins[] = { 0x3f, }; 656 static int jz4770_ssi0_ce1_d_pins[] = { 0x77, }; 657 static int jz4770_ssi0_ce1_e_pins[] = { 0x92, }; 658 static int jz4770_ssi1_dt_b_pins[] = { 0x35, }; 659 static int jz4770_ssi1_dt_d_pins[] = { 0x75, }; 660 static int jz4770_ssi1_dt_e_pins[] = { 0x91, }; 661 static int jz4770_ssi1_dr_b_pins[] = { 0x34, }; 662 static int jz4770_ssi1_dr_d_pins[] = { 0x74, }; 663 static int jz4770_ssi1_dr_e_pins[] = { 0x8e, }; 664 static int jz4770_ssi1_clk_b_pins[] = { 0x3c, }; 665 static int jz4770_ssi1_clk_d_pins[] = { 0x78, }; 666 static int jz4770_ssi1_clk_e_pins[] = { 0x8f, }; 667 static int jz4770_ssi1_gpc_b_pins[] = { 0x3e, }; 668 static int jz4770_ssi1_gpc_d_pins[] = { 0x76, }; 669 static int jz4770_ssi1_gpc_e_pins[] = { 0x93, }; 670 static int jz4770_ssi1_ce0_b_pins[] = { 0x3d, }; 671 static int jz4770_ssi1_ce0_d_pins[] = { 0x79, }; 672 static int jz4770_ssi1_ce0_e_pins[] = { 0x90, }; 673 static int jz4770_ssi1_ce1_b_pins[] = { 0x3f, }; 674 static int jz4770_ssi1_ce1_d_pins[] = { 0x77, }; 675 static int jz4770_ssi1_ce1_e_pins[] = { 0x92, }; 676 static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; 677 static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; 678 static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 679 static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 680 static int jz4770_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 681 static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; 682 static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; 683 static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 684 static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 685 static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 686 static int jz4770_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, }; 687 static int jz4770_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, }; 688 static int jz4770_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 689 static int jz4770_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 690 static int jz4770_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 691 static int jz4770_nemc_8bit_data_pins[] = { 692 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 693 }; 694 static int jz4770_nemc_16bit_data_pins[] = { 695 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 696 }; 697 static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, }; 698 static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; 699 static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, }; 700 static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; 701 static int jz4770_nemc_wait_pins[] = { 0x1b, }; 702 static int jz4770_nemc_cs1_pins[] = { 0x15, }; 703 static int jz4770_nemc_cs2_pins[] = { 0x16, }; 704 static int jz4770_nemc_cs3_pins[] = { 0x17, }; 705 static int jz4770_nemc_cs4_pins[] = { 0x18, }; 706 static int jz4770_nemc_cs5_pins[] = { 0x19, }; 707 static int jz4770_nemc_cs6_pins[] = { 0x1a, }; 708 static int jz4770_i2c0_pins[] = { 0x7e, 0x7f, }; 709 static int jz4770_i2c1_pins[] = { 0x9e, 0x9f, }; 710 static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, }; 711 static int jz4770_cim_8bit_pins[] = { 712 0x26, 0x27, 0x28, 0x29, 713 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 714 }; 715 static int jz4770_cim_12bit_pins[] = { 716 0x32, 0x33, 0xb0, 0xb1, 717 }; 718 static int jz4770_lcd_24bit_pins[] = { 719 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 720 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 721 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 722 0x58, 0x59, 0x5a, 0x5b, 723 }; 724 static int jz4770_pwm_pwm0_pins[] = { 0x80, }; 725 static int jz4770_pwm_pwm1_pins[] = { 0x81, }; 726 static int jz4770_pwm_pwm2_pins[] = { 0x82, }; 727 static int jz4770_pwm_pwm3_pins[] = { 0x83, }; 728 static int jz4770_pwm_pwm4_pins[] = { 0x84, }; 729 static int jz4770_pwm_pwm5_pins[] = { 0x85, }; 730 static int jz4770_pwm_pwm6_pins[] = { 0x6a, }; 731 static int jz4770_pwm_pwm7_pins[] = { 0x6b, }; 732 static int jz4770_mac_rmii_pins[] = { 733 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8, 734 }; 735 static int jz4770_mac_mii_pins[] = { 0xa7, 0xaf, }; 736 static int jz4770_otg_pins[] = { 0x8a, }; 737 738 static int jz4770_uart0_data_funcs[] = { 0, 0, }; 739 static int jz4770_uart0_hwflow_funcs[] = { 0, 0, }; 740 static int jz4770_uart1_data_funcs[] = { 0, 0, }; 741 static int jz4770_uart1_hwflow_funcs[] = { 0, 0, }; 742 static int jz4770_uart2_data_funcs[] = { 0, 0, }; 743 static int jz4770_uart2_hwflow_funcs[] = { 0, 0, }; 744 static int jz4770_uart3_data_funcs[] = { 0, 1, }; 745 static int jz4770_uart3_hwflow_funcs[] = { 0, 0, }; 746 static int jz4770_ssi0_dt_a_funcs[] = { 2, }; 747 static int jz4770_ssi0_dt_b_funcs[] = { 1, }; 748 static int jz4770_ssi0_dt_d_funcs[] = { 1, }; 749 static int jz4770_ssi0_dt_e_funcs[] = { 0, }; 750 static int jz4770_ssi0_dr_a_funcs[] = { 1, }; 751 static int jz4770_ssi0_dr_b_funcs[] = { 1, }; 752 static int jz4770_ssi0_dr_d_funcs[] = { 1, }; 753 static int jz4770_ssi0_dr_e_funcs[] = { 0, }; 754 static int jz4770_ssi0_clk_a_funcs[] = { 2, }; 755 static int jz4770_ssi0_clk_b_funcs[] = { 1, }; 756 static int jz4770_ssi0_clk_d_funcs[] = { 1, }; 757 static int jz4770_ssi0_clk_e_funcs[] = { 0, }; 758 static int jz4770_ssi0_gpc_b_funcs[] = { 1, }; 759 static int jz4770_ssi0_gpc_d_funcs[] = { 1, }; 760 static int jz4770_ssi0_gpc_e_funcs[] = { 0, }; 761 static int jz4770_ssi0_ce0_a_funcs[] = { 2, }; 762 static int jz4770_ssi0_ce0_b_funcs[] = { 1, }; 763 static int jz4770_ssi0_ce0_d_funcs[] = { 1, }; 764 static int jz4770_ssi0_ce0_e_funcs[] = { 0, }; 765 static int jz4770_ssi0_ce1_b_funcs[] = { 1, }; 766 static int jz4770_ssi0_ce1_d_funcs[] = { 1, }; 767 static int jz4770_ssi0_ce1_e_funcs[] = { 0, }; 768 static int jz4770_ssi1_dt_b_funcs[] = { 2, }; 769 static int jz4770_ssi1_dt_d_funcs[] = { 2, }; 770 static int jz4770_ssi1_dt_e_funcs[] = { 1, }; 771 static int jz4770_ssi1_dr_b_funcs[] = { 2, }; 772 static int jz4770_ssi1_dr_d_funcs[] = { 2, }; 773 static int jz4770_ssi1_dr_e_funcs[] = { 1, }; 774 static int jz4770_ssi1_clk_b_funcs[] = { 2, }; 775 static int jz4770_ssi1_clk_d_funcs[] = { 2, }; 776 static int jz4770_ssi1_clk_e_funcs[] = { 1, }; 777 static int jz4770_ssi1_gpc_b_funcs[] = { 2, }; 778 static int jz4770_ssi1_gpc_d_funcs[] = { 2, }; 779 static int jz4770_ssi1_gpc_e_funcs[] = { 1, }; 780 static int jz4770_ssi1_ce0_b_funcs[] = { 2, }; 781 static int jz4770_ssi1_ce0_d_funcs[] = { 2, }; 782 static int jz4770_ssi1_ce0_e_funcs[] = { 1, }; 783 static int jz4770_ssi1_ce1_b_funcs[] = { 2, }; 784 static int jz4770_ssi1_ce1_d_funcs[] = { 2, }; 785 static int jz4770_ssi1_ce1_e_funcs[] = { 1, }; 786 static int jz4770_mmc0_1bit_a_funcs[] = { 1, 1, 0, }; 787 static int jz4770_mmc0_4bit_a_funcs[] = { 1, 1, 1, }; 788 static int jz4770_mmc0_1bit_e_funcs[] = { 0, 0, 0, }; 789 static int jz4770_mmc0_4bit_e_funcs[] = { 0, 0, 0, }; 790 static int jz4770_mmc0_8bit_e_funcs[] = { 0, 0, 0, 0, }; 791 static int jz4770_mmc1_1bit_d_funcs[] = { 0, 0, 0, }; 792 static int jz4770_mmc1_4bit_d_funcs[] = { 0, 0, 0, }; 793 static int jz4770_mmc1_1bit_e_funcs[] = { 1, 1, 1, }; 794 static int jz4770_mmc1_4bit_e_funcs[] = { 1, 1, 1, }; 795 static int jz4770_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, }; 796 static int jz4770_mmc2_1bit_b_funcs[] = { 0, 0, 0, }; 797 static int jz4770_mmc2_4bit_b_funcs[] = { 0, 0, 0, }; 798 static int jz4770_mmc2_1bit_e_funcs[] = { 2, 2, 2, }; 799 static int jz4770_mmc2_4bit_e_funcs[] = { 2, 2, 2, }; 800 static int jz4770_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, }; 801 static int jz4770_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 802 static int jz4770_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 803 static int jz4770_nemc_cle_ale_funcs[] = { 0, 0, }; 804 static int jz4770_nemc_addr_funcs[] = { 0, 0, 0, 0, }; 805 static int jz4770_nemc_rd_we_funcs[] = { 0, 0, }; 806 static int jz4770_nemc_frd_fwe_funcs[] = { 0, 0, }; 807 static int jz4770_nemc_wait_funcs[] = { 0, }; 808 static int jz4770_nemc_cs1_funcs[] = { 0, }; 809 static int jz4770_nemc_cs2_funcs[] = { 0, }; 810 static int jz4770_nemc_cs3_funcs[] = { 0, }; 811 static int jz4770_nemc_cs4_funcs[] = { 0, }; 812 static int jz4770_nemc_cs5_funcs[] = { 0, }; 813 static int jz4770_nemc_cs6_funcs[] = { 0, }; 814 static int jz4770_i2c0_funcs[] = { 0, 0, }; 815 static int jz4770_i2c1_funcs[] = { 0, 0, }; 816 static int jz4770_i2c2_funcs[] = { 2, 2, }; 817 static int jz4770_cim_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 818 static int jz4770_cim_12bit_funcs[] = { 0, 0, 0, 0, }; 819 static int jz4770_lcd_24bit_funcs[] = { 820 0, 0, 0, 0, 0, 0, 0, 0, 821 0, 0, 0, 0, 0, 0, 0, 0, 822 0, 0, 0, 0, 0, 0, 0, 0, 823 0, 0, 0, 0, 824 }; 825 static int jz4770_pwm_pwm0_funcs[] = { 0, }; 826 static int jz4770_pwm_pwm1_funcs[] = { 0, }; 827 static int jz4770_pwm_pwm2_funcs[] = { 0, }; 828 static int jz4770_pwm_pwm3_funcs[] = { 0, }; 829 static int jz4770_pwm_pwm4_funcs[] = { 0, }; 830 static int jz4770_pwm_pwm5_funcs[] = { 0, }; 831 static int jz4770_pwm_pwm6_funcs[] = { 0, }; 832 static int jz4770_pwm_pwm7_funcs[] = { 0, }; 833 static int jz4770_mac_rmii_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 834 static int jz4770_mac_mii_funcs[] = { 0, 0, }; 835 static int jz4770_otg_funcs[] = { 0, }; 836 837 static const struct group_desc jz4770_groups[] = { 838 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data), 839 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow), 840 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data), 841 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow), 842 INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data), 843 INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow), 844 INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data), 845 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow), 846 INGENIC_PIN_GROUP("ssi0-dt-a", jz4770_ssi0_dt_a), 847 INGENIC_PIN_GROUP("ssi0-dt-b", jz4770_ssi0_dt_b), 848 INGENIC_PIN_GROUP("ssi0-dt-d", jz4770_ssi0_dt_d), 849 INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e), 850 INGENIC_PIN_GROUP("ssi0-dr-a", jz4770_ssi0_dr_a), 851 INGENIC_PIN_GROUP("ssi0-dr-b", jz4770_ssi0_dr_b), 852 INGENIC_PIN_GROUP("ssi0-dr-d", jz4770_ssi0_dr_d), 853 INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e), 854 INGENIC_PIN_GROUP("ssi0-clk-a", jz4770_ssi0_clk_a), 855 INGENIC_PIN_GROUP("ssi0-clk-b", jz4770_ssi0_clk_b), 856 INGENIC_PIN_GROUP("ssi0-clk-d", jz4770_ssi0_clk_d), 857 INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e), 858 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4770_ssi0_gpc_b), 859 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4770_ssi0_gpc_d), 860 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e), 861 INGENIC_PIN_GROUP("ssi0-ce0-a", jz4770_ssi0_ce0_a), 862 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4770_ssi0_ce0_b), 863 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4770_ssi0_ce0_d), 864 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e), 865 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4770_ssi0_ce1_b), 866 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4770_ssi0_ce1_d), 867 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e), 868 INGENIC_PIN_GROUP("ssi1-dt-b", jz4770_ssi1_dt_b), 869 INGENIC_PIN_GROUP("ssi1-dt-d", jz4770_ssi1_dt_d), 870 INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e), 871 INGENIC_PIN_GROUP("ssi1-dr-b", jz4770_ssi1_dr_b), 872 INGENIC_PIN_GROUP("ssi1-dr-d", jz4770_ssi1_dr_d), 873 INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e), 874 INGENIC_PIN_GROUP("ssi1-clk-b", jz4770_ssi1_clk_b), 875 INGENIC_PIN_GROUP("ssi1-clk-d", jz4770_ssi1_clk_d), 876 INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e), 877 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4770_ssi1_gpc_b), 878 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4770_ssi1_gpc_d), 879 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e), 880 INGENIC_PIN_GROUP("ssi1-ce0-b", jz4770_ssi1_ce0_b), 881 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4770_ssi1_ce0_d), 882 INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e), 883 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4770_ssi1_ce1_b), 884 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4770_ssi1_ce1_d), 885 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e), 886 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a), 887 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a), 888 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e), 889 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e), 890 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e), 891 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d), 892 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d), 893 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e), 894 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e), 895 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e), 896 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b), 897 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b), 898 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e), 899 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e), 900 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e), 901 INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data), 902 INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data), 903 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale), 904 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr), 905 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we), 906 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe), 907 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait), 908 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1), 909 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2), 910 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3), 911 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4), 912 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5), 913 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6), 914 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0), 915 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1), 916 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2), 917 INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit), 918 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit), 919 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit), 920 { "lcd-no-pins", }, 921 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0), 922 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1), 923 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2), 924 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3), 925 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4), 926 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5), 927 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6), 928 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7), 929 INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii), 930 INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii), 931 INGENIC_PIN_GROUP("otg-vbus", jz4770_otg), 932 }; 933 934 static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 935 static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 936 static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 937 static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 938 static const char *jz4770_ssi0_groups[] = { 939 "ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e", 940 "ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e", 941 "ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e", 942 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e", 943 "ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e", 944 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e", 945 }; 946 static const char *jz4770_ssi1_groups[] = { 947 "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e", 948 "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e", 949 "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e", 950 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e", 951 "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e", 952 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e", 953 }; 954 static const char *jz4770_mmc0_groups[] = { 955 "mmc0-1bit-a", "mmc0-4bit-a", 956 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e", 957 }; 958 static const char *jz4770_mmc1_groups[] = { 959 "mmc1-1bit-d", "mmc1-4bit-d", 960 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e", 961 }; 962 static const char *jz4770_mmc2_groups[] = { 963 "mmc2-1bit-b", "mmc2-4bit-b", 964 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e", 965 }; 966 static const char *jz4770_nemc_groups[] = { 967 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale", 968 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 969 }; 970 static const char *jz4770_cs1_groups[] = { "nemc-cs1", }; 971 static const char *jz4770_cs2_groups[] = { "nemc-cs2", }; 972 static const char *jz4770_cs3_groups[] = { "nemc-cs3", }; 973 static const char *jz4770_cs4_groups[] = { "nemc-cs4", }; 974 static const char *jz4770_cs5_groups[] = { "nemc-cs5", }; 975 static const char *jz4770_cs6_groups[] = { "nemc-cs6", }; 976 static const char *jz4770_i2c0_groups[] = { "i2c0-data", }; 977 static const char *jz4770_i2c1_groups[] = { "i2c1-data", }; 978 static const char *jz4770_i2c2_groups[] = { "i2c2-data", }; 979 static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", }; 980 static const char *jz4770_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", }; 981 static const char *jz4770_pwm0_groups[] = { "pwm0", }; 982 static const char *jz4770_pwm1_groups[] = { "pwm1", }; 983 static const char *jz4770_pwm2_groups[] = { "pwm2", }; 984 static const char *jz4770_pwm3_groups[] = { "pwm3", }; 985 static const char *jz4770_pwm4_groups[] = { "pwm4", }; 986 static const char *jz4770_pwm5_groups[] = { "pwm5", }; 987 static const char *jz4770_pwm6_groups[] = { "pwm6", }; 988 static const char *jz4770_pwm7_groups[] = { "pwm7", }; 989 static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", }; 990 static const char *jz4770_otg_groups[] = { "otg-vbus", }; 991 992 static const struct function_desc jz4770_functions[] = { 993 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), }, 994 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), }, 995 { "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), }, 996 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), }, 997 { "ssi0", jz4770_ssi0_groups, ARRAY_SIZE(jz4770_ssi0_groups), }, 998 { "ssi1", jz4770_ssi1_groups, ARRAY_SIZE(jz4770_ssi1_groups), }, 999 { "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), }, 1000 { "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), }, 1001 { "mmc2", jz4770_mmc2_groups, ARRAY_SIZE(jz4770_mmc2_groups), }, 1002 { "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), }, 1003 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), }, 1004 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), }, 1005 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), }, 1006 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), }, 1007 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), }, 1008 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), }, 1009 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), }, 1010 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), }, 1011 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), }, 1012 { "cim", jz4770_cim_groups, ARRAY_SIZE(jz4770_cim_groups), }, 1013 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), }, 1014 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), }, 1015 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), }, 1016 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), }, 1017 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), }, 1018 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), }, 1019 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), }, 1020 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), }, 1021 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), }, 1022 { "mac", jz4770_mac_groups, ARRAY_SIZE(jz4770_mac_groups), }, 1023 { "otg", jz4770_otg_groups, ARRAY_SIZE(jz4770_otg_groups), }, 1024 }; 1025 1026 static const struct ingenic_chip_info jz4770_chip_info = { 1027 .num_chips = 6, 1028 .reg_offset = 0x100, 1029 .version = ID_JZ4770, 1030 .groups = jz4770_groups, 1031 .num_groups = ARRAY_SIZE(jz4770_groups), 1032 .functions = jz4770_functions, 1033 .num_functions = ARRAY_SIZE(jz4770_functions), 1034 .pull_ups = jz4770_pull_ups, 1035 .pull_downs = jz4770_pull_downs, 1036 }; 1037 1038 static const u32 jz4780_pull_ups[6] = { 1039 0x3fffffff, 0xfff0f3fc, 0x0fffffff, 0xffff4fff, 0xfffffb7c, 0x7fa7f00f, 1040 }; 1041 1042 static const u32 jz4780_pull_downs[6] = { 1043 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0, 1044 }; 1045 1046 static int jz4780_uart2_data_pins[] = { 0x66, 0x67, }; 1047 static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, }; 1048 static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, }; 1049 static int jz4780_ssi0_dt_a_19_pins[] = { 0x13, }; 1050 static int jz4780_ssi0_dt_a_21_pins[] = { 0x15, }; 1051 static int jz4780_ssi0_dt_a_28_pins[] = { 0x1c, }; 1052 static int jz4780_ssi0_dt_b_pins[] = { 0x3d, }; 1053 static int jz4780_ssi0_dt_d_pins[] = { 0x79, }; 1054 static int jz4780_ssi0_dr_a_20_pins[] = { 0x14, }; 1055 static int jz4780_ssi0_dr_a_27_pins[] = { 0x1b, }; 1056 static int jz4780_ssi0_dr_b_pins[] = { 0x34, }; 1057 static int jz4780_ssi0_dr_d_pins[] = { 0x74, }; 1058 static int jz4780_ssi0_clk_a_pins[] = { 0x12, }; 1059 static int jz4780_ssi0_clk_b_5_pins[] = { 0x25, }; 1060 static int jz4780_ssi0_clk_b_28_pins[] = { 0x3c, }; 1061 static int jz4780_ssi0_clk_d_pins[] = { 0x78, }; 1062 static int jz4780_ssi0_gpc_b_pins[] = { 0x3e, }; 1063 static int jz4780_ssi0_gpc_d_pins[] = { 0x76, }; 1064 static int jz4780_ssi0_ce0_a_23_pins[] = { 0x17, }; 1065 static int jz4780_ssi0_ce0_a_25_pins[] = { 0x19, }; 1066 static int jz4780_ssi0_ce0_b_pins[] = { 0x3f, }; 1067 static int jz4780_ssi0_ce0_d_pins[] = { 0x77, }; 1068 static int jz4780_ssi0_ce1_b_pins[] = { 0x35, }; 1069 static int jz4780_ssi0_ce1_d_pins[] = { 0x75, }; 1070 static int jz4780_ssi1_dt_b_pins[] = { 0x3d, }; 1071 static int jz4780_ssi1_dt_d_pins[] = { 0x79, }; 1072 static int jz4780_ssi1_dr_b_pins[] = { 0x34, }; 1073 static int jz4780_ssi1_dr_d_pins[] = { 0x74, }; 1074 static int jz4780_ssi1_clk_b_pins[] = { 0x3c, }; 1075 static int jz4780_ssi1_clk_d_pins[] = { 0x78, }; 1076 static int jz4780_ssi1_gpc_b_pins[] = { 0x3e, }; 1077 static int jz4780_ssi1_gpc_d_pins[] = { 0x76, }; 1078 static int jz4780_ssi1_ce0_b_pins[] = { 0x3f, }; 1079 static int jz4780_ssi1_ce0_d_pins[] = { 0x77, }; 1080 static int jz4780_ssi1_ce1_b_pins[] = { 0x35, }; 1081 static int jz4780_ssi1_ce1_d_pins[] = { 0x75, }; 1082 static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, }; 1083 static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, }; 1084 static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, }; 1085 static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, }; 1086 static int jz4780_i2s_data_tx_pins[] = { 0x87, }; 1087 static int jz4780_i2s_data_rx_pins[] = { 0x86, }; 1088 static int jz4780_i2s_clk_txrx_pins[] = { 0x6c, 0x6d, }; 1089 static int jz4780_i2s_clk_rx_pins[] = { 0x88, 0x89, }; 1090 static int jz4780_i2s_sysclk_pins[] = { 0x85, }; 1091 static int jz4780_hdmi_ddc_pins[] = { 0xb9, 0xb8, }; 1092 1093 static int jz4780_uart2_data_funcs[] = { 1, 1, }; 1094 static int jz4780_uart2_hwflow_funcs[] = { 1, 1, }; 1095 static int jz4780_uart4_data_funcs[] = { 2, 2, }; 1096 static int jz4780_ssi0_dt_a_19_funcs[] = { 2, }; 1097 static int jz4780_ssi0_dt_a_21_funcs[] = { 2, }; 1098 static int jz4780_ssi0_dt_a_28_funcs[] = { 2, }; 1099 static int jz4780_ssi0_dt_b_funcs[] = { 1, }; 1100 static int jz4780_ssi0_dt_d_funcs[] = { 1, }; 1101 static int jz4780_ssi0_dr_a_20_funcs[] = { 2, }; 1102 static int jz4780_ssi0_dr_a_27_funcs[] = { 2, }; 1103 static int jz4780_ssi0_dr_b_funcs[] = { 1, }; 1104 static int jz4780_ssi0_dr_d_funcs[] = { 1, }; 1105 static int jz4780_ssi0_clk_a_funcs[] = { 2, }; 1106 static int jz4780_ssi0_clk_b_5_funcs[] = { 1, }; 1107 static int jz4780_ssi0_clk_b_28_funcs[] = { 1, }; 1108 static int jz4780_ssi0_clk_d_funcs[] = { 1, }; 1109 static int jz4780_ssi0_gpc_b_funcs[] = { 1, }; 1110 static int jz4780_ssi0_gpc_d_funcs[] = { 1, }; 1111 static int jz4780_ssi0_ce0_a_23_funcs[] = { 2, }; 1112 static int jz4780_ssi0_ce0_a_25_funcs[] = { 2, }; 1113 static int jz4780_ssi0_ce0_b_funcs[] = { 1, }; 1114 static int jz4780_ssi0_ce0_d_funcs[] = { 1, }; 1115 static int jz4780_ssi0_ce1_b_funcs[] = { 1, }; 1116 static int jz4780_ssi0_ce1_d_funcs[] = { 1, }; 1117 static int jz4780_ssi1_dt_b_funcs[] = { 2, }; 1118 static int jz4780_ssi1_dt_d_funcs[] = { 2, }; 1119 static int jz4780_ssi1_dr_b_funcs[] = { 2, }; 1120 static int jz4780_ssi1_dr_d_funcs[] = { 2, }; 1121 static int jz4780_ssi1_clk_b_funcs[] = { 2, }; 1122 static int jz4780_ssi1_clk_d_funcs[] = { 2, }; 1123 static int jz4780_ssi1_gpc_b_funcs[] = { 2, }; 1124 static int jz4780_ssi1_gpc_d_funcs[] = { 2, }; 1125 static int jz4780_ssi1_ce0_b_funcs[] = { 2, }; 1126 static int jz4780_ssi1_ce0_d_funcs[] = { 2, }; 1127 static int jz4780_ssi1_ce1_b_funcs[] = { 2, }; 1128 static int jz4780_ssi1_ce1_d_funcs[] = { 2, }; 1129 static int jz4780_mmc0_8bit_a_funcs[] = { 1, 1, 1, 1, 1, }; 1130 static int jz4780_i2c3_funcs[] = { 1, 1, }; 1131 static int jz4780_i2c4_e_funcs[] = { 1, 1, }; 1132 static int jz4780_i2c4_f_funcs[] = { 1, 1, }; 1133 static int jz4780_i2s_data_tx_funcs[] = { 0, }; 1134 static int jz4780_i2s_data_rx_funcs[] = { 0, }; 1135 static int jz4780_i2s_clk_txrx_funcs[] = { 1, 0, }; 1136 static int jz4780_i2s_clk_rx_funcs[] = { 1, 1, }; 1137 static int jz4780_i2s_sysclk_funcs[] = { 2, }; 1138 static int jz4780_hdmi_ddc_funcs[] = { 0, 0, }; 1139 1140 static const struct group_desc jz4780_groups[] = { 1141 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data), 1142 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow), 1143 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data), 1144 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow), 1145 INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data), 1146 INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow), 1147 INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data), 1148 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow), 1149 INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data), 1150 INGENIC_PIN_GROUP("ssi0-dt-a-19", jz4780_ssi0_dt_a_19), 1151 INGENIC_PIN_GROUP("ssi0-dt-a-21", jz4780_ssi0_dt_a_21), 1152 INGENIC_PIN_GROUP("ssi0-dt-a-28", jz4780_ssi0_dt_a_28), 1153 INGENIC_PIN_GROUP("ssi0-dt-b", jz4780_ssi0_dt_b), 1154 INGENIC_PIN_GROUP("ssi0-dt-d", jz4780_ssi0_dt_d), 1155 INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e), 1156 INGENIC_PIN_GROUP("ssi0-dr-a-20", jz4780_ssi0_dr_a_20), 1157 INGENIC_PIN_GROUP("ssi0-dr-a-27", jz4780_ssi0_dr_a_27), 1158 INGENIC_PIN_GROUP("ssi0-dr-b", jz4780_ssi0_dr_b), 1159 INGENIC_PIN_GROUP("ssi0-dr-d", jz4780_ssi0_dr_d), 1160 INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e), 1161 INGENIC_PIN_GROUP("ssi0-clk-a", jz4780_ssi0_clk_a), 1162 INGENIC_PIN_GROUP("ssi0-clk-b-5", jz4780_ssi0_clk_b_5), 1163 INGENIC_PIN_GROUP("ssi0-clk-b-28", jz4780_ssi0_clk_b_28), 1164 INGENIC_PIN_GROUP("ssi0-clk-d", jz4780_ssi0_clk_d), 1165 INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e), 1166 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4780_ssi0_gpc_b), 1167 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4780_ssi0_gpc_d), 1168 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e), 1169 INGENIC_PIN_GROUP("ssi0-ce0-a-23", jz4780_ssi0_ce0_a_23), 1170 INGENIC_PIN_GROUP("ssi0-ce0-a-25", jz4780_ssi0_ce0_a_25), 1171 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4780_ssi0_ce0_b), 1172 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4780_ssi0_ce0_d), 1173 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e), 1174 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4780_ssi0_ce1_b), 1175 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4780_ssi0_ce1_d), 1176 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e), 1177 INGENIC_PIN_GROUP("ssi1-dt-b", jz4780_ssi1_dt_b), 1178 INGENIC_PIN_GROUP("ssi1-dt-d", jz4780_ssi1_dt_d), 1179 INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e), 1180 INGENIC_PIN_GROUP("ssi1-dr-b", jz4780_ssi1_dr_b), 1181 INGENIC_PIN_GROUP("ssi1-dr-d", jz4780_ssi1_dr_d), 1182 INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e), 1183 INGENIC_PIN_GROUP("ssi1-clk-b", jz4780_ssi1_clk_b), 1184 INGENIC_PIN_GROUP("ssi1-clk-d", jz4780_ssi1_clk_d), 1185 INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e), 1186 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4780_ssi1_gpc_b), 1187 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4780_ssi1_gpc_d), 1188 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e), 1189 INGENIC_PIN_GROUP("ssi1-ce0-b", jz4780_ssi1_ce0_b), 1190 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4780_ssi1_ce0_d), 1191 INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e), 1192 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4780_ssi1_ce1_b), 1193 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4780_ssi1_ce1_d), 1194 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e), 1195 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a), 1196 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a), 1197 INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a), 1198 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e), 1199 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e), 1200 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d), 1201 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d), 1202 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e), 1203 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e), 1204 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b), 1205 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b), 1206 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e), 1207 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e), 1208 INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data), 1209 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale), 1210 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr), 1211 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we), 1212 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe), 1213 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait), 1214 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1), 1215 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2), 1216 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3), 1217 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4), 1218 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5), 1219 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6), 1220 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0), 1221 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1), 1222 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2), 1223 INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3), 1224 INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e), 1225 INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f), 1226 INGENIC_PIN_GROUP("i2s-data-tx", jz4780_i2s_data_tx), 1227 INGENIC_PIN_GROUP("i2s-data-rx", jz4780_i2s_data_rx), 1228 INGENIC_PIN_GROUP("i2s-clk-txrx", jz4780_i2s_clk_txrx), 1229 INGENIC_PIN_GROUP("i2s-clk-rx", jz4780_i2s_clk_rx), 1230 INGENIC_PIN_GROUP("i2s-sysclk", jz4780_i2s_sysclk), 1231 INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc), 1232 INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit), 1233 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit), 1234 { "lcd-no-pins", }, 1235 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0), 1236 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1), 1237 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2), 1238 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3), 1239 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4), 1240 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5), 1241 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6), 1242 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7), 1243 }; 1244 1245 static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 1246 static const char *jz4780_uart4_groups[] = { "uart4-data", }; 1247 static const char *jz4780_ssi0_groups[] = { 1248 "ssi0-dt-a-19", "ssi0-dt-a-21", "ssi0-dt-a-28", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e", 1249 "ssi0-dr-a-20", "ssi0-dr-a-27", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e", 1250 "ssi0-clk-a", "ssi0-clk-b-5", "ssi0-clk-b-28", "ssi0-clk-d", "ssi0-clk-e", 1251 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e", 1252 "ssi0-ce0-a-23", "ssi0-ce0-a-25", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e", 1253 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e", 1254 }; 1255 static const char *jz4780_ssi1_groups[] = { 1256 "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e", 1257 "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e", 1258 "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e", 1259 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e", 1260 "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e", 1261 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e", 1262 }; 1263 static const char *jz4780_mmc0_groups[] = { 1264 "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a", 1265 "mmc0-1bit-e", "mmc0-4bit-e", 1266 }; 1267 static const char *jz4780_mmc1_groups[] = { 1268 "mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e", 1269 }; 1270 static const char *jz4780_mmc2_groups[] = { 1271 "mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e", 1272 }; 1273 static const char *jz4780_nemc_groups[] = { 1274 "nemc-data", "nemc-cle-ale", "nemc-addr", 1275 "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 1276 }; 1277 static const char *jz4780_i2c3_groups[] = { "i2c3-data", }; 1278 static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", }; 1279 static const char *jz4780_i2s_groups[] = { 1280 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk", 1281 }; 1282 static const char *jz4780_cim_groups[] = { "cim-data", }; 1283 static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", }; 1284 1285 static const struct function_desc jz4780_functions[] = { 1286 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), }, 1287 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), }, 1288 { "uart2", jz4780_uart2_groups, ARRAY_SIZE(jz4780_uart2_groups), }, 1289 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), }, 1290 { "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), }, 1291 { "ssi0", jz4780_ssi0_groups, ARRAY_SIZE(jz4780_ssi0_groups), }, 1292 { "ssi1", jz4780_ssi1_groups, ARRAY_SIZE(jz4780_ssi1_groups), }, 1293 { "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), }, 1294 { "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), }, 1295 { "mmc2", jz4780_mmc2_groups, ARRAY_SIZE(jz4780_mmc2_groups), }, 1296 { "nemc", jz4780_nemc_groups, ARRAY_SIZE(jz4780_nemc_groups), }, 1297 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), }, 1298 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), }, 1299 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), }, 1300 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), }, 1301 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), }, 1302 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), }, 1303 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), }, 1304 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), }, 1305 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), }, 1306 { "i2c3", jz4780_i2c3_groups, ARRAY_SIZE(jz4780_i2c3_groups), }, 1307 { "i2c4", jz4780_i2c4_groups, ARRAY_SIZE(jz4780_i2c4_groups), }, 1308 { "i2s", jz4780_i2s_groups, ARRAY_SIZE(jz4780_i2s_groups), }, 1309 { "cim", jz4780_cim_groups, ARRAY_SIZE(jz4780_cim_groups), }, 1310 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), }, 1311 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), }, 1312 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), }, 1313 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), }, 1314 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), }, 1315 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), }, 1316 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), }, 1317 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), }, 1318 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), }, 1319 { "hdmi-ddc", jz4780_hdmi_ddc_groups, 1320 ARRAY_SIZE(jz4780_hdmi_ddc_groups), }, 1321 }; 1322 1323 static const struct ingenic_chip_info jz4780_chip_info = { 1324 .num_chips = 6, 1325 .reg_offset = 0x100, 1326 .version = ID_JZ4780, 1327 .groups = jz4780_groups, 1328 .num_groups = ARRAY_SIZE(jz4780_groups), 1329 .functions = jz4780_functions, 1330 .num_functions = ARRAY_SIZE(jz4780_functions), 1331 .pull_ups = jz4780_pull_ups, 1332 .pull_downs = jz4780_pull_downs, 1333 }; 1334 1335 static const u32 x1000_pull_ups[4] = { 1336 0xffffffff, 0xfdffffff, 0x0dffffff, 0x0000003f, 1337 }; 1338 1339 static const u32 x1000_pull_downs[4] = { 1340 0x00000000, 0x02000000, 0x02000000, 0x00000000, 1341 }; 1342 1343 static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, }; 1344 static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, }; 1345 static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, }; 1346 static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, }; 1347 static int x1000_uart1_hwflow_pins[] = { 0x64, 0x65, }; 1348 static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, }; 1349 static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, }; 1350 static int x1000_sfc_pins[] = { 0x1d, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, }; 1351 static int x1000_ssi_dt_a_22_pins[] = { 0x16, }; 1352 static int x1000_ssi_dt_a_29_pins[] = { 0x1d, }; 1353 static int x1000_ssi_dt_d_pins[] = { 0x62, }; 1354 static int x1000_ssi_dr_a_23_pins[] = { 0x17, }; 1355 static int x1000_ssi_dr_a_28_pins[] = { 0x1c, }; 1356 static int x1000_ssi_dr_d_pins[] = { 0x63, }; 1357 static int x1000_ssi_clk_a_24_pins[] = { 0x18, }; 1358 static int x1000_ssi_clk_a_26_pins[] = { 0x1a, }; 1359 static int x1000_ssi_clk_d_pins[] = { 0x60, }; 1360 static int x1000_ssi_gpc_a_20_pins[] = { 0x14, }; 1361 static int x1000_ssi_gpc_a_31_pins[] = { 0x1f, }; 1362 static int x1000_ssi_ce0_a_25_pins[] = { 0x19, }; 1363 static int x1000_ssi_ce0_a_27_pins[] = { 0x1b, }; 1364 static int x1000_ssi_ce0_d_pins[] = { 0x61, }; 1365 static int x1000_ssi_ce1_a_21_pins[] = { 0x15, }; 1366 static int x1000_ssi_ce1_a_30_pins[] = { 0x1e, }; 1367 static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, }; 1368 static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, }; 1369 static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, }; 1370 static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, }; 1371 static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, }; 1372 static int x1000_emc_8bit_data_pins[] = { 1373 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 1374 }; 1375 static int x1000_emc_16bit_data_pins[] = { 1376 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 1377 }; 1378 static int x1000_emc_addr_pins[] = { 1379 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 1380 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 1381 }; 1382 static int x1000_emc_rd_we_pins[] = { 0x30, 0x31, }; 1383 static int x1000_emc_wait_pins[] = { 0x34, }; 1384 static int x1000_emc_cs1_pins[] = { 0x32, }; 1385 static int x1000_emc_cs2_pins[] = { 0x33, }; 1386 static int x1000_i2c0_pins[] = { 0x38, 0x37, }; 1387 static int x1000_i2c1_a_pins[] = { 0x01, 0x00, }; 1388 static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, }; 1389 static int x1000_i2c2_pins[] = { 0x61, 0x60, }; 1390 static int x1000_i2s_data_tx_pins[] = { 0x24, }; 1391 static int x1000_i2s_data_rx_pins[] = { 0x23, }; 1392 static int x1000_i2s_clk_txrx_pins[] = { 0x21, 0x22, }; 1393 static int x1000_i2s_sysclk_pins[] = { 0x20, }; 1394 static int x1000_cim_pins[] = { 1395 0x08, 0x09, 0x0a, 0x0b, 1396 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 1397 }; 1398 static int x1000_lcd_8bit_pins[] = { 1399 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 1400 0x30, 0x31, 0x32, 0x33, 0x34, 1401 }; 1402 static int x1000_lcd_16bit_pins[] = { 1403 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 1404 }; 1405 static int x1000_pwm_pwm0_pins[] = { 0x59, }; 1406 static int x1000_pwm_pwm1_pins[] = { 0x5a, }; 1407 static int x1000_pwm_pwm2_pins[] = { 0x5b, }; 1408 static int x1000_pwm_pwm3_pins[] = { 0x26, }; 1409 static int x1000_pwm_pwm4_pins[] = { 0x58, }; 1410 static int x1000_mac_pins[] = { 1411 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x26, 1412 }; 1413 1414 static int x1000_uart0_data_funcs[] = { 0, 0, }; 1415 static int x1000_uart0_hwflow_funcs[] = { 0, 0, }; 1416 static int x1000_uart1_data_a_funcs[] = { 2, 2, }; 1417 static int x1000_uart1_data_d_funcs[] = { 1, 1, }; 1418 static int x1000_uart1_hwflow_funcs[] = { 1, 1, }; 1419 static int x1000_uart2_data_a_funcs[] = { 2, 2, }; 1420 static int x1000_uart2_data_d_funcs[] = { 0, 0, }; 1421 static int x1000_sfc_funcs[] = { 1, 1, 1, 1, 1, 1, }; 1422 static int x1000_ssi_dt_a_22_funcs[] = { 2, }; 1423 static int x1000_ssi_dt_a_29_funcs[] = { 2, }; 1424 static int x1000_ssi_dt_d_funcs[] = { 0, }; 1425 static int x1000_ssi_dr_a_23_funcs[] = { 2, }; 1426 static int x1000_ssi_dr_a_28_funcs[] = { 2, }; 1427 static int x1000_ssi_dr_d_funcs[] = { 0, }; 1428 static int x1000_ssi_clk_a_24_funcs[] = { 2, }; 1429 static int x1000_ssi_clk_a_26_funcs[] = { 2, }; 1430 static int x1000_ssi_clk_d_funcs[] = { 0, }; 1431 static int x1000_ssi_gpc_a_20_funcs[] = { 2, }; 1432 static int x1000_ssi_gpc_a_31_funcs[] = { 2, }; 1433 static int x1000_ssi_ce0_a_25_funcs[] = { 2, }; 1434 static int x1000_ssi_ce0_a_27_funcs[] = { 2, }; 1435 static int x1000_ssi_ce0_d_funcs[] = { 0, }; 1436 static int x1000_ssi_ce1_a_21_funcs[] = { 2, }; 1437 static int x1000_ssi_ce1_a_30_funcs[] = { 2, }; 1438 static int x1000_mmc0_1bit_funcs[] = { 1, 1, 1, }; 1439 static int x1000_mmc0_4bit_funcs[] = { 1, 1, 1, }; 1440 static int x1000_mmc0_8bit_funcs[] = { 1, 1, 1, 1, 1, }; 1441 static int x1000_mmc1_1bit_funcs[] = { 0, 0, 0, }; 1442 static int x1000_mmc1_4bit_funcs[] = { 0, 0, 0, }; 1443 static int x1000_emc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 1444 static int x1000_emc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 1445 static int x1000_emc_addr_funcs[] = { 1446 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1447 }; 1448 static int x1000_emc_rd_we_funcs[] = { 0, 0, }; 1449 static int x1000_emc_wait_funcs[] = { 0, }; 1450 static int x1000_emc_cs1_funcs[] = { 0, }; 1451 static int x1000_emc_cs2_funcs[] = { 0, }; 1452 static int x1000_i2c0_funcs[] = { 0, 0, }; 1453 static int x1000_i2c1_a_funcs[] = { 2, 2, }; 1454 static int x1000_i2c1_c_funcs[] = { 0, 0, }; 1455 static int x1000_i2c2_funcs[] = { 1, 1, }; 1456 static int x1000_i2s_data_tx_funcs[] = { 1, }; 1457 static int x1000_i2s_data_rx_funcs[] = { 1, }; 1458 static int x1000_i2s_clk_txrx_funcs[] = { 1, 1, }; 1459 static int x1000_i2s_sysclk_funcs[] = { 1, }; 1460 static int x1000_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; 1461 static int x1000_lcd_8bit_funcs[] = { 1462 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1463 }; 1464 static int x1000_lcd_16bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, }; 1465 static int x1000_pwm_pwm0_funcs[] = { 0, }; 1466 static int x1000_pwm_pwm1_funcs[] = { 1, }; 1467 static int x1000_pwm_pwm2_funcs[] = { 1, }; 1468 static int x1000_pwm_pwm3_funcs[] = { 2, }; 1469 static int x1000_pwm_pwm4_funcs[] = { 0, }; 1470 static int x1000_mac_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; 1471 1472 static const struct group_desc x1000_groups[] = { 1473 INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data), 1474 INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow), 1475 INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a), 1476 INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d), 1477 INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow), 1478 INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a), 1479 INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d), 1480 INGENIC_PIN_GROUP("sfc", x1000_sfc), 1481 INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22), 1482 INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29), 1483 INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d), 1484 INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23), 1485 INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28), 1486 INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d), 1487 INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24), 1488 INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26), 1489 INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d), 1490 INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20), 1491 INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31), 1492 INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25), 1493 INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27), 1494 INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d), 1495 INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21), 1496 INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30), 1497 INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit), 1498 INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit), 1499 INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit), 1500 INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit), 1501 INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit), 1502 INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data), 1503 INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data), 1504 INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr), 1505 INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we), 1506 INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait), 1507 INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1), 1508 INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2), 1509 INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0), 1510 INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a), 1511 INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c), 1512 INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2), 1513 INGENIC_PIN_GROUP("i2s-data-tx", x1000_i2s_data_tx), 1514 INGENIC_PIN_GROUP("i2s-data-rx", x1000_i2s_data_rx), 1515 INGENIC_PIN_GROUP("i2s-clk-txrx", x1000_i2s_clk_txrx), 1516 INGENIC_PIN_GROUP("i2s-sysclk", x1000_i2s_sysclk), 1517 INGENIC_PIN_GROUP("cim-data", x1000_cim), 1518 INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit), 1519 INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit), 1520 { "lcd-no-pins", }, 1521 INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0), 1522 INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1), 1523 INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2), 1524 INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3), 1525 INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4), 1526 INGENIC_PIN_GROUP("mac", x1000_mac), 1527 }; 1528 1529 static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1530 static const char *x1000_uart1_groups[] = { 1531 "uart1-data-a", "uart1-data-d", "uart1-hwflow", 1532 }; 1533 static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; 1534 static const char *x1000_sfc_groups[] = { "sfc", }; 1535 static const char *x1000_ssi_groups[] = { 1536 "ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d", 1537 "ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d", 1538 "ssi-clk-a-24", "ssi-clk-a-26", "ssi-clk-d", 1539 "ssi-gpc-a-20", "ssi-gpc-a-31", 1540 "ssi-ce0-a-25", "ssi-ce0-a-27", "ssi-ce0-d", 1541 "ssi-ce1-a-21", "ssi-ce1-a-30", 1542 }; 1543 static const char *x1000_mmc0_groups[] = { 1544 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", 1545 }; 1546 static const char *x1000_mmc1_groups[] = { 1547 "mmc1-1bit", "mmc1-4bit", 1548 }; 1549 static const char *x1000_emc_groups[] = { 1550 "emc-8bit-data", "emc-16bit-data", 1551 "emc-addr", "emc-rd-we", "emc-wait", 1552 }; 1553 static const char *x1000_cs1_groups[] = { "emc-cs1", }; 1554 static const char *x1000_cs2_groups[] = { "emc-cs2", }; 1555 static const char *x1000_i2c0_groups[] = { "i2c0-data", }; 1556 static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; 1557 static const char *x1000_i2c2_groups[] = { "i2c2-data", }; 1558 static const char *x1000_i2s_groups[] = { 1559 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk", 1560 }; 1561 static const char *x1000_cim_groups[] = { "cim-data", }; 1562 static const char *x1000_lcd_groups[] = { 1563 "lcd-8bit", "lcd-16bit", "lcd-no-pins", 1564 }; 1565 static const char *x1000_pwm0_groups[] = { "pwm0", }; 1566 static const char *x1000_pwm1_groups[] = { "pwm1", }; 1567 static const char *x1000_pwm2_groups[] = { "pwm2", }; 1568 static const char *x1000_pwm3_groups[] = { "pwm3", }; 1569 static const char *x1000_pwm4_groups[] = { "pwm4", }; 1570 static const char *x1000_mac_groups[] = { "mac", }; 1571 1572 static const struct function_desc x1000_functions[] = { 1573 { "uart0", x1000_uart0_groups, ARRAY_SIZE(x1000_uart0_groups), }, 1574 { "uart1", x1000_uart1_groups, ARRAY_SIZE(x1000_uart1_groups), }, 1575 { "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), }, 1576 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), }, 1577 { "ssi", x1000_ssi_groups, ARRAY_SIZE(x1000_ssi_groups), }, 1578 { "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), }, 1579 { "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), }, 1580 { "emc", x1000_emc_groups, ARRAY_SIZE(x1000_emc_groups), }, 1581 { "emc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), }, 1582 { "emc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), }, 1583 { "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), }, 1584 { "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), }, 1585 { "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), }, 1586 { "i2s", x1000_i2s_groups, ARRAY_SIZE(x1000_i2s_groups), }, 1587 { "cim", x1000_cim_groups, ARRAY_SIZE(x1000_cim_groups), }, 1588 { "lcd", x1000_lcd_groups, ARRAY_SIZE(x1000_lcd_groups), }, 1589 { "pwm0", x1000_pwm0_groups, ARRAY_SIZE(x1000_pwm0_groups), }, 1590 { "pwm1", x1000_pwm1_groups, ARRAY_SIZE(x1000_pwm1_groups), }, 1591 { "pwm2", x1000_pwm2_groups, ARRAY_SIZE(x1000_pwm2_groups), }, 1592 { "pwm3", x1000_pwm3_groups, ARRAY_SIZE(x1000_pwm3_groups), }, 1593 { "pwm4", x1000_pwm4_groups, ARRAY_SIZE(x1000_pwm4_groups), }, 1594 { "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), }, 1595 }; 1596 1597 static const struct ingenic_chip_info x1000_chip_info = { 1598 .num_chips = 4, 1599 .reg_offset = 0x100, 1600 .version = ID_X1000, 1601 .groups = x1000_groups, 1602 .num_groups = ARRAY_SIZE(x1000_groups), 1603 .functions = x1000_functions, 1604 .num_functions = ARRAY_SIZE(x1000_functions), 1605 .pull_ups = x1000_pull_ups, 1606 .pull_downs = x1000_pull_downs, 1607 }; 1608 1609 static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, }; 1610 static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, }; 1611 static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, }; 1612 static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, }; 1613 static int x1500_uart1_hwflow_pins[] = { 0x64, 0x65, }; 1614 static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, }; 1615 static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, }; 1616 static int x1500_mmc_1bit_pins[] = { 0x18, 0x19, 0x17, }; 1617 static int x1500_mmc_4bit_pins[] = { 0x16, 0x15, 0x14, }; 1618 static int x1500_i2c0_pins[] = { 0x38, 0x37, }; 1619 static int x1500_i2c1_a_pins[] = { 0x01, 0x00, }; 1620 static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, }; 1621 static int x1500_i2c2_pins[] = { 0x61, 0x60, }; 1622 static int x1500_i2s_data_tx_pins[] = { 0x24, }; 1623 static int x1500_i2s_data_rx_pins[] = { 0x23, }; 1624 static int x1500_i2s_clk_txrx_pins[] = { 0x21, 0x22, }; 1625 static int x1500_i2s_sysclk_pins[] = { 0x20, }; 1626 static int x1500_cim_pins[] = { 1627 0x08, 0x09, 0x0a, 0x0b, 1628 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 1629 }; 1630 static int x1500_pwm_pwm0_pins[] = { 0x59, }; 1631 static int x1500_pwm_pwm1_pins[] = { 0x5a, }; 1632 static int x1500_pwm_pwm2_pins[] = { 0x5b, }; 1633 static int x1500_pwm_pwm3_pins[] = { 0x26, }; 1634 static int x1500_pwm_pwm4_pins[] = { 0x58, }; 1635 1636 static int x1500_uart0_data_funcs[] = { 0, 0, }; 1637 static int x1500_uart0_hwflow_funcs[] = { 0, 0, }; 1638 static int x1500_uart1_data_a_funcs[] = { 2, 2, }; 1639 static int x1500_uart1_data_d_funcs[] = { 1, 1, }; 1640 static int x1500_uart1_hwflow_funcs[] = { 1, 1, }; 1641 static int x1500_uart2_data_a_funcs[] = { 2, 2, }; 1642 static int x1500_uart2_data_d_funcs[] = { 0, 0, }; 1643 static int x1500_mmc_1bit_funcs[] = { 1, 1, 1, }; 1644 static int x1500_mmc_4bit_funcs[] = { 1, 1, 1, }; 1645 static int x1500_i2c0_funcs[] = { 0, 0, }; 1646 static int x1500_i2c1_a_funcs[] = { 2, 2, }; 1647 static int x1500_i2c1_c_funcs[] = { 0, 0, }; 1648 static int x1500_i2c2_funcs[] = { 1, 1, }; 1649 static int x1500_i2s_data_tx_funcs[] = { 1, }; 1650 static int x1500_i2s_data_rx_funcs[] = { 1, }; 1651 static int x1500_i2s_clk_txrx_funcs[] = { 1, 1, }; 1652 static int x1500_i2s_sysclk_funcs[] = { 1, }; 1653 static int x1500_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; 1654 static int x1500_pwm_pwm0_funcs[] = { 0, }; 1655 static int x1500_pwm_pwm1_funcs[] = { 1, }; 1656 static int x1500_pwm_pwm2_funcs[] = { 1, }; 1657 static int x1500_pwm_pwm3_funcs[] = { 2, }; 1658 static int x1500_pwm_pwm4_funcs[] = { 0, }; 1659 1660 static const struct group_desc x1500_groups[] = { 1661 INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data), 1662 INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow), 1663 INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a), 1664 INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d), 1665 INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow), 1666 INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a), 1667 INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d), 1668 INGENIC_PIN_GROUP("sfc", x1000_sfc), 1669 INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit), 1670 INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit), 1671 INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0), 1672 INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a), 1673 INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c), 1674 INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2), 1675 INGENIC_PIN_GROUP("i2s-data-tx", x1500_i2s_data_tx), 1676 INGENIC_PIN_GROUP("i2s-data-rx", x1500_i2s_data_rx), 1677 INGENIC_PIN_GROUP("i2s-clk-txrx", x1500_i2s_clk_txrx), 1678 INGENIC_PIN_GROUP("i2s-sysclk", x1500_i2s_sysclk), 1679 INGENIC_PIN_GROUP("cim-data", x1500_cim), 1680 { "lcd-no-pins", }, 1681 INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0), 1682 INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1), 1683 INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2), 1684 INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3), 1685 INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4), 1686 }; 1687 1688 static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1689 static const char *x1500_uart1_groups[] = { 1690 "uart1-data-a", "uart1-data-d", "uart1-hwflow", 1691 }; 1692 static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; 1693 static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; 1694 static const char *x1500_i2c0_groups[] = { "i2c0-data", }; 1695 static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; 1696 static const char *x1500_i2c2_groups[] = { "i2c2-data", }; 1697 static const char *x1500_i2s_groups[] = { 1698 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk", 1699 }; 1700 static const char *x1500_cim_groups[] = { "cim-data", }; 1701 static const char *x1500_lcd_groups[] = { "lcd-no-pins", }; 1702 static const char *x1500_pwm0_groups[] = { "pwm0", }; 1703 static const char *x1500_pwm1_groups[] = { "pwm1", }; 1704 static const char *x1500_pwm2_groups[] = { "pwm2", }; 1705 static const char *x1500_pwm3_groups[] = { "pwm3", }; 1706 static const char *x1500_pwm4_groups[] = { "pwm4", }; 1707 1708 static const struct function_desc x1500_functions[] = { 1709 { "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), }, 1710 { "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), }, 1711 { "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), }, 1712 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), }, 1713 { "mmc", x1500_mmc_groups, ARRAY_SIZE(x1500_mmc_groups), }, 1714 { "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), }, 1715 { "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), }, 1716 { "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), }, 1717 { "i2s", x1500_i2s_groups, ARRAY_SIZE(x1500_i2s_groups), }, 1718 { "cim", x1500_cim_groups, ARRAY_SIZE(x1500_cim_groups), }, 1719 { "lcd", x1500_lcd_groups, ARRAY_SIZE(x1500_lcd_groups), }, 1720 { "pwm0", x1500_pwm0_groups, ARRAY_SIZE(x1500_pwm0_groups), }, 1721 { "pwm1", x1500_pwm1_groups, ARRAY_SIZE(x1500_pwm1_groups), }, 1722 { "pwm2", x1500_pwm2_groups, ARRAY_SIZE(x1500_pwm2_groups), }, 1723 { "pwm3", x1500_pwm3_groups, ARRAY_SIZE(x1500_pwm3_groups), }, 1724 { "pwm4", x1500_pwm4_groups, ARRAY_SIZE(x1500_pwm4_groups), }, 1725 }; 1726 1727 static const struct ingenic_chip_info x1500_chip_info = { 1728 .num_chips = 4, 1729 .reg_offset = 0x100, 1730 .version = ID_X1500, 1731 .groups = x1500_groups, 1732 .num_groups = ARRAY_SIZE(x1500_groups), 1733 .functions = x1500_functions, 1734 .num_functions = ARRAY_SIZE(x1500_functions), 1735 .pull_ups = x1000_pull_ups, 1736 .pull_downs = x1000_pull_downs, 1737 }; 1738 1739 static const u32 x1830_pull_ups[4] = { 1740 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc, 1741 }; 1742 1743 static const u32 x1830_pull_downs[4] = { 1744 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc, 1745 }; 1746 1747 static int x1830_uart0_data_pins[] = { 0x33, 0x36, }; 1748 static int x1830_uart0_hwflow_pins[] = { 0x34, 0x35, }; 1749 static int x1830_uart1_data_pins[] = { 0x38, 0x37, }; 1750 static int x1830_sfc_pins[] = { 0x17, 0x18, 0x1a, 0x19, 0x1b, 0x1c, }; 1751 static int x1830_ssi0_dt_pins[] = { 0x4c, }; 1752 static int x1830_ssi0_dr_pins[] = { 0x4b, }; 1753 static int x1830_ssi0_clk_pins[] = { 0x4f, }; 1754 static int x1830_ssi0_gpc_pins[] = { 0x4d, }; 1755 static int x1830_ssi0_ce0_pins[] = { 0x50, }; 1756 static int x1830_ssi0_ce1_pins[] = { 0x4e, }; 1757 static int x1830_ssi1_dt_c_pins[] = { 0x53, }; 1758 static int x1830_ssi1_dr_c_pins[] = { 0x54, }; 1759 static int x1830_ssi1_clk_c_pins[] = { 0x57, }; 1760 static int x1830_ssi1_gpc_c_pins[] = { 0x55, }; 1761 static int x1830_ssi1_ce0_c_pins[] = { 0x58, }; 1762 static int x1830_ssi1_ce1_c_pins[] = { 0x56, }; 1763 static int x1830_ssi1_dt_d_pins[] = { 0x62, }; 1764 static int x1830_ssi1_dr_d_pins[] = { 0x63, }; 1765 static int x1830_ssi1_clk_d_pins[] = { 0x66, }; 1766 static int x1830_ssi1_gpc_d_pins[] = { 0x64, }; 1767 static int x1830_ssi1_ce0_d_pins[] = { 0x67, }; 1768 static int x1830_ssi1_ce1_d_pins[] = { 0x65, }; 1769 static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, }; 1770 static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, }; 1771 static int x1830_mmc1_1bit_pins[] = { 0x42, 0x43, 0x44, }; 1772 static int x1830_mmc1_4bit_pins[] = { 0x45, 0x46, 0x47, }; 1773 static int x1830_i2c0_pins[] = { 0x0c, 0x0d, }; 1774 static int x1830_i2c1_pins[] = { 0x39, 0x3a, }; 1775 static int x1830_i2c2_pins[] = { 0x5b, 0x5c, }; 1776 static int x1830_i2s_data_tx_pins[] = { 0x53, }; 1777 static int x1830_i2s_data_rx_pins[] = { 0x54, }; 1778 static int x1830_i2s_clk_txrx_pins[] = { 0x58, 0x52, }; 1779 static int x1830_i2s_clk_rx_pins[] = { 0x56, 0x55, }; 1780 static int x1830_i2s_sysclk_pins[] = { 0x57, }; 1781 static int x1830_lcd_rgb_18bit_pins[] = { 1782 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 1783 0x68, 0x69, 0x6c, 0x6d, 0x6e, 0x6f, 1784 0x70, 0x71, 0x72, 0x73, 0x76, 0x77, 1785 0x78, 0x79, 0x7a, 0x7b, 1786 }; 1787 static int x1830_lcd_slcd_8bit_pins[] = { 1788 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x6c, 0x6d, 1789 0x69, 0x72, 0x73, 0x7b, 0x7a, 1790 }; 1791 static int x1830_lcd_slcd_16bit_pins[] = { 1792 0x6e, 0x6f, 0x70, 0x71, 0x76, 0x77, 0x78, 0x79, 1793 }; 1794 static int x1830_pwm_pwm0_b_pins[] = { 0x31, }; 1795 static int x1830_pwm_pwm0_c_pins[] = { 0x4b, }; 1796 static int x1830_pwm_pwm1_b_pins[] = { 0x32, }; 1797 static int x1830_pwm_pwm1_c_pins[] = { 0x4c, }; 1798 static int x1830_pwm_pwm2_c_8_pins[] = { 0x48, }; 1799 static int x1830_pwm_pwm2_c_13_pins[] = { 0x4d, }; 1800 static int x1830_pwm_pwm3_c_9_pins[] = { 0x49, }; 1801 static int x1830_pwm_pwm3_c_14_pins[] = { 0x4e, }; 1802 static int x1830_pwm_pwm4_c_15_pins[] = { 0x4f, }; 1803 static int x1830_pwm_pwm4_c_25_pins[] = { 0x59, }; 1804 static int x1830_pwm_pwm5_c_16_pins[] = { 0x50, }; 1805 static int x1830_pwm_pwm5_c_26_pins[] = { 0x5a, }; 1806 static int x1830_pwm_pwm6_c_17_pins[] = { 0x51, }; 1807 static int x1830_pwm_pwm6_c_27_pins[] = { 0x5b, }; 1808 static int x1830_pwm_pwm7_c_18_pins[] = { 0x52, }; 1809 static int x1830_pwm_pwm7_c_28_pins[] = { 0x5c, }; 1810 static int x1830_mac_pins[] = { 1811 0x29, 0x30, 0x2f, 0x28, 0x2e, 0x2d, 0x2a, 0x2b, 0x26, 0x27, 1812 }; 1813 1814 static int x1830_uart0_data_funcs[] = { 0, 0, }; 1815 static int x1830_uart0_hwflow_funcs[] = { 0, 0, }; 1816 static int x1830_uart1_data_funcs[] = { 0, 0, }; 1817 static int x1830_sfc_funcs[] = { 1, 1, 1, 1, 1, 1, }; 1818 static int x1830_ssi0_dt_funcs[] = { 0, }; 1819 static int x1830_ssi0_dr_funcs[] = { 0, }; 1820 static int x1830_ssi0_clk_funcs[] = { 0, }; 1821 static int x1830_ssi0_gpc_funcs[] = { 0, }; 1822 static int x1830_ssi0_ce0_funcs[] = { 0, }; 1823 static int x1830_ssi0_ce1_funcs[] = { 0, }; 1824 static int x1830_ssi1_dt_c_funcs[] = { 1, }; 1825 static int x1830_ssi1_dr_c_funcs[] = { 1, }; 1826 static int x1830_ssi1_clk_c_funcs[] = { 1, }; 1827 static int x1830_ssi1_gpc_c_funcs[] = { 1, }; 1828 static int x1830_ssi1_ce0_c_funcs[] = { 1, }; 1829 static int x1830_ssi1_ce1_c_funcs[] = { 1, }; 1830 static int x1830_ssi1_dt_d_funcs[] = { 2, }; 1831 static int x1830_ssi1_dr_d_funcs[] = { 2, }; 1832 static int x1830_ssi1_clk_d_funcs[] = { 2, }; 1833 static int x1830_ssi1_gpc_d_funcs[] = { 2, }; 1834 static int x1830_ssi1_ce0_d_funcs[] = { 2, }; 1835 static int x1830_ssi1_ce1_d_funcs[] = { 2, }; 1836 static int x1830_mmc0_1bit_funcs[] = { 0, 0, 0, }; 1837 static int x1830_mmc0_4bit_funcs[] = { 0, 0, 0, }; 1838 static int x1830_mmc1_1bit_funcs[] = { 0, 0, 0, }; 1839 static int x1830_mmc1_4bit_funcs[] = { 0, 0, 0, }; 1840 static int x1830_i2c0_funcs[] = { 1, 1, }; 1841 static int x1830_i2c1_funcs[] = { 0, 0, }; 1842 static int x1830_i2c2_funcs[] = { 1, 1, }; 1843 static int x1830_i2s_data_tx_funcs[] = { 0, }; 1844 static int x1830_i2s_data_rx_funcs[] = { 0, }; 1845 static int x1830_i2s_clk_txrx_funcs[] = { 0, 0, }; 1846 static int x1830_i2s_clk_rx_funcs[] = { 0, 0, }; 1847 static int x1830_i2s_sysclk_funcs[] = { 0, }; 1848 static int x1830_lcd_rgb_18bit_funcs[] = { 1849 0, 0, 0, 0, 0, 0, 1850 0, 0, 0, 0, 0, 0, 1851 0, 0, 0, 0, 0, 0, 1852 0, 0, 0, 0, 1853 }; 1854 static int x1830_lcd_slcd_8bit_funcs[] = { 1855 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1856 }; 1857 static int x1830_lcd_slcd_16bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, }; 1858 static int x1830_pwm_pwm0_b_funcs[] = { 0, }; 1859 static int x1830_pwm_pwm0_c_funcs[] = { 1, }; 1860 static int x1830_pwm_pwm1_b_funcs[] = { 0, }; 1861 static int x1830_pwm_pwm1_c_funcs[] = { 1, }; 1862 static int x1830_pwm_pwm2_c_8_funcs[] = { 0, }; 1863 static int x1830_pwm_pwm2_c_13_funcs[] = { 1, }; 1864 static int x1830_pwm_pwm3_c_9_funcs[] = { 0, }; 1865 static int x1830_pwm_pwm3_c_14_funcs[] = { 1, }; 1866 static int x1830_pwm_pwm4_c_15_funcs[] = { 1, }; 1867 static int x1830_pwm_pwm4_c_25_funcs[] = { 0, }; 1868 static int x1830_pwm_pwm5_c_16_funcs[] = { 1, }; 1869 static int x1830_pwm_pwm5_c_26_funcs[] = { 0, }; 1870 static int x1830_pwm_pwm6_c_17_funcs[] = { 1, }; 1871 static int x1830_pwm_pwm6_c_27_funcs[] = { 0, }; 1872 static int x1830_pwm_pwm7_c_18_funcs[] = { 1, }; 1873 static int x1830_pwm_pwm7_c_28_funcs[] = { 0, }; 1874 static int x1830_mac_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 1875 1876 static const struct group_desc x1830_groups[] = { 1877 INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data), 1878 INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow), 1879 INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data), 1880 INGENIC_PIN_GROUP("sfc", x1830_sfc), 1881 INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt), 1882 INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr), 1883 INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk), 1884 INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc), 1885 INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0), 1886 INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1), 1887 INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c), 1888 INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c), 1889 INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c), 1890 INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c), 1891 INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c), 1892 INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c), 1893 INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d), 1894 INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d), 1895 INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d), 1896 INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d), 1897 INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d), 1898 INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d), 1899 INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit), 1900 INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit), 1901 INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit), 1902 INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit), 1903 INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0), 1904 INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1), 1905 INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2), 1906 INGENIC_PIN_GROUP("i2s-data-tx", x1830_i2s_data_tx), 1907 INGENIC_PIN_GROUP("i2s-data-rx", x1830_i2s_data_rx), 1908 INGENIC_PIN_GROUP("i2s-clk-txrx", x1830_i2s_clk_txrx), 1909 INGENIC_PIN_GROUP("i2s-clk-rx", x1830_i2s_clk_rx), 1910 INGENIC_PIN_GROUP("i2s-sysclk", x1830_i2s_sysclk), 1911 INGENIC_PIN_GROUP("lcd-rgb-18bit", x1830_lcd_rgb_18bit), 1912 INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit), 1913 INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit), 1914 { "lcd-no-pins", }, 1915 INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b), 1916 INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c), 1917 INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b), 1918 INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c), 1919 INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8), 1920 INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13), 1921 INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9), 1922 INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14), 1923 INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15), 1924 INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25), 1925 INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16), 1926 INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26), 1927 INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17), 1928 INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27), 1929 INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18), 1930 INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28), 1931 INGENIC_PIN_GROUP("mac", x1830_mac), 1932 }; 1933 1934 static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1935 static const char *x1830_uart1_groups[] = { "uart1-data", }; 1936 static const char *x1830_sfc_groups[] = { "sfc", }; 1937 static const char *x1830_ssi0_groups[] = { 1938 "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1", 1939 }; 1940 static const char *x1830_ssi1_groups[] = { 1941 "ssi1-dt-c", "ssi1-dt-d", 1942 "ssi1-dr-c", "ssi1-dr-d", 1943 "ssi1-clk-c", "ssi1-clk-d", 1944 "ssi1-gpc-c", "ssi1-gpc-d", 1945 "ssi1-ce0-c", "ssi1-ce0-d", 1946 "ssi1-ce1-c", "ssi1-ce1-d", 1947 }; 1948 static const char *x1830_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 1949 static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 1950 static const char *x1830_i2c0_groups[] = { "i2c0-data", }; 1951 static const char *x1830_i2c1_groups[] = { "i2c1-data", }; 1952 static const char *x1830_i2c2_groups[] = { "i2c2-data", }; 1953 static const char *x1830_i2s_groups[] = { 1954 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk", 1955 }; 1956 static const char *x1830_lcd_groups[] = { 1957 "lcd-rgb-18bit", "lcd-slcd-8bit", "lcd-slcd-16bit", "lcd-no-pins", 1958 }; 1959 static const char *x1830_pwm0_groups[] = { "pwm0-b", "pwm0-c", }; 1960 static const char *x1830_pwm1_groups[] = { "pwm1-b", "pwm1-c", }; 1961 static const char *x1830_pwm2_groups[] = { "pwm2-c-8", "pwm2-c-13", }; 1962 static const char *x1830_pwm3_groups[] = { "pwm3-c-9", "pwm3-c-14", }; 1963 static const char *x1830_pwm4_groups[] = { "pwm4-c-15", "pwm4-c-25", }; 1964 static const char *x1830_pwm5_groups[] = { "pwm5-c-16", "pwm5-c-26", }; 1965 static const char *x1830_pwm6_groups[] = { "pwm6-c-17", "pwm6-c-27", }; 1966 static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", }; 1967 static const char *x1830_mac_groups[] = { "mac", }; 1968 1969 static const struct function_desc x1830_functions[] = { 1970 { "uart0", x1830_uart0_groups, ARRAY_SIZE(x1830_uart0_groups), }, 1971 { "uart1", x1830_uart1_groups, ARRAY_SIZE(x1830_uart1_groups), }, 1972 { "sfc", x1830_sfc_groups, ARRAY_SIZE(x1830_sfc_groups), }, 1973 { "ssi0", x1830_ssi0_groups, ARRAY_SIZE(x1830_ssi0_groups), }, 1974 { "ssi1", x1830_ssi1_groups, ARRAY_SIZE(x1830_ssi1_groups), }, 1975 { "mmc0", x1830_mmc0_groups, ARRAY_SIZE(x1830_mmc0_groups), }, 1976 { "mmc1", x1830_mmc1_groups, ARRAY_SIZE(x1830_mmc1_groups), }, 1977 { "i2c0", x1830_i2c0_groups, ARRAY_SIZE(x1830_i2c0_groups), }, 1978 { "i2c1", x1830_i2c1_groups, ARRAY_SIZE(x1830_i2c1_groups), }, 1979 { "i2c2", x1830_i2c2_groups, ARRAY_SIZE(x1830_i2c2_groups), }, 1980 { "i2s", x1830_i2s_groups, ARRAY_SIZE(x1830_i2s_groups), }, 1981 { "lcd", x1830_lcd_groups, ARRAY_SIZE(x1830_lcd_groups), }, 1982 { "pwm0", x1830_pwm0_groups, ARRAY_SIZE(x1830_pwm0_groups), }, 1983 { "pwm1", x1830_pwm1_groups, ARRAY_SIZE(x1830_pwm1_groups), }, 1984 { "pwm2", x1830_pwm2_groups, ARRAY_SIZE(x1830_pwm2_groups), }, 1985 { "pwm3", x1830_pwm3_groups, ARRAY_SIZE(x1830_pwm3_groups), }, 1986 { "pwm4", x1830_pwm4_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 1987 { "pwm5", x1830_pwm5_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 1988 { "pwm6", x1830_pwm6_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 1989 { "pwm7", x1830_pwm7_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 1990 { "mac", x1830_mac_groups, ARRAY_SIZE(x1830_mac_groups), }, 1991 }; 1992 1993 static const struct ingenic_chip_info x1830_chip_info = { 1994 .num_chips = 4, 1995 .reg_offset = 0x1000, 1996 .version = ID_X1830, 1997 .groups = x1830_groups, 1998 .num_groups = ARRAY_SIZE(x1830_groups), 1999 .functions = x1830_functions, 2000 .num_functions = ARRAY_SIZE(x1830_functions), 2001 .pull_ups = x1830_pull_ups, 2002 .pull_downs = x1830_pull_downs, 2003 }; 2004 2005 static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg) 2006 { 2007 unsigned int val; 2008 2009 regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val); 2010 2011 return (u32) val; 2012 } 2013 2014 static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc, 2015 u8 reg, u8 offset, bool set) 2016 { 2017 if (set) 2018 reg = REG_SET(reg); 2019 else 2020 reg = REG_CLEAR(reg); 2021 2022 regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset)); 2023 } 2024 2025 static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc, 2026 u8 reg, u8 offset, bool set) 2027 { 2028 if (set) 2029 reg = REG_SET(reg); 2030 else 2031 reg = REG_CLEAR(reg); 2032 2033 regmap_write(jzgc->jzpc->map, REG_PZ_BASE( 2034 jzgc->jzpc->info->reg_offset) + reg, BIT(offset)); 2035 } 2036 2037 static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc) 2038 { 2039 regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD( 2040 jzgc->jzpc->info->reg_offset), 2041 jzgc->gc.base / PINS_PER_GPIO_CHIP); 2042 } 2043 2044 static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc, 2045 u8 offset) 2046 { 2047 unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN); 2048 2049 return !!(val & BIT(offset)); 2050 } 2051 2052 static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc, 2053 u8 offset, int value) 2054 { 2055 if (jzgc->jzpc->info->version >= ID_JZ4760) 2056 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_PAT0, offset, !!value); 2057 else 2058 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value); 2059 } 2060 2061 static void irq_set_type(struct ingenic_gpio_chip *jzgc, 2062 u8 offset, unsigned int type) 2063 { 2064 u8 reg1, reg2; 2065 bool val1, val2; 2066 2067 switch (type) { 2068 case IRQ_TYPE_EDGE_RISING: 2069 val1 = val2 = true; 2070 break; 2071 case IRQ_TYPE_EDGE_FALLING: 2072 val1 = false; 2073 val2 = true; 2074 break; 2075 case IRQ_TYPE_LEVEL_HIGH: 2076 val1 = true; 2077 val2 = false; 2078 break; 2079 case IRQ_TYPE_LEVEL_LOW: 2080 default: 2081 val1 = val2 = false; 2082 break; 2083 } 2084 2085 if (jzgc->jzpc->info->version >= ID_JZ4760) { 2086 reg1 = JZ4760_GPIO_PAT1; 2087 reg2 = JZ4760_GPIO_PAT0; 2088 } else { 2089 reg1 = JZ4740_GPIO_TRIG; 2090 reg2 = JZ4740_GPIO_DIR; 2091 } 2092 2093 if (jzgc->jzpc->info->version >= ID_X1000) { 2094 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1); 2095 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2); 2096 ingenic_gpio_shadow_set_bit_load(jzgc); 2097 } else { 2098 ingenic_gpio_set_bit(jzgc, reg2, offset, val1); 2099 ingenic_gpio_set_bit(jzgc, reg1, offset, val2); 2100 } 2101 } 2102 2103 static void ingenic_gpio_irq_mask(struct irq_data *irqd) 2104 { 2105 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 2106 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 2107 2108 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true); 2109 } 2110 2111 static void ingenic_gpio_irq_unmask(struct irq_data *irqd) 2112 { 2113 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 2114 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 2115 2116 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false); 2117 } 2118 2119 static void ingenic_gpio_irq_enable(struct irq_data *irqd) 2120 { 2121 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 2122 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 2123 int irq = irqd->hwirq; 2124 2125 if (jzgc->jzpc->info->version >= ID_JZ4760) 2126 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, true); 2127 else 2128 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true); 2129 2130 ingenic_gpio_irq_unmask(irqd); 2131 } 2132 2133 static void ingenic_gpio_irq_disable(struct irq_data *irqd) 2134 { 2135 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 2136 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 2137 int irq = irqd->hwirq; 2138 2139 ingenic_gpio_irq_mask(irqd); 2140 2141 if (jzgc->jzpc->info->version >= ID_JZ4760) 2142 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, false); 2143 else 2144 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false); 2145 } 2146 2147 static void ingenic_gpio_irq_ack(struct irq_data *irqd) 2148 { 2149 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 2150 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 2151 int irq = irqd->hwirq; 2152 bool high; 2153 2154 if (irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) { 2155 /* 2156 * Switch to an interrupt for the opposite edge to the one that 2157 * triggered the interrupt being ACKed. 2158 */ 2159 high = ingenic_gpio_get_value(jzgc, irq); 2160 if (high) 2161 irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_LOW); 2162 else 2163 irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_HIGH); 2164 } 2165 2166 if (jzgc->jzpc->info->version >= ID_JZ4760) 2167 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_FLAG, irq, false); 2168 else 2169 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true); 2170 } 2171 2172 static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) 2173 { 2174 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 2175 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 2176 2177 switch (type) { 2178 case IRQ_TYPE_EDGE_BOTH: 2179 case IRQ_TYPE_EDGE_RISING: 2180 case IRQ_TYPE_EDGE_FALLING: 2181 irq_set_handler_locked(irqd, handle_edge_irq); 2182 break; 2183 case IRQ_TYPE_LEVEL_HIGH: 2184 case IRQ_TYPE_LEVEL_LOW: 2185 irq_set_handler_locked(irqd, handle_level_irq); 2186 break; 2187 default: 2188 irq_set_handler_locked(irqd, handle_bad_irq); 2189 } 2190 2191 if (type == IRQ_TYPE_EDGE_BOTH) { 2192 /* 2193 * The hardware does not support interrupts on both edges. The 2194 * best we can do is to set up a single-edge interrupt and then 2195 * switch to the opposing edge when ACKing the interrupt. 2196 */ 2197 bool high = ingenic_gpio_get_value(jzgc, irqd->hwirq); 2198 2199 type = high ? IRQ_TYPE_LEVEL_LOW : IRQ_TYPE_LEVEL_HIGH; 2200 } 2201 2202 irq_set_type(jzgc, irqd->hwirq, type); 2203 return 0; 2204 } 2205 2206 static int ingenic_gpio_irq_set_wake(struct irq_data *irqd, unsigned int on) 2207 { 2208 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 2209 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 2210 2211 return irq_set_irq_wake(jzgc->irq, on); 2212 } 2213 2214 static void ingenic_gpio_irq_handler(struct irq_desc *desc) 2215 { 2216 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 2217 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 2218 struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data); 2219 unsigned long flag, i; 2220 2221 chained_irq_enter(irq_chip, desc); 2222 2223 if (jzgc->jzpc->info->version >= ID_JZ4760) 2224 flag = ingenic_gpio_read_reg(jzgc, JZ4760_GPIO_FLAG); 2225 else 2226 flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG); 2227 2228 for_each_set_bit(i, &flag, 32) 2229 generic_handle_irq(irq_linear_revmap(gc->irq.domain, i)); 2230 chained_irq_exit(irq_chip, desc); 2231 } 2232 2233 static void ingenic_gpio_set(struct gpio_chip *gc, 2234 unsigned int offset, int value) 2235 { 2236 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 2237 2238 ingenic_gpio_set_value(jzgc, offset, value); 2239 } 2240 2241 static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset) 2242 { 2243 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 2244 2245 return (int) ingenic_gpio_get_value(jzgc, offset); 2246 } 2247 2248 static int ingenic_gpio_direction_input(struct gpio_chip *gc, 2249 unsigned int offset) 2250 { 2251 return pinctrl_gpio_direction_input(gc->base + offset); 2252 } 2253 2254 static int ingenic_gpio_direction_output(struct gpio_chip *gc, 2255 unsigned int offset, int value) 2256 { 2257 ingenic_gpio_set(gc, offset, value); 2258 return pinctrl_gpio_direction_output(gc->base + offset); 2259 } 2260 2261 static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc, 2262 unsigned int pin, u8 reg, bool set) 2263 { 2264 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 2265 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 2266 2267 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 2268 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); 2269 } 2270 2271 static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc, 2272 unsigned int pin, u8 reg, bool set) 2273 { 2274 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 2275 2276 regmap_write(jzpc->map, REG_PZ_BASE(jzpc->info->reg_offset) + 2277 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); 2278 } 2279 2280 static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc, 2281 unsigned int pin) 2282 { 2283 regmap_write(jzpc->map, REG_PZ_GID2LD(jzpc->info->reg_offset), 2284 pin / PINS_PER_GPIO_CHIP); 2285 } 2286 2287 static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc, 2288 unsigned int pin, u8 reg) 2289 { 2290 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 2291 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 2292 unsigned int val; 2293 2294 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + reg, &val); 2295 2296 return val & BIT(idx); 2297 } 2298 2299 static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 2300 { 2301 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 2302 struct ingenic_pinctrl *jzpc = jzgc->jzpc; 2303 unsigned int pin = gc->base + offset; 2304 2305 if (jzpc->info->version >= ID_JZ4760) { 2306 if (ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_INT) || 2307 ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PAT1)) 2308 return GPIO_LINE_DIRECTION_IN; 2309 return GPIO_LINE_DIRECTION_OUT; 2310 } 2311 2312 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT)) 2313 return GPIO_LINE_DIRECTION_IN; 2314 2315 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_DIR)) 2316 return GPIO_LINE_DIRECTION_OUT; 2317 2318 return GPIO_LINE_DIRECTION_IN; 2319 } 2320 2321 static const struct pinctrl_ops ingenic_pctlops = { 2322 .get_groups_count = pinctrl_generic_get_group_count, 2323 .get_group_name = pinctrl_generic_get_group_name, 2324 .get_group_pins = pinctrl_generic_get_group_pins, 2325 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 2326 .dt_free_map = pinconf_generic_dt_free_map, 2327 }; 2328 2329 static int ingenic_gpio_irq_request(struct irq_data *data) 2330 { 2331 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 2332 int ret; 2333 2334 ret = ingenic_gpio_direction_input(gpio_chip, data->hwirq); 2335 if (ret) 2336 return ret; 2337 2338 return gpiochip_reqres_irq(gpio_chip, data->hwirq); 2339 } 2340 2341 static void ingenic_gpio_irq_release(struct irq_data *data) 2342 { 2343 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 2344 2345 return gpiochip_relres_irq(gpio_chip, data->hwirq); 2346 } 2347 2348 static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc, 2349 int pin, int func) 2350 { 2351 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 2352 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 2353 2354 dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n", 2355 'A' + offt, idx, func); 2356 2357 if (jzpc->info->version >= ID_X1000) { 2358 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); 2359 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false); 2360 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2); 2361 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1); 2362 ingenic_shadow_config_pin_load(jzpc, pin); 2363 } else if (jzpc->info->version >= ID_JZ4760) { 2364 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); 2365 ingenic_config_pin(jzpc, pin, GPIO_MSK, false); 2366 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2); 2367 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1); 2368 } else { 2369 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true); 2370 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2); 2371 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func > 0); 2372 } 2373 2374 return 0; 2375 } 2376 2377 static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev, 2378 unsigned int selector, unsigned int group) 2379 { 2380 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 2381 struct function_desc *func; 2382 struct group_desc *grp; 2383 unsigned int i; 2384 2385 func = pinmux_generic_get_function(pctldev, selector); 2386 if (!func) 2387 return -EINVAL; 2388 2389 grp = pinctrl_generic_get_group(pctldev, group); 2390 if (!grp) 2391 return -EINVAL; 2392 2393 dev_dbg(pctldev->dev, "enable function %s group %s\n", 2394 func->name, grp->name); 2395 2396 for (i = 0; i < grp->num_pins; i++) { 2397 int *pin_modes = grp->data; 2398 2399 ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]); 2400 } 2401 2402 return 0; 2403 } 2404 2405 static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, 2406 struct pinctrl_gpio_range *range, 2407 unsigned int pin, bool input) 2408 { 2409 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 2410 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 2411 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 2412 2413 dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n", 2414 'A' + offt, idx, input ? "in" : "out"); 2415 2416 if (jzpc->info->version >= ID_X1000) { 2417 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); 2418 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true); 2419 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input); 2420 ingenic_shadow_config_pin_load(jzpc, pin); 2421 } else if (jzpc->info->version >= ID_JZ4760) { 2422 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); 2423 ingenic_config_pin(jzpc, pin, GPIO_MSK, true); 2424 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input); 2425 } else { 2426 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false); 2427 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input); 2428 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false); 2429 } 2430 2431 return 0; 2432 } 2433 2434 static const struct pinmux_ops ingenic_pmxops = { 2435 .get_functions_count = pinmux_generic_get_function_count, 2436 .get_function_name = pinmux_generic_get_function_name, 2437 .get_function_groups = pinmux_generic_get_function_groups, 2438 .set_mux = ingenic_pinmux_set_mux, 2439 .gpio_set_direction = ingenic_pinmux_gpio_set_direction, 2440 }; 2441 2442 static int ingenic_pinconf_get(struct pinctrl_dev *pctldev, 2443 unsigned int pin, unsigned long *config) 2444 { 2445 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 2446 enum pin_config_param param = pinconf_to_config_param(*config); 2447 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 2448 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 2449 bool pull; 2450 2451 if (jzpc->info->version >= ID_JZ4760) 2452 pull = !ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PEN); 2453 else 2454 pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS); 2455 2456 switch (param) { 2457 case PIN_CONFIG_BIAS_DISABLE: 2458 if (pull) 2459 return -EINVAL; 2460 break; 2461 2462 case PIN_CONFIG_BIAS_PULL_UP: 2463 if (!pull || !(jzpc->info->pull_ups[offt] & BIT(idx))) 2464 return -EINVAL; 2465 break; 2466 2467 case PIN_CONFIG_BIAS_PULL_DOWN: 2468 if (!pull || !(jzpc->info->pull_downs[offt] & BIT(idx))) 2469 return -EINVAL; 2470 break; 2471 2472 default: 2473 return -ENOTSUPP; 2474 } 2475 2476 *config = pinconf_to_config_packed(param, 1); 2477 return 0; 2478 } 2479 2480 static void ingenic_set_bias(struct ingenic_pinctrl *jzpc, 2481 unsigned int pin, unsigned int bias) 2482 { 2483 if (jzpc->info->version >= ID_X1830) { 2484 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 2485 unsigned int half = PINS_PER_GPIO_CHIP / 2; 2486 unsigned int idxh = pin % half * 2; 2487 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 2488 2489 if (idx < half) { 2490 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 2491 REG_CLEAR(X1830_GPIO_PEL), 3 << idxh); 2492 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 2493 REG_SET(X1830_GPIO_PEL), bias << idxh); 2494 } else { 2495 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 2496 REG_CLEAR(X1830_GPIO_PEH), 3 << idxh); 2497 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 2498 REG_SET(X1830_GPIO_PEH), bias << idxh); 2499 } 2500 2501 } else if (jzpc->info->version >= ID_JZ4760) { 2502 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PEN, !bias); 2503 } else { 2504 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !bias); 2505 } 2506 } 2507 2508 static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc, 2509 unsigned int pin, bool high) 2510 { 2511 if (jzpc->info->version >= ID_JZ4760) 2512 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, high); 2513 else 2514 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DATA, high); 2515 } 2516 2517 static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 2518 unsigned long *configs, unsigned int num_configs) 2519 { 2520 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 2521 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 2522 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 2523 unsigned int cfg, arg; 2524 int ret; 2525 2526 for (cfg = 0; cfg < num_configs; cfg++) { 2527 switch (pinconf_to_config_param(configs[cfg])) { 2528 case PIN_CONFIG_BIAS_DISABLE: 2529 case PIN_CONFIG_BIAS_PULL_UP: 2530 case PIN_CONFIG_BIAS_PULL_DOWN: 2531 case PIN_CONFIG_OUTPUT: 2532 continue; 2533 default: 2534 return -ENOTSUPP; 2535 } 2536 } 2537 2538 for (cfg = 0; cfg < num_configs; cfg++) { 2539 arg = pinconf_to_config_argument(configs[cfg]); 2540 2541 switch (pinconf_to_config_param(configs[cfg])) { 2542 case PIN_CONFIG_BIAS_DISABLE: 2543 dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n", 2544 'A' + offt, idx); 2545 ingenic_set_bias(jzpc, pin, GPIO_PULL_DIS); 2546 break; 2547 2548 case PIN_CONFIG_BIAS_PULL_UP: 2549 if (!(jzpc->info->pull_ups[offt] & BIT(idx))) 2550 return -EINVAL; 2551 dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n", 2552 'A' + offt, idx); 2553 ingenic_set_bias(jzpc, pin, GPIO_PULL_UP); 2554 break; 2555 2556 case PIN_CONFIG_BIAS_PULL_DOWN: 2557 if (!(jzpc->info->pull_downs[offt] & BIT(idx))) 2558 return -EINVAL; 2559 dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n", 2560 'A' + offt, idx); 2561 ingenic_set_bias(jzpc, pin, GPIO_PULL_DOWN); 2562 break; 2563 2564 case PIN_CONFIG_OUTPUT: 2565 ret = pinctrl_gpio_direction_output(pin); 2566 if (ret) 2567 return ret; 2568 2569 ingenic_set_output_level(jzpc, pin, arg); 2570 break; 2571 2572 default: 2573 /* unreachable */ 2574 break; 2575 } 2576 } 2577 2578 return 0; 2579 } 2580 2581 static int ingenic_pinconf_group_get(struct pinctrl_dev *pctldev, 2582 unsigned int group, unsigned long *config) 2583 { 2584 const unsigned int *pins; 2585 unsigned int i, npins, old = 0; 2586 int ret; 2587 2588 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 2589 if (ret) 2590 return ret; 2591 2592 for (i = 0; i < npins; i++) { 2593 if (ingenic_pinconf_get(pctldev, pins[i], config)) 2594 return -ENOTSUPP; 2595 2596 /* configs do not match between two pins */ 2597 if (i && (old != *config)) 2598 return -ENOTSUPP; 2599 2600 old = *config; 2601 } 2602 2603 return 0; 2604 } 2605 2606 static int ingenic_pinconf_group_set(struct pinctrl_dev *pctldev, 2607 unsigned int group, unsigned long *configs, 2608 unsigned int num_configs) 2609 { 2610 const unsigned int *pins; 2611 unsigned int i, npins; 2612 int ret; 2613 2614 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 2615 if (ret) 2616 return ret; 2617 2618 for (i = 0; i < npins; i++) { 2619 ret = ingenic_pinconf_set(pctldev, 2620 pins[i], configs, num_configs); 2621 if (ret) 2622 return ret; 2623 } 2624 2625 return 0; 2626 } 2627 2628 static const struct pinconf_ops ingenic_confops = { 2629 .is_generic = true, 2630 .pin_config_get = ingenic_pinconf_get, 2631 .pin_config_set = ingenic_pinconf_set, 2632 .pin_config_group_get = ingenic_pinconf_group_get, 2633 .pin_config_group_set = ingenic_pinconf_group_set, 2634 }; 2635 2636 static const struct regmap_config ingenic_pinctrl_regmap_config = { 2637 .reg_bits = 32, 2638 .val_bits = 32, 2639 .reg_stride = 4, 2640 }; 2641 2642 static const struct of_device_id ingenic_gpio_of_match[] __initconst = { 2643 { .compatible = "ingenic,jz4740-gpio", }, 2644 { .compatible = "ingenic,jz4725b-gpio", }, 2645 { .compatible = "ingenic,jz4760-gpio", }, 2646 { .compatible = "ingenic,jz4770-gpio", }, 2647 { .compatible = "ingenic,jz4780-gpio", }, 2648 { .compatible = "ingenic,x1000-gpio", }, 2649 { .compatible = "ingenic,x1830-gpio", }, 2650 {}, 2651 }; 2652 2653 static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc, 2654 struct device_node *node) 2655 { 2656 struct ingenic_gpio_chip *jzgc; 2657 struct device *dev = jzpc->dev; 2658 struct gpio_irq_chip *girq; 2659 unsigned int bank; 2660 int err; 2661 2662 err = of_property_read_u32(node, "reg", &bank); 2663 if (err) { 2664 dev_err(dev, "Cannot read \"reg\" property: %i\n", err); 2665 return err; 2666 } 2667 2668 jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL); 2669 if (!jzgc) 2670 return -ENOMEM; 2671 2672 jzgc->jzpc = jzpc; 2673 jzgc->reg_base = bank * jzpc->info->reg_offset; 2674 2675 jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank); 2676 if (!jzgc->gc.label) 2677 return -ENOMEM; 2678 2679 /* DO NOT EXPAND THIS: FOR BACKWARD GPIO NUMBERSPACE COMPATIBIBILITY 2680 * ONLY: WORK TO TRANSITION CONSUMERS TO USE THE GPIO DESCRIPTOR API IN 2681 * <linux/gpio/consumer.h> INSTEAD. 2682 */ 2683 jzgc->gc.base = bank * 32; 2684 2685 jzgc->gc.ngpio = 32; 2686 jzgc->gc.parent = dev; 2687 jzgc->gc.of_node = node; 2688 jzgc->gc.owner = THIS_MODULE; 2689 2690 jzgc->gc.set = ingenic_gpio_set; 2691 jzgc->gc.get = ingenic_gpio_get; 2692 jzgc->gc.direction_input = ingenic_gpio_direction_input; 2693 jzgc->gc.direction_output = ingenic_gpio_direction_output; 2694 jzgc->gc.get_direction = ingenic_gpio_get_direction; 2695 jzgc->gc.request = gpiochip_generic_request; 2696 jzgc->gc.free = gpiochip_generic_free; 2697 2698 jzgc->irq = irq_of_parse_and_map(node, 0); 2699 if (!jzgc->irq) 2700 return -EINVAL; 2701 2702 jzgc->irq_chip.name = jzgc->gc.label; 2703 jzgc->irq_chip.irq_enable = ingenic_gpio_irq_enable; 2704 jzgc->irq_chip.irq_disable = ingenic_gpio_irq_disable; 2705 jzgc->irq_chip.irq_unmask = ingenic_gpio_irq_unmask; 2706 jzgc->irq_chip.irq_mask = ingenic_gpio_irq_mask; 2707 jzgc->irq_chip.irq_ack = ingenic_gpio_irq_ack; 2708 jzgc->irq_chip.irq_set_type = ingenic_gpio_irq_set_type; 2709 jzgc->irq_chip.irq_set_wake = ingenic_gpio_irq_set_wake; 2710 jzgc->irq_chip.irq_request_resources = ingenic_gpio_irq_request; 2711 jzgc->irq_chip.irq_release_resources = ingenic_gpio_irq_release; 2712 jzgc->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND; 2713 2714 girq = &jzgc->gc.irq; 2715 girq->chip = &jzgc->irq_chip; 2716 girq->parent_handler = ingenic_gpio_irq_handler; 2717 girq->num_parents = 1; 2718 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), 2719 GFP_KERNEL); 2720 if (!girq->parents) 2721 return -ENOMEM; 2722 girq->parents[0] = jzgc->irq; 2723 girq->default_type = IRQ_TYPE_NONE; 2724 girq->handler = handle_level_irq; 2725 2726 err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc); 2727 if (err) 2728 return err; 2729 2730 return 0; 2731 } 2732 2733 static int __init ingenic_pinctrl_probe(struct platform_device *pdev) 2734 { 2735 struct device *dev = &pdev->dev; 2736 struct ingenic_pinctrl *jzpc; 2737 struct pinctrl_desc *pctl_desc; 2738 void __iomem *base; 2739 const struct ingenic_chip_info *chip_info; 2740 struct device_node *node; 2741 unsigned int i; 2742 int err; 2743 2744 jzpc = devm_kzalloc(dev, sizeof(*jzpc), GFP_KERNEL); 2745 if (!jzpc) 2746 return -ENOMEM; 2747 2748 base = devm_platform_ioremap_resource(pdev, 0); 2749 if (IS_ERR(base)) 2750 return PTR_ERR(base); 2751 2752 jzpc->map = devm_regmap_init_mmio(dev, base, 2753 &ingenic_pinctrl_regmap_config); 2754 if (IS_ERR(jzpc->map)) { 2755 dev_err(dev, "Failed to create regmap\n"); 2756 return PTR_ERR(jzpc->map); 2757 } 2758 2759 jzpc->dev = dev; 2760 jzpc->info = chip_info = of_device_get_match_data(dev); 2761 2762 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL); 2763 if (!pctl_desc) 2764 return -ENOMEM; 2765 2766 /* fill in pinctrl_desc structure */ 2767 pctl_desc->name = dev_name(dev); 2768 pctl_desc->owner = THIS_MODULE; 2769 pctl_desc->pctlops = &ingenic_pctlops; 2770 pctl_desc->pmxops = &ingenic_pmxops; 2771 pctl_desc->confops = &ingenic_confops; 2772 pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP; 2773 pctl_desc->pins = jzpc->pdesc = devm_kcalloc(&pdev->dev, 2774 pctl_desc->npins, sizeof(*jzpc->pdesc), GFP_KERNEL); 2775 if (!jzpc->pdesc) 2776 return -ENOMEM; 2777 2778 for (i = 0; i < pctl_desc->npins; i++) { 2779 jzpc->pdesc[i].number = i; 2780 jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d", 2781 'A' + (i / PINS_PER_GPIO_CHIP), 2782 i % PINS_PER_GPIO_CHIP); 2783 } 2784 2785 jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc); 2786 if (IS_ERR(jzpc->pctl)) { 2787 dev_err(dev, "Failed to register pinctrl\n"); 2788 return PTR_ERR(jzpc->pctl); 2789 } 2790 2791 for (i = 0; i < chip_info->num_groups; i++) { 2792 const struct group_desc *group = &chip_info->groups[i]; 2793 2794 err = pinctrl_generic_add_group(jzpc->pctl, group->name, 2795 group->pins, group->num_pins, group->data); 2796 if (err < 0) { 2797 dev_err(dev, "Failed to register group %s\n", 2798 group->name); 2799 return err; 2800 } 2801 } 2802 2803 for (i = 0; i < chip_info->num_functions; i++) { 2804 const struct function_desc *func = &chip_info->functions[i]; 2805 2806 err = pinmux_generic_add_function(jzpc->pctl, func->name, 2807 func->group_names, func->num_group_names, 2808 func->data); 2809 if (err < 0) { 2810 dev_err(dev, "Failed to register function %s\n", 2811 func->name); 2812 return err; 2813 } 2814 } 2815 2816 dev_set_drvdata(dev, jzpc->map); 2817 2818 for_each_child_of_node(dev->of_node, node) { 2819 if (of_match_node(ingenic_gpio_of_match, node)) { 2820 err = ingenic_gpio_probe(jzpc, node); 2821 if (err) 2822 return err; 2823 } 2824 } 2825 2826 return 0; 2827 } 2828 2829 static const struct of_device_id ingenic_pinctrl_of_match[] = { 2830 { .compatible = "ingenic,jz4740-pinctrl", .data = &jz4740_chip_info }, 2831 { .compatible = "ingenic,jz4725b-pinctrl", .data = &jz4725b_chip_info }, 2832 { .compatible = "ingenic,jz4760-pinctrl", .data = &jz4760_chip_info }, 2833 { .compatible = "ingenic,jz4760b-pinctrl", .data = &jz4760_chip_info }, 2834 { .compatible = "ingenic,jz4770-pinctrl", .data = &jz4770_chip_info }, 2835 { .compatible = "ingenic,jz4780-pinctrl", .data = &jz4780_chip_info }, 2836 { .compatible = "ingenic,x1000-pinctrl", .data = &x1000_chip_info }, 2837 { .compatible = "ingenic,x1000e-pinctrl", .data = &x1000_chip_info }, 2838 { .compatible = "ingenic,x1500-pinctrl", .data = &x1500_chip_info }, 2839 { .compatible = "ingenic,x1830-pinctrl", .data = &x1830_chip_info }, 2840 {}, 2841 }; 2842 2843 static struct platform_driver ingenic_pinctrl_driver = { 2844 .driver = { 2845 .name = "pinctrl-ingenic", 2846 .of_match_table = ingenic_pinctrl_of_match, 2847 }, 2848 }; 2849 2850 static int __init ingenic_pinctrl_drv_register(void) 2851 { 2852 return platform_driver_probe(&ingenic_pinctrl_driver, 2853 ingenic_pinctrl_probe); 2854 } 2855 subsys_initcall(ingenic_pinctrl_drv_register); 2856