1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Ingenic SoCs pinctrl driver 4 * 5 * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net> 6 * Copyright (c) 2017, 2019 Paul Boddie <paul@boddie.org.uk> 7 * Copyright (c) 2019, 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> 8 */ 9 10 #include <linux/compiler.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/of_device.h> 15 #include <linux/of_irq.h> 16 #include <linux/of_platform.h> 17 #include <linux/pinctrl/pinctrl.h> 18 #include <linux/pinctrl/pinmux.h> 19 #include <linux/pinctrl/pinconf.h> 20 #include <linux/pinctrl/pinconf-generic.h> 21 #include <linux/platform_device.h> 22 #include <linux/regmap.h> 23 #include <linux/slab.h> 24 25 #include "core.h" 26 #include "pinconf.h" 27 #include "pinmux.h" 28 29 #define GPIO_PIN 0x00 30 #define GPIO_MSK 0x20 31 32 #define JZ4730_GPIO_DATA 0x00 33 #define JZ4730_GPIO_GPDIR 0x04 34 #define JZ4730_GPIO_GPPUR 0x0c 35 #define JZ4730_GPIO_GPALR 0x10 36 #define JZ4730_GPIO_GPAUR 0x14 37 #define JZ4730_GPIO_GPIDLR 0x18 38 #define JZ4730_GPIO_GPIDUR 0x1c 39 #define JZ4730_GPIO_GPIER 0x20 40 #define JZ4730_GPIO_GPIMR 0x24 41 #define JZ4730_GPIO_GPFR 0x28 42 43 #define JZ4740_GPIO_DATA 0x10 44 #define JZ4740_GPIO_PULL_DIS 0x30 45 #define JZ4740_GPIO_FUNC 0x40 46 #define JZ4740_GPIO_SELECT 0x50 47 #define JZ4740_GPIO_DIR 0x60 48 #define JZ4740_GPIO_TRIG 0x70 49 #define JZ4740_GPIO_FLAG 0x80 50 51 #define JZ4770_GPIO_INT 0x10 52 #define JZ4770_GPIO_PAT1 0x30 53 #define JZ4770_GPIO_PAT0 0x40 54 #define JZ4770_GPIO_FLAG 0x50 55 #define JZ4770_GPIO_PEN 0x70 56 57 #define X1830_GPIO_PEL 0x110 58 #define X1830_GPIO_PEH 0x120 59 #define X1830_GPIO_SR 0x150 60 #define X1830_GPIO_SMT 0x160 61 62 #define X2000_GPIO_EDG 0x70 63 #define X2000_GPIO_PEPU 0x80 64 #define X2000_GPIO_PEPD 0x90 65 #define X2000_GPIO_SR 0xd0 66 #define X2000_GPIO_SMT 0xe0 67 68 #define REG_SET(x) ((x) + 0x4) 69 #define REG_CLEAR(x) ((x) + 0x8) 70 71 #define REG_PZ_BASE(x) ((x) * 7) 72 #define REG_PZ_GID2LD(x) ((x) * 7 + 0xf0) 73 74 #define GPIO_PULL_DIS 0 75 #define GPIO_PULL_UP 1 76 #define GPIO_PULL_DOWN 2 77 78 #define PINS_PER_GPIO_CHIP 32 79 #define JZ4730_PINS_PER_PAIRED_REG 16 80 81 #define INGENIC_PIN_GROUP_FUNCS(name, id, funcs) \ 82 { \ 83 name, \ 84 id##_pins, \ 85 ARRAY_SIZE(id##_pins), \ 86 funcs, \ 87 } 88 89 #define INGENIC_PIN_GROUP(name, id, func) \ 90 INGENIC_PIN_GROUP_FUNCS(name, id, (void *)(func)) 91 92 enum jz_version { 93 ID_JZ4730, 94 ID_JZ4740, 95 ID_JZ4725B, 96 ID_JZ4750, 97 ID_JZ4755, 98 ID_JZ4760, 99 ID_JZ4770, 100 ID_JZ4775, 101 ID_JZ4780, 102 ID_X1000, 103 ID_X1500, 104 ID_X1830, 105 ID_X2000, 106 }; 107 108 struct ingenic_chip_info { 109 unsigned int num_chips; 110 unsigned int reg_offset; 111 enum jz_version version; 112 113 const struct group_desc *groups; 114 unsigned int num_groups; 115 116 const struct function_desc *functions; 117 unsigned int num_functions; 118 119 const u32 *pull_ups, *pull_downs; 120 }; 121 122 struct ingenic_pinctrl { 123 struct device *dev; 124 struct regmap *map; 125 struct pinctrl_dev *pctl; 126 struct pinctrl_pin_desc *pdesc; 127 128 const struct ingenic_chip_info *info; 129 }; 130 131 struct ingenic_gpio_chip { 132 struct ingenic_pinctrl *jzpc; 133 struct gpio_chip gc; 134 struct irq_chip irq_chip; 135 unsigned int irq, reg_base; 136 }; 137 138 static const u32 jz4730_pull_ups[4] = { 139 0x3fa3320f, 0xf200ffff, 0xffffffff, 0xffffffff, 140 }; 141 142 static const u32 jz4730_pull_downs[4] = { 143 0x00000df0, 0x0dff0000, 0x00000000, 0x00000000, 144 }; 145 146 static int jz4730_mmc_1bit_pins[] = { 0x27, 0x26, 0x22, }; 147 static int jz4730_mmc_4bit_pins[] = { 0x23, 0x24, 0x25, }; 148 static int jz4730_uart0_data_pins[] = { 0x7e, 0x7f, }; 149 static int jz4730_uart1_data_pins[] = { 0x18, 0x19, }; 150 static int jz4730_uart2_data_pins[] = { 0x6f, 0x7d, }; 151 static int jz4730_uart3_data_pins[] = { 0x10, 0x15, }; 152 static int jz4730_uart3_hwflow_pins[] = { 0x11, 0x17, }; 153 static int jz4730_lcd_8bit_pins[] = { 154 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 155 0x3a, 0x39, 0x38, 156 }; 157 static int jz4730_lcd_16bit_pins[] = { 158 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 159 }; 160 static int jz4730_lcd_special_pins[] = { 0x3d, 0x3c, 0x3e, 0x3f, }; 161 static int jz4730_lcd_generic_pins[] = { 0x3b, }; 162 static int jz4730_nand_cs1_pins[] = { 0x53, }; 163 static int jz4730_nand_cs2_pins[] = { 0x54, }; 164 static int jz4730_nand_cs3_pins[] = { 0x55, }; 165 static int jz4730_nand_cs4_pins[] = { 0x56, }; 166 static int jz4730_nand_cs5_pins[] = { 0x57, }; 167 static int jz4730_pwm_pwm0_pins[] = { 0x5e, }; 168 static int jz4730_pwm_pwm1_pins[] = { 0x5f, }; 169 170 static u8 jz4730_lcd_8bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, }; 171 172 static const struct group_desc jz4730_groups[] = { 173 INGENIC_PIN_GROUP("mmc-1bit", jz4730_mmc_1bit, 1), 174 INGENIC_PIN_GROUP("mmc-4bit", jz4730_mmc_4bit, 1), 175 INGENIC_PIN_GROUP("uart0-data", jz4730_uart0_data, 1), 176 INGENIC_PIN_GROUP("uart1-data", jz4730_uart1_data, 1), 177 INGENIC_PIN_GROUP("uart2-data", jz4730_uart2_data, 1), 178 INGENIC_PIN_GROUP("uart3-data", jz4730_uart3_data, 1), 179 INGENIC_PIN_GROUP("uart3-hwflow", jz4730_uart3_hwflow, 1), 180 INGENIC_PIN_GROUP_FUNCS("lcd-8bit", jz4730_lcd_8bit, jz4730_lcd_8bit_funcs), 181 INGENIC_PIN_GROUP("lcd-16bit", jz4730_lcd_16bit, 1), 182 INGENIC_PIN_GROUP("lcd-special", jz4730_lcd_special, 1), 183 INGENIC_PIN_GROUP("lcd-generic", jz4730_lcd_generic, 1), 184 INGENIC_PIN_GROUP("nand-cs1", jz4730_nand_cs1, 1), 185 INGENIC_PIN_GROUP("nand-cs2", jz4730_nand_cs2, 1), 186 INGENIC_PIN_GROUP("nand-cs3", jz4730_nand_cs3, 1), 187 INGENIC_PIN_GROUP("nand-cs4", jz4730_nand_cs4, 1), 188 INGENIC_PIN_GROUP("nand-cs5", jz4730_nand_cs5, 1), 189 INGENIC_PIN_GROUP("pwm0", jz4730_pwm_pwm0, 1), 190 INGENIC_PIN_GROUP("pwm1", jz4730_pwm_pwm1, 1), 191 }; 192 193 static const char *jz4730_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; 194 static const char *jz4730_uart0_groups[] = { "uart0-data", }; 195 static const char *jz4730_uart1_groups[] = { "uart1-data", }; 196 static const char *jz4730_uart2_groups[] = { "uart2-data", }; 197 static const char *jz4730_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 198 static const char *jz4730_lcd_groups[] = { 199 "lcd-8bit", "lcd-16bit", "lcd-special", "lcd-generic", 200 }; 201 static const char *jz4730_nand_groups[] = { 202 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-cs5", 203 }; 204 static const char *jz4730_pwm0_groups[] = { "pwm0", }; 205 static const char *jz4730_pwm1_groups[] = { "pwm1", }; 206 207 static const struct function_desc jz4730_functions[] = { 208 { "mmc", jz4730_mmc_groups, ARRAY_SIZE(jz4730_mmc_groups), }, 209 { "uart0", jz4730_uart0_groups, ARRAY_SIZE(jz4730_uart0_groups), }, 210 { "uart1", jz4730_uart1_groups, ARRAY_SIZE(jz4730_uart1_groups), }, 211 { "uart2", jz4730_uart2_groups, ARRAY_SIZE(jz4730_uart2_groups), }, 212 { "uart3", jz4730_uart3_groups, ARRAY_SIZE(jz4730_uart3_groups), }, 213 { "lcd", jz4730_lcd_groups, ARRAY_SIZE(jz4730_lcd_groups), }, 214 { "nand", jz4730_nand_groups, ARRAY_SIZE(jz4730_nand_groups), }, 215 { "pwm0", jz4730_pwm0_groups, ARRAY_SIZE(jz4730_pwm0_groups), }, 216 { "pwm1", jz4730_pwm1_groups, ARRAY_SIZE(jz4730_pwm1_groups), }, 217 }; 218 219 static const struct ingenic_chip_info jz4730_chip_info = { 220 .num_chips = 4, 221 .reg_offset = 0x30, 222 .version = ID_JZ4730, 223 .groups = jz4730_groups, 224 .num_groups = ARRAY_SIZE(jz4730_groups), 225 .functions = jz4730_functions, 226 .num_functions = ARRAY_SIZE(jz4730_functions), 227 .pull_ups = jz4730_pull_ups, 228 .pull_downs = jz4730_pull_downs, 229 }; 230 231 static const u32 jz4740_pull_ups[4] = { 232 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 233 }; 234 235 static const u32 jz4740_pull_downs[4] = { 236 0x00000000, 0x00000000, 0x00000000, 0x00000000, 237 }; 238 239 static int jz4740_mmc_1bit_pins[] = { 0x69, 0x68, 0x6a, }; 240 static int jz4740_mmc_4bit_pins[] = { 0x6b, 0x6c, 0x6d, }; 241 static int jz4740_uart0_data_pins[] = { 0x7a, 0x79, }; 242 static int jz4740_uart0_hwflow_pins[] = { 0x7e, 0x7f, }; 243 static int jz4740_uart1_data_pins[] = { 0x7e, 0x7f, }; 244 static int jz4740_lcd_8bit_pins[] = { 245 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 246 0x52, 0x53, 0x54, 247 }; 248 static int jz4740_lcd_16bit_pins[] = { 249 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 250 }; 251 static int jz4740_lcd_18bit_pins[] = { 0x50, 0x51, }; 252 static int jz4740_lcd_special_pins[] = { 0x31, 0x32, 0x56, 0x57, }; 253 static int jz4740_lcd_generic_pins[] = { 0x55, }; 254 static int jz4740_nand_cs1_pins[] = { 0x39, }; 255 static int jz4740_nand_cs2_pins[] = { 0x3a, }; 256 static int jz4740_nand_cs3_pins[] = { 0x3b, }; 257 static int jz4740_nand_cs4_pins[] = { 0x3c, }; 258 static int jz4740_nand_fre_fwe_pins[] = { 0x5c, 0x5d, }; 259 static int jz4740_pwm_pwm0_pins[] = { 0x77, }; 260 static int jz4740_pwm_pwm1_pins[] = { 0x78, }; 261 static int jz4740_pwm_pwm2_pins[] = { 0x79, }; 262 static int jz4740_pwm_pwm3_pins[] = { 0x7a, }; 263 static int jz4740_pwm_pwm4_pins[] = { 0x7b, }; 264 static int jz4740_pwm_pwm5_pins[] = { 0x7c, }; 265 static int jz4740_pwm_pwm6_pins[] = { 0x7e, }; 266 static int jz4740_pwm_pwm7_pins[] = { 0x7f, }; 267 268 static const struct group_desc jz4740_groups[] = { 269 INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit, 0), 270 INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit, 0), 271 INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data, 1), 272 INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow, 1), 273 INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data, 2), 274 INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit, 0), 275 INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit, 0), 276 INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit, 0), 277 INGENIC_PIN_GROUP("lcd-special", jz4740_lcd_special, 0), 278 INGENIC_PIN_GROUP("lcd-generic", jz4740_lcd_generic, 0), 279 INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1, 0), 280 INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2, 0), 281 INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3, 0), 282 INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4, 0), 283 INGENIC_PIN_GROUP("nand-fre-fwe", jz4740_nand_fre_fwe, 0), 284 INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0, 0), 285 INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1, 0), 286 INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2, 0), 287 INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3, 0), 288 INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4, 0), 289 INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5, 0), 290 INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6, 0), 291 INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7, 0), 292 }; 293 294 static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; 295 static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 296 static const char *jz4740_uart1_groups[] = { "uart1-data", }; 297 static const char *jz4740_lcd_groups[] = { 298 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-special", "lcd-generic", 299 }; 300 static const char *jz4740_nand_groups[] = { 301 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe", 302 }; 303 static const char *jz4740_pwm0_groups[] = { "pwm0", }; 304 static const char *jz4740_pwm1_groups[] = { "pwm1", }; 305 static const char *jz4740_pwm2_groups[] = { "pwm2", }; 306 static const char *jz4740_pwm3_groups[] = { "pwm3", }; 307 static const char *jz4740_pwm4_groups[] = { "pwm4", }; 308 static const char *jz4740_pwm5_groups[] = { "pwm5", }; 309 static const char *jz4740_pwm6_groups[] = { "pwm6", }; 310 static const char *jz4740_pwm7_groups[] = { "pwm7", }; 311 312 static const struct function_desc jz4740_functions[] = { 313 { "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), }, 314 { "uart0", jz4740_uart0_groups, ARRAY_SIZE(jz4740_uart0_groups), }, 315 { "uart1", jz4740_uart1_groups, ARRAY_SIZE(jz4740_uart1_groups), }, 316 { "lcd", jz4740_lcd_groups, ARRAY_SIZE(jz4740_lcd_groups), }, 317 { "nand", jz4740_nand_groups, ARRAY_SIZE(jz4740_nand_groups), }, 318 { "pwm0", jz4740_pwm0_groups, ARRAY_SIZE(jz4740_pwm0_groups), }, 319 { "pwm1", jz4740_pwm1_groups, ARRAY_SIZE(jz4740_pwm1_groups), }, 320 { "pwm2", jz4740_pwm2_groups, ARRAY_SIZE(jz4740_pwm2_groups), }, 321 { "pwm3", jz4740_pwm3_groups, ARRAY_SIZE(jz4740_pwm3_groups), }, 322 { "pwm4", jz4740_pwm4_groups, ARRAY_SIZE(jz4740_pwm4_groups), }, 323 { "pwm5", jz4740_pwm5_groups, ARRAY_SIZE(jz4740_pwm5_groups), }, 324 { "pwm6", jz4740_pwm6_groups, ARRAY_SIZE(jz4740_pwm6_groups), }, 325 { "pwm7", jz4740_pwm7_groups, ARRAY_SIZE(jz4740_pwm7_groups), }, 326 }; 327 328 static const struct ingenic_chip_info jz4740_chip_info = { 329 .num_chips = 4, 330 .reg_offset = 0x100, 331 .version = ID_JZ4740, 332 .groups = jz4740_groups, 333 .num_groups = ARRAY_SIZE(jz4740_groups), 334 .functions = jz4740_functions, 335 .num_functions = ARRAY_SIZE(jz4740_functions), 336 .pull_ups = jz4740_pull_ups, 337 .pull_downs = jz4740_pull_downs, 338 }; 339 340 static int jz4725b_mmc0_1bit_pins[] = { 0x48, 0x49, 0x5c, }; 341 static int jz4725b_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x56, }; 342 static int jz4725b_mmc1_1bit_pins[] = { 0x7a, 0x7b, 0x7c, }; 343 static int jz4725b_mmc1_4bit_pins[] = { 0x7d, 0x7e, 0x7f, }; 344 static int jz4725b_uart_data_pins[] = { 0x4c, 0x4d, }; 345 static int jz4725b_lcd_8bit_pins[] = { 346 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 347 0x72, 0x73, 0x74, 348 }; 349 static int jz4725b_lcd_16bit_pins[] = { 350 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 351 }; 352 static int jz4725b_lcd_18bit_pins[] = { 0x70, 0x71, }; 353 static int jz4725b_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 354 static int jz4725b_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 355 static int jz4725b_lcd_generic_pins[] = { 0x75, }; 356 static int jz4725b_nand_cs1_pins[] = { 0x55, }; 357 static int jz4725b_nand_cs2_pins[] = { 0x56, }; 358 static int jz4725b_nand_cs3_pins[] = { 0x57, }; 359 static int jz4725b_nand_cs4_pins[] = { 0x58, }; 360 static int jz4725b_nand_cle_ale_pins[] = { 0x48, 0x49 }; 361 static int jz4725b_nand_fre_fwe_pins[] = { 0x5c, 0x5d }; 362 static int jz4725b_pwm_pwm0_pins[] = { 0x4a, }; 363 static int jz4725b_pwm_pwm1_pins[] = { 0x4b, }; 364 static int jz4725b_pwm_pwm2_pins[] = { 0x4c, }; 365 static int jz4725b_pwm_pwm3_pins[] = { 0x4d, }; 366 static int jz4725b_pwm_pwm4_pins[] = { 0x4e, }; 367 static int jz4725b_pwm_pwm5_pins[] = { 0x4f, }; 368 369 static u8 jz4725b_mmc0_4bit_funcs[] = { 1, 0, 1, }; 370 371 static const struct group_desc jz4725b_groups[] = { 372 INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit, 1), 373 INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4725b_mmc0_4bit, 374 jz4725b_mmc0_4bit_funcs), 375 INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit, 0), 376 INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit, 0), 377 INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data, 1), 378 INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit, 0), 379 INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit, 0), 380 INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit, 0), 381 INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit, 1), 382 INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special, 0), 383 INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic, 0), 384 INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1, 0), 385 INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2, 0), 386 INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3, 0), 387 INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4, 0), 388 INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale, 0), 389 INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe, 0), 390 INGENIC_PIN_GROUP("pwm0", jz4725b_pwm_pwm0, 0), 391 INGENIC_PIN_GROUP("pwm1", jz4725b_pwm_pwm1, 0), 392 INGENIC_PIN_GROUP("pwm2", jz4725b_pwm_pwm2, 0), 393 INGENIC_PIN_GROUP("pwm3", jz4725b_pwm_pwm3, 0), 394 INGENIC_PIN_GROUP("pwm4", jz4725b_pwm_pwm4, 0), 395 INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5, 0), 396 }; 397 398 static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 399 static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 400 static const char *jz4725b_uart_groups[] = { "uart-data", }; 401 static const char *jz4725b_lcd_groups[] = { 402 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 403 "lcd-special", "lcd-generic", 404 }; 405 static const char *jz4725b_nand_groups[] = { 406 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", 407 "nand-cle-ale", "nand-fre-fwe", 408 }; 409 static const char *jz4725b_pwm0_groups[] = { "pwm0", }; 410 static const char *jz4725b_pwm1_groups[] = { "pwm1", }; 411 static const char *jz4725b_pwm2_groups[] = { "pwm2", }; 412 static const char *jz4725b_pwm3_groups[] = { "pwm3", }; 413 static const char *jz4725b_pwm4_groups[] = { "pwm4", }; 414 static const char *jz4725b_pwm5_groups[] = { "pwm5", }; 415 416 static const struct function_desc jz4725b_functions[] = { 417 { "mmc0", jz4725b_mmc0_groups, ARRAY_SIZE(jz4725b_mmc0_groups), }, 418 { "mmc1", jz4725b_mmc1_groups, ARRAY_SIZE(jz4725b_mmc1_groups), }, 419 { "uart", jz4725b_uart_groups, ARRAY_SIZE(jz4725b_uart_groups), }, 420 { "nand", jz4725b_nand_groups, ARRAY_SIZE(jz4725b_nand_groups), }, 421 { "pwm0", jz4725b_pwm0_groups, ARRAY_SIZE(jz4725b_pwm0_groups), }, 422 { "pwm1", jz4725b_pwm1_groups, ARRAY_SIZE(jz4725b_pwm1_groups), }, 423 { "pwm2", jz4725b_pwm2_groups, ARRAY_SIZE(jz4725b_pwm2_groups), }, 424 { "pwm3", jz4725b_pwm3_groups, ARRAY_SIZE(jz4725b_pwm3_groups), }, 425 { "pwm4", jz4725b_pwm4_groups, ARRAY_SIZE(jz4725b_pwm4_groups), }, 426 { "pwm5", jz4725b_pwm5_groups, ARRAY_SIZE(jz4725b_pwm5_groups), }, 427 { "lcd", jz4725b_lcd_groups, ARRAY_SIZE(jz4725b_lcd_groups), }, 428 }; 429 430 static const struct ingenic_chip_info jz4725b_chip_info = { 431 .num_chips = 4, 432 .reg_offset = 0x100, 433 .version = ID_JZ4725B, 434 .groups = jz4725b_groups, 435 .num_groups = ARRAY_SIZE(jz4725b_groups), 436 .functions = jz4725b_functions, 437 .num_functions = ARRAY_SIZE(jz4725b_functions), 438 .pull_ups = jz4740_pull_ups, 439 .pull_downs = jz4740_pull_downs, 440 }; 441 442 static const u32 jz4750_pull_ups[6] = { 443 0xffffffff, 0xffffffff, 0x3fffffff, 0x7fffffff, 0x1fff3fff, 0x00ffffff, 444 }; 445 446 static const u32 jz4750_pull_downs[6] = { 447 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 448 }; 449 450 static int jz4750_uart0_data_pins[] = { 0xa4, 0xa5, }; 451 static int jz4750_uart0_hwflow_pins[] = { 0xa6, 0xa7, }; 452 static int jz4750_uart1_data_pins[] = { 0x90, 0x91, }; 453 static int jz4750_uart1_hwflow_pins[] = { 0x92, 0x93, }; 454 static int jz4750_uart2_data_pins[] = { 0x9b, 0x9a, }; 455 static int jz4750_uart3_data_pins[] = { 0xb0, 0xb1, }; 456 static int jz4750_uart3_hwflow_pins[] = { 0xb2, 0xb3, }; 457 static int jz4750_mmc0_1bit_pins[] = { 0xa8, 0xa9, 0xa0, }; 458 static int jz4750_mmc0_4bit_pins[] = { 0xa1, 0xa2, 0xa3, }; 459 static int jz4750_mmc0_8bit_pins[] = { 0xa4, 0xa5, 0xa6, 0xa7, }; 460 static int jz4750_mmc1_1bit_pins[] = { 0xae, 0xaf, 0xaa, }; 461 static int jz4750_mmc1_4bit_pins[] = { 0xab, 0xac, 0xad, }; 462 static int jz4750_i2c_pins[] = { 0x8c, 0x8d, }; 463 static int jz4750_cim_pins[] = { 464 0x89, 0x8b, 0x8a, 0x88, 465 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 466 }; 467 static int jz4750_lcd_8bit_pins[] = { 468 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 469 0x72, 0x73, 0x74, 470 }; 471 static int jz4750_lcd_16bit_pins[] = { 472 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 473 }; 474 static int jz4750_lcd_18bit_pins[] = { 0x70, 0x71, }; 475 static int jz4750_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, 0xb2, 0xb3, }; 476 static int jz4750_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 477 static int jz4750_lcd_generic_pins[] = { 0x75, }; 478 static int jz4750_nand_cs1_pins[] = { 0x55, }; 479 static int jz4750_nand_cs2_pins[] = { 0x56, }; 480 static int jz4750_nand_cs3_pins[] = { 0x57, }; 481 static int jz4750_nand_cs4_pins[] = { 0x58, }; 482 static int jz4750_nand_fre_fwe_pins[] = { 0x5c, 0x5d, }; 483 static int jz4750_pwm_pwm0_pins[] = { 0x94, }; 484 static int jz4750_pwm_pwm1_pins[] = { 0x95, }; 485 static int jz4750_pwm_pwm2_pins[] = { 0x96, }; 486 static int jz4750_pwm_pwm3_pins[] = { 0x97, }; 487 static int jz4750_pwm_pwm4_pins[] = { 0x98, }; 488 static int jz4750_pwm_pwm5_pins[] = { 0x99, }; 489 490 static const struct group_desc jz4750_groups[] = { 491 INGENIC_PIN_GROUP("uart0-data", jz4750_uart0_data, 1), 492 INGENIC_PIN_GROUP("uart0-hwflow", jz4750_uart0_hwflow, 1), 493 INGENIC_PIN_GROUP("uart1-data", jz4750_uart1_data, 0), 494 INGENIC_PIN_GROUP("uart1-hwflow", jz4750_uart1_hwflow, 0), 495 INGENIC_PIN_GROUP("uart2-data", jz4750_uart2_data, 1), 496 INGENIC_PIN_GROUP("uart3-data", jz4750_uart3_data, 0), 497 INGENIC_PIN_GROUP("uart3-hwflow", jz4750_uart3_hwflow, 0), 498 INGENIC_PIN_GROUP("mmc0-1bit", jz4750_mmc0_1bit, 0), 499 INGENIC_PIN_GROUP("mmc0-4bit", jz4750_mmc0_4bit, 0), 500 INGENIC_PIN_GROUP("mmc0-8bit", jz4750_mmc0_8bit, 0), 501 INGENIC_PIN_GROUP("mmc1-1bit", jz4750_mmc1_1bit, 0), 502 INGENIC_PIN_GROUP("mmc1-4bit", jz4750_mmc1_4bit, 0), 503 INGENIC_PIN_GROUP("i2c-data", jz4750_i2c, 0), 504 INGENIC_PIN_GROUP("cim-data", jz4750_cim, 0), 505 INGENIC_PIN_GROUP("lcd-8bit", jz4750_lcd_8bit, 0), 506 INGENIC_PIN_GROUP("lcd-16bit", jz4750_lcd_16bit, 0), 507 INGENIC_PIN_GROUP("lcd-18bit", jz4750_lcd_18bit, 0), 508 INGENIC_PIN_GROUP("lcd-24bit", jz4750_lcd_24bit, 1), 509 INGENIC_PIN_GROUP("lcd-special", jz4750_lcd_special, 0), 510 INGENIC_PIN_GROUP("lcd-generic", jz4750_lcd_generic, 0), 511 INGENIC_PIN_GROUP("nand-cs1", jz4750_nand_cs1, 0), 512 INGENIC_PIN_GROUP("nand-cs2", jz4750_nand_cs2, 0), 513 INGENIC_PIN_GROUP("nand-cs3", jz4750_nand_cs3, 0), 514 INGENIC_PIN_GROUP("nand-cs4", jz4750_nand_cs4, 0), 515 INGENIC_PIN_GROUP("nand-fre-fwe", jz4750_nand_fre_fwe, 0), 516 INGENIC_PIN_GROUP("pwm0", jz4750_pwm_pwm0, 0), 517 INGENIC_PIN_GROUP("pwm1", jz4750_pwm_pwm1, 0), 518 INGENIC_PIN_GROUP("pwm2", jz4750_pwm_pwm2, 0), 519 INGENIC_PIN_GROUP("pwm3", jz4750_pwm_pwm3, 0), 520 INGENIC_PIN_GROUP("pwm4", jz4750_pwm_pwm4, 0), 521 INGENIC_PIN_GROUP("pwm5", jz4750_pwm_pwm5, 0), 522 }; 523 524 static const char *jz4750_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 525 static const char *jz4750_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 526 static const char *jz4750_uart2_groups[] = { "uart2-data", }; 527 static const char *jz4750_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 528 static const char *jz4750_mmc0_groups[] = { 529 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", 530 }; 531 static const char *jz4750_mmc1_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 532 static const char *jz4750_i2c_groups[] = { "i2c-data", }; 533 static const char *jz4750_cim_groups[] = { "cim-data", }; 534 static const char *jz4750_lcd_groups[] = { 535 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 536 "lcd-special", "lcd-generic", 537 }; 538 static const char *jz4750_nand_groups[] = { 539 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe", 540 }; 541 static const char *jz4750_pwm0_groups[] = { "pwm0", }; 542 static const char *jz4750_pwm1_groups[] = { "pwm1", }; 543 static const char *jz4750_pwm2_groups[] = { "pwm2", }; 544 static const char *jz4750_pwm3_groups[] = { "pwm3", }; 545 static const char *jz4750_pwm4_groups[] = { "pwm4", }; 546 static const char *jz4750_pwm5_groups[] = { "pwm5", }; 547 548 static const struct function_desc jz4750_functions[] = { 549 { "uart0", jz4750_uart0_groups, ARRAY_SIZE(jz4750_uart0_groups), }, 550 { "uart1", jz4750_uart1_groups, ARRAY_SIZE(jz4750_uart1_groups), }, 551 { "uart2", jz4750_uart2_groups, ARRAY_SIZE(jz4750_uart2_groups), }, 552 { "uart3", jz4750_uart3_groups, ARRAY_SIZE(jz4750_uart3_groups), }, 553 { "mmc0", jz4750_mmc0_groups, ARRAY_SIZE(jz4750_mmc0_groups), }, 554 { "mmc1", jz4750_mmc1_groups, ARRAY_SIZE(jz4750_mmc1_groups), }, 555 { "i2c", jz4750_i2c_groups, ARRAY_SIZE(jz4750_i2c_groups), }, 556 { "cim", jz4750_cim_groups, ARRAY_SIZE(jz4750_cim_groups), }, 557 { "lcd", jz4750_lcd_groups, ARRAY_SIZE(jz4750_lcd_groups), }, 558 { "nand", jz4750_nand_groups, ARRAY_SIZE(jz4750_nand_groups), }, 559 { "pwm0", jz4750_pwm0_groups, ARRAY_SIZE(jz4750_pwm0_groups), }, 560 { "pwm1", jz4750_pwm1_groups, ARRAY_SIZE(jz4750_pwm1_groups), }, 561 { "pwm2", jz4750_pwm2_groups, ARRAY_SIZE(jz4750_pwm2_groups), }, 562 { "pwm3", jz4750_pwm3_groups, ARRAY_SIZE(jz4750_pwm3_groups), }, 563 { "pwm4", jz4750_pwm4_groups, ARRAY_SIZE(jz4750_pwm4_groups), }, 564 { "pwm5", jz4750_pwm5_groups, ARRAY_SIZE(jz4750_pwm5_groups), }, 565 }; 566 567 static const struct ingenic_chip_info jz4750_chip_info = { 568 .num_chips = 6, 569 .reg_offset = 0x100, 570 .version = ID_JZ4750, 571 .groups = jz4750_groups, 572 .num_groups = ARRAY_SIZE(jz4750_groups), 573 .functions = jz4750_functions, 574 .num_functions = ARRAY_SIZE(jz4750_functions), 575 .pull_ups = jz4750_pull_ups, 576 .pull_downs = jz4750_pull_downs, 577 }; 578 579 static const u32 jz4755_pull_ups[6] = { 580 0xffffffff, 0xffffffff, 0x0fffffff, 0xffffffff, 0x33dc3fff, 0x0000fc00, 581 }; 582 583 static const u32 jz4755_pull_downs[6] = { 584 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 585 }; 586 587 static int jz4755_uart0_data_pins[] = { 0x7c, 0x7d, }; 588 static int jz4755_uart0_hwflow_pins[] = { 0x7e, 0x7f, }; 589 static int jz4755_uart1_data_pins[] = { 0x97, 0x99, }; 590 static int jz4755_uart2_data_pins[] = { 0x9f, }; 591 static int jz4755_mmc0_1bit_pins[] = { 0x2f, 0x50, 0x5c, }; 592 static int jz4755_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x51, }; 593 static int jz4755_mmc1_1bit_pins[] = { 0x3a, 0x3d, 0x3c, }; 594 static int jz4755_mmc1_4bit_pins[] = { 0x3b, 0x3e, 0x3f, }; 595 static int jz4755_i2c_pins[] = { 0x8c, 0x8d, }; 596 static int jz4755_cim_pins[] = { 597 0x89, 0x8b, 0x8a, 0x88, 598 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 599 }; 600 static int jz4755_lcd_8bit_pins[] = { 601 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 602 0x72, 0x73, 0x74, 603 }; 604 static int jz4755_lcd_16bit_pins[] = { 605 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 606 }; 607 static int jz4755_lcd_18bit_pins[] = { 0x70, 0x71, }; 608 static int jz4755_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, }; 609 static int jz4755_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 610 static int jz4755_lcd_generic_pins[] = { 0x75, }; 611 static int jz4755_nand_cs1_pins[] = { 0x55, }; 612 static int jz4755_nand_cs2_pins[] = { 0x56, }; 613 static int jz4755_nand_cs3_pins[] = { 0x57, }; 614 static int jz4755_nand_cs4_pins[] = { 0x58, }; 615 static int jz4755_nand_fre_fwe_pins[] = { 0x5c, 0x5d, }; 616 static int jz4755_pwm_pwm0_pins[] = { 0x94, }; 617 static int jz4755_pwm_pwm1_pins[] = { 0xab, }; 618 static int jz4755_pwm_pwm2_pins[] = { 0x96, }; 619 static int jz4755_pwm_pwm3_pins[] = { 0x97, }; 620 static int jz4755_pwm_pwm4_pins[] = { 0x98, }; 621 static int jz4755_pwm_pwm5_pins[] = { 0x99, }; 622 623 static u8 jz4755_mmc0_1bit_funcs[] = { 2, 2, 1, }; 624 static u8 jz4755_mmc0_4bit_funcs[] = { 1, 0, 1, }; 625 static u8 jz4755_lcd_24bit_funcs[] = { 1, 1, 1, 1, 0, 0, }; 626 627 static const struct group_desc jz4755_groups[] = { 628 INGENIC_PIN_GROUP("uart0-data", jz4755_uart0_data, 0), 629 INGENIC_PIN_GROUP("uart0-hwflow", jz4755_uart0_hwflow, 0), 630 INGENIC_PIN_GROUP("uart1-data", jz4755_uart1_data, 0), 631 INGENIC_PIN_GROUP("uart2-data", jz4755_uart2_data, 1), 632 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit", jz4755_mmc0_1bit, 633 jz4755_mmc0_1bit_funcs), 634 INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4755_mmc0_4bit, 635 jz4755_mmc0_4bit_funcs), 636 INGENIC_PIN_GROUP("mmc1-1bit", jz4755_mmc1_1bit, 1), 637 INGENIC_PIN_GROUP("mmc1-4bit", jz4755_mmc1_4bit, 1), 638 INGENIC_PIN_GROUP("i2c-data", jz4755_i2c, 0), 639 INGENIC_PIN_GROUP("cim-data", jz4755_cim, 0), 640 INGENIC_PIN_GROUP("lcd-8bit", jz4755_lcd_8bit, 0), 641 INGENIC_PIN_GROUP("lcd-16bit", jz4755_lcd_16bit, 0), 642 INGENIC_PIN_GROUP("lcd-18bit", jz4755_lcd_18bit, 0), 643 INGENIC_PIN_GROUP_FUNCS("lcd-24bit", jz4755_lcd_24bit, 644 jz4755_lcd_24bit_funcs), 645 INGENIC_PIN_GROUP("lcd-special", jz4755_lcd_special, 0), 646 INGENIC_PIN_GROUP("lcd-generic", jz4755_lcd_generic, 0), 647 INGENIC_PIN_GROUP("nand-cs1", jz4755_nand_cs1, 0), 648 INGENIC_PIN_GROUP("nand-cs2", jz4755_nand_cs2, 0), 649 INGENIC_PIN_GROUP("nand-cs3", jz4755_nand_cs3, 0), 650 INGENIC_PIN_GROUP("nand-cs4", jz4755_nand_cs4, 0), 651 INGENIC_PIN_GROUP("nand-fre-fwe", jz4755_nand_fre_fwe, 0), 652 INGENIC_PIN_GROUP("pwm0", jz4755_pwm_pwm0, 0), 653 INGENIC_PIN_GROUP("pwm1", jz4755_pwm_pwm1, 1), 654 INGENIC_PIN_GROUP("pwm2", jz4755_pwm_pwm2, 0), 655 INGENIC_PIN_GROUP("pwm3", jz4755_pwm_pwm3, 0), 656 INGENIC_PIN_GROUP("pwm4", jz4755_pwm_pwm4, 0), 657 INGENIC_PIN_GROUP("pwm5", jz4755_pwm_pwm5, 0), 658 }; 659 660 static const char *jz4755_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 661 static const char *jz4755_uart1_groups[] = { "uart1-data", }; 662 static const char *jz4755_uart2_groups[] = { "uart2-data", }; 663 static const char *jz4755_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 664 static const char *jz4755_mmc1_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 665 static const char *jz4755_i2c_groups[] = { "i2c-data", }; 666 static const char *jz4755_cim_groups[] = { "cim-data", }; 667 static const char *jz4755_lcd_groups[] = { 668 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 669 "lcd-special", "lcd-generic", 670 }; 671 static const char *jz4755_nand_groups[] = { 672 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe", 673 }; 674 static const char *jz4755_pwm0_groups[] = { "pwm0", }; 675 static const char *jz4755_pwm1_groups[] = { "pwm1", }; 676 static const char *jz4755_pwm2_groups[] = { "pwm2", }; 677 static const char *jz4755_pwm3_groups[] = { "pwm3", }; 678 static const char *jz4755_pwm4_groups[] = { "pwm4", }; 679 static const char *jz4755_pwm5_groups[] = { "pwm5", }; 680 681 static const struct function_desc jz4755_functions[] = { 682 { "uart0", jz4755_uart0_groups, ARRAY_SIZE(jz4755_uart0_groups), }, 683 { "uart1", jz4755_uart1_groups, ARRAY_SIZE(jz4755_uart1_groups), }, 684 { "uart2", jz4755_uart2_groups, ARRAY_SIZE(jz4755_uart2_groups), }, 685 { "mmc0", jz4755_mmc0_groups, ARRAY_SIZE(jz4755_mmc0_groups), }, 686 { "mmc1", jz4755_mmc1_groups, ARRAY_SIZE(jz4755_mmc1_groups), }, 687 { "i2c", jz4755_i2c_groups, ARRAY_SIZE(jz4755_i2c_groups), }, 688 { "cim", jz4755_cim_groups, ARRAY_SIZE(jz4755_cim_groups), }, 689 { "lcd", jz4755_lcd_groups, ARRAY_SIZE(jz4755_lcd_groups), }, 690 { "nand", jz4755_nand_groups, ARRAY_SIZE(jz4755_nand_groups), }, 691 { "pwm0", jz4755_pwm0_groups, ARRAY_SIZE(jz4755_pwm0_groups), }, 692 { "pwm1", jz4755_pwm1_groups, ARRAY_SIZE(jz4755_pwm1_groups), }, 693 { "pwm2", jz4755_pwm2_groups, ARRAY_SIZE(jz4755_pwm2_groups), }, 694 { "pwm3", jz4755_pwm3_groups, ARRAY_SIZE(jz4755_pwm3_groups), }, 695 { "pwm4", jz4755_pwm4_groups, ARRAY_SIZE(jz4755_pwm4_groups), }, 696 { "pwm5", jz4755_pwm5_groups, ARRAY_SIZE(jz4755_pwm5_groups), }, 697 }; 698 699 static const struct ingenic_chip_info jz4755_chip_info = { 700 .num_chips = 6, 701 .reg_offset = 0x100, 702 .version = ID_JZ4755, 703 .groups = jz4755_groups, 704 .num_groups = ARRAY_SIZE(jz4755_groups), 705 .functions = jz4755_functions, 706 .num_functions = ARRAY_SIZE(jz4755_functions), 707 .pull_ups = jz4755_pull_ups, 708 .pull_downs = jz4755_pull_downs, 709 }; 710 711 static const u32 jz4760_pull_ups[6] = { 712 0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0xfffff00f, 713 }; 714 715 static const u32 jz4760_pull_downs[6] = { 716 0x00000000, 0x00030c00, 0x00000000, 0x00003000, 0x00000483, 0x00000ff0, 717 }; 718 719 static int jz4760_uart0_data_pins[] = { 0xa0, 0xa3, }; 720 static int jz4760_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; 721 static int jz4760_uart1_data_pins[] = { 0x7a, 0x7c, }; 722 static int jz4760_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; 723 static int jz4760_uart2_data_pins[] = { 0x5c, 0x5e, }; 724 static int jz4760_uart2_hwflow_pins[] = { 0x5d, 0x5f, }; 725 static int jz4760_uart3_data_pins[] = { 0x6c, 0x85, }; 726 static int jz4760_uart3_hwflow_pins[] = { 0x88, 0x89, }; 727 static int jz4760_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; 728 static int jz4760_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; 729 static int jz4760_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 730 static int jz4760_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 731 static int jz4760_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 732 static int jz4760_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; 733 static int jz4760_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; 734 static int jz4760_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 735 static int jz4760_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 736 static int jz4760_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 737 static int jz4760_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, }; 738 static int jz4760_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, }; 739 static int jz4760_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 740 static int jz4760_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 741 static int jz4760_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 742 static int jz4760_nemc_8bit_data_pins[] = { 743 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 744 }; 745 static int jz4760_nemc_16bit_data_pins[] = { 746 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 747 }; 748 static int jz4760_nemc_cle_ale_pins[] = { 0x20, 0x21, }; 749 static int jz4760_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; 750 static int jz4760_nemc_rd_we_pins[] = { 0x10, 0x11, }; 751 static int jz4760_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; 752 static int jz4760_nemc_wait_pins[] = { 0x1b, }; 753 static int jz4760_nemc_cs1_pins[] = { 0x15, }; 754 static int jz4760_nemc_cs2_pins[] = { 0x16, }; 755 static int jz4760_nemc_cs3_pins[] = { 0x17, }; 756 static int jz4760_nemc_cs4_pins[] = { 0x18, }; 757 static int jz4760_nemc_cs5_pins[] = { 0x19, }; 758 static int jz4760_nemc_cs6_pins[] = { 0x1a, }; 759 static int jz4760_i2c0_pins[] = { 0x7e, 0x7f, }; 760 static int jz4760_i2c1_pins[] = { 0x9e, 0x9f, }; 761 static int jz4760_cim_pins[] = { 762 0x26, 0x27, 0x28, 0x29, 763 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 764 }; 765 static int jz4760_lcd_8bit_pins[] = { 766 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x4c, 767 0x4d, 0x52, 0x53, 768 }; 769 static int jz4760_lcd_16bit_pins[] = { 770 0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59, 771 }; 772 static int jz4760_lcd_18bit_pins[] = { 773 0x5a, 0x5b, 774 }; 775 static int jz4760_lcd_24bit_pins[] = { 776 0x40, 0x41, 0x4a, 0x4b, 0x54, 0x55, 777 }; 778 static int jz4760_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, }; 779 static int jz4760_lcd_generic_pins[] = { 0x49, }; 780 static int jz4760_pwm_pwm0_pins[] = { 0x80, }; 781 static int jz4760_pwm_pwm1_pins[] = { 0x81, }; 782 static int jz4760_pwm_pwm2_pins[] = { 0x82, }; 783 static int jz4760_pwm_pwm3_pins[] = { 0x83, }; 784 static int jz4760_pwm_pwm4_pins[] = { 0x84, }; 785 static int jz4760_pwm_pwm5_pins[] = { 0x85, }; 786 static int jz4760_pwm_pwm6_pins[] = { 0x6a, }; 787 static int jz4760_pwm_pwm7_pins[] = { 0x6b, }; 788 static int jz4760_otg_pins[] = { 0x8a, }; 789 790 static u8 jz4760_uart3_data_funcs[] = { 0, 1, }; 791 static u8 jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, }; 792 793 static const struct group_desc jz4760_groups[] = { 794 INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data, 0), 795 INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow, 0), 796 INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data, 0), 797 INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow, 0), 798 INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data, 0), 799 INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow, 0), 800 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4760_uart3_data, 801 jz4760_uart3_data_funcs), 802 INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow, 0), 803 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4760_mmc0_1bit_a, 804 jz4760_mmc0_1bit_a_funcs), 805 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a, 1), 806 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e, 0), 807 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e, 0), 808 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e, 0), 809 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d, 0), 810 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d, 0), 811 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e, 1), 812 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e, 1), 813 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e, 1), 814 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b, 0), 815 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b, 0), 816 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e, 2), 817 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e, 2), 818 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e, 2), 819 INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data, 0), 820 INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data, 0), 821 INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale, 0), 822 INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr, 0), 823 INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we, 0), 824 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe, 0), 825 INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait, 0), 826 INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1, 0), 827 INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2, 0), 828 INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3, 0), 829 INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4, 0), 830 INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5, 0), 831 INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6, 0), 832 INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0, 0), 833 INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1, 0), 834 INGENIC_PIN_GROUP("cim-data", jz4760_cim, 0), 835 INGENIC_PIN_GROUP("lcd-8bit", jz4760_lcd_8bit, 0), 836 INGENIC_PIN_GROUP("lcd-16bit", jz4760_lcd_16bit, 0), 837 INGENIC_PIN_GROUP("lcd-18bit", jz4760_lcd_18bit, 0), 838 INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit, 0), 839 INGENIC_PIN_GROUP("lcd-special", jz4760_lcd_special, 1), 840 INGENIC_PIN_GROUP("lcd-generic", jz4760_lcd_generic, 0), 841 INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0, 0), 842 INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1, 0), 843 INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2, 0), 844 INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3, 0), 845 INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4, 0), 846 INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5, 0), 847 INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6, 0), 848 INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7, 0), 849 INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0), 850 }; 851 852 static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 853 static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 854 static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 855 static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 856 static const char *jz4760_mmc0_groups[] = { 857 "mmc0-1bit-a", "mmc0-4bit-a", 858 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e", 859 }; 860 static const char *jz4760_mmc1_groups[] = { 861 "mmc1-1bit-d", "mmc1-4bit-d", 862 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e", 863 }; 864 static const char *jz4760_mmc2_groups[] = { 865 "mmc2-1bit-b", "mmc2-4bit-b", 866 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e", 867 }; 868 static const char *jz4760_nemc_groups[] = { 869 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale", 870 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 871 }; 872 static const char *jz4760_cs1_groups[] = { "nemc-cs1", }; 873 static const char *jz4760_cs2_groups[] = { "nemc-cs2", }; 874 static const char *jz4760_cs3_groups[] = { "nemc-cs3", }; 875 static const char *jz4760_cs4_groups[] = { "nemc-cs4", }; 876 static const char *jz4760_cs5_groups[] = { "nemc-cs5", }; 877 static const char *jz4760_cs6_groups[] = { "nemc-cs6", }; 878 static const char *jz4760_i2c0_groups[] = { "i2c0-data", }; 879 static const char *jz4760_i2c1_groups[] = { "i2c1-data", }; 880 static const char *jz4760_cim_groups[] = { "cim-data", }; 881 static const char *jz4760_lcd_groups[] = { 882 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 883 "lcd-special", "lcd-generic", 884 }; 885 static const char *jz4760_pwm0_groups[] = { "pwm0", }; 886 static const char *jz4760_pwm1_groups[] = { "pwm1", }; 887 static const char *jz4760_pwm2_groups[] = { "pwm2", }; 888 static const char *jz4760_pwm3_groups[] = { "pwm3", }; 889 static const char *jz4760_pwm4_groups[] = { "pwm4", }; 890 static const char *jz4760_pwm5_groups[] = { "pwm5", }; 891 static const char *jz4760_pwm6_groups[] = { "pwm6", }; 892 static const char *jz4760_pwm7_groups[] = { "pwm7", }; 893 static const char *jz4760_otg_groups[] = { "otg-vbus", }; 894 895 static const struct function_desc jz4760_functions[] = { 896 { "uart0", jz4760_uart0_groups, ARRAY_SIZE(jz4760_uart0_groups), }, 897 { "uart1", jz4760_uart1_groups, ARRAY_SIZE(jz4760_uart1_groups), }, 898 { "uart2", jz4760_uart2_groups, ARRAY_SIZE(jz4760_uart2_groups), }, 899 { "uart3", jz4760_uart3_groups, ARRAY_SIZE(jz4760_uart3_groups), }, 900 { "mmc0", jz4760_mmc0_groups, ARRAY_SIZE(jz4760_mmc0_groups), }, 901 { "mmc1", jz4760_mmc1_groups, ARRAY_SIZE(jz4760_mmc1_groups), }, 902 { "mmc2", jz4760_mmc2_groups, ARRAY_SIZE(jz4760_mmc2_groups), }, 903 { "nemc", jz4760_nemc_groups, ARRAY_SIZE(jz4760_nemc_groups), }, 904 { "nemc-cs1", jz4760_cs1_groups, ARRAY_SIZE(jz4760_cs1_groups), }, 905 { "nemc-cs2", jz4760_cs2_groups, ARRAY_SIZE(jz4760_cs2_groups), }, 906 { "nemc-cs3", jz4760_cs3_groups, ARRAY_SIZE(jz4760_cs3_groups), }, 907 { "nemc-cs4", jz4760_cs4_groups, ARRAY_SIZE(jz4760_cs4_groups), }, 908 { "nemc-cs5", jz4760_cs5_groups, ARRAY_SIZE(jz4760_cs5_groups), }, 909 { "nemc-cs6", jz4760_cs6_groups, ARRAY_SIZE(jz4760_cs6_groups), }, 910 { "i2c0", jz4760_i2c0_groups, ARRAY_SIZE(jz4760_i2c0_groups), }, 911 { "i2c1", jz4760_i2c1_groups, ARRAY_SIZE(jz4760_i2c1_groups), }, 912 { "cim", jz4760_cim_groups, ARRAY_SIZE(jz4760_cim_groups), }, 913 { "lcd", jz4760_lcd_groups, ARRAY_SIZE(jz4760_lcd_groups), }, 914 { "pwm0", jz4760_pwm0_groups, ARRAY_SIZE(jz4760_pwm0_groups), }, 915 { "pwm1", jz4760_pwm1_groups, ARRAY_SIZE(jz4760_pwm1_groups), }, 916 { "pwm2", jz4760_pwm2_groups, ARRAY_SIZE(jz4760_pwm2_groups), }, 917 { "pwm3", jz4760_pwm3_groups, ARRAY_SIZE(jz4760_pwm3_groups), }, 918 { "pwm4", jz4760_pwm4_groups, ARRAY_SIZE(jz4760_pwm4_groups), }, 919 { "pwm5", jz4760_pwm5_groups, ARRAY_SIZE(jz4760_pwm5_groups), }, 920 { "pwm6", jz4760_pwm6_groups, ARRAY_SIZE(jz4760_pwm6_groups), }, 921 { "pwm7", jz4760_pwm7_groups, ARRAY_SIZE(jz4760_pwm7_groups), }, 922 { "otg", jz4760_otg_groups, ARRAY_SIZE(jz4760_otg_groups), }, 923 }; 924 925 static const struct ingenic_chip_info jz4760_chip_info = { 926 .num_chips = 6, 927 .reg_offset = 0x100, 928 .version = ID_JZ4760, 929 .groups = jz4760_groups, 930 .num_groups = ARRAY_SIZE(jz4760_groups), 931 .functions = jz4760_functions, 932 .num_functions = ARRAY_SIZE(jz4760_functions), 933 .pull_ups = jz4760_pull_ups, 934 .pull_downs = jz4760_pull_downs, 935 }; 936 937 static const u32 jz4770_pull_ups[6] = { 938 0x3fffffff, 0xfff0030c, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0xffa7f00f, 939 }; 940 941 static const u32 jz4770_pull_downs[6] = { 942 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0, 943 }; 944 945 static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, }; 946 static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; 947 static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, }; 948 static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; 949 static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, }; 950 static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, }; 951 static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, }; 952 static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, }; 953 static int jz4770_ssi0_dt_a_pins[] = { 0x15, }; 954 static int jz4770_ssi0_dt_b_pins[] = { 0x35, }; 955 static int jz4770_ssi0_dt_d_pins[] = { 0x75, }; 956 static int jz4770_ssi0_dt_e_pins[] = { 0x91, }; 957 static int jz4770_ssi0_dr_a_pins[] = { 0x14, }; 958 static int jz4770_ssi0_dr_b_pins[] = { 0x34, }; 959 static int jz4770_ssi0_dr_d_pins[] = { 0x74, }; 960 static int jz4770_ssi0_dr_e_pins[] = { 0x8e, }; 961 static int jz4770_ssi0_clk_a_pins[] = { 0x12, }; 962 static int jz4770_ssi0_clk_b_pins[] = { 0x3c, }; 963 static int jz4770_ssi0_clk_d_pins[] = { 0x78, }; 964 static int jz4770_ssi0_clk_e_pins[] = { 0x8f, }; 965 static int jz4770_ssi0_gpc_b_pins[] = { 0x3e, }; 966 static int jz4770_ssi0_gpc_d_pins[] = { 0x76, }; 967 static int jz4770_ssi0_gpc_e_pins[] = { 0x93, }; 968 static int jz4770_ssi0_ce0_a_pins[] = { 0x13, }; 969 static int jz4770_ssi0_ce0_b_pins[] = { 0x3d, }; 970 static int jz4770_ssi0_ce0_d_pins[] = { 0x79, }; 971 static int jz4770_ssi0_ce0_e_pins[] = { 0x90, }; 972 static int jz4770_ssi0_ce1_b_pins[] = { 0x3f, }; 973 static int jz4770_ssi0_ce1_d_pins[] = { 0x77, }; 974 static int jz4770_ssi0_ce1_e_pins[] = { 0x92, }; 975 static int jz4770_ssi1_dt_b_pins[] = { 0x35, }; 976 static int jz4770_ssi1_dt_d_pins[] = { 0x75, }; 977 static int jz4770_ssi1_dt_e_pins[] = { 0x91, }; 978 static int jz4770_ssi1_dr_b_pins[] = { 0x34, }; 979 static int jz4770_ssi1_dr_d_pins[] = { 0x74, }; 980 static int jz4770_ssi1_dr_e_pins[] = { 0x8e, }; 981 static int jz4770_ssi1_clk_b_pins[] = { 0x3c, }; 982 static int jz4770_ssi1_clk_d_pins[] = { 0x78, }; 983 static int jz4770_ssi1_clk_e_pins[] = { 0x8f, }; 984 static int jz4770_ssi1_gpc_b_pins[] = { 0x3e, }; 985 static int jz4770_ssi1_gpc_d_pins[] = { 0x76, }; 986 static int jz4770_ssi1_gpc_e_pins[] = { 0x93, }; 987 static int jz4770_ssi1_ce0_b_pins[] = { 0x3d, }; 988 static int jz4770_ssi1_ce0_d_pins[] = { 0x79, }; 989 static int jz4770_ssi1_ce0_e_pins[] = { 0x90, }; 990 static int jz4770_ssi1_ce1_b_pins[] = { 0x3f, }; 991 static int jz4770_ssi1_ce1_d_pins[] = { 0x77, }; 992 static int jz4770_ssi1_ce1_e_pins[] = { 0x92, }; 993 static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; 994 static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; 995 static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 996 static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 997 static int jz4770_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 998 static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; 999 static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; 1000 static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1001 static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1002 static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 1003 static int jz4770_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, }; 1004 static int jz4770_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, }; 1005 static int jz4770_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1006 static int jz4770_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1007 static int jz4770_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 1008 static int jz4770_nemc_8bit_data_pins[] = { 1009 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 1010 }; 1011 static int jz4770_nemc_16bit_data_pins[] = { 1012 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 1013 }; 1014 static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, }; 1015 static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; 1016 static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, }; 1017 static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; 1018 static int jz4770_nemc_wait_pins[] = { 0x1b, }; 1019 static int jz4770_nemc_cs1_pins[] = { 0x15, }; 1020 static int jz4770_nemc_cs2_pins[] = { 0x16, }; 1021 static int jz4770_nemc_cs3_pins[] = { 0x17, }; 1022 static int jz4770_nemc_cs4_pins[] = { 0x18, }; 1023 static int jz4770_nemc_cs5_pins[] = { 0x19, }; 1024 static int jz4770_nemc_cs6_pins[] = { 0x1a, }; 1025 static int jz4770_i2c0_pins[] = { 0x7e, 0x7f, }; 1026 static int jz4770_i2c1_pins[] = { 0x9e, 0x9f, }; 1027 static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, }; 1028 static int jz4770_cim_8bit_pins[] = { 1029 0x26, 0x27, 0x28, 0x29, 1030 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 1031 }; 1032 static int jz4770_cim_12bit_pins[] = { 1033 0x32, 0x33, 0xb0, 0xb1, 1034 }; 1035 static int jz4770_lcd_8bit_pins[] = { 1036 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d, 1037 0x48, 0x52, 0x53, 1038 }; 1039 static int jz4770_lcd_16bit_pins[] = { 1040 0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59, 1041 }; 1042 static int jz4770_lcd_18bit_pins[] = { 1043 0x5a, 0x5b, 1044 }; 1045 static int jz4770_lcd_24bit_pins[] = { 1046 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 1047 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 1048 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 1049 0x58, 0x59, 0x5a, 0x5b, 1050 }; 1051 static int jz4770_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, }; 1052 static int jz4770_lcd_generic_pins[] = { 0x49, }; 1053 static int jz4770_pwm_pwm0_pins[] = { 0x80, }; 1054 static int jz4770_pwm_pwm1_pins[] = { 0x81, }; 1055 static int jz4770_pwm_pwm2_pins[] = { 0x82, }; 1056 static int jz4770_pwm_pwm3_pins[] = { 0x83, }; 1057 static int jz4770_pwm_pwm4_pins[] = { 0x84, }; 1058 static int jz4770_pwm_pwm5_pins[] = { 0x85, }; 1059 static int jz4770_pwm_pwm6_pins[] = { 0x6a, }; 1060 static int jz4770_pwm_pwm7_pins[] = { 0x6b, }; 1061 static int jz4770_mac_rmii_pins[] = { 1062 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8, 1063 }; 1064 static int jz4770_mac_mii_pins[] = { 1065 0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf, 1066 }; 1067 1068 static const struct group_desc jz4770_groups[] = { 1069 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0), 1070 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0), 1071 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0), 1072 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0), 1073 INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data, 0), 1074 INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow, 0), 1075 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data, 1076 jz4760_uart3_data_funcs), 1077 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0), 1078 INGENIC_PIN_GROUP("ssi0-dt-a", jz4770_ssi0_dt_a, 2), 1079 INGENIC_PIN_GROUP("ssi0-dt-b", jz4770_ssi0_dt_b, 1), 1080 INGENIC_PIN_GROUP("ssi0-dt-d", jz4770_ssi0_dt_d, 1), 1081 INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0), 1082 INGENIC_PIN_GROUP("ssi0-dr-a", jz4770_ssi0_dr_a, 1), 1083 INGENIC_PIN_GROUP("ssi0-dr-b", jz4770_ssi0_dr_b, 1), 1084 INGENIC_PIN_GROUP("ssi0-dr-d", jz4770_ssi0_dr_d, 1), 1085 INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0), 1086 INGENIC_PIN_GROUP("ssi0-clk-a", jz4770_ssi0_clk_a, 2), 1087 INGENIC_PIN_GROUP("ssi0-clk-b", jz4770_ssi0_clk_b, 1), 1088 INGENIC_PIN_GROUP("ssi0-clk-d", jz4770_ssi0_clk_d, 1), 1089 INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0), 1090 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4770_ssi0_gpc_b, 1), 1091 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4770_ssi0_gpc_d, 1), 1092 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0), 1093 INGENIC_PIN_GROUP("ssi0-ce0-a", jz4770_ssi0_ce0_a, 2), 1094 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4770_ssi0_ce0_b, 1), 1095 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4770_ssi0_ce0_d, 1), 1096 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0), 1097 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4770_ssi0_ce1_b, 1), 1098 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4770_ssi0_ce1_d, 1), 1099 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0), 1100 INGENIC_PIN_GROUP("ssi1-dt-b", jz4770_ssi1_dt_b, 2), 1101 INGENIC_PIN_GROUP("ssi1-dt-d", jz4770_ssi1_dt_d, 2), 1102 INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1), 1103 INGENIC_PIN_GROUP("ssi1-dr-b", jz4770_ssi1_dr_b, 2), 1104 INGENIC_PIN_GROUP("ssi1-dr-d", jz4770_ssi1_dr_d, 2), 1105 INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1), 1106 INGENIC_PIN_GROUP("ssi1-clk-b", jz4770_ssi1_clk_b, 2), 1107 INGENIC_PIN_GROUP("ssi1-clk-d", jz4770_ssi1_clk_d, 2), 1108 INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1), 1109 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4770_ssi1_gpc_b, 2), 1110 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4770_ssi1_gpc_d, 2), 1111 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1), 1112 INGENIC_PIN_GROUP("ssi1-ce0-b", jz4770_ssi1_ce0_b, 2), 1113 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4770_ssi1_ce0_d, 2), 1114 INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1), 1115 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4770_ssi1_ce1_b, 2), 1116 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4770_ssi1_ce1_d, 2), 1117 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1), 1118 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a, 1119 jz4760_mmc0_1bit_a_funcs), 1120 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1), 1121 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0), 1122 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0), 1123 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e, 0), 1124 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0), 1125 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0), 1126 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1), 1127 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1), 1128 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e, 1), 1129 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0), 1130 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0), 1131 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2), 1132 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2), 1133 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e, 2), 1134 INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data, 0), 1135 INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data, 0), 1136 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0), 1137 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0), 1138 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0), 1139 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0), 1140 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0), 1141 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0), 1142 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0), 1143 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0), 1144 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0), 1145 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0), 1146 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0), 1147 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0), 1148 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0), 1149 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2), 1150 INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit, 0), 1151 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0), 1152 INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0), 1153 INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0), 1154 INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0), 1155 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0), 1156 INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1), 1157 INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0), 1158 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0), 1159 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0), 1160 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0), 1161 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0), 1162 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0), 1163 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0), 1164 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0), 1165 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0), 1166 INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii, 0), 1167 INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii, 0), 1168 INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0), 1169 }; 1170 1171 static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1172 static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 1173 static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 1174 static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 1175 static const char *jz4770_ssi0_groups[] = { 1176 "ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e", 1177 "ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e", 1178 "ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e", 1179 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e", 1180 "ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e", 1181 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e", 1182 }; 1183 static const char *jz4770_ssi1_groups[] = { 1184 "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e", 1185 "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e", 1186 "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e", 1187 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e", 1188 "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e", 1189 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e", 1190 }; 1191 static const char *jz4770_mmc0_groups[] = { 1192 "mmc0-1bit-a", "mmc0-4bit-a", 1193 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e", 1194 }; 1195 static const char *jz4770_mmc1_groups[] = { 1196 "mmc1-1bit-d", "mmc1-4bit-d", 1197 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e", 1198 }; 1199 static const char *jz4770_mmc2_groups[] = { 1200 "mmc2-1bit-b", "mmc2-4bit-b", 1201 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e", 1202 }; 1203 static const char *jz4770_nemc_groups[] = { 1204 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale", 1205 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 1206 }; 1207 static const char *jz4770_cs1_groups[] = { "nemc-cs1", }; 1208 static const char *jz4770_cs2_groups[] = { "nemc-cs2", }; 1209 static const char *jz4770_cs3_groups[] = { "nemc-cs3", }; 1210 static const char *jz4770_cs4_groups[] = { "nemc-cs4", }; 1211 static const char *jz4770_cs5_groups[] = { "nemc-cs5", }; 1212 static const char *jz4770_cs6_groups[] = { "nemc-cs6", }; 1213 static const char *jz4770_i2c0_groups[] = { "i2c0-data", }; 1214 static const char *jz4770_i2c1_groups[] = { "i2c1-data", }; 1215 static const char *jz4770_i2c2_groups[] = { "i2c2-data", }; 1216 static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", }; 1217 static const char *jz4770_lcd_groups[] = { 1218 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 1219 "lcd-special", "lcd-generic", 1220 }; 1221 static const char *jz4770_pwm0_groups[] = { "pwm0", }; 1222 static const char *jz4770_pwm1_groups[] = { "pwm1", }; 1223 static const char *jz4770_pwm2_groups[] = { "pwm2", }; 1224 static const char *jz4770_pwm3_groups[] = { "pwm3", }; 1225 static const char *jz4770_pwm4_groups[] = { "pwm4", }; 1226 static const char *jz4770_pwm5_groups[] = { "pwm5", }; 1227 static const char *jz4770_pwm6_groups[] = { "pwm6", }; 1228 static const char *jz4770_pwm7_groups[] = { "pwm7", }; 1229 static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", }; 1230 1231 static const struct function_desc jz4770_functions[] = { 1232 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), }, 1233 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), }, 1234 { "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), }, 1235 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), }, 1236 { "ssi0", jz4770_ssi0_groups, ARRAY_SIZE(jz4770_ssi0_groups), }, 1237 { "ssi1", jz4770_ssi1_groups, ARRAY_SIZE(jz4770_ssi1_groups), }, 1238 { "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), }, 1239 { "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), }, 1240 { "mmc2", jz4770_mmc2_groups, ARRAY_SIZE(jz4770_mmc2_groups), }, 1241 { "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), }, 1242 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), }, 1243 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), }, 1244 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), }, 1245 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), }, 1246 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), }, 1247 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), }, 1248 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), }, 1249 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), }, 1250 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), }, 1251 { "cim", jz4770_cim_groups, ARRAY_SIZE(jz4770_cim_groups), }, 1252 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), }, 1253 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), }, 1254 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), }, 1255 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), }, 1256 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), }, 1257 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), }, 1258 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), }, 1259 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), }, 1260 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), }, 1261 { "mac", jz4770_mac_groups, ARRAY_SIZE(jz4770_mac_groups), }, 1262 { "otg", jz4760_otg_groups, ARRAY_SIZE(jz4760_otg_groups), }, 1263 }; 1264 1265 static const struct ingenic_chip_info jz4770_chip_info = { 1266 .num_chips = 6, 1267 .reg_offset = 0x100, 1268 .version = ID_JZ4770, 1269 .groups = jz4770_groups, 1270 .num_groups = ARRAY_SIZE(jz4770_groups), 1271 .functions = jz4770_functions, 1272 .num_functions = ARRAY_SIZE(jz4770_functions), 1273 .pull_ups = jz4770_pull_ups, 1274 .pull_downs = jz4770_pull_downs, 1275 }; 1276 1277 static const u32 jz4775_pull_ups[7] = { 1278 0x28ff00ff, 0xf030f3fc, 0x0fffffff, 0xfffe4000, 0xf0f0000c, 0x0000f00f, 0x0000f3c0, 1279 }; 1280 1281 static const u32 jz4775_pull_downs[7] = { 1282 0x00000000, 0x00030c03, 0x00000000, 0x00008000, 0x00000403, 0x00000ff0, 0x00030c00, 1283 }; 1284 1285 static int jz4775_uart0_data_pins[] = { 0xa0, 0xa3, }; 1286 static int jz4775_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; 1287 static int jz4775_uart1_data_pins[] = { 0x7a, 0x7c, }; 1288 static int jz4775_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; 1289 static int jz4775_uart2_data_c_pins[] = { 0x54, 0x4a, }; 1290 static int jz4775_uart2_data_f_pins[] = { 0xa5, 0xa4, }; 1291 static int jz4775_uart3_data_pins[] = { 0x1e, 0x1f, }; 1292 static int jz4775_ssi_dt_a_pins[] = { 0x13, }; 1293 static int jz4775_ssi_dt_d_pins[] = { 0x75, }; 1294 static int jz4775_ssi_dr_a_pins[] = { 0x14, }; 1295 static int jz4775_ssi_dr_d_pins[] = { 0x74, }; 1296 static int jz4775_ssi_clk_a_pins[] = { 0x12, }; 1297 static int jz4775_ssi_clk_d_pins[] = { 0x78, }; 1298 static int jz4775_ssi_gpc_pins[] = { 0x76, }; 1299 static int jz4775_ssi_ce0_a_pins[] = { 0x17, }; 1300 static int jz4775_ssi_ce0_d_pins[] = { 0x79, }; 1301 static int jz4775_ssi_ce1_pins[] = { 0x77, }; 1302 static int jz4775_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; 1303 static int jz4775_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; 1304 static int jz4775_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, }; 1305 static int jz4775_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1306 static int jz4775_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1307 static int jz4775_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; 1308 static int jz4775_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; 1309 static int jz4775_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1310 static int jz4775_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1311 static int jz4775_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, }; 1312 static int jz4775_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, }; 1313 static int jz4775_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1314 static int jz4775_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1315 static int jz4775_nemc_8bit_data_pins[] = { 1316 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 1317 }; 1318 static int jz4775_nemc_16bit_data_pins[] = { 1319 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, 0xd0, 0xd1, 1320 }; 1321 static int jz4775_nemc_cle_ale_pins[] = { 0x20, 0x21, }; 1322 static int jz4775_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; 1323 static int jz4775_nemc_rd_we_pins[] = { 0x10, 0x11, }; 1324 static int jz4775_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; 1325 static int jz4775_nemc_wait_pins[] = { 0x1b, }; 1326 static int jz4775_nemc_cs1_pins[] = { 0x15, }; 1327 static int jz4775_nemc_cs2_pins[] = { 0x16, }; 1328 static int jz4775_nemc_cs3_pins[] = { 0x17, }; 1329 static int jz4775_i2c0_pins[] = { 0x7e, 0x7f, }; 1330 static int jz4775_i2c1_pins[] = { 0x9e, 0x9f, }; 1331 static int jz4775_i2c2_pins[] = { 0x80, 0x83, }; 1332 static int jz4775_i2s_data_tx_pins[] = { 0xa3, }; 1333 static int jz4775_i2s_data_rx_pins[] = { 0xa2, }; 1334 static int jz4775_i2s_clk_txrx_pins[] = { 0xa0, 0xa1, }; 1335 static int jz4775_i2s_sysclk_pins[] = { 0x83, }; 1336 static int jz4775_dmic_pins[] = { 0xaa, 0xab, }; 1337 static int jz4775_cim_pins[] = { 1338 0x26, 0x27, 0x28, 0x29, 1339 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 1340 }; 1341 static int jz4775_lcd_8bit_pins[] = { 1342 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d, 1343 0x48, 0x52, 0x53, 1344 }; 1345 static int jz4775_lcd_16bit_pins[] = { 1346 0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59, 1347 }; 1348 static int jz4775_lcd_18bit_pins[] = { 1349 0x5a, 0x5b, 1350 }; 1351 static int jz4775_lcd_24bit_pins[] = { 1352 0x40, 0x41, 0x4a, 0x4b, 0x54, 0x55, 1353 }; 1354 static int jz4775_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, }; 1355 static int jz4775_lcd_generic_pins[] = { 0x49, }; 1356 static int jz4775_pwm_pwm0_pins[] = { 0x80, }; 1357 static int jz4775_pwm_pwm1_pins[] = { 0x81, }; 1358 static int jz4775_pwm_pwm2_pins[] = { 0x82, }; 1359 static int jz4775_pwm_pwm3_pins[] = { 0x83, }; 1360 static int jz4775_mac_rmii_pins[] = { 1361 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8, 1362 }; 1363 static int jz4775_mac_mii_pins[] = { 1364 0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf, 1365 }; 1366 static int jz4775_mac_rgmii_pins[] = { 1367 0xa9, 0x7b, 0x7a, 0xab, 0xaa, 0xac, 0x7d, 0x7c, 0xa5, 0xa4, 1368 0xad, 0xae, 0xa7, 0xa6, 1369 }; 1370 static int jz4775_mac_gmii_pins[] = { 1371 0x31, 0x30, 0x2f, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 1372 0xa8, 0x28, 0x24, 0xaf, 1373 }; 1374 static int jz4775_otg_pins[] = { 0x8a, }; 1375 1376 static u8 jz4775_uart3_data_funcs[] = { 0, 1, }; 1377 static u8 jz4775_mac_mii_funcs[] = { 1, 1, 1, 1, 0, 1, 0, }; 1378 static u8 jz4775_mac_rgmii_funcs[] = { 1379 0, 1, 1, 0, 0, 0, 1, 1, 0, 0, 1380 0, 0, 0, 0, 1381 }; 1382 static u8 jz4775_mac_gmii_funcs[] = { 1383 1, 1, 1, 1, 1, 1, 1, 1, 1384 0, 1, 1, 0, 1385 }; 1386 1387 static const struct group_desc jz4775_groups[] = { 1388 INGENIC_PIN_GROUP("uart0-data", jz4775_uart0_data, 0), 1389 INGENIC_PIN_GROUP("uart0-hwflow", jz4775_uart0_hwflow, 0), 1390 INGENIC_PIN_GROUP("uart1-data", jz4775_uart1_data, 0), 1391 INGENIC_PIN_GROUP("uart1-hwflow", jz4775_uart1_hwflow, 0), 1392 INGENIC_PIN_GROUP("uart2-data-c", jz4775_uart2_data_c, 2), 1393 INGENIC_PIN_GROUP("uart2-data-f", jz4775_uart2_data_f, 1), 1394 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4775_uart3_data, 1395 jz4775_uart3_data_funcs), 1396 INGENIC_PIN_GROUP("ssi-dt-a", jz4775_ssi_dt_a, 2), 1397 INGENIC_PIN_GROUP("ssi-dt-d", jz4775_ssi_dt_d, 1), 1398 INGENIC_PIN_GROUP("ssi-dr-a", jz4775_ssi_dr_a, 2), 1399 INGENIC_PIN_GROUP("ssi-dr-d", jz4775_ssi_dr_d, 1), 1400 INGENIC_PIN_GROUP("ssi-clk-a", jz4775_ssi_clk_a, 2), 1401 INGENIC_PIN_GROUP("ssi-clk-d", jz4775_ssi_clk_d, 1), 1402 INGENIC_PIN_GROUP("ssi-gpc", jz4775_ssi_gpc, 1), 1403 INGENIC_PIN_GROUP("ssi-ce0-a", jz4775_ssi_ce0_a, 2), 1404 INGENIC_PIN_GROUP("ssi-ce0-d", jz4775_ssi_ce0_d, 1), 1405 INGENIC_PIN_GROUP("ssi-ce1", jz4775_ssi_ce1, 1), 1406 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4775_mmc0_1bit_a, 1), 1407 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4775_mmc0_4bit_a, 1), 1408 INGENIC_PIN_GROUP("mmc0-8bit-a", jz4775_mmc0_8bit_a, 1), 1409 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4775_mmc0_1bit_e, 0), 1410 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4775_mmc0_4bit_e, 0), 1411 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4775_mmc1_1bit_d, 0), 1412 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4775_mmc1_4bit_d, 0), 1413 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4775_mmc1_1bit_e, 1), 1414 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4775_mmc1_4bit_e, 1), 1415 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4775_mmc2_1bit_b, 0), 1416 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4775_mmc2_4bit_b, 0), 1417 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4775_mmc2_1bit_e, 2), 1418 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4775_mmc2_4bit_e, 2), 1419 INGENIC_PIN_GROUP("nemc-8bit-data", jz4775_nemc_8bit_data, 0), 1420 INGENIC_PIN_GROUP("nemc-16bit-data", jz4775_nemc_16bit_data, 1), 1421 INGENIC_PIN_GROUP("nemc-cle-ale", jz4775_nemc_cle_ale, 0), 1422 INGENIC_PIN_GROUP("nemc-addr", jz4775_nemc_addr, 0), 1423 INGENIC_PIN_GROUP("nemc-rd-we", jz4775_nemc_rd_we, 0), 1424 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4775_nemc_frd_fwe, 0), 1425 INGENIC_PIN_GROUP("nemc-wait", jz4775_nemc_wait, 0), 1426 INGENIC_PIN_GROUP("nemc-cs1", jz4775_nemc_cs1, 0), 1427 INGENIC_PIN_GROUP("nemc-cs2", jz4775_nemc_cs2, 0), 1428 INGENIC_PIN_GROUP("nemc-cs3", jz4775_nemc_cs3, 0), 1429 INGENIC_PIN_GROUP("i2c0-data", jz4775_i2c0, 0), 1430 INGENIC_PIN_GROUP("i2c1-data", jz4775_i2c1, 0), 1431 INGENIC_PIN_GROUP("i2c2-data", jz4775_i2c2, 1), 1432 INGENIC_PIN_GROUP("i2s-data-tx", jz4775_i2s_data_tx, 1), 1433 INGENIC_PIN_GROUP("i2s-data-rx", jz4775_i2s_data_rx, 1), 1434 INGENIC_PIN_GROUP("i2s-clk-txrx", jz4775_i2s_clk_txrx, 1), 1435 INGENIC_PIN_GROUP("i2s-sysclk", jz4775_i2s_sysclk, 2), 1436 INGENIC_PIN_GROUP("dmic", jz4775_dmic, 1), 1437 INGENIC_PIN_GROUP("cim-data", jz4775_cim, 0), 1438 INGENIC_PIN_GROUP("lcd-8bit", jz4775_lcd_8bit, 0), 1439 INGENIC_PIN_GROUP("lcd-16bit", jz4775_lcd_16bit, 0), 1440 INGENIC_PIN_GROUP("lcd-18bit", jz4775_lcd_18bit, 0), 1441 INGENIC_PIN_GROUP("lcd-24bit", jz4775_lcd_24bit, 0), 1442 INGENIC_PIN_GROUP("lcd-generic", jz4775_lcd_generic, 0), 1443 INGENIC_PIN_GROUP("lcd-special", jz4775_lcd_special, 1), 1444 INGENIC_PIN_GROUP("pwm0", jz4775_pwm_pwm0, 0), 1445 INGENIC_PIN_GROUP("pwm1", jz4775_pwm_pwm1, 0), 1446 INGENIC_PIN_GROUP("pwm2", jz4775_pwm_pwm2, 0), 1447 INGENIC_PIN_GROUP("pwm3", jz4775_pwm_pwm3, 0), 1448 INGENIC_PIN_GROUP("mac-rmii", jz4775_mac_rmii, 0), 1449 INGENIC_PIN_GROUP_FUNCS("mac-mii", jz4775_mac_mii, 1450 jz4775_mac_mii_funcs), 1451 INGENIC_PIN_GROUP_FUNCS("mac-rgmii", jz4775_mac_rgmii, 1452 jz4775_mac_rgmii_funcs), 1453 INGENIC_PIN_GROUP_FUNCS("mac-gmii", jz4775_mac_gmii, 1454 jz4775_mac_gmii_funcs), 1455 INGENIC_PIN_GROUP("otg-vbus", jz4775_otg, 0), 1456 }; 1457 1458 static const char *jz4775_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1459 static const char *jz4775_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 1460 static const char *jz4775_uart2_groups[] = { "uart2-data-c", "uart2-data-f", }; 1461 static const char *jz4775_uart3_groups[] = { "uart3-data", }; 1462 static const char *jz4775_ssi_groups[] = { 1463 "ssi-dt-a", "ssi-dt-d", 1464 "ssi-dr-a", "ssi-dr-d", 1465 "ssi-clk-a", "ssi-clk-d", 1466 "ssi-gpc", 1467 "ssi-ce0-a", "ssi-ce0-d", 1468 "ssi-ce1", 1469 }; 1470 static const char *jz4775_mmc0_groups[] = { 1471 "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a", 1472 "mmc0-1bit-e", "mmc0-4bit-e", 1473 }; 1474 static const char *jz4775_mmc1_groups[] = { 1475 "mmc1-1bit-d", "mmc1-4bit-d", 1476 "mmc1-1bit-e", "mmc1-4bit-e", 1477 }; 1478 static const char *jz4775_mmc2_groups[] = { 1479 "mmc2-1bit-b", "mmc2-4bit-b", 1480 "mmc2-1bit-e", "mmc2-4bit-e", 1481 }; 1482 static const char *jz4775_nemc_groups[] = { 1483 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale", 1484 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 1485 }; 1486 static const char *jz4775_cs1_groups[] = { "nemc-cs1", }; 1487 static const char *jz4775_cs2_groups[] = { "nemc-cs2", }; 1488 static const char *jz4775_cs3_groups[] = { "nemc-cs3", }; 1489 static const char *jz4775_i2c0_groups[] = { "i2c0-data", }; 1490 static const char *jz4775_i2c1_groups[] = { "i2c1-data", }; 1491 static const char *jz4775_i2c2_groups[] = { "i2c2-data", }; 1492 static const char *jz4775_i2s_groups[] = { 1493 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk", 1494 }; 1495 static const char *jz4775_dmic_groups[] = { "dmic", }; 1496 static const char *jz4775_cim_groups[] = { "cim-data", }; 1497 static const char *jz4775_lcd_groups[] = { 1498 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 1499 "lcd-special", "lcd-generic", 1500 }; 1501 static const char *jz4775_pwm0_groups[] = { "pwm0", }; 1502 static const char *jz4775_pwm1_groups[] = { "pwm1", }; 1503 static const char *jz4775_pwm2_groups[] = { "pwm2", }; 1504 static const char *jz4775_pwm3_groups[] = { "pwm3", }; 1505 static const char *jz4775_mac_groups[] = { 1506 "mac-rmii", "mac-mii", "mac-rgmii", "mac-gmii", 1507 }; 1508 static const char *jz4775_otg_groups[] = { "otg-vbus", }; 1509 1510 static const struct function_desc jz4775_functions[] = { 1511 { "uart0", jz4775_uart0_groups, ARRAY_SIZE(jz4775_uart0_groups), }, 1512 { "uart1", jz4775_uart1_groups, ARRAY_SIZE(jz4775_uart1_groups), }, 1513 { "uart2", jz4775_uart2_groups, ARRAY_SIZE(jz4775_uart2_groups), }, 1514 { "uart3", jz4775_uart3_groups, ARRAY_SIZE(jz4775_uart3_groups), }, 1515 { "ssi", jz4775_ssi_groups, ARRAY_SIZE(jz4775_ssi_groups), }, 1516 { "mmc0", jz4775_mmc0_groups, ARRAY_SIZE(jz4775_mmc0_groups), }, 1517 { "mmc1", jz4775_mmc1_groups, ARRAY_SIZE(jz4775_mmc1_groups), }, 1518 { "mmc2", jz4775_mmc2_groups, ARRAY_SIZE(jz4775_mmc2_groups), }, 1519 { "nemc", jz4775_nemc_groups, ARRAY_SIZE(jz4775_nemc_groups), }, 1520 { "nemc-cs1", jz4775_cs1_groups, ARRAY_SIZE(jz4775_cs1_groups), }, 1521 { "nemc-cs2", jz4775_cs2_groups, ARRAY_SIZE(jz4775_cs2_groups), }, 1522 { "nemc-cs3", jz4775_cs3_groups, ARRAY_SIZE(jz4775_cs3_groups), }, 1523 { "i2c0", jz4775_i2c0_groups, ARRAY_SIZE(jz4775_i2c0_groups), }, 1524 { "i2c1", jz4775_i2c1_groups, ARRAY_SIZE(jz4775_i2c1_groups), }, 1525 { "i2c2", jz4775_i2c2_groups, ARRAY_SIZE(jz4775_i2c2_groups), }, 1526 { "i2s", jz4775_i2s_groups, ARRAY_SIZE(jz4775_i2s_groups), }, 1527 { "dmic", jz4775_dmic_groups, ARRAY_SIZE(jz4775_dmic_groups), }, 1528 { "cim", jz4775_cim_groups, ARRAY_SIZE(jz4775_cim_groups), }, 1529 { "lcd", jz4775_lcd_groups, ARRAY_SIZE(jz4775_lcd_groups), }, 1530 { "pwm0", jz4775_pwm0_groups, ARRAY_SIZE(jz4775_pwm0_groups), }, 1531 { "pwm1", jz4775_pwm1_groups, ARRAY_SIZE(jz4775_pwm1_groups), }, 1532 { "pwm2", jz4775_pwm2_groups, ARRAY_SIZE(jz4775_pwm2_groups), }, 1533 { "pwm3", jz4775_pwm3_groups, ARRAY_SIZE(jz4775_pwm3_groups), }, 1534 { "mac", jz4775_mac_groups, ARRAY_SIZE(jz4775_mac_groups), }, 1535 { "otg", jz4775_otg_groups, ARRAY_SIZE(jz4775_otg_groups), }, 1536 }; 1537 1538 static const struct ingenic_chip_info jz4775_chip_info = { 1539 .num_chips = 7, 1540 .reg_offset = 0x100, 1541 .version = ID_JZ4775, 1542 .groups = jz4775_groups, 1543 .num_groups = ARRAY_SIZE(jz4775_groups), 1544 .functions = jz4775_functions, 1545 .num_functions = ARRAY_SIZE(jz4775_functions), 1546 .pull_ups = jz4775_pull_ups, 1547 .pull_downs = jz4775_pull_downs, 1548 }; 1549 1550 static const u32 jz4780_pull_ups[6] = { 1551 0x3fffffff, 0xfff0f3fc, 0x0fffffff, 0xffff4fff, 0xfffffb7c, 0x7fa7f00f, 1552 }; 1553 1554 static const u32 jz4780_pull_downs[6] = { 1555 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0, 1556 }; 1557 1558 static int jz4780_uart2_data_pins[] = { 0x66, 0x67, }; 1559 static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, }; 1560 static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, }; 1561 static int jz4780_ssi0_dt_a_19_pins[] = { 0x13, }; 1562 static int jz4780_ssi0_dt_a_21_pins[] = { 0x15, }; 1563 static int jz4780_ssi0_dt_a_28_pins[] = { 0x1c, }; 1564 static int jz4780_ssi0_dt_b_pins[] = { 0x3d, }; 1565 static int jz4780_ssi0_dt_d_pins[] = { 0x79, }; 1566 static int jz4780_ssi0_dr_a_20_pins[] = { 0x14, }; 1567 static int jz4780_ssi0_dr_a_27_pins[] = { 0x1b, }; 1568 static int jz4780_ssi0_dr_b_pins[] = { 0x34, }; 1569 static int jz4780_ssi0_dr_d_pins[] = { 0x74, }; 1570 static int jz4780_ssi0_clk_a_pins[] = { 0x12, }; 1571 static int jz4780_ssi0_clk_b_5_pins[] = { 0x25, }; 1572 static int jz4780_ssi0_clk_b_28_pins[] = { 0x3c, }; 1573 static int jz4780_ssi0_clk_d_pins[] = { 0x78, }; 1574 static int jz4780_ssi0_gpc_b_pins[] = { 0x3e, }; 1575 static int jz4780_ssi0_gpc_d_pins[] = { 0x76, }; 1576 static int jz4780_ssi0_ce0_a_23_pins[] = { 0x17, }; 1577 static int jz4780_ssi0_ce0_a_25_pins[] = { 0x19, }; 1578 static int jz4780_ssi0_ce0_b_pins[] = { 0x3f, }; 1579 static int jz4780_ssi0_ce0_d_pins[] = { 0x77, }; 1580 static int jz4780_ssi0_ce1_b_pins[] = { 0x35, }; 1581 static int jz4780_ssi0_ce1_d_pins[] = { 0x75, }; 1582 static int jz4780_ssi1_dt_b_pins[] = { 0x3d, }; 1583 static int jz4780_ssi1_dt_d_pins[] = { 0x79, }; 1584 static int jz4780_ssi1_dr_b_pins[] = { 0x34, }; 1585 static int jz4780_ssi1_dr_d_pins[] = { 0x74, }; 1586 static int jz4780_ssi1_clk_b_pins[] = { 0x3c, }; 1587 static int jz4780_ssi1_clk_d_pins[] = { 0x78, }; 1588 static int jz4780_ssi1_gpc_b_pins[] = { 0x3e, }; 1589 static int jz4780_ssi1_gpc_d_pins[] = { 0x76, }; 1590 static int jz4780_ssi1_ce0_b_pins[] = { 0x3f, }; 1591 static int jz4780_ssi1_ce0_d_pins[] = { 0x77, }; 1592 static int jz4780_ssi1_ce1_b_pins[] = { 0x35, }; 1593 static int jz4780_ssi1_ce1_d_pins[] = { 0x75, }; 1594 static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, }; 1595 static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, }; 1596 static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, }; 1597 static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, }; 1598 static int jz4780_i2s_data_tx_pins[] = { 0x87, }; 1599 static int jz4780_i2s_data_rx_pins[] = { 0x86, }; 1600 static int jz4780_i2s_clk_txrx_pins[] = { 0x6c, 0x6d, }; 1601 static int jz4780_i2s_clk_rx_pins[] = { 0x88, 0x89, }; 1602 static int jz4780_i2s_sysclk_pins[] = { 0x85, }; 1603 static int jz4780_dmic_pins[] = { 0x32, 0x33, }; 1604 static int jz4780_hdmi_ddc_pins[] = { 0xb9, 0xb8, }; 1605 1606 static u8 jz4780_i2s_clk_txrx_funcs[] = { 1, 0, }; 1607 1608 static const struct group_desc jz4780_groups[] = { 1609 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0), 1610 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0), 1611 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0), 1612 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0), 1613 INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data, 1), 1614 INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow, 1), 1615 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data, 1616 jz4760_uart3_data_funcs), 1617 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0), 1618 INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data, 2), 1619 INGENIC_PIN_GROUP("ssi0-dt-a-19", jz4780_ssi0_dt_a_19, 2), 1620 INGENIC_PIN_GROUP("ssi0-dt-a-21", jz4780_ssi0_dt_a_21, 2), 1621 INGENIC_PIN_GROUP("ssi0-dt-a-28", jz4780_ssi0_dt_a_28, 2), 1622 INGENIC_PIN_GROUP("ssi0-dt-b", jz4780_ssi0_dt_b, 1), 1623 INGENIC_PIN_GROUP("ssi0-dt-d", jz4780_ssi0_dt_d, 1), 1624 INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0), 1625 INGENIC_PIN_GROUP("ssi0-dr-a-20", jz4780_ssi0_dr_a_20, 2), 1626 INGENIC_PIN_GROUP("ssi0-dr-a-27", jz4780_ssi0_dr_a_27, 2), 1627 INGENIC_PIN_GROUP("ssi0-dr-b", jz4780_ssi0_dr_b, 1), 1628 INGENIC_PIN_GROUP("ssi0-dr-d", jz4780_ssi0_dr_d, 1), 1629 INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0), 1630 INGENIC_PIN_GROUP("ssi0-clk-a", jz4780_ssi0_clk_a, 2), 1631 INGENIC_PIN_GROUP("ssi0-clk-b-5", jz4780_ssi0_clk_b_5, 1), 1632 INGENIC_PIN_GROUP("ssi0-clk-b-28", jz4780_ssi0_clk_b_28, 1), 1633 INGENIC_PIN_GROUP("ssi0-clk-d", jz4780_ssi0_clk_d, 1), 1634 INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0), 1635 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4780_ssi0_gpc_b, 1), 1636 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4780_ssi0_gpc_d, 1), 1637 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0), 1638 INGENIC_PIN_GROUP("ssi0-ce0-a-23", jz4780_ssi0_ce0_a_23, 2), 1639 INGENIC_PIN_GROUP("ssi0-ce0-a-25", jz4780_ssi0_ce0_a_25, 2), 1640 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4780_ssi0_ce0_b, 1), 1641 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4780_ssi0_ce0_d, 1), 1642 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0), 1643 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4780_ssi0_ce1_b, 1), 1644 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4780_ssi0_ce1_d, 1), 1645 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0), 1646 INGENIC_PIN_GROUP("ssi1-dt-b", jz4780_ssi1_dt_b, 2), 1647 INGENIC_PIN_GROUP("ssi1-dt-d", jz4780_ssi1_dt_d, 2), 1648 INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1), 1649 INGENIC_PIN_GROUP("ssi1-dr-b", jz4780_ssi1_dr_b, 2), 1650 INGENIC_PIN_GROUP("ssi1-dr-d", jz4780_ssi1_dr_d, 2), 1651 INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1), 1652 INGENIC_PIN_GROUP("ssi1-clk-b", jz4780_ssi1_clk_b, 2), 1653 INGENIC_PIN_GROUP("ssi1-clk-d", jz4780_ssi1_clk_d, 2), 1654 INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1), 1655 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4780_ssi1_gpc_b, 2), 1656 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4780_ssi1_gpc_d, 2), 1657 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1), 1658 INGENIC_PIN_GROUP("ssi1-ce0-b", jz4780_ssi1_ce0_b, 2), 1659 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4780_ssi1_ce0_d, 2), 1660 INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1), 1661 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4780_ssi1_ce1_b, 2), 1662 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4780_ssi1_ce1_d, 2), 1663 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1), 1664 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a, 1665 jz4760_mmc0_1bit_a_funcs), 1666 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1), 1667 INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a, 1), 1668 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0), 1669 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0), 1670 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0), 1671 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0), 1672 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1), 1673 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1), 1674 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0), 1675 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0), 1676 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2), 1677 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2), 1678 INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data, 0), 1679 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0), 1680 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0), 1681 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0), 1682 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0), 1683 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0), 1684 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0), 1685 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0), 1686 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0), 1687 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0), 1688 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0), 1689 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0), 1690 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0), 1691 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0), 1692 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2), 1693 INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3, 1), 1694 INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e, 1), 1695 INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f, 1), 1696 INGENIC_PIN_GROUP("i2s-data-tx", jz4780_i2s_data_tx, 0), 1697 INGENIC_PIN_GROUP("i2s-data-rx", jz4780_i2s_data_rx, 0), 1698 INGENIC_PIN_GROUP_FUNCS("i2s-clk-txrx", jz4780_i2s_clk_txrx, 1699 jz4780_i2s_clk_txrx_funcs), 1700 INGENIC_PIN_GROUP("i2s-clk-rx", jz4780_i2s_clk_rx, 1), 1701 INGENIC_PIN_GROUP("i2s-sysclk", jz4780_i2s_sysclk, 2), 1702 INGENIC_PIN_GROUP("dmic", jz4780_dmic, 1), 1703 INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc, 0), 1704 INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit, 0), 1705 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0), 1706 INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0), 1707 INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0), 1708 INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0), 1709 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0), 1710 INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1), 1711 INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0), 1712 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0), 1713 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0), 1714 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0), 1715 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0), 1716 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0), 1717 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0), 1718 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0), 1719 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0), 1720 }; 1721 1722 static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 1723 static const char *jz4780_uart4_groups[] = { "uart4-data", }; 1724 static const char *jz4780_ssi0_groups[] = { 1725 "ssi0-dt-a-19", "ssi0-dt-a-21", "ssi0-dt-a-28", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e", 1726 "ssi0-dr-a-20", "ssi0-dr-a-27", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e", 1727 "ssi0-clk-a", "ssi0-clk-b-5", "ssi0-clk-b-28", "ssi0-clk-d", "ssi0-clk-e", 1728 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e", 1729 "ssi0-ce0-a-23", "ssi0-ce0-a-25", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e", 1730 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e", 1731 }; 1732 static const char *jz4780_ssi1_groups[] = { 1733 "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e", 1734 "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e", 1735 "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e", 1736 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e", 1737 "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e", 1738 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e", 1739 }; 1740 static const char *jz4780_mmc0_groups[] = { 1741 "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a", 1742 "mmc0-1bit-e", "mmc0-4bit-e", 1743 }; 1744 static const char *jz4780_mmc1_groups[] = { 1745 "mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e", 1746 }; 1747 static const char *jz4780_mmc2_groups[] = { 1748 "mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e", 1749 }; 1750 static const char *jz4780_nemc_groups[] = { 1751 "nemc-data", "nemc-cle-ale", "nemc-addr", 1752 "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 1753 }; 1754 static const char *jz4780_i2c3_groups[] = { "i2c3-data", }; 1755 static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", }; 1756 static const char *jz4780_i2s_groups[] = { 1757 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk", 1758 }; 1759 static const char *jz4780_dmic_groups[] = { "dmic", }; 1760 static const char *jz4780_cim_groups[] = { "cim-data", }; 1761 static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", }; 1762 1763 static const struct function_desc jz4780_functions[] = { 1764 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), }, 1765 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), }, 1766 { "uart2", jz4780_uart2_groups, ARRAY_SIZE(jz4780_uart2_groups), }, 1767 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), }, 1768 { "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), }, 1769 { "ssi0", jz4780_ssi0_groups, ARRAY_SIZE(jz4780_ssi0_groups), }, 1770 { "ssi1", jz4780_ssi1_groups, ARRAY_SIZE(jz4780_ssi1_groups), }, 1771 { "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), }, 1772 { "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), }, 1773 { "mmc2", jz4780_mmc2_groups, ARRAY_SIZE(jz4780_mmc2_groups), }, 1774 { "nemc", jz4780_nemc_groups, ARRAY_SIZE(jz4780_nemc_groups), }, 1775 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), }, 1776 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), }, 1777 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), }, 1778 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), }, 1779 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), }, 1780 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), }, 1781 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), }, 1782 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), }, 1783 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), }, 1784 { "i2c3", jz4780_i2c3_groups, ARRAY_SIZE(jz4780_i2c3_groups), }, 1785 { "i2c4", jz4780_i2c4_groups, ARRAY_SIZE(jz4780_i2c4_groups), }, 1786 { "i2s", jz4780_i2s_groups, ARRAY_SIZE(jz4780_i2s_groups), }, 1787 { "dmic", jz4780_dmic_groups, ARRAY_SIZE(jz4780_dmic_groups), }, 1788 { "cim", jz4780_cim_groups, ARRAY_SIZE(jz4780_cim_groups), }, 1789 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), }, 1790 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), }, 1791 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), }, 1792 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), }, 1793 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), }, 1794 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), }, 1795 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), }, 1796 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), }, 1797 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), }, 1798 { "hdmi-ddc", jz4780_hdmi_ddc_groups, 1799 ARRAY_SIZE(jz4780_hdmi_ddc_groups), }, 1800 }; 1801 1802 static const struct ingenic_chip_info jz4780_chip_info = { 1803 .num_chips = 6, 1804 .reg_offset = 0x100, 1805 .version = ID_JZ4780, 1806 .groups = jz4780_groups, 1807 .num_groups = ARRAY_SIZE(jz4780_groups), 1808 .functions = jz4780_functions, 1809 .num_functions = ARRAY_SIZE(jz4780_functions), 1810 .pull_ups = jz4780_pull_ups, 1811 .pull_downs = jz4780_pull_downs, 1812 }; 1813 1814 static const u32 x1000_pull_ups[4] = { 1815 0xffffffff, 0xfdffffff, 0x0dffffff, 0x0000003f, 1816 }; 1817 1818 static const u32 x1000_pull_downs[4] = { 1819 0x00000000, 0x02000000, 0x02000000, 0x00000000, 1820 }; 1821 1822 static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, }; 1823 static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, }; 1824 static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, }; 1825 static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, }; 1826 static int x1000_uart1_hwflow_pins[] = { 0x64, 0x65, }; 1827 static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, }; 1828 static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, }; 1829 static int x1000_sfc_pins[] = { 0x1d, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, }; 1830 static int x1000_ssi_dt_a_22_pins[] = { 0x16, }; 1831 static int x1000_ssi_dt_a_29_pins[] = { 0x1d, }; 1832 static int x1000_ssi_dt_d_pins[] = { 0x62, }; 1833 static int x1000_ssi_dr_a_23_pins[] = { 0x17, }; 1834 static int x1000_ssi_dr_a_28_pins[] = { 0x1c, }; 1835 static int x1000_ssi_dr_d_pins[] = { 0x63, }; 1836 static int x1000_ssi_clk_a_24_pins[] = { 0x18, }; 1837 static int x1000_ssi_clk_a_26_pins[] = { 0x1a, }; 1838 static int x1000_ssi_clk_d_pins[] = { 0x60, }; 1839 static int x1000_ssi_gpc_a_20_pins[] = { 0x14, }; 1840 static int x1000_ssi_gpc_a_31_pins[] = { 0x1f, }; 1841 static int x1000_ssi_ce0_a_25_pins[] = { 0x19, }; 1842 static int x1000_ssi_ce0_a_27_pins[] = { 0x1b, }; 1843 static int x1000_ssi_ce0_d_pins[] = { 0x61, }; 1844 static int x1000_ssi_ce1_a_21_pins[] = { 0x15, }; 1845 static int x1000_ssi_ce1_a_30_pins[] = { 0x1e, }; 1846 static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, }; 1847 static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, }; 1848 static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, }; 1849 static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, }; 1850 static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, }; 1851 static int x1000_emc_8bit_data_pins[] = { 1852 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 1853 }; 1854 static int x1000_emc_16bit_data_pins[] = { 1855 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 1856 }; 1857 static int x1000_emc_addr_pins[] = { 1858 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 1859 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 1860 }; 1861 static int x1000_emc_rd_we_pins[] = { 0x30, 0x31, }; 1862 static int x1000_emc_wait_pins[] = { 0x34, }; 1863 static int x1000_emc_cs1_pins[] = { 0x32, }; 1864 static int x1000_emc_cs2_pins[] = { 0x33, }; 1865 static int x1000_i2c0_pins[] = { 0x38, 0x37, }; 1866 static int x1000_i2c1_a_pins[] = { 0x01, 0x00, }; 1867 static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, }; 1868 static int x1000_i2c2_pins[] = { 0x61, 0x60, }; 1869 static int x1000_i2s_data_tx_pins[] = { 0x24, }; 1870 static int x1000_i2s_data_rx_pins[] = { 0x23, }; 1871 static int x1000_i2s_clk_txrx_pins[] = { 0x21, 0x22, }; 1872 static int x1000_i2s_sysclk_pins[] = { 0x20, }; 1873 static int x1000_dmic0_pins[] = { 0x35, 0x36, }; 1874 static int x1000_dmic1_pins[] = { 0x25, }; 1875 static int x1000_cim_pins[] = { 1876 0x08, 0x09, 0x0a, 0x0b, 1877 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 1878 }; 1879 static int x1000_lcd_8bit_pins[] = { 1880 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 1881 0x30, 0x31, 0x32, 0x33, 0x34, 1882 }; 1883 static int x1000_lcd_16bit_pins[] = { 1884 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 1885 }; 1886 static int x1000_pwm_pwm0_pins[] = { 0x59, }; 1887 static int x1000_pwm_pwm1_pins[] = { 0x5a, }; 1888 static int x1000_pwm_pwm2_pins[] = { 0x5b, }; 1889 static int x1000_pwm_pwm3_pins[] = { 0x26, }; 1890 static int x1000_pwm_pwm4_pins[] = { 0x58, }; 1891 static int x1000_mac_pins[] = { 1892 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x26, 1893 }; 1894 1895 static const struct group_desc x1000_groups[] = { 1896 INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data, 0), 1897 INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow, 0), 1898 INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a, 2), 1899 INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d, 1), 1900 INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow, 1), 1901 INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a, 2), 1902 INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d, 0), 1903 INGENIC_PIN_GROUP("sfc", x1000_sfc, 1), 1904 INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22, 2), 1905 INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29, 2), 1906 INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d, 0), 1907 INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23, 2), 1908 INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28, 2), 1909 INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d, 0), 1910 INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24, 2), 1911 INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26, 2), 1912 INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d, 0), 1913 INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20, 2), 1914 INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31, 2), 1915 INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25, 2), 1916 INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27, 2), 1917 INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d, 0), 1918 INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21, 2), 1919 INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30, 2), 1920 INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit, 1), 1921 INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit, 1), 1922 INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit, 1), 1923 INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit, 0), 1924 INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit, 0), 1925 INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data, 0), 1926 INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data, 0), 1927 INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr, 0), 1928 INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we, 0), 1929 INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait, 0), 1930 INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1, 0), 1931 INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2, 0), 1932 INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0, 0), 1933 INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a, 2), 1934 INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c, 0), 1935 INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2, 1), 1936 INGENIC_PIN_GROUP("i2s-data-tx", x1000_i2s_data_tx, 1), 1937 INGENIC_PIN_GROUP("i2s-data-rx", x1000_i2s_data_rx, 1), 1938 INGENIC_PIN_GROUP("i2s-clk-txrx", x1000_i2s_clk_txrx, 1), 1939 INGENIC_PIN_GROUP("i2s-sysclk", x1000_i2s_sysclk, 1), 1940 INGENIC_PIN_GROUP("dmic0", x1000_dmic0, 0), 1941 INGENIC_PIN_GROUP("dmic1", x1000_dmic1, 1), 1942 INGENIC_PIN_GROUP("cim-data", x1000_cim, 2), 1943 INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit, 1), 1944 INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit, 1), 1945 INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0, 0), 1946 INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1, 1), 1947 INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2, 1), 1948 INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3, 2), 1949 INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4, 0), 1950 INGENIC_PIN_GROUP("mac", x1000_mac, 1), 1951 }; 1952 1953 static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1954 static const char *x1000_uart1_groups[] = { 1955 "uart1-data-a", "uart1-data-d", "uart1-hwflow", 1956 }; 1957 static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; 1958 static const char *x1000_sfc_groups[] = { "sfc", }; 1959 static const char *x1000_ssi_groups[] = { 1960 "ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d", 1961 "ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d", 1962 "ssi-clk-a-24", "ssi-clk-a-26", "ssi-clk-d", 1963 "ssi-gpc-a-20", "ssi-gpc-a-31", 1964 "ssi-ce0-a-25", "ssi-ce0-a-27", "ssi-ce0-d", 1965 "ssi-ce1-a-21", "ssi-ce1-a-30", 1966 }; 1967 static const char *x1000_mmc0_groups[] = { 1968 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", 1969 }; 1970 static const char *x1000_mmc1_groups[] = { 1971 "mmc1-1bit", "mmc1-4bit", 1972 }; 1973 static const char *x1000_emc_groups[] = { 1974 "emc-8bit-data", "emc-16bit-data", 1975 "emc-addr", "emc-rd-we", "emc-wait", 1976 }; 1977 static const char *x1000_cs1_groups[] = { "emc-cs1", }; 1978 static const char *x1000_cs2_groups[] = { "emc-cs2", }; 1979 static const char *x1000_i2c0_groups[] = { "i2c0-data", }; 1980 static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; 1981 static const char *x1000_i2c2_groups[] = { "i2c2-data", }; 1982 static const char *x1000_i2s_groups[] = { 1983 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk", 1984 }; 1985 static const char *x1000_dmic_groups[] = { "dmic0", "dmic1", }; 1986 static const char *x1000_cim_groups[] = { "cim-data", }; 1987 static const char *x1000_lcd_groups[] = { "lcd-8bit", "lcd-16bit", }; 1988 static const char *x1000_pwm0_groups[] = { "pwm0", }; 1989 static const char *x1000_pwm1_groups[] = { "pwm1", }; 1990 static const char *x1000_pwm2_groups[] = { "pwm2", }; 1991 static const char *x1000_pwm3_groups[] = { "pwm3", }; 1992 static const char *x1000_pwm4_groups[] = { "pwm4", }; 1993 static const char *x1000_mac_groups[] = { "mac", }; 1994 1995 static const struct function_desc x1000_functions[] = { 1996 { "uart0", x1000_uart0_groups, ARRAY_SIZE(x1000_uart0_groups), }, 1997 { "uart1", x1000_uart1_groups, ARRAY_SIZE(x1000_uart1_groups), }, 1998 { "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), }, 1999 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), }, 2000 { "ssi", x1000_ssi_groups, ARRAY_SIZE(x1000_ssi_groups), }, 2001 { "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), }, 2002 { "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), }, 2003 { "emc", x1000_emc_groups, ARRAY_SIZE(x1000_emc_groups), }, 2004 { "emc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), }, 2005 { "emc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), }, 2006 { "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), }, 2007 { "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), }, 2008 { "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), }, 2009 { "i2s", x1000_i2s_groups, ARRAY_SIZE(x1000_i2s_groups), }, 2010 { "dmic", x1000_dmic_groups, ARRAY_SIZE(x1000_dmic_groups), }, 2011 { "cim", x1000_cim_groups, ARRAY_SIZE(x1000_cim_groups), }, 2012 { "lcd", x1000_lcd_groups, ARRAY_SIZE(x1000_lcd_groups), }, 2013 { "pwm0", x1000_pwm0_groups, ARRAY_SIZE(x1000_pwm0_groups), }, 2014 { "pwm1", x1000_pwm1_groups, ARRAY_SIZE(x1000_pwm1_groups), }, 2015 { "pwm2", x1000_pwm2_groups, ARRAY_SIZE(x1000_pwm2_groups), }, 2016 { "pwm3", x1000_pwm3_groups, ARRAY_SIZE(x1000_pwm3_groups), }, 2017 { "pwm4", x1000_pwm4_groups, ARRAY_SIZE(x1000_pwm4_groups), }, 2018 { "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), }, 2019 }; 2020 2021 static const struct ingenic_chip_info x1000_chip_info = { 2022 .num_chips = 4, 2023 .reg_offset = 0x100, 2024 .version = ID_X1000, 2025 .groups = x1000_groups, 2026 .num_groups = ARRAY_SIZE(x1000_groups), 2027 .functions = x1000_functions, 2028 .num_functions = ARRAY_SIZE(x1000_functions), 2029 .pull_ups = x1000_pull_ups, 2030 .pull_downs = x1000_pull_downs, 2031 }; 2032 2033 static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, }; 2034 static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, }; 2035 static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, }; 2036 static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, }; 2037 static int x1500_uart1_hwflow_pins[] = { 0x64, 0x65, }; 2038 static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, }; 2039 static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, }; 2040 static int x1500_mmc_1bit_pins[] = { 0x18, 0x19, 0x17, }; 2041 static int x1500_mmc_4bit_pins[] = { 0x16, 0x15, 0x14, }; 2042 static int x1500_i2c0_pins[] = { 0x38, 0x37, }; 2043 static int x1500_i2c1_a_pins[] = { 0x01, 0x00, }; 2044 static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, }; 2045 static int x1500_i2c2_pins[] = { 0x61, 0x60, }; 2046 static int x1500_i2s_data_tx_pins[] = { 0x24, }; 2047 static int x1500_i2s_data_rx_pins[] = { 0x23, }; 2048 static int x1500_i2s_clk_txrx_pins[] = { 0x21, 0x22, }; 2049 static int x1500_i2s_sysclk_pins[] = { 0x20, }; 2050 static int x1500_dmic0_pins[] = { 0x35, 0x36, }; 2051 static int x1500_dmic1_pins[] = { 0x25, }; 2052 static int x1500_cim_pins[] = { 2053 0x08, 0x09, 0x0a, 0x0b, 2054 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 2055 }; 2056 static int x1500_pwm_pwm0_pins[] = { 0x59, }; 2057 static int x1500_pwm_pwm1_pins[] = { 0x5a, }; 2058 static int x1500_pwm_pwm2_pins[] = { 0x5b, }; 2059 static int x1500_pwm_pwm3_pins[] = { 0x26, }; 2060 static int x1500_pwm_pwm4_pins[] = { 0x58, }; 2061 2062 static const struct group_desc x1500_groups[] = { 2063 INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data, 0), 2064 INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow, 0), 2065 INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a, 2), 2066 INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d, 1), 2067 INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow, 1), 2068 INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a, 2), 2069 INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d, 0), 2070 INGENIC_PIN_GROUP("sfc", x1000_sfc, 1), 2071 INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit, 1), 2072 INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit, 1), 2073 INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0, 0), 2074 INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a, 2), 2075 INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c, 0), 2076 INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2, 1), 2077 INGENIC_PIN_GROUP("i2s-data-tx", x1500_i2s_data_tx, 1), 2078 INGENIC_PIN_GROUP("i2s-data-rx", x1500_i2s_data_rx, 1), 2079 INGENIC_PIN_GROUP("i2s-clk-txrx", x1500_i2s_clk_txrx, 1), 2080 INGENIC_PIN_GROUP("i2s-sysclk", x1500_i2s_sysclk, 1), 2081 INGENIC_PIN_GROUP("dmic0", x1500_dmic0, 0), 2082 INGENIC_PIN_GROUP("dmic1", x1500_dmic1, 1), 2083 INGENIC_PIN_GROUP("cim-data", x1500_cim, 2), 2084 INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0, 0), 2085 INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1, 1), 2086 INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2, 1), 2087 INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3, 2), 2088 INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4, 0), 2089 }; 2090 2091 static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 2092 static const char *x1500_uart1_groups[] = { 2093 "uart1-data-a", "uart1-data-d", "uart1-hwflow", 2094 }; 2095 static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; 2096 static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; 2097 static const char *x1500_i2c0_groups[] = { "i2c0-data", }; 2098 static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; 2099 static const char *x1500_i2c2_groups[] = { "i2c2-data", }; 2100 static const char *x1500_i2s_groups[] = { 2101 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk", 2102 }; 2103 static const char *x1500_dmic_groups[] = { "dmic0", "dmic1", }; 2104 static const char *x1500_cim_groups[] = { "cim-data", }; 2105 static const char *x1500_pwm0_groups[] = { "pwm0", }; 2106 static const char *x1500_pwm1_groups[] = { "pwm1", }; 2107 static const char *x1500_pwm2_groups[] = { "pwm2", }; 2108 static const char *x1500_pwm3_groups[] = { "pwm3", }; 2109 static const char *x1500_pwm4_groups[] = { "pwm4", }; 2110 2111 static const struct function_desc x1500_functions[] = { 2112 { "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), }, 2113 { "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), }, 2114 { "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), }, 2115 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), }, 2116 { "mmc", x1500_mmc_groups, ARRAY_SIZE(x1500_mmc_groups), }, 2117 { "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), }, 2118 { "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), }, 2119 { "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), }, 2120 { "i2s", x1500_i2s_groups, ARRAY_SIZE(x1500_i2s_groups), }, 2121 { "dmic", x1500_dmic_groups, ARRAY_SIZE(x1500_dmic_groups), }, 2122 { "cim", x1500_cim_groups, ARRAY_SIZE(x1500_cim_groups), }, 2123 { "pwm0", x1500_pwm0_groups, ARRAY_SIZE(x1500_pwm0_groups), }, 2124 { "pwm1", x1500_pwm1_groups, ARRAY_SIZE(x1500_pwm1_groups), }, 2125 { "pwm2", x1500_pwm2_groups, ARRAY_SIZE(x1500_pwm2_groups), }, 2126 { "pwm3", x1500_pwm3_groups, ARRAY_SIZE(x1500_pwm3_groups), }, 2127 { "pwm4", x1500_pwm4_groups, ARRAY_SIZE(x1500_pwm4_groups), }, 2128 }; 2129 2130 static const struct ingenic_chip_info x1500_chip_info = { 2131 .num_chips = 4, 2132 .reg_offset = 0x100, 2133 .version = ID_X1500, 2134 .groups = x1500_groups, 2135 .num_groups = ARRAY_SIZE(x1500_groups), 2136 .functions = x1500_functions, 2137 .num_functions = ARRAY_SIZE(x1500_functions), 2138 .pull_ups = x1000_pull_ups, 2139 .pull_downs = x1000_pull_downs, 2140 }; 2141 2142 static const u32 x1830_pull_ups[4] = { 2143 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc, 2144 }; 2145 2146 static const u32 x1830_pull_downs[4] = { 2147 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc, 2148 }; 2149 2150 static int x1830_uart0_data_pins[] = { 0x33, 0x36, }; 2151 static int x1830_uart0_hwflow_pins[] = { 0x34, 0x35, }; 2152 static int x1830_uart1_data_pins[] = { 0x38, 0x37, }; 2153 static int x1830_sfc_pins[] = { 0x17, 0x18, 0x1a, 0x19, 0x1b, 0x1c, }; 2154 static int x1830_ssi0_dt_pins[] = { 0x4c, }; 2155 static int x1830_ssi0_dr_pins[] = { 0x4b, }; 2156 static int x1830_ssi0_clk_pins[] = { 0x4f, }; 2157 static int x1830_ssi0_gpc_pins[] = { 0x4d, }; 2158 static int x1830_ssi0_ce0_pins[] = { 0x50, }; 2159 static int x1830_ssi0_ce1_pins[] = { 0x4e, }; 2160 static int x1830_ssi1_dt_c_pins[] = { 0x53, }; 2161 static int x1830_ssi1_dt_d_pins[] = { 0x62, }; 2162 static int x1830_ssi1_dr_c_pins[] = { 0x54, }; 2163 static int x1830_ssi1_dr_d_pins[] = { 0x63, }; 2164 static int x1830_ssi1_clk_c_pins[] = { 0x57, }; 2165 static int x1830_ssi1_clk_d_pins[] = { 0x66, }; 2166 static int x1830_ssi1_gpc_c_pins[] = { 0x55, }; 2167 static int x1830_ssi1_gpc_d_pins[] = { 0x64, }; 2168 static int x1830_ssi1_ce0_c_pins[] = { 0x58, }; 2169 static int x1830_ssi1_ce0_d_pins[] = { 0x67, }; 2170 static int x1830_ssi1_ce1_c_pins[] = { 0x56, }; 2171 static int x1830_ssi1_ce1_d_pins[] = { 0x65, }; 2172 static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, }; 2173 static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, }; 2174 static int x1830_mmc1_1bit_pins[] = { 0x42, 0x43, 0x44, }; 2175 static int x1830_mmc1_4bit_pins[] = { 0x45, 0x46, 0x47, }; 2176 static int x1830_i2c0_pins[] = { 0x0c, 0x0d, }; 2177 static int x1830_i2c1_pins[] = { 0x39, 0x3a, }; 2178 static int x1830_i2c2_pins[] = { 0x5b, 0x5c, }; 2179 static int x1830_i2s_data_tx_pins[] = { 0x53, }; 2180 static int x1830_i2s_data_rx_pins[] = { 0x54, }; 2181 static int x1830_i2s_clk_txrx_pins[] = { 0x58, 0x52, }; 2182 static int x1830_i2s_clk_rx_pins[] = { 0x56, 0x55, }; 2183 static int x1830_i2s_sysclk_pins[] = { 0x57, }; 2184 static int x1830_dmic0_pins[] = { 0x48, 0x59, }; 2185 static int x1830_dmic1_pins[] = { 0x5a, }; 2186 static int x1830_lcd_tft_8bit_pins[] = { 2187 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 2188 0x68, 0x73, 0x72, 0x69, 2189 }; 2190 static int x1830_lcd_tft_24bit_pins[] = { 2191 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71, 2192 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, 2193 }; 2194 static int x1830_lcd_slcd_8bit_pins[] = { 2195 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x6c, 0x6d, 2196 0x69, 0x72, 0x73, 0x7b, 0x7a, 2197 }; 2198 static int x1830_lcd_slcd_16bit_pins[] = { 2199 0x6e, 0x6f, 0x70, 0x71, 0x76, 0x77, 0x78, 0x79, 2200 }; 2201 static int x1830_pwm_pwm0_b_pins[] = { 0x31, }; 2202 static int x1830_pwm_pwm0_c_pins[] = { 0x4b, }; 2203 static int x1830_pwm_pwm1_b_pins[] = { 0x32, }; 2204 static int x1830_pwm_pwm1_c_pins[] = { 0x4c, }; 2205 static int x1830_pwm_pwm2_c_8_pins[] = { 0x48, }; 2206 static int x1830_pwm_pwm2_c_13_pins[] = { 0x4d, }; 2207 static int x1830_pwm_pwm3_c_9_pins[] = { 0x49, }; 2208 static int x1830_pwm_pwm3_c_14_pins[] = { 0x4e, }; 2209 static int x1830_pwm_pwm4_c_15_pins[] = { 0x4f, }; 2210 static int x1830_pwm_pwm4_c_25_pins[] = { 0x59, }; 2211 static int x1830_pwm_pwm5_c_16_pins[] = { 0x50, }; 2212 static int x1830_pwm_pwm5_c_26_pins[] = { 0x5a, }; 2213 static int x1830_pwm_pwm6_c_17_pins[] = { 0x51, }; 2214 static int x1830_pwm_pwm6_c_27_pins[] = { 0x5b, }; 2215 static int x1830_pwm_pwm7_c_18_pins[] = { 0x52, }; 2216 static int x1830_pwm_pwm7_c_28_pins[] = { 0x5c, }; 2217 static int x1830_mac_pins[] = { 2218 0x29, 0x30, 0x2f, 0x28, 0x2e, 0x2d, 0x2a, 0x2b, 0x26, 0x27, 2219 }; 2220 2221 static const struct group_desc x1830_groups[] = { 2222 INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data, 0), 2223 INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow, 0), 2224 INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data, 0), 2225 INGENIC_PIN_GROUP("sfc", x1830_sfc, 1), 2226 INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt, 0), 2227 INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr, 0), 2228 INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk, 0), 2229 INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc, 0), 2230 INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0, 0), 2231 INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1, 0), 2232 INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c, 1), 2233 INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c, 1), 2234 INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c, 1), 2235 INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c, 1), 2236 INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c, 1), 2237 INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c, 1), 2238 INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d, 2), 2239 INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d, 2), 2240 INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d, 2), 2241 INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d, 2), 2242 INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d, 2), 2243 INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d, 2), 2244 INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit, 0), 2245 INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit, 0), 2246 INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit, 0), 2247 INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit, 0), 2248 INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0, 1), 2249 INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1, 0), 2250 INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2, 1), 2251 INGENIC_PIN_GROUP("i2s-data-tx", x1830_i2s_data_tx, 0), 2252 INGENIC_PIN_GROUP("i2s-data-rx", x1830_i2s_data_rx, 0), 2253 INGENIC_PIN_GROUP("i2s-clk-txrx", x1830_i2s_clk_txrx, 0), 2254 INGENIC_PIN_GROUP("i2s-clk-rx", x1830_i2s_clk_rx, 0), 2255 INGENIC_PIN_GROUP("i2s-sysclk", x1830_i2s_sysclk, 0), 2256 INGENIC_PIN_GROUP("dmic0", x1830_dmic0, 2), 2257 INGENIC_PIN_GROUP("dmic1", x1830_dmic1, 2), 2258 INGENIC_PIN_GROUP("lcd-tft-8bit", x1830_lcd_tft_8bit, 0), 2259 INGENIC_PIN_GROUP("lcd-tft-24bit", x1830_lcd_tft_24bit, 0), 2260 INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit, 1), 2261 INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit, 1), 2262 INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b, 0), 2263 INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c, 1), 2264 INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b, 0), 2265 INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c, 1), 2266 INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8, 0), 2267 INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13, 1), 2268 INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9, 0), 2269 INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14, 1), 2270 INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15, 1), 2271 INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25, 0), 2272 INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16, 1), 2273 INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26, 0), 2274 INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17, 1), 2275 INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27, 0), 2276 INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18, 1), 2277 INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28, 0), 2278 INGENIC_PIN_GROUP("mac", x1830_mac, 0), 2279 }; 2280 2281 static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 2282 static const char *x1830_uart1_groups[] = { "uart1-data", }; 2283 static const char *x1830_sfc_groups[] = { "sfc", }; 2284 static const char *x1830_ssi0_groups[] = { 2285 "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1", 2286 }; 2287 static const char *x1830_ssi1_groups[] = { 2288 "ssi1-dt-c", "ssi1-dt-d", 2289 "ssi1-dr-c", "ssi1-dr-d", 2290 "ssi1-clk-c", "ssi1-clk-d", 2291 "ssi1-gpc-c", "ssi1-gpc-d", 2292 "ssi1-ce0-c", "ssi1-ce0-d", 2293 "ssi1-ce1-c", "ssi1-ce1-d", 2294 }; 2295 static const char *x1830_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 2296 static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 2297 static const char *x1830_i2c0_groups[] = { "i2c0-data", }; 2298 static const char *x1830_i2c1_groups[] = { "i2c1-data", }; 2299 static const char *x1830_i2c2_groups[] = { "i2c2-data", }; 2300 static const char *x1830_i2s_groups[] = { 2301 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk", 2302 }; 2303 static const char *x1830_dmic_groups[] = { "dmic0", "dmic1", }; 2304 static const char *x1830_lcd_groups[] = { 2305 "lcd-tft-8bit", "lcd-tft-24bit", "lcd-slcd-8bit", "lcd-slcd-16bit", 2306 }; 2307 static const char *x1830_pwm0_groups[] = { "pwm0-b", "pwm0-c", }; 2308 static const char *x1830_pwm1_groups[] = { "pwm1-b", "pwm1-c", }; 2309 static const char *x1830_pwm2_groups[] = { "pwm2-c-8", "pwm2-c-13", }; 2310 static const char *x1830_pwm3_groups[] = { "pwm3-c-9", "pwm3-c-14", }; 2311 static const char *x1830_pwm4_groups[] = { "pwm4-c-15", "pwm4-c-25", }; 2312 static const char *x1830_pwm5_groups[] = { "pwm5-c-16", "pwm5-c-26", }; 2313 static const char *x1830_pwm6_groups[] = { "pwm6-c-17", "pwm6-c-27", }; 2314 static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", }; 2315 static const char *x1830_mac_groups[] = { "mac", }; 2316 2317 static const struct function_desc x1830_functions[] = { 2318 { "uart0", x1830_uart0_groups, ARRAY_SIZE(x1830_uart0_groups), }, 2319 { "uart1", x1830_uart1_groups, ARRAY_SIZE(x1830_uart1_groups), }, 2320 { "sfc", x1830_sfc_groups, ARRAY_SIZE(x1830_sfc_groups), }, 2321 { "ssi0", x1830_ssi0_groups, ARRAY_SIZE(x1830_ssi0_groups), }, 2322 { "ssi1", x1830_ssi1_groups, ARRAY_SIZE(x1830_ssi1_groups), }, 2323 { "mmc0", x1830_mmc0_groups, ARRAY_SIZE(x1830_mmc0_groups), }, 2324 { "mmc1", x1830_mmc1_groups, ARRAY_SIZE(x1830_mmc1_groups), }, 2325 { "i2c0", x1830_i2c0_groups, ARRAY_SIZE(x1830_i2c0_groups), }, 2326 { "i2c1", x1830_i2c1_groups, ARRAY_SIZE(x1830_i2c1_groups), }, 2327 { "i2c2", x1830_i2c2_groups, ARRAY_SIZE(x1830_i2c2_groups), }, 2328 { "i2s", x1830_i2s_groups, ARRAY_SIZE(x1830_i2s_groups), }, 2329 { "dmic", x1830_dmic_groups, ARRAY_SIZE(x1830_dmic_groups), }, 2330 { "lcd", x1830_lcd_groups, ARRAY_SIZE(x1830_lcd_groups), }, 2331 { "pwm0", x1830_pwm0_groups, ARRAY_SIZE(x1830_pwm0_groups), }, 2332 { "pwm1", x1830_pwm1_groups, ARRAY_SIZE(x1830_pwm1_groups), }, 2333 { "pwm2", x1830_pwm2_groups, ARRAY_SIZE(x1830_pwm2_groups), }, 2334 { "pwm3", x1830_pwm3_groups, ARRAY_SIZE(x1830_pwm3_groups), }, 2335 { "pwm4", x1830_pwm4_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 2336 { "pwm5", x1830_pwm5_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 2337 { "pwm6", x1830_pwm6_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 2338 { "pwm7", x1830_pwm7_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 2339 { "mac", x1830_mac_groups, ARRAY_SIZE(x1830_mac_groups), }, 2340 }; 2341 2342 static const struct ingenic_chip_info x1830_chip_info = { 2343 .num_chips = 4, 2344 .reg_offset = 0x1000, 2345 .version = ID_X1830, 2346 .groups = x1830_groups, 2347 .num_groups = ARRAY_SIZE(x1830_groups), 2348 .functions = x1830_functions, 2349 .num_functions = ARRAY_SIZE(x1830_functions), 2350 .pull_ups = x1830_pull_ups, 2351 .pull_downs = x1830_pull_downs, 2352 }; 2353 2354 static const u32 x2000_pull_ups[5] = { 2355 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0xc7fe3f3f, 0x8fff003f, 2356 }; 2357 2358 static const u32 x2000_pull_downs[5] = { 2359 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0x00000000, 0x8fff003f, 2360 }; 2361 2362 static int x2000_uart0_data_pins[] = { 0x77, 0x78, }; 2363 static int x2000_uart0_hwflow_pins[] = { 0x79, 0x7a, }; 2364 static int x2000_uart1_data_pins[] = { 0x57, 0x58, }; 2365 static int x2000_uart1_hwflow_pins[] = { 0x55, 0x56, }; 2366 static int x2000_uart2_data_pins[] = { 0x7e, 0x7f, }; 2367 static int x2000_uart3_data_c_pins[] = { 0x59, 0x5a, }; 2368 static int x2000_uart3_data_d_pins[] = { 0x62, 0x63, }; 2369 static int x2000_uart3_hwflow_c_pins[] = { 0x5b, 0x5c, }; 2370 static int x2000_uart3_hwflow_d_pins[] = { 0x60, 0x61, }; 2371 static int x2000_uart4_data_a_pins[] = { 0x02, 0x03, }; 2372 static int x2000_uart4_data_c_pins[] = { 0x4b, 0x4c, }; 2373 static int x2000_uart4_hwflow_a_pins[] = { 0x00, 0x01, }; 2374 static int x2000_uart4_hwflow_c_pins[] = { 0x49, 0x4a, }; 2375 static int x2000_uart5_data_a_pins[] = { 0x04, 0x05, }; 2376 static int x2000_uart5_data_c_pins[] = { 0x45, 0x46, }; 2377 static int x2000_uart6_data_a_pins[] = { 0x06, 0x07, }; 2378 static int x2000_uart6_data_c_pins[] = { 0x47, 0x48, }; 2379 static int x2000_uart7_data_a_pins[] = { 0x08, 0x09, }; 2380 static int x2000_uart7_data_c_pins[] = { 0x41, 0x42, }; 2381 static int x2000_uart8_data_pins[] = { 0x3c, 0x3d, }; 2382 static int x2000_uart9_data_pins[] = { 0x3e, 0x3f, }; 2383 static int x2000_sfc0_d_pins[] = { 0x73, 0x74, 0x75, 0x76, 0x71, 0x72, }; 2384 static int x2000_sfc0_e_pins[] = { 0x92, 0x93, 0x94, 0x95, 0x90, 0x91, }; 2385 static int x2000_sfc1_pins[] = { 0x77, 0x78, 0x79, 0x7a, }; 2386 static int x2000_ssi0_dt_b_pins[] = { 0x3e, }; 2387 static int x2000_ssi0_dt_d_pins[] = { 0x69, }; 2388 static int x2000_ssi0_dr_b_pins[] = { 0x3d, }; 2389 static int x2000_ssi0_dr_d_pins[] = { 0x6a, }; 2390 static int x2000_ssi0_clk_b_pins[] = { 0x3f, }; 2391 static int x2000_ssi0_clk_d_pins[] = { 0x68, }; 2392 static int x2000_ssi0_ce0_b_pins[] = { 0x3c, }; 2393 static int x2000_ssi0_ce0_d_pins[] = { 0x6d, }; 2394 static int x2000_ssi1_dt_c_pins[] = { 0x4b, }; 2395 static int x2000_ssi1_dt_d_pins[] = { 0x72, }; 2396 static int x2000_ssi1_dt_e_pins[] = { 0x91, }; 2397 static int x2000_ssi1_dr_c_pins[] = { 0x4a, }; 2398 static int x2000_ssi1_dr_d_pins[] = { 0x73, }; 2399 static int x2000_ssi1_dr_e_pins[] = { 0x92, }; 2400 static int x2000_ssi1_clk_c_pins[] = { 0x4c, }; 2401 static int x2000_ssi1_clk_d_pins[] = { 0x71, }; 2402 static int x2000_ssi1_clk_e_pins[] = { 0x90, }; 2403 static int x2000_ssi1_ce0_c_pins[] = { 0x49, }; 2404 static int x2000_ssi1_ce0_d_pins[] = { 0x76, }; 2405 static int x2000_ssi1_ce0_e_pins[] = { 0x95, }; 2406 static int x2000_mmc0_1bit_pins[] = { 0x71, 0x72, 0x73, }; 2407 static int x2000_mmc0_4bit_pins[] = { 0x74, 0x75, 0x75, }; 2408 static int x2000_mmc0_8bit_pins[] = { 0x77, 0x78, 0x79, 0x7a, }; 2409 static int x2000_mmc1_1bit_pins[] = { 0x68, 0x69, 0x6a, }; 2410 static int x2000_mmc1_4bit_pins[] = { 0x6b, 0x6c, 0x6d, }; 2411 static int x2000_mmc2_1bit_pins[] = { 0x80, 0x81, 0x82, }; 2412 static int x2000_mmc2_4bit_pins[] = { 0x83, 0x84, 0x85, }; 2413 static int x2000_emc_8bit_data_pins[] = { 2414 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 2415 }; 2416 static int x2000_emc_16bit_data_pins[] = { 2417 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, 2418 }; 2419 static int x2000_emc_addr_pins[] = { 2420 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 2421 0x28, 0x29, 0x2a, 0x2b, 0x2c, 2422 }; 2423 static int x2000_emc_rd_we_pins[] = { 0x2d, 0x2e, }; 2424 static int x2000_emc_wait_pins[] = { 0x2f, }; 2425 static int x2000_emc_cs1_pins[] = { 0x57, }; 2426 static int x2000_emc_cs2_pins[] = { 0x58, }; 2427 static int x2000_i2c0_pins[] = { 0x4e, 0x4d, }; 2428 static int x2000_i2c1_c_pins[] = { 0x58, 0x57, }; 2429 static int x2000_i2c1_d_pins[] = { 0x6c, 0x6b, }; 2430 static int x2000_i2c2_b_pins[] = { 0x37, 0x36, }; 2431 static int x2000_i2c2_d_pins[] = { 0x75, 0x74, }; 2432 static int x2000_i2c2_e_pins[] = { 0x94, 0x93, }; 2433 static int x2000_i2c3_a_pins[] = { 0x11, 0x10, }; 2434 static int x2000_i2c3_d_pins[] = { 0x7f, 0x7e, }; 2435 static int x2000_i2c4_c_pins[] = { 0x5a, 0x59, }; 2436 static int x2000_i2c4_d_pins[] = { 0x61, 0x60, }; 2437 static int x2000_i2c5_c_pins[] = { 0x5c, 0x5b, }; 2438 static int x2000_i2c5_d_pins[] = { 0x65, 0x64, }; 2439 static int x2000_i2s1_data_tx_pins[] = { 0x47, }; 2440 static int x2000_i2s1_data_rx_pins[] = { 0x44, }; 2441 static int x2000_i2s1_clk_tx_pins[] = { 0x45, 0x46, }; 2442 static int x2000_i2s1_clk_rx_pins[] = { 0x42, 0x43, }; 2443 static int x2000_i2s1_sysclk_tx_pins[] = { 0x48, }; 2444 static int x2000_i2s1_sysclk_rx_pins[] = { 0x41, }; 2445 static int x2000_i2s2_data_rx0_pins[] = { 0x0a, }; 2446 static int x2000_i2s2_data_rx1_pins[] = { 0x0b, }; 2447 static int x2000_i2s2_data_rx2_pins[] = { 0x0c, }; 2448 static int x2000_i2s2_data_rx3_pins[] = { 0x0d, }; 2449 static int x2000_i2s2_clk_rx_pins[] = { 0x11, 0x09, }; 2450 static int x2000_i2s2_sysclk_rx_pins[] = { 0x07, }; 2451 static int x2000_i2s3_data_tx0_pins[] = { 0x03, }; 2452 static int x2000_i2s3_data_tx1_pins[] = { 0x04, }; 2453 static int x2000_i2s3_data_tx2_pins[] = { 0x05, }; 2454 static int x2000_i2s3_data_tx3_pins[] = { 0x06, }; 2455 static int x2000_i2s3_clk_tx_pins[] = { 0x10, 0x02, }; 2456 static int x2000_i2s3_sysclk_tx_pins[] = { 0x00, }; 2457 static int x2000_dmic0_pins[] = { 0x54, 0x55, }; 2458 static int x2000_dmic1_pins[] = { 0x56, }; 2459 static int x2000_dmic2_pins[] = { 0x57, }; 2460 static int x2000_dmic3_pins[] = { 0x58, }; 2461 static int x2000_cim_8bit_pins[] = { 2462 0x0e, 0x0c, 0x0d, 0x4f, 2463 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 2464 }; 2465 static int x2000_cim_12bit_pins[] = { 0x08, 0x09, 0x0a, 0x0b, }; 2466 static int x2000_lcd_tft_8bit_pins[] = { 2467 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 2468 0x38, 0x3a, 0x39, 0x3b, 2469 }; 2470 static int x2000_lcd_tft_16bit_pins[] = { 2471 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 2472 }; 2473 static int x2000_lcd_tft_18bit_pins[] = { 2474 0x30, 0x31, 2475 }; 2476 static int x2000_lcd_tft_24bit_pins[] = { 2477 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 2478 }; 2479 static int x2000_lcd_slcd_8bit_pins[] = { 2480 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 2481 0x3a, 0x38, 0x3b, 0x30, 0x39, 2482 }; 2483 static int x2000_pwm_pwm0_c_pins[] = { 0x40, }; 2484 static int x2000_pwm_pwm0_d_pins[] = { 0x7e, }; 2485 static int x2000_pwm_pwm1_c_pins[] = { 0x41, }; 2486 static int x2000_pwm_pwm1_d_pins[] = { 0x7f, }; 2487 static int x2000_pwm_pwm2_c_pins[] = { 0x42, }; 2488 static int x2000_pwm_pwm2_e_pins[] = { 0x80, }; 2489 static int x2000_pwm_pwm3_c_pins[] = { 0x43, }; 2490 static int x2000_pwm_pwm3_e_pins[] = { 0x81, }; 2491 static int x2000_pwm_pwm4_c_pins[] = { 0x44, }; 2492 static int x2000_pwm_pwm4_e_pins[] = { 0x82, }; 2493 static int x2000_pwm_pwm5_c_pins[] = { 0x45, }; 2494 static int x2000_pwm_pwm5_e_pins[] = { 0x83, }; 2495 static int x2000_pwm_pwm6_c_pins[] = { 0x46, }; 2496 static int x2000_pwm_pwm6_e_pins[] = { 0x84, }; 2497 static int x2000_pwm_pwm7_c_pins[] = { 0x47, }; 2498 static int x2000_pwm_pwm7_e_pins[] = { 0x85, }; 2499 static int x2000_pwm_pwm8_pins[] = { 0x48, }; 2500 static int x2000_pwm_pwm9_pins[] = { 0x49, }; 2501 static int x2000_pwm_pwm10_pins[] = { 0x4a, }; 2502 static int x2000_pwm_pwm11_pins[] = { 0x4b, }; 2503 static int x2000_pwm_pwm12_pins[] = { 0x4c, }; 2504 static int x2000_pwm_pwm13_pins[] = { 0x4d, }; 2505 static int x2000_pwm_pwm14_pins[] = { 0x4e, }; 2506 static int x2000_pwm_pwm15_pins[] = { 0x4f, }; 2507 static int x2000_mac0_rmii_pins[] = { 2508 0x4b, 0x47, 0x46, 0x4a, 0x43, 0x42, 0x4c, 0x4d, 0x4e, 0x41, 2509 }; 2510 static int x2000_mac0_rgmii_pins[] = { 2511 0x4b, 0x49, 0x48, 0x47, 0x46, 0x4a, 0x45, 0x44, 0x43, 0x42, 2512 0x4c, 0x4d, 0x4f, 0x4e, 0x41, 2513 }; 2514 static int x2000_mac1_rmii_pins[] = { 2515 0x32, 0x2d, 0x2c, 0x31, 0x29, 0x28, 0x33, 0x34, 0x35, 0x37, 2516 }; 2517 static int x2000_mac1_rgmii_pins[] = { 2518 0x32, 0x2f, 0x2e, 0x2d, 0x2c, 0x31, 0x2b, 0x2a, 0x29, 0x28, 2519 0x33, 0x34, 0x36, 0x35, 0x37, 2520 }; 2521 static int x2000_otg_pins[] = { 0x96, }; 2522 2523 static u8 x2000_cim_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, }; 2524 2525 static const struct group_desc x2000_groups[] = { 2526 INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2), 2527 INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2), 2528 INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1), 2529 INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1), 2530 INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0), 2531 INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0), 2532 INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1), 2533 INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0), 2534 INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1), 2535 INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1), 2536 INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3), 2537 INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1), 2538 INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3), 2539 INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1), 2540 INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3), 2541 INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1), 2542 INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3), 2543 INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1), 2544 INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3), 2545 INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3), 2546 INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3), 2547 INGENIC_PIN_GROUP("sfc0-d", x2000_sfc0_d, 1), 2548 INGENIC_PIN_GROUP("sfc0-e", x2000_sfc0_e, 0), 2549 INGENIC_PIN_GROUP("sfc1", x2000_sfc1, 1), 2550 INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1), 2551 INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1), 2552 INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1), 2553 INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1), 2554 INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1), 2555 INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1), 2556 INGENIC_PIN_GROUP("ssi0-ce0-b", x2000_ssi0_ce0_b, 1), 2557 INGENIC_PIN_GROUP("ssi0-ce0-d", x2000_ssi0_ce0_d, 1), 2558 INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2), 2559 INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2), 2560 INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1), 2561 INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2), 2562 INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2), 2563 INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1), 2564 INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2), 2565 INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2), 2566 INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1), 2567 INGENIC_PIN_GROUP("ssi1-ce0-c", x2000_ssi1_ce0_c, 2), 2568 INGENIC_PIN_GROUP("ssi1-ce0-d", x2000_ssi1_ce0_d, 2), 2569 INGENIC_PIN_GROUP("ssi1-ce0-e", x2000_ssi1_ce0_e, 1), 2570 INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0), 2571 INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0), 2572 INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0), 2573 INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0), 2574 INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0), 2575 INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0), 2576 INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0), 2577 INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0), 2578 INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0), 2579 INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0), 2580 INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0), 2581 INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0), 2582 INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3), 2583 INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3), 2584 INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3), 2585 INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2), 2586 INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1), 2587 INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2), 2588 INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2), 2589 INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1), 2590 INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0), 2591 INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1), 2592 INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1), 2593 INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2), 2594 INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1), 2595 INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1), 2596 INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2), 2597 INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2), 2598 INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2), 2599 INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2), 2600 INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2), 2601 INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2), 2602 INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2), 2603 INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2), 2604 INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2), 2605 INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2), 2606 INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2), 2607 INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2), 2608 INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2), 2609 INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2), 2610 INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2), 2611 INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2), 2612 INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2), 2613 INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2), 2614 INGENIC_PIN_GROUP("dmic0", x2000_dmic0, 0), 2615 INGENIC_PIN_GROUP("dmic1", x2000_dmic1, 0), 2616 INGENIC_PIN_GROUP("dmic2", x2000_dmic2, 0), 2617 INGENIC_PIN_GROUP("dmic3", x2000_dmic3, 0), 2618 INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit, 2619 x2000_cim_8bit_funcs), 2620 INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0), 2621 INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1), 2622 INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1), 2623 INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1), 2624 INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1), 2625 INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2), 2626 INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2), 2627 INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0), 2628 INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2), 2629 INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0), 2630 INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2), 2631 INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0), 2632 INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1), 2633 INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0), 2634 INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1), 2635 INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0), 2636 INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1), 2637 INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0), 2638 INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1), 2639 INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0), 2640 INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1), 2641 INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0), 2642 INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1), 2643 INGENIC_PIN_GROUP("pwm8", x2000_pwm_pwm8, 0), 2644 INGENIC_PIN_GROUP("pwm9", x2000_pwm_pwm9, 0), 2645 INGENIC_PIN_GROUP("pwm10", x2000_pwm_pwm10, 0), 2646 INGENIC_PIN_GROUP("pwm11", x2000_pwm_pwm11, 0), 2647 INGENIC_PIN_GROUP("pwm12", x2000_pwm_pwm12, 0), 2648 INGENIC_PIN_GROUP("pwm13", x2000_pwm_pwm13, 0), 2649 INGENIC_PIN_GROUP("pwm14", x2000_pwm_pwm14, 0), 2650 INGENIC_PIN_GROUP("pwm15", x2000_pwm_pwm15, 0), 2651 INGENIC_PIN_GROUP("mac0-rmii", x2000_mac0_rmii, 1), 2652 INGENIC_PIN_GROUP("mac0-rgmii", x2000_mac0_rgmii, 1), 2653 INGENIC_PIN_GROUP("mac1-rmii", x2000_mac1_rmii, 3), 2654 INGENIC_PIN_GROUP("mac1-rgmii", x2000_mac1_rgmii, 3), 2655 INGENIC_PIN_GROUP("otg-vbus", x2000_otg, 0), 2656 }; 2657 2658 static const char *x2000_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 2659 static const char *x2000_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 2660 static const char *x2000_uart2_groups[] = { "uart2-data", }; 2661 static const char *x2000_uart3_groups[] = { 2662 "uart3-data-c", "uart3-data-d", "uart3-hwflow-c", "uart3-hwflow-d", 2663 }; 2664 static const char *x2000_uart4_groups[] = { 2665 "uart4-data-a", "uart4-data-c", "uart4-hwflow-a", "uart4-hwflow-c", 2666 }; 2667 static const char *x2000_uart5_groups[] = { "uart5-data-a", "uart5-data-c", }; 2668 static const char *x2000_uart6_groups[] = { "uart6-data-a", "uart6-data-c", }; 2669 static const char *x2000_uart7_groups[] = { "uart7-data-a", "uart7-data-c", }; 2670 static const char *x2000_uart8_groups[] = { "uart8-data", }; 2671 static const char *x2000_uart9_groups[] = { "uart9-data", }; 2672 static const char *x2000_sfc_groups[] = { "sfc0-d", "sfc0-e", "sfc1", }; 2673 static const char *x2000_ssi0_groups[] = { 2674 "ssi0-dt-b", "ssi0-dt-d", 2675 "ssi0-dr-b", "ssi0-dr-d", 2676 "ssi0-clk-b", "ssi0-clk-d", 2677 "ssi0-ce0-b", "ssi0-ce0-d", 2678 }; 2679 static const char *x2000_ssi1_groups[] = { 2680 "ssi1-dt-c", "ssi1-dt-d", "ssi1-dt-e", 2681 "ssi1-dr-c", "ssi1-dr-d", "ssi1-dr-e", 2682 "ssi1-clk-c", "ssi1-clk-d", "ssi1-clk-e", 2683 "ssi1-ce0-c", "ssi1-ce0-d", "ssi1-ce0-e", 2684 }; 2685 static const char *x2000_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", }; 2686 static const char *x2000_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 2687 static const char *x2000_mmc2_groups[] = { "mmc2-1bit", "mmc2-4bit", }; 2688 static const char *x2000_emc_groups[] = { 2689 "emc-8bit-data", "emc-16bit-data", 2690 "emc-addr", "emc-rd-we", "emc-wait", 2691 }; 2692 static const char *x2000_cs1_groups[] = { "emc-cs1", }; 2693 static const char *x2000_cs2_groups[] = { "emc-cs2", }; 2694 static const char *x2000_i2c0_groups[] = { "i2c0-data", }; 2695 static const char *x2000_i2c1_groups[] = { "i2c1-data-c", "i2c1-data-d", }; 2696 static const char *x2000_i2c2_groups[] = { "i2c2-data-b", "i2c2-data-d", }; 2697 static const char *x2000_i2c3_groups[] = { "i2c3-data-a", "i2c3-data-d", }; 2698 static const char *x2000_i2c4_groups[] = { "i2c4-data-c", "i2c4-data-d", }; 2699 static const char *x2000_i2c5_groups[] = { "i2c5-data-c", "i2c5-data-d", }; 2700 static const char *x2000_i2s1_groups[] = { 2701 "i2s1-data-tx", "i2s1-data-rx", 2702 "i2s1-clk-tx", "i2s1-clk-rx", 2703 "i2s1-sysclk-tx", "i2s1-sysclk-rx", 2704 }; 2705 static const char *x2000_i2s2_groups[] = { 2706 "i2s2-data-rx0", "i2s2-data-rx1", "i2s2-data-rx2", "i2s2-data-rx3", 2707 "i2s2-clk-rx", "i2s2-sysclk-rx", 2708 }; 2709 static const char *x2000_i2s3_groups[] = { 2710 "i2s3-data-tx0", "i2s3-data-tx1", "i2s3-data-tx2", "i2s3-data-tx3", 2711 "i2s3-clk-tx", "i2s3-sysclk-tx", 2712 }; 2713 static const char *x2000_dmic_groups[] = { "dmic0", "dmic1", "dmic2", "dmic3", }; 2714 static const char *x2000_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", }; 2715 static const char *x2000_lcd_groups[] = { 2716 "lcd-tft-8bit", "lcd-tft-16bit", "lcd-tft-18bit", "lcd-tft-24bit", 2717 "lcd-slcd-8bit", "lcd-slcd-16bit", 2718 }; 2719 static const char *x2000_pwm0_groups[] = { "pwm0-c", "pwm0-d", }; 2720 static const char *x2000_pwm1_groups[] = { "pwm1-c", "pwm1-d", }; 2721 static const char *x2000_pwm2_groups[] = { "pwm2-c", "pwm2-e", }; 2722 static const char *x2000_pwm3_groups[] = { "pwm3-c", "pwm3-r", }; 2723 static const char *x2000_pwm4_groups[] = { "pwm4-c", "pwm4-e", }; 2724 static const char *x2000_pwm5_groups[] = { "pwm5-c", "pwm5-e", }; 2725 static const char *x2000_pwm6_groups[] = { "pwm6-c", "pwm6-e", }; 2726 static const char *x2000_pwm7_groups[] = { "pwm7-c", "pwm7-e", }; 2727 static const char *x2000_pwm8_groups[] = { "pwm8", }; 2728 static const char *x2000_pwm9_groups[] = { "pwm9", }; 2729 static const char *x2000_pwm10_groups[] = { "pwm10", }; 2730 static const char *x2000_pwm11_groups[] = { "pwm11", }; 2731 static const char *x2000_pwm12_groups[] = { "pwm12", }; 2732 static const char *x2000_pwm13_groups[] = { "pwm13", }; 2733 static const char *x2000_pwm14_groups[] = { "pwm14", }; 2734 static const char *x2000_pwm15_groups[] = { "pwm15", }; 2735 static const char *x2000_mac0_groups[] = { "mac0-rmii", "mac0-rgmii", }; 2736 static const char *x2000_mac1_groups[] = { "mac1-rmii", "mac1-rgmii", }; 2737 static const char *x2000_otg_groups[] = { "otg-vbus", }; 2738 2739 static const struct function_desc x2000_functions[] = { 2740 { "uart0", x2000_uart0_groups, ARRAY_SIZE(x2000_uart0_groups), }, 2741 { "uart1", x2000_uart1_groups, ARRAY_SIZE(x2000_uart1_groups), }, 2742 { "uart2", x2000_uart2_groups, ARRAY_SIZE(x2000_uart2_groups), }, 2743 { "uart3", x2000_uart3_groups, ARRAY_SIZE(x2000_uart3_groups), }, 2744 { "uart4", x2000_uart4_groups, ARRAY_SIZE(x2000_uart4_groups), }, 2745 { "uart5", x2000_uart5_groups, ARRAY_SIZE(x2000_uart5_groups), }, 2746 { "uart6", x2000_uart6_groups, ARRAY_SIZE(x2000_uart6_groups), }, 2747 { "uart7", x2000_uart7_groups, ARRAY_SIZE(x2000_uart7_groups), }, 2748 { "uart8", x2000_uart8_groups, ARRAY_SIZE(x2000_uart8_groups), }, 2749 { "uart9", x2000_uart9_groups, ARRAY_SIZE(x2000_uart9_groups), }, 2750 { "sfc", x2000_sfc_groups, ARRAY_SIZE(x2000_sfc_groups), }, 2751 { "ssi0", x2000_ssi0_groups, ARRAY_SIZE(x2000_ssi0_groups), }, 2752 { "ssi1", x2000_ssi1_groups, ARRAY_SIZE(x2000_ssi1_groups), }, 2753 { "mmc0", x2000_mmc0_groups, ARRAY_SIZE(x2000_mmc0_groups), }, 2754 { "mmc1", x2000_mmc1_groups, ARRAY_SIZE(x2000_mmc1_groups), }, 2755 { "mmc2", x2000_mmc2_groups, ARRAY_SIZE(x2000_mmc2_groups), }, 2756 { "emc", x2000_emc_groups, ARRAY_SIZE(x2000_emc_groups), }, 2757 { "emc-cs1", x2000_cs1_groups, ARRAY_SIZE(x2000_cs1_groups), }, 2758 { "emc-cs2", x2000_cs2_groups, ARRAY_SIZE(x2000_cs2_groups), }, 2759 { "i2c0", x2000_i2c0_groups, ARRAY_SIZE(x2000_i2c0_groups), }, 2760 { "i2c1", x2000_i2c1_groups, ARRAY_SIZE(x2000_i2c1_groups), }, 2761 { "i2c2", x2000_i2c2_groups, ARRAY_SIZE(x2000_i2c2_groups), }, 2762 { "i2c3", x2000_i2c3_groups, ARRAY_SIZE(x2000_i2c3_groups), }, 2763 { "i2c4", x2000_i2c4_groups, ARRAY_SIZE(x2000_i2c4_groups), }, 2764 { "i2c5", x2000_i2c5_groups, ARRAY_SIZE(x2000_i2c5_groups), }, 2765 { "i2s1", x2000_i2s1_groups, ARRAY_SIZE(x2000_i2s1_groups), }, 2766 { "i2s2", x2000_i2s2_groups, ARRAY_SIZE(x2000_i2s2_groups), }, 2767 { "i2s3", x2000_i2s3_groups, ARRAY_SIZE(x2000_i2s3_groups), }, 2768 { "dmic", x2000_dmic_groups, ARRAY_SIZE(x2000_dmic_groups), }, 2769 { "cim", x2000_cim_groups, ARRAY_SIZE(x2000_cim_groups), }, 2770 { "lcd", x2000_lcd_groups, ARRAY_SIZE(x2000_lcd_groups), }, 2771 { "pwm0", x2000_pwm0_groups, ARRAY_SIZE(x2000_pwm0_groups), }, 2772 { "pwm1", x2000_pwm1_groups, ARRAY_SIZE(x2000_pwm1_groups), }, 2773 { "pwm2", x2000_pwm2_groups, ARRAY_SIZE(x2000_pwm2_groups), }, 2774 { "pwm3", x2000_pwm3_groups, ARRAY_SIZE(x2000_pwm3_groups), }, 2775 { "pwm4", x2000_pwm4_groups, ARRAY_SIZE(x2000_pwm4_groups), }, 2776 { "pwm5", x2000_pwm5_groups, ARRAY_SIZE(x2000_pwm5_groups), }, 2777 { "pwm6", x2000_pwm6_groups, ARRAY_SIZE(x2000_pwm6_groups), }, 2778 { "pwm7", x2000_pwm7_groups, ARRAY_SIZE(x2000_pwm7_groups), }, 2779 { "pwm8", x2000_pwm8_groups, ARRAY_SIZE(x2000_pwm8_groups), }, 2780 { "pwm9", x2000_pwm9_groups, ARRAY_SIZE(x2000_pwm9_groups), }, 2781 { "pwm10", x2000_pwm10_groups, ARRAY_SIZE(x2000_pwm10_groups), }, 2782 { "pwm11", x2000_pwm11_groups, ARRAY_SIZE(x2000_pwm11_groups), }, 2783 { "pwm12", x2000_pwm12_groups, ARRAY_SIZE(x2000_pwm12_groups), }, 2784 { "pwm13", x2000_pwm13_groups, ARRAY_SIZE(x2000_pwm13_groups), }, 2785 { "pwm14", x2000_pwm14_groups, ARRAY_SIZE(x2000_pwm14_groups), }, 2786 { "pwm15", x2000_pwm15_groups, ARRAY_SIZE(x2000_pwm15_groups), }, 2787 { "mac0", x2000_mac0_groups, ARRAY_SIZE(x2000_mac0_groups), }, 2788 { "mac1", x2000_mac1_groups, ARRAY_SIZE(x2000_mac1_groups), }, 2789 { "otg", x2000_otg_groups, ARRAY_SIZE(x2000_otg_groups), }, 2790 }; 2791 2792 static const struct ingenic_chip_info x2000_chip_info = { 2793 .num_chips = 5, 2794 .reg_offset = 0x100, 2795 .version = ID_X2000, 2796 .groups = x2000_groups, 2797 .num_groups = ARRAY_SIZE(x2000_groups), 2798 .functions = x2000_functions, 2799 .num_functions = ARRAY_SIZE(x2000_functions), 2800 .pull_ups = x2000_pull_ups, 2801 .pull_downs = x2000_pull_downs, 2802 }; 2803 2804 static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg) 2805 { 2806 unsigned int val; 2807 2808 regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val); 2809 2810 return (u32) val; 2811 } 2812 2813 static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc, 2814 u8 reg, u8 offset, bool set) 2815 { 2816 if (jzgc->jzpc->info->version == ID_JZ4730) { 2817 regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg, 2818 BIT(offset), set ? BIT(offset) : 0); 2819 return; 2820 } 2821 2822 if (set) 2823 reg = REG_SET(reg); 2824 else 2825 reg = REG_CLEAR(reg); 2826 2827 regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset)); 2828 } 2829 2830 static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc, 2831 u8 reg, u8 offset, bool set) 2832 { 2833 if (set) 2834 reg = REG_SET(reg); 2835 else 2836 reg = REG_CLEAR(reg); 2837 2838 regmap_write(jzgc->jzpc->map, REG_PZ_BASE( 2839 jzgc->jzpc->info->reg_offset) + reg, BIT(offset)); 2840 } 2841 2842 static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc) 2843 { 2844 regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD( 2845 jzgc->jzpc->info->reg_offset), 2846 jzgc->gc.base / PINS_PER_GPIO_CHIP); 2847 } 2848 2849 static void jz4730_gpio_set_bits(struct ingenic_gpio_chip *jzgc, 2850 u8 reg_upper, u8 reg_lower, u8 offset, u8 value) 2851 { 2852 /* 2853 * JZ4730 function and IRQ registers support two-bits-per-pin 2854 * definitions, split into two groups of 16. 2855 */ 2856 u8 reg = offset < JZ4730_PINS_PER_PAIRED_REG ? reg_lower : reg_upper; 2857 unsigned int idx = offset % JZ4730_PINS_PER_PAIRED_REG; 2858 unsigned int mask = GENMASK(1, 0) << idx * 2; 2859 2860 regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg, mask, value << (idx * 2)); 2861 } 2862 2863 static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc, 2864 u8 offset) 2865 { 2866 unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN); 2867 2868 return !!(val & BIT(offset)); 2869 } 2870 2871 static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc, 2872 u8 offset, int value) 2873 { 2874 if (jzgc->jzpc->info->version >= ID_JZ4770) 2875 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value); 2876 else if (jzgc->jzpc->info->version >= ID_JZ4740) 2877 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value); 2878 else 2879 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_DATA, offset, !!value); 2880 } 2881 2882 static void irq_set_type(struct ingenic_gpio_chip *jzgc, 2883 u8 offset, unsigned int type) 2884 { 2885 u8 reg1, reg2; 2886 bool val1, val2, val3; 2887 2888 switch (type) { 2889 case IRQ_TYPE_EDGE_BOTH: 2890 val1 = val2 = false; 2891 val3 = true; 2892 break; 2893 case IRQ_TYPE_EDGE_RISING: 2894 val1 = val2 = true; 2895 val3 = false; 2896 break; 2897 case IRQ_TYPE_EDGE_FALLING: 2898 val1 = val3 = false; 2899 val2 = true; 2900 break; 2901 case IRQ_TYPE_LEVEL_HIGH: 2902 val1 = true; 2903 val2 = val3 = false; 2904 break; 2905 case IRQ_TYPE_LEVEL_LOW: 2906 default: 2907 val1 = val2 = val3 = false; 2908 break; 2909 } 2910 2911 if (jzgc->jzpc->info->version >= ID_JZ4770) { 2912 reg1 = JZ4770_GPIO_PAT1; 2913 reg2 = JZ4770_GPIO_PAT0; 2914 } else if (jzgc->jzpc->info->version >= ID_JZ4740) { 2915 reg1 = JZ4740_GPIO_TRIG; 2916 reg2 = JZ4740_GPIO_DIR; 2917 } else { 2918 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPDIR, offset, false); 2919 jz4730_gpio_set_bits(jzgc, JZ4730_GPIO_GPIDUR, 2920 JZ4730_GPIO_GPIDLR, offset, (val2 << 1) | val1); 2921 return; 2922 } 2923 2924 if (jzgc->jzpc->info->version >= ID_X2000) { 2925 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1); 2926 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2); 2927 ingenic_gpio_shadow_set_bit_load(jzgc); 2928 ingenic_gpio_set_bit(jzgc, X2000_GPIO_EDG, offset, val3); 2929 } else if (jzgc->jzpc->info->version >= ID_X1000) { 2930 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1); 2931 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2); 2932 ingenic_gpio_shadow_set_bit_load(jzgc); 2933 } else { 2934 ingenic_gpio_set_bit(jzgc, reg2, offset, val1); 2935 ingenic_gpio_set_bit(jzgc, reg1, offset, val2); 2936 } 2937 } 2938 2939 static void ingenic_gpio_irq_mask(struct irq_data *irqd) 2940 { 2941 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 2942 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 2943 int irq = irqd->hwirq; 2944 2945 if (jzgc->jzpc->info->version >= ID_JZ4740) 2946 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, true); 2947 else 2948 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, true); 2949 } 2950 2951 static void ingenic_gpio_irq_unmask(struct irq_data *irqd) 2952 { 2953 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 2954 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 2955 int irq = irqd->hwirq; 2956 2957 if (jzgc->jzpc->info->version >= ID_JZ4740) 2958 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, false); 2959 else 2960 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, false); 2961 } 2962 2963 static void ingenic_gpio_irq_enable(struct irq_data *irqd) 2964 { 2965 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 2966 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 2967 int irq = irqd->hwirq; 2968 2969 if (jzgc->jzpc->info->version >= ID_JZ4770) 2970 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, true); 2971 else if (jzgc->jzpc->info->version >= ID_JZ4740) 2972 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true); 2973 else 2974 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, true); 2975 2976 ingenic_gpio_irq_unmask(irqd); 2977 } 2978 2979 static void ingenic_gpio_irq_disable(struct irq_data *irqd) 2980 { 2981 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 2982 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 2983 int irq = irqd->hwirq; 2984 2985 ingenic_gpio_irq_mask(irqd); 2986 2987 if (jzgc->jzpc->info->version >= ID_JZ4770) 2988 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, false); 2989 else if (jzgc->jzpc->info->version >= ID_JZ4740) 2990 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false); 2991 else 2992 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, false); 2993 } 2994 2995 static void ingenic_gpio_irq_ack(struct irq_data *irqd) 2996 { 2997 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 2998 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 2999 int irq = irqd->hwirq; 3000 bool high; 3001 3002 if ((irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) && 3003 (jzgc->jzpc->info->version < ID_X2000)) { 3004 /* 3005 * Switch to an interrupt for the opposite edge to the one that 3006 * triggered the interrupt being ACKed. 3007 */ 3008 high = ingenic_gpio_get_value(jzgc, irq); 3009 if (high) 3010 irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_LOW); 3011 else 3012 irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_HIGH); 3013 } 3014 3015 if (jzgc->jzpc->info->version >= ID_JZ4770) 3016 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false); 3017 else if (jzgc->jzpc->info->version >= ID_JZ4740) 3018 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true); 3019 else 3020 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPFR, irq, false); 3021 } 3022 3023 static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) 3024 { 3025 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 3026 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3027 3028 switch (type) { 3029 case IRQ_TYPE_EDGE_BOTH: 3030 case IRQ_TYPE_EDGE_RISING: 3031 case IRQ_TYPE_EDGE_FALLING: 3032 irq_set_handler_locked(irqd, handle_edge_irq); 3033 break; 3034 case IRQ_TYPE_LEVEL_HIGH: 3035 case IRQ_TYPE_LEVEL_LOW: 3036 irq_set_handler_locked(irqd, handle_level_irq); 3037 break; 3038 default: 3039 irq_set_handler_locked(irqd, handle_bad_irq); 3040 } 3041 3042 if ((type == IRQ_TYPE_EDGE_BOTH) && (jzgc->jzpc->info->version < ID_X2000)) { 3043 /* 3044 * The hardware does not support interrupts on both edges. The 3045 * best we can do is to set up a single-edge interrupt and then 3046 * switch to the opposing edge when ACKing the interrupt. 3047 */ 3048 bool high = ingenic_gpio_get_value(jzgc, irqd->hwirq); 3049 3050 type = high ? IRQ_TYPE_LEVEL_LOW : IRQ_TYPE_LEVEL_HIGH; 3051 } 3052 3053 irq_set_type(jzgc, irqd->hwirq, type); 3054 return 0; 3055 } 3056 3057 static int ingenic_gpio_irq_set_wake(struct irq_data *irqd, unsigned int on) 3058 { 3059 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 3060 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3061 3062 return irq_set_irq_wake(jzgc->irq, on); 3063 } 3064 3065 static void ingenic_gpio_irq_handler(struct irq_desc *desc) 3066 { 3067 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 3068 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3069 struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data); 3070 unsigned long flag, i; 3071 3072 chained_irq_enter(irq_chip, desc); 3073 3074 if (jzgc->jzpc->info->version >= ID_JZ4770) 3075 flag = ingenic_gpio_read_reg(jzgc, JZ4770_GPIO_FLAG); 3076 else if (jzgc->jzpc->info->version >= ID_JZ4740) 3077 flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG); 3078 else 3079 flag = ingenic_gpio_read_reg(jzgc, JZ4730_GPIO_GPFR); 3080 3081 for_each_set_bit(i, &flag, 32) 3082 generic_handle_irq(irq_linear_revmap(gc->irq.domain, i)); 3083 chained_irq_exit(irq_chip, desc); 3084 } 3085 3086 static void ingenic_gpio_set(struct gpio_chip *gc, 3087 unsigned int offset, int value) 3088 { 3089 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3090 3091 ingenic_gpio_set_value(jzgc, offset, value); 3092 } 3093 3094 static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset) 3095 { 3096 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3097 3098 return (int) ingenic_gpio_get_value(jzgc, offset); 3099 } 3100 3101 static int ingenic_gpio_direction_input(struct gpio_chip *gc, 3102 unsigned int offset) 3103 { 3104 return pinctrl_gpio_direction_input(gc->base + offset); 3105 } 3106 3107 static int ingenic_gpio_direction_output(struct gpio_chip *gc, 3108 unsigned int offset, int value) 3109 { 3110 ingenic_gpio_set(gc, offset, value); 3111 return pinctrl_gpio_direction_output(gc->base + offset); 3112 } 3113 3114 static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc, 3115 unsigned int pin, unsigned int reg, bool set) 3116 { 3117 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3118 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3119 3120 if (set) { 3121 if (jzpc->info->version >= ID_JZ4740) 3122 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 3123 REG_SET(reg), BIT(idx)); 3124 else 3125 regmap_set_bits(jzpc->map, offt * jzpc->info->reg_offset + 3126 reg, BIT(idx)); 3127 } else { 3128 if (jzpc->info->version >= ID_JZ4740) 3129 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 3130 REG_CLEAR(reg), BIT(idx)); 3131 else 3132 regmap_clear_bits(jzpc->map, offt * jzpc->info->reg_offset + 3133 reg, BIT(idx)); 3134 } 3135 } 3136 3137 static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc, 3138 unsigned int pin, u8 reg, bool set) 3139 { 3140 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3141 3142 regmap_write(jzpc->map, REG_PZ_BASE(jzpc->info->reg_offset) + 3143 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); 3144 } 3145 3146 static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc, 3147 unsigned int pin) 3148 { 3149 regmap_write(jzpc->map, REG_PZ_GID2LD(jzpc->info->reg_offset), 3150 pin / PINS_PER_GPIO_CHIP); 3151 } 3152 3153 static inline void jz4730_config_pin_function(struct ingenic_pinctrl *jzpc, 3154 unsigned int pin, u8 reg_upper, u8 reg_lower, u8 value) 3155 { 3156 /* 3157 * JZ4730 function and IRQ registers support two-bits-per-pin 3158 * definitions, split into two groups of 16. 3159 */ 3160 unsigned int idx = pin % JZ4730_PINS_PER_PAIRED_REG; 3161 unsigned int mask = GENMASK(1, 0) << idx * 2; 3162 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3163 u8 reg = (pin % PINS_PER_GPIO_CHIP) < JZ4730_PINS_PER_PAIRED_REG ? reg_lower : reg_upper; 3164 3165 regmap_update_bits(jzpc->map, offt * jzpc->info->reg_offset + reg, 3166 mask, value << (idx * 2)); 3167 } 3168 3169 static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc, 3170 unsigned int pin, unsigned int reg) 3171 { 3172 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3173 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3174 unsigned int val; 3175 3176 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + reg, &val); 3177 3178 return val & BIT(idx); 3179 } 3180 3181 static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 3182 { 3183 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3184 struct ingenic_pinctrl *jzpc = jzgc->jzpc; 3185 unsigned int pin = gc->base + offset; 3186 3187 if (jzpc->info->version >= ID_JZ4770) { 3188 if (ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_INT) || 3189 ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PAT1)) 3190 return GPIO_LINE_DIRECTION_IN; 3191 return GPIO_LINE_DIRECTION_OUT; 3192 } else if (jzpc->info->version == ID_JZ4730) { 3193 if (!ingenic_get_pin_config(jzpc, pin, JZ4730_GPIO_GPDIR)) 3194 return GPIO_LINE_DIRECTION_IN; 3195 return GPIO_LINE_DIRECTION_OUT; 3196 } 3197 3198 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT)) 3199 return GPIO_LINE_DIRECTION_IN; 3200 3201 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_DIR)) 3202 return GPIO_LINE_DIRECTION_OUT; 3203 3204 return GPIO_LINE_DIRECTION_IN; 3205 } 3206 3207 static const struct pinctrl_ops ingenic_pctlops = { 3208 .get_groups_count = pinctrl_generic_get_group_count, 3209 .get_group_name = pinctrl_generic_get_group_name, 3210 .get_group_pins = pinctrl_generic_get_group_pins, 3211 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 3212 .dt_free_map = pinconf_generic_dt_free_map, 3213 }; 3214 3215 static int ingenic_gpio_irq_request(struct irq_data *data) 3216 { 3217 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 3218 int ret; 3219 3220 ret = ingenic_gpio_direction_input(gpio_chip, data->hwirq); 3221 if (ret) 3222 return ret; 3223 3224 return gpiochip_reqres_irq(gpio_chip, data->hwirq); 3225 } 3226 3227 static void ingenic_gpio_irq_release(struct irq_data *data) 3228 { 3229 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 3230 3231 return gpiochip_relres_irq(gpio_chip, data->hwirq); 3232 } 3233 3234 static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc, 3235 int pin, int func) 3236 { 3237 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3238 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3239 3240 dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n", 3241 'A' + offt, idx, func); 3242 3243 if (jzpc->info->version >= ID_X1000) { 3244 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_INT, false); 3245 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false); 3246 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2); 3247 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1); 3248 ingenic_shadow_config_pin_load(jzpc, pin); 3249 } else if (jzpc->info->version >= ID_JZ4770) { 3250 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false); 3251 ingenic_config_pin(jzpc, pin, GPIO_MSK, false); 3252 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2); 3253 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1); 3254 } else if (jzpc->info->version >= ID_JZ4740) { 3255 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true); 3256 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2); 3257 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func & 0x1); 3258 } else { 3259 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPIER, false); 3260 jz4730_config_pin_function(jzpc, pin, JZ4730_GPIO_GPAUR, JZ4730_GPIO_GPALR, func); 3261 } 3262 3263 return 0; 3264 } 3265 3266 static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev, 3267 unsigned int selector, unsigned int group) 3268 { 3269 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 3270 struct function_desc *func; 3271 struct group_desc *grp; 3272 unsigned int i; 3273 uintptr_t mode; 3274 u8 *pin_modes; 3275 3276 func = pinmux_generic_get_function(pctldev, selector); 3277 if (!func) 3278 return -EINVAL; 3279 3280 grp = pinctrl_generic_get_group(pctldev, group); 3281 if (!grp) 3282 return -EINVAL; 3283 3284 dev_dbg(pctldev->dev, "enable function %s group %s\n", 3285 func->name, grp->name); 3286 3287 mode = (uintptr_t)grp->data; 3288 if (mode <= 3) { 3289 for (i = 0; i < grp->num_pins; i++) 3290 ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], mode); 3291 } else { 3292 pin_modes = grp->data; 3293 3294 for (i = 0; i < grp->num_pins; i++) 3295 ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]); 3296 } 3297 3298 return 0; 3299 } 3300 3301 static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, 3302 struct pinctrl_gpio_range *range, 3303 unsigned int pin, bool input) 3304 { 3305 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 3306 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3307 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3308 3309 dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n", 3310 'A' + offt, idx, input ? "in" : "out"); 3311 3312 if (jzpc->info->version >= ID_X1000) { 3313 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_INT, false); 3314 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true); 3315 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input); 3316 ingenic_shadow_config_pin_load(jzpc, pin); 3317 } else if (jzpc->info->version >= ID_JZ4770) { 3318 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false); 3319 ingenic_config_pin(jzpc, pin, GPIO_MSK, true); 3320 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input); 3321 } else if (jzpc->info->version >= ID_JZ4740) { 3322 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false); 3323 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input); 3324 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false); 3325 } else { 3326 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPIER, false); 3327 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPDIR, !input); 3328 jz4730_config_pin_function(jzpc, pin, JZ4730_GPIO_GPAUR, JZ4730_GPIO_GPALR, 0); 3329 } 3330 3331 return 0; 3332 } 3333 3334 static const struct pinmux_ops ingenic_pmxops = { 3335 .get_functions_count = pinmux_generic_get_function_count, 3336 .get_function_name = pinmux_generic_get_function_name, 3337 .get_function_groups = pinmux_generic_get_function_groups, 3338 .set_mux = ingenic_pinmux_set_mux, 3339 .gpio_set_direction = ingenic_pinmux_gpio_set_direction, 3340 }; 3341 3342 static int ingenic_pinconf_get(struct pinctrl_dev *pctldev, 3343 unsigned int pin, unsigned long *config) 3344 { 3345 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 3346 enum pin_config_param param = pinconf_to_config_param(*config); 3347 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3348 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3349 unsigned int arg = 1; 3350 unsigned int bias, reg; 3351 bool pull, pullup, pulldown; 3352 3353 if (jzpc->info->version >= ID_X2000) { 3354 pullup = ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPU) && 3355 !ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPD) && 3356 (jzpc->info->pull_ups[offt] & BIT(idx)); 3357 pulldown = ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPD) && 3358 !ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPU) && 3359 (jzpc->info->pull_downs[offt] & BIT(idx)); 3360 3361 } else if (jzpc->info->version >= ID_X1830) { 3362 unsigned int half = PINS_PER_GPIO_CHIP / 2; 3363 unsigned int idxh = (pin % half) * 2; 3364 3365 if (idx < half) 3366 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + 3367 X1830_GPIO_PEL, &bias); 3368 else 3369 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + 3370 X1830_GPIO_PEH, &bias); 3371 3372 bias = (bias >> idxh) & (GPIO_PULL_UP | GPIO_PULL_DOWN); 3373 3374 pullup = (bias == GPIO_PULL_UP) && (jzpc->info->pull_ups[offt] & BIT(idx)); 3375 pulldown = (bias == GPIO_PULL_DOWN) && (jzpc->info->pull_downs[offt] & BIT(idx)); 3376 3377 } else { 3378 if (jzpc->info->version >= ID_JZ4770) 3379 pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN); 3380 else if (jzpc->info->version >= ID_JZ4740) 3381 pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS); 3382 else 3383 pull = ingenic_get_pin_config(jzpc, pin, JZ4730_GPIO_GPPUR); 3384 3385 pullup = pull && (jzpc->info->pull_ups[offt] & BIT(idx)); 3386 pulldown = pull && (jzpc->info->pull_downs[offt] & BIT(idx)); 3387 } 3388 3389 switch (param) { 3390 case PIN_CONFIG_BIAS_DISABLE: 3391 if (pullup || pulldown) 3392 return -EINVAL; 3393 3394 break; 3395 3396 case PIN_CONFIG_BIAS_PULL_UP: 3397 if (!pullup) 3398 return -EINVAL; 3399 3400 break; 3401 3402 case PIN_CONFIG_BIAS_PULL_DOWN: 3403 if (!pulldown) 3404 return -EINVAL; 3405 3406 break; 3407 3408 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 3409 if (jzpc->info->version >= ID_X2000) 3410 reg = X2000_GPIO_SMT; 3411 else if (jzpc->info->version >= ID_X1830) 3412 reg = X1830_GPIO_SMT; 3413 else 3414 return -EINVAL; 3415 3416 arg = !!ingenic_get_pin_config(jzpc, pin, reg); 3417 break; 3418 3419 case PIN_CONFIG_SLEW_RATE: 3420 if (jzpc->info->version >= ID_X2000) 3421 reg = X2000_GPIO_SR; 3422 else if (jzpc->info->version >= ID_X1830) 3423 reg = X1830_GPIO_SR; 3424 else 3425 return -EINVAL; 3426 3427 arg = !!ingenic_get_pin_config(jzpc, pin, reg); 3428 break; 3429 3430 default: 3431 return -ENOTSUPP; 3432 } 3433 3434 *config = pinconf_to_config_packed(param, arg); 3435 return 0; 3436 } 3437 3438 static void ingenic_set_bias(struct ingenic_pinctrl *jzpc, 3439 unsigned int pin, unsigned int bias) 3440 { 3441 if (jzpc->info->version >= ID_X2000) { 3442 switch (bias) { 3443 case PIN_CONFIG_BIAS_PULL_UP: 3444 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false); 3445 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, true); 3446 break; 3447 3448 case PIN_CONFIG_BIAS_PULL_DOWN: 3449 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, false); 3450 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, true); 3451 break; 3452 3453 case PIN_CONFIG_BIAS_DISABLE: 3454 default: 3455 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, false); 3456 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false); 3457 } 3458 3459 } else if (jzpc->info->version >= ID_X1830) { 3460 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3461 unsigned int half = PINS_PER_GPIO_CHIP / 2; 3462 unsigned int idxh = (pin % half) * 2; 3463 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3464 3465 if (idx < half) { 3466 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 3467 REG_CLEAR(X1830_GPIO_PEL), 3 << idxh); 3468 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 3469 REG_SET(X1830_GPIO_PEL), bias << idxh); 3470 } else { 3471 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 3472 REG_CLEAR(X1830_GPIO_PEH), 3 << idxh); 3473 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 3474 REG_SET(X1830_GPIO_PEH), bias << idxh); 3475 } 3476 3477 } else if (jzpc->info->version >= ID_JZ4770) { 3478 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PEN, !bias); 3479 } else if (jzpc->info->version >= ID_JZ4740) { 3480 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !bias); 3481 } else { 3482 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPPUR, bias); 3483 } 3484 } 3485 3486 static void ingenic_set_schmitt_trigger(struct ingenic_pinctrl *jzpc, 3487 unsigned int pin, bool enable) 3488 { 3489 if (jzpc->info->version >= ID_X2000) 3490 ingenic_config_pin(jzpc, pin, X2000_GPIO_SMT, enable); 3491 else 3492 ingenic_config_pin(jzpc, pin, X1830_GPIO_SMT, enable); 3493 } 3494 3495 static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc, 3496 unsigned int pin, bool high) 3497 { 3498 if (jzpc->info->version >= ID_JZ4770) 3499 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, high); 3500 else if (jzpc->info->version >= ID_JZ4740) 3501 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DATA, high); 3502 else 3503 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_DATA, high); 3504 } 3505 3506 static void ingenic_set_slew_rate(struct ingenic_pinctrl *jzpc, 3507 unsigned int pin, unsigned int slew) 3508 { 3509 if (jzpc->info->version >= ID_X2000) 3510 ingenic_config_pin(jzpc, pin, X2000_GPIO_SR, slew); 3511 else 3512 ingenic_config_pin(jzpc, pin, X1830_GPIO_SR, slew); 3513 } 3514 3515 static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 3516 unsigned long *configs, unsigned int num_configs) 3517 { 3518 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 3519 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3520 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3521 unsigned int cfg, arg; 3522 int ret; 3523 3524 for (cfg = 0; cfg < num_configs; cfg++) { 3525 switch (pinconf_to_config_param(configs[cfg])) { 3526 case PIN_CONFIG_BIAS_DISABLE: 3527 case PIN_CONFIG_BIAS_PULL_UP: 3528 case PIN_CONFIG_BIAS_PULL_DOWN: 3529 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 3530 case PIN_CONFIG_OUTPUT: 3531 case PIN_CONFIG_SLEW_RATE: 3532 continue; 3533 default: 3534 return -ENOTSUPP; 3535 } 3536 } 3537 3538 for (cfg = 0; cfg < num_configs; cfg++) { 3539 arg = pinconf_to_config_argument(configs[cfg]); 3540 3541 switch (pinconf_to_config_param(configs[cfg])) { 3542 case PIN_CONFIG_BIAS_DISABLE: 3543 dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n", 3544 'A' + offt, idx); 3545 ingenic_set_bias(jzpc, pin, GPIO_PULL_DIS); 3546 break; 3547 3548 case PIN_CONFIG_BIAS_PULL_UP: 3549 if (!(jzpc->info->pull_ups[offt] & BIT(idx))) 3550 return -EINVAL; 3551 dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n", 3552 'A' + offt, idx); 3553 ingenic_set_bias(jzpc, pin, GPIO_PULL_UP); 3554 break; 3555 3556 case PIN_CONFIG_BIAS_PULL_DOWN: 3557 if (!(jzpc->info->pull_downs[offt] & BIT(idx))) 3558 return -EINVAL; 3559 dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n", 3560 'A' + offt, idx); 3561 ingenic_set_bias(jzpc, pin, GPIO_PULL_DOWN); 3562 break; 3563 3564 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 3565 if (jzpc->info->version < ID_X1830) 3566 return -EINVAL; 3567 3568 ingenic_set_schmitt_trigger(jzpc, pin, arg); 3569 break; 3570 3571 case PIN_CONFIG_OUTPUT: 3572 ret = pinctrl_gpio_direction_output(pin); 3573 if (ret) 3574 return ret; 3575 3576 ingenic_set_output_level(jzpc, pin, arg); 3577 break; 3578 3579 case PIN_CONFIG_SLEW_RATE: 3580 if (jzpc->info->version < ID_X1830) 3581 return -EINVAL; 3582 3583 ingenic_set_slew_rate(jzpc, pin, arg); 3584 break; 3585 3586 default: 3587 /* unreachable */ 3588 break; 3589 } 3590 } 3591 3592 return 0; 3593 } 3594 3595 static int ingenic_pinconf_group_get(struct pinctrl_dev *pctldev, 3596 unsigned int group, unsigned long *config) 3597 { 3598 const unsigned int *pins; 3599 unsigned int i, npins, old = 0; 3600 int ret; 3601 3602 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 3603 if (ret) 3604 return ret; 3605 3606 for (i = 0; i < npins; i++) { 3607 if (ingenic_pinconf_get(pctldev, pins[i], config)) 3608 return -ENOTSUPP; 3609 3610 /* configs do not match between two pins */ 3611 if (i && (old != *config)) 3612 return -ENOTSUPP; 3613 3614 old = *config; 3615 } 3616 3617 return 0; 3618 } 3619 3620 static int ingenic_pinconf_group_set(struct pinctrl_dev *pctldev, 3621 unsigned int group, unsigned long *configs, 3622 unsigned int num_configs) 3623 { 3624 const unsigned int *pins; 3625 unsigned int i, npins; 3626 int ret; 3627 3628 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 3629 if (ret) 3630 return ret; 3631 3632 for (i = 0; i < npins; i++) { 3633 ret = ingenic_pinconf_set(pctldev, 3634 pins[i], configs, num_configs); 3635 if (ret) 3636 return ret; 3637 } 3638 3639 return 0; 3640 } 3641 3642 static const struct pinconf_ops ingenic_confops = { 3643 .is_generic = true, 3644 .pin_config_get = ingenic_pinconf_get, 3645 .pin_config_set = ingenic_pinconf_set, 3646 .pin_config_group_get = ingenic_pinconf_group_get, 3647 .pin_config_group_set = ingenic_pinconf_group_set, 3648 }; 3649 3650 static const struct regmap_config ingenic_pinctrl_regmap_config = { 3651 .reg_bits = 32, 3652 .val_bits = 32, 3653 .reg_stride = 4, 3654 }; 3655 3656 static const struct of_device_id ingenic_gpio_of_match[] __initconst = { 3657 { .compatible = "ingenic,jz4730-gpio", }, 3658 { .compatible = "ingenic,jz4740-gpio", }, 3659 { .compatible = "ingenic,jz4725b-gpio", }, 3660 { .compatible = "ingenic,jz4750-gpio", }, 3661 { .compatible = "ingenic,jz4755-gpio", }, 3662 { .compatible = "ingenic,jz4760-gpio", }, 3663 { .compatible = "ingenic,jz4770-gpio", }, 3664 { .compatible = "ingenic,jz4775-gpio", }, 3665 { .compatible = "ingenic,jz4780-gpio", }, 3666 { .compatible = "ingenic,x1000-gpio", }, 3667 { .compatible = "ingenic,x1830-gpio", }, 3668 { .compatible = "ingenic,x2000-gpio", }, 3669 {}, 3670 }; 3671 3672 static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc, 3673 struct device_node *node) 3674 { 3675 struct ingenic_gpio_chip *jzgc; 3676 struct device *dev = jzpc->dev; 3677 struct gpio_irq_chip *girq; 3678 unsigned int bank; 3679 int err; 3680 3681 err = of_property_read_u32(node, "reg", &bank); 3682 if (err) { 3683 dev_err(dev, "Cannot read \"reg\" property: %i\n", err); 3684 return err; 3685 } 3686 3687 jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL); 3688 if (!jzgc) 3689 return -ENOMEM; 3690 3691 jzgc->jzpc = jzpc; 3692 jzgc->reg_base = bank * jzpc->info->reg_offset; 3693 3694 jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank); 3695 if (!jzgc->gc.label) 3696 return -ENOMEM; 3697 3698 /* DO NOT EXPAND THIS: FOR BACKWARD GPIO NUMBERSPACE COMPATIBIBILITY 3699 * ONLY: WORK TO TRANSITION CONSUMERS TO USE THE GPIO DESCRIPTOR API IN 3700 * <linux/gpio/consumer.h> INSTEAD. 3701 */ 3702 jzgc->gc.base = bank * 32; 3703 3704 jzgc->gc.ngpio = 32; 3705 jzgc->gc.parent = dev; 3706 jzgc->gc.of_node = node; 3707 jzgc->gc.owner = THIS_MODULE; 3708 3709 jzgc->gc.set = ingenic_gpio_set; 3710 jzgc->gc.get = ingenic_gpio_get; 3711 jzgc->gc.direction_input = ingenic_gpio_direction_input; 3712 jzgc->gc.direction_output = ingenic_gpio_direction_output; 3713 jzgc->gc.get_direction = ingenic_gpio_get_direction; 3714 jzgc->gc.request = gpiochip_generic_request; 3715 jzgc->gc.free = gpiochip_generic_free; 3716 3717 jzgc->irq = irq_of_parse_and_map(node, 0); 3718 if (!jzgc->irq) 3719 return -EINVAL; 3720 3721 jzgc->irq_chip.name = jzgc->gc.label; 3722 jzgc->irq_chip.irq_enable = ingenic_gpio_irq_enable; 3723 jzgc->irq_chip.irq_disable = ingenic_gpio_irq_disable; 3724 jzgc->irq_chip.irq_unmask = ingenic_gpio_irq_unmask; 3725 jzgc->irq_chip.irq_mask = ingenic_gpio_irq_mask; 3726 jzgc->irq_chip.irq_ack = ingenic_gpio_irq_ack; 3727 jzgc->irq_chip.irq_set_type = ingenic_gpio_irq_set_type; 3728 jzgc->irq_chip.irq_set_wake = ingenic_gpio_irq_set_wake; 3729 jzgc->irq_chip.irq_request_resources = ingenic_gpio_irq_request; 3730 jzgc->irq_chip.irq_release_resources = ingenic_gpio_irq_release; 3731 jzgc->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND; 3732 3733 girq = &jzgc->gc.irq; 3734 girq->chip = &jzgc->irq_chip; 3735 girq->parent_handler = ingenic_gpio_irq_handler; 3736 girq->num_parents = 1; 3737 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), 3738 GFP_KERNEL); 3739 if (!girq->parents) 3740 return -ENOMEM; 3741 3742 girq->parents[0] = jzgc->irq; 3743 girq->default_type = IRQ_TYPE_NONE; 3744 girq->handler = handle_level_irq; 3745 3746 err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc); 3747 if (err) 3748 return err; 3749 3750 return 0; 3751 } 3752 3753 static int __init ingenic_pinctrl_probe(struct platform_device *pdev) 3754 { 3755 struct device *dev = &pdev->dev; 3756 struct ingenic_pinctrl *jzpc; 3757 struct pinctrl_desc *pctl_desc; 3758 void __iomem *base; 3759 const struct ingenic_chip_info *chip_info; 3760 struct device_node *node; 3761 unsigned int i; 3762 int err; 3763 3764 chip_info = of_device_get_match_data(dev); 3765 if (!chip_info) { 3766 dev_err(dev, "Unsupported SoC\n"); 3767 return -EINVAL; 3768 } 3769 3770 jzpc = devm_kzalloc(dev, sizeof(*jzpc), GFP_KERNEL); 3771 if (!jzpc) 3772 return -ENOMEM; 3773 3774 base = devm_platform_ioremap_resource(pdev, 0); 3775 if (IS_ERR(base)) 3776 return PTR_ERR(base); 3777 3778 jzpc->map = devm_regmap_init_mmio(dev, base, 3779 &ingenic_pinctrl_regmap_config); 3780 if (IS_ERR(jzpc->map)) { 3781 dev_err(dev, "Failed to create regmap\n"); 3782 return PTR_ERR(jzpc->map); 3783 } 3784 3785 jzpc->dev = dev; 3786 jzpc->info = chip_info; 3787 3788 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL); 3789 if (!pctl_desc) 3790 return -ENOMEM; 3791 3792 /* fill in pinctrl_desc structure */ 3793 pctl_desc->name = dev_name(dev); 3794 pctl_desc->owner = THIS_MODULE; 3795 pctl_desc->pctlops = &ingenic_pctlops; 3796 pctl_desc->pmxops = &ingenic_pmxops; 3797 pctl_desc->confops = &ingenic_confops; 3798 pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP; 3799 pctl_desc->pins = jzpc->pdesc = devm_kcalloc(&pdev->dev, 3800 pctl_desc->npins, sizeof(*jzpc->pdesc), GFP_KERNEL); 3801 if (!jzpc->pdesc) 3802 return -ENOMEM; 3803 3804 for (i = 0; i < pctl_desc->npins; i++) { 3805 jzpc->pdesc[i].number = i; 3806 jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d", 3807 'A' + (i / PINS_PER_GPIO_CHIP), 3808 i % PINS_PER_GPIO_CHIP); 3809 } 3810 3811 jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc); 3812 if (IS_ERR(jzpc->pctl)) { 3813 dev_err(dev, "Failed to register pinctrl\n"); 3814 return PTR_ERR(jzpc->pctl); 3815 } 3816 3817 for (i = 0; i < chip_info->num_groups; i++) { 3818 const struct group_desc *group = &chip_info->groups[i]; 3819 3820 err = pinctrl_generic_add_group(jzpc->pctl, group->name, 3821 group->pins, group->num_pins, group->data); 3822 if (err < 0) { 3823 dev_err(dev, "Failed to register group %s\n", 3824 group->name); 3825 return err; 3826 } 3827 } 3828 3829 for (i = 0; i < chip_info->num_functions; i++) { 3830 const struct function_desc *func = &chip_info->functions[i]; 3831 3832 err = pinmux_generic_add_function(jzpc->pctl, func->name, 3833 func->group_names, func->num_group_names, 3834 func->data); 3835 if (err < 0) { 3836 dev_err(dev, "Failed to register function %s\n", 3837 func->name); 3838 return err; 3839 } 3840 } 3841 3842 dev_set_drvdata(dev, jzpc->map); 3843 3844 for_each_child_of_node(dev->of_node, node) { 3845 if (of_match_node(ingenic_gpio_of_match, node)) { 3846 err = ingenic_gpio_probe(jzpc, node); 3847 if (err) { 3848 of_node_put(node); 3849 return err; 3850 } 3851 } 3852 } 3853 3854 return 0; 3855 } 3856 3857 static const struct of_device_id ingenic_pinctrl_of_match[] = { 3858 { 3859 .compatible = "ingenic,jz4730-pinctrl", 3860 .data = IF_ENABLED(CONFIG_MACH_JZ4730, &jz4730_chip_info) 3861 }, 3862 { 3863 .compatible = "ingenic,jz4740-pinctrl", 3864 .data = IF_ENABLED(CONFIG_MACH_JZ4740, &jz4740_chip_info) 3865 }, 3866 { 3867 .compatible = "ingenic,jz4725b-pinctrl", 3868 .data = IF_ENABLED(CONFIG_MACH_JZ4725B, &jz4725b_chip_info) 3869 }, 3870 { 3871 .compatible = "ingenic,jz4750-pinctrl", 3872 .data = IF_ENABLED(CONFIG_MACH_JZ4750, &jz4750_chip_info) 3873 }, 3874 { 3875 .compatible = "ingenic,jz4755-pinctrl", 3876 .data = IF_ENABLED(CONFIG_MACH_JZ4755, &jz4755_chip_info) 3877 }, 3878 { 3879 .compatible = "ingenic,jz4760-pinctrl", 3880 .data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info) 3881 }, 3882 { 3883 .compatible = "ingenic,jz4760b-pinctrl", 3884 .data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info) 3885 }, 3886 { 3887 .compatible = "ingenic,jz4770-pinctrl", 3888 .data = IF_ENABLED(CONFIG_MACH_JZ4770, &jz4770_chip_info) 3889 }, 3890 { 3891 .compatible = "ingenic,jz4775-pinctrl", 3892 .data = IF_ENABLED(CONFIG_MACH_JZ4775, &jz4775_chip_info) 3893 }, 3894 { 3895 .compatible = "ingenic,jz4780-pinctrl", 3896 .data = IF_ENABLED(CONFIG_MACH_JZ4780, &jz4780_chip_info) 3897 }, 3898 { 3899 .compatible = "ingenic,x1000-pinctrl", 3900 .data = IF_ENABLED(CONFIG_MACH_X1000, &x1000_chip_info) 3901 }, 3902 { 3903 .compatible = "ingenic,x1000e-pinctrl", 3904 .data = IF_ENABLED(CONFIG_MACH_X1000, &x1000_chip_info) 3905 }, 3906 { 3907 .compatible = "ingenic,x1500-pinctrl", 3908 .data = IF_ENABLED(CONFIG_MACH_X1500, &x1500_chip_info) 3909 }, 3910 { 3911 .compatible = "ingenic,x1830-pinctrl", 3912 .data = IF_ENABLED(CONFIG_MACH_X1830, &x1830_chip_info) 3913 }, 3914 { 3915 .compatible = "ingenic,x2000-pinctrl", 3916 .data = IF_ENABLED(CONFIG_MACH_X2000, &x2000_chip_info) 3917 }, 3918 { 3919 .compatible = "ingenic,x2000e-pinctrl", 3920 .data = IF_ENABLED(CONFIG_MACH_X2000, &x2000_chip_info) 3921 }, 3922 { /* sentinel */ }, 3923 }; 3924 3925 static struct platform_driver ingenic_pinctrl_driver = { 3926 .driver = { 3927 .name = "pinctrl-ingenic", 3928 .of_match_table = ingenic_pinctrl_of_match, 3929 }, 3930 }; 3931 3932 static int __init ingenic_pinctrl_drv_register(void) 3933 { 3934 return platform_driver_probe(&ingenic_pinctrl_driver, 3935 ingenic_pinctrl_probe); 3936 } 3937 subsys_initcall(ingenic_pinctrl_drv_register); 3938