1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Ingenic SoCs pinctrl driver 4 * 5 * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net> 6 * Copyright (c) 2017, 2019 Paul Boddie <paul@boddie.org.uk> 7 * Copyright (c) 2019, 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> 8 */ 9 10 #include <linux/compiler.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/kernel.h> 15 #include <linux/of_device.h> 16 #include <linux/of_irq.h> 17 #include <linux/of_platform.h> 18 #include <linux/pinctrl/pinctrl.h> 19 #include <linux/pinctrl/pinmux.h> 20 #include <linux/pinctrl/pinconf.h> 21 #include <linux/pinctrl/pinconf-generic.h> 22 #include <linux/platform_device.h> 23 #include <linux/regmap.h> 24 #include <linux/slab.h> 25 26 #include "core.h" 27 #include "pinconf.h" 28 #include "pinmux.h" 29 30 #define GPIO_PIN 0x00 31 #define GPIO_MSK 0x20 32 33 #define JZ4730_GPIO_DATA 0x00 34 #define JZ4730_GPIO_GPDIR 0x04 35 #define JZ4730_GPIO_GPPUR 0x0c 36 #define JZ4730_GPIO_GPALR 0x10 37 #define JZ4730_GPIO_GPAUR 0x14 38 #define JZ4730_GPIO_GPIDLR 0x18 39 #define JZ4730_GPIO_GPIDUR 0x1c 40 #define JZ4730_GPIO_GPIER 0x20 41 #define JZ4730_GPIO_GPIMR 0x24 42 #define JZ4730_GPIO_GPFR 0x28 43 44 #define JZ4740_GPIO_DATA 0x10 45 #define JZ4740_GPIO_PULL_DIS 0x30 46 #define JZ4740_GPIO_FUNC 0x40 47 #define JZ4740_GPIO_SELECT 0x50 48 #define JZ4740_GPIO_DIR 0x60 49 #define JZ4740_GPIO_TRIG 0x70 50 #define JZ4740_GPIO_FLAG 0x80 51 52 #define JZ4770_GPIO_INT 0x10 53 #define JZ4770_GPIO_PAT1 0x30 54 #define JZ4770_GPIO_PAT0 0x40 55 #define JZ4770_GPIO_FLAG 0x50 56 #define JZ4770_GPIO_PEN 0x70 57 58 #define X1830_GPIO_PEL 0x110 59 #define X1830_GPIO_PEH 0x120 60 #define X1830_GPIO_SR 0x150 61 #define X1830_GPIO_SMT 0x160 62 63 #define X2000_GPIO_EDG 0x70 64 #define X2000_GPIO_PEPU 0x80 65 #define X2000_GPIO_PEPD 0x90 66 #define X2000_GPIO_SR 0xd0 67 #define X2000_GPIO_SMT 0xe0 68 69 #define REG_SET(x) ((x) + 0x4) 70 #define REG_CLEAR(x) ((x) + 0x8) 71 72 #define REG_PZ_BASE(x) ((x) * 7) 73 #define REG_PZ_GID2LD(x) ((x) * 7 + 0xf0) 74 75 #define GPIO_PULL_DIS 0 76 #define GPIO_PULL_UP 1 77 #define GPIO_PULL_DOWN 2 78 79 #define PINS_PER_GPIO_CHIP 32 80 #define JZ4730_PINS_PER_PAIRED_REG 16 81 82 #define INGENIC_PIN_GROUP_FUNCS(name, id, funcs) \ 83 { \ 84 name, \ 85 id##_pins, \ 86 ARRAY_SIZE(id##_pins), \ 87 funcs, \ 88 } 89 90 #define INGENIC_PIN_GROUP(name, id, func) \ 91 INGENIC_PIN_GROUP_FUNCS(name, id, (void *)(func)) 92 93 enum jz_version { 94 ID_JZ4730, 95 ID_JZ4740, 96 ID_JZ4725B, 97 ID_JZ4750, 98 ID_JZ4755, 99 ID_JZ4760, 100 ID_JZ4770, 101 ID_JZ4775, 102 ID_JZ4780, 103 ID_X1000, 104 ID_X1500, 105 ID_X1830, 106 ID_X2000, 107 ID_X2100, 108 }; 109 110 struct ingenic_chip_info { 111 unsigned int num_chips; 112 unsigned int reg_offset; 113 enum jz_version version; 114 115 const struct group_desc *groups; 116 unsigned int num_groups; 117 118 const struct function_desc *functions; 119 unsigned int num_functions; 120 121 const u32 *pull_ups, *pull_downs; 122 123 const struct regmap_access_table *access_table; 124 }; 125 126 struct ingenic_pinctrl { 127 struct device *dev; 128 struct regmap *map; 129 struct pinctrl_dev *pctl; 130 struct pinctrl_pin_desc *pdesc; 131 132 const struct ingenic_chip_info *info; 133 }; 134 135 struct ingenic_gpio_chip { 136 struct ingenic_pinctrl *jzpc; 137 struct gpio_chip gc; 138 struct irq_chip irq_chip; 139 unsigned int irq, reg_base; 140 }; 141 142 static const u32 jz4730_pull_ups[4] = { 143 0x3fa3320f, 0xf200ffff, 0xffffffff, 0xffffffff, 144 }; 145 146 static const u32 jz4730_pull_downs[4] = { 147 0x00000df0, 0x0dff0000, 0x00000000, 0x00000000, 148 }; 149 150 static int jz4730_mmc_1bit_pins[] = { 0x27, 0x26, 0x22, }; 151 static int jz4730_mmc_4bit_pins[] = { 0x23, 0x24, 0x25, }; 152 static int jz4730_uart0_data_pins[] = { 0x7e, 0x7f, }; 153 static int jz4730_uart1_data_pins[] = { 0x18, 0x19, }; 154 static int jz4730_uart2_data_pins[] = { 0x6f, 0x7d, }; 155 static int jz4730_uart3_data_pins[] = { 0x10, 0x15, }; 156 static int jz4730_uart3_hwflow_pins[] = { 0x11, 0x17, }; 157 static int jz4730_lcd_8bit_pins[] = { 158 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 159 0x3a, 0x39, 0x38, 160 }; 161 static int jz4730_lcd_16bit_pins[] = { 162 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 163 }; 164 static int jz4730_lcd_special_pins[] = { 0x3d, 0x3c, 0x3e, 0x3f, }; 165 static int jz4730_lcd_generic_pins[] = { 0x3b, }; 166 static int jz4730_nand_cs1_pins[] = { 0x53, }; 167 static int jz4730_nand_cs2_pins[] = { 0x54, }; 168 static int jz4730_nand_cs3_pins[] = { 0x55, }; 169 static int jz4730_nand_cs4_pins[] = { 0x56, }; 170 static int jz4730_nand_cs5_pins[] = { 0x57, }; 171 static int jz4730_pwm_pwm0_pins[] = { 0x5e, }; 172 static int jz4730_pwm_pwm1_pins[] = { 0x5f, }; 173 174 static u8 jz4730_lcd_8bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, }; 175 176 static const struct group_desc jz4730_groups[] = { 177 INGENIC_PIN_GROUP("mmc-1bit", jz4730_mmc_1bit, 1), 178 INGENIC_PIN_GROUP("mmc-4bit", jz4730_mmc_4bit, 1), 179 INGENIC_PIN_GROUP("uart0-data", jz4730_uart0_data, 1), 180 INGENIC_PIN_GROUP("uart1-data", jz4730_uart1_data, 1), 181 INGENIC_PIN_GROUP("uart2-data", jz4730_uart2_data, 1), 182 INGENIC_PIN_GROUP("uart3-data", jz4730_uart3_data, 1), 183 INGENIC_PIN_GROUP("uart3-hwflow", jz4730_uart3_hwflow, 1), 184 INGENIC_PIN_GROUP_FUNCS("lcd-8bit", jz4730_lcd_8bit, jz4730_lcd_8bit_funcs), 185 INGENIC_PIN_GROUP("lcd-16bit", jz4730_lcd_16bit, 1), 186 INGENIC_PIN_GROUP("lcd-special", jz4730_lcd_special, 1), 187 INGENIC_PIN_GROUP("lcd-generic", jz4730_lcd_generic, 1), 188 INGENIC_PIN_GROUP("nand-cs1", jz4730_nand_cs1, 1), 189 INGENIC_PIN_GROUP("nand-cs2", jz4730_nand_cs2, 1), 190 INGENIC_PIN_GROUP("nand-cs3", jz4730_nand_cs3, 1), 191 INGENIC_PIN_GROUP("nand-cs4", jz4730_nand_cs4, 1), 192 INGENIC_PIN_GROUP("nand-cs5", jz4730_nand_cs5, 1), 193 INGENIC_PIN_GROUP("pwm0", jz4730_pwm_pwm0, 1), 194 INGENIC_PIN_GROUP("pwm1", jz4730_pwm_pwm1, 1), 195 }; 196 197 static const char *jz4730_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; 198 static const char *jz4730_uart0_groups[] = { "uart0-data", }; 199 static const char *jz4730_uart1_groups[] = { "uart1-data", }; 200 static const char *jz4730_uart2_groups[] = { "uart2-data", }; 201 static const char *jz4730_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 202 static const char *jz4730_lcd_groups[] = { 203 "lcd-8bit", "lcd-16bit", "lcd-special", "lcd-generic", 204 }; 205 static const char *jz4730_nand_groups[] = { 206 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-cs5", 207 }; 208 static const char *jz4730_pwm0_groups[] = { "pwm0", }; 209 static const char *jz4730_pwm1_groups[] = { "pwm1", }; 210 211 static const struct function_desc jz4730_functions[] = { 212 { "mmc", jz4730_mmc_groups, ARRAY_SIZE(jz4730_mmc_groups), }, 213 { "uart0", jz4730_uart0_groups, ARRAY_SIZE(jz4730_uart0_groups), }, 214 { "uart1", jz4730_uart1_groups, ARRAY_SIZE(jz4730_uart1_groups), }, 215 { "uart2", jz4730_uart2_groups, ARRAY_SIZE(jz4730_uart2_groups), }, 216 { "uart3", jz4730_uart3_groups, ARRAY_SIZE(jz4730_uart3_groups), }, 217 { "lcd", jz4730_lcd_groups, ARRAY_SIZE(jz4730_lcd_groups), }, 218 { "nand", jz4730_nand_groups, ARRAY_SIZE(jz4730_nand_groups), }, 219 { "pwm0", jz4730_pwm0_groups, ARRAY_SIZE(jz4730_pwm0_groups), }, 220 { "pwm1", jz4730_pwm1_groups, ARRAY_SIZE(jz4730_pwm1_groups), }, 221 }; 222 223 static const struct ingenic_chip_info jz4730_chip_info = { 224 .num_chips = 4, 225 .reg_offset = 0x30, 226 .version = ID_JZ4730, 227 .groups = jz4730_groups, 228 .num_groups = ARRAY_SIZE(jz4730_groups), 229 .functions = jz4730_functions, 230 .num_functions = ARRAY_SIZE(jz4730_functions), 231 .pull_ups = jz4730_pull_ups, 232 .pull_downs = jz4730_pull_downs, 233 }; 234 235 static const u32 jz4740_pull_ups[4] = { 236 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 237 }; 238 239 static const u32 jz4740_pull_downs[4] = { 240 0x00000000, 0x00000000, 0x00000000, 0x00000000, 241 }; 242 243 static int jz4740_mmc_1bit_pins[] = { 0x69, 0x68, 0x6a, }; 244 static int jz4740_mmc_4bit_pins[] = { 0x6b, 0x6c, 0x6d, }; 245 static int jz4740_uart0_data_pins[] = { 0x7a, 0x79, }; 246 static int jz4740_uart0_hwflow_pins[] = { 0x7e, 0x7f, }; 247 static int jz4740_uart1_data_pins[] = { 0x7e, 0x7f, }; 248 static int jz4740_lcd_8bit_pins[] = { 249 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 250 0x52, 0x53, 0x54, 251 }; 252 static int jz4740_lcd_16bit_pins[] = { 253 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 254 }; 255 static int jz4740_lcd_18bit_pins[] = { 0x50, 0x51, }; 256 static int jz4740_lcd_special_pins[] = { 0x31, 0x32, 0x56, 0x57, }; 257 static int jz4740_lcd_generic_pins[] = { 0x55, }; 258 static int jz4740_nand_cs1_pins[] = { 0x39, }; 259 static int jz4740_nand_cs2_pins[] = { 0x3a, }; 260 static int jz4740_nand_cs3_pins[] = { 0x3b, }; 261 static int jz4740_nand_cs4_pins[] = { 0x3c, }; 262 static int jz4740_nand_fre_fwe_pins[] = { 0x5c, 0x5d, }; 263 static int jz4740_pwm_pwm0_pins[] = { 0x77, }; 264 static int jz4740_pwm_pwm1_pins[] = { 0x78, }; 265 static int jz4740_pwm_pwm2_pins[] = { 0x79, }; 266 static int jz4740_pwm_pwm3_pins[] = { 0x7a, }; 267 static int jz4740_pwm_pwm4_pins[] = { 0x7b, }; 268 static int jz4740_pwm_pwm5_pins[] = { 0x7c, }; 269 static int jz4740_pwm_pwm6_pins[] = { 0x7e, }; 270 static int jz4740_pwm_pwm7_pins[] = { 0x7f, }; 271 272 static const struct group_desc jz4740_groups[] = { 273 INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit, 0), 274 INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit, 0), 275 INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data, 1), 276 INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow, 1), 277 INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data, 2), 278 INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit, 0), 279 INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit, 0), 280 INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit, 0), 281 INGENIC_PIN_GROUP("lcd-special", jz4740_lcd_special, 0), 282 INGENIC_PIN_GROUP("lcd-generic", jz4740_lcd_generic, 0), 283 INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1, 0), 284 INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2, 0), 285 INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3, 0), 286 INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4, 0), 287 INGENIC_PIN_GROUP("nand-fre-fwe", jz4740_nand_fre_fwe, 0), 288 INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0, 0), 289 INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1, 0), 290 INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2, 0), 291 INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3, 0), 292 INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4, 0), 293 INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5, 0), 294 INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6, 0), 295 INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7, 0), 296 }; 297 298 static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; 299 static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 300 static const char *jz4740_uart1_groups[] = { "uart1-data", }; 301 static const char *jz4740_lcd_groups[] = { 302 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-special", "lcd-generic", 303 }; 304 static const char *jz4740_nand_groups[] = { 305 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe", 306 }; 307 static const char *jz4740_pwm0_groups[] = { "pwm0", }; 308 static const char *jz4740_pwm1_groups[] = { "pwm1", }; 309 static const char *jz4740_pwm2_groups[] = { "pwm2", }; 310 static const char *jz4740_pwm3_groups[] = { "pwm3", }; 311 static const char *jz4740_pwm4_groups[] = { "pwm4", }; 312 static const char *jz4740_pwm5_groups[] = { "pwm5", }; 313 static const char *jz4740_pwm6_groups[] = { "pwm6", }; 314 static const char *jz4740_pwm7_groups[] = { "pwm7", }; 315 316 static const struct function_desc jz4740_functions[] = { 317 { "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), }, 318 { "uart0", jz4740_uart0_groups, ARRAY_SIZE(jz4740_uart0_groups), }, 319 { "uart1", jz4740_uart1_groups, ARRAY_SIZE(jz4740_uart1_groups), }, 320 { "lcd", jz4740_lcd_groups, ARRAY_SIZE(jz4740_lcd_groups), }, 321 { "nand", jz4740_nand_groups, ARRAY_SIZE(jz4740_nand_groups), }, 322 { "pwm0", jz4740_pwm0_groups, ARRAY_SIZE(jz4740_pwm0_groups), }, 323 { "pwm1", jz4740_pwm1_groups, ARRAY_SIZE(jz4740_pwm1_groups), }, 324 { "pwm2", jz4740_pwm2_groups, ARRAY_SIZE(jz4740_pwm2_groups), }, 325 { "pwm3", jz4740_pwm3_groups, ARRAY_SIZE(jz4740_pwm3_groups), }, 326 { "pwm4", jz4740_pwm4_groups, ARRAY_SIZE(jz4740_pwm4_groups), }, 327 { "pwm5", jz4740_pwm5_groups, ARRAY_SIZE(jz4740_pwm5_groups), }, 328 { "pwm6", jz4740_pwm6_groups, ARRAY_SIZE(jz4740_pwm6_groups), }, 329 { "pwm7", jz4740_pwm7_groups, ARRAY_SIZE(jz4740_pwm7_groups), }, 330 }; 331 332 static const struct ingenic_chip_info jz4740_chip_info = { 333 .num_chips = 4, 334 .reg_offset = 0x100, 335 .version = ID_JZ4740, 336 .groups = jz4740_groups, 337 .num_groups = ARRAY_SIZE(jz4740_groups), 338 .functions = jz4740_functions, 339 .num_functions = ARRAY_SIZE(jz4740_functions), 340 .pull_ups = jz4740_pull_ups, 341 .pull_downs = jz4740_pull_downs, 342 }; 343 344 static int jz4725b_mmc0_1bit_pins[] = { 0x48, 0x49, 0x5c, }; 345 static int jz4725b_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x56, }; 346 static int jz4725b_mmc1_1bit_pins[] = { 0x7a, 0x7b, 0x7c, }; 347 static int jz4725b_mmc1_4bit_pins[] = { 0x7d, 0x7e, 0x7f, }; 348 static int jz4725b_uart_data_pins[] = { 0x4c, 0x4d, }; 349 static int jz4725b_lcd_8bit_pins[] = { 350 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 351 0x72, 0x73, 0x74, 352 }; 353 static int jz4725b_lcd_16bit_pins[] = { 354 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 355 }; 356 static int jz4725b_lcd_18bit_pins[] = { 0x70, 0x71, }; 357 static int jz4725b_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 358 static int jz4725b_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 359 static int jz4725b_lcd_generic_pins[] = { 0x75, }; 360 static int jz4725b_nand_cs1_pins[] = { 0x55, }; 361 static int jz4725b_nand_cs2_pins[] = { 0x56, }; 362 static int jz4725b_nand_cs3_pins[] = { 0x57, }; 363 static int jz4725b_nand_cs4_pins[] = { 0x58, }; 364 static int jz4725b_nand_cle_ale_pins[] = { 0x48, 0x49 }; 365 static int jz4725b_nand_fre_fwe_pins[] = { 0x5c, 0x5d }; 366 static int jz4725b_pwm_pwm0_pins[] = { 0x4a, }; 367 static int jz4725b_pwm_pwm1_pins[] = { 0x4b, }; 368 static int jz4725b_pwm_pwm2_pins[] = { 0x4c, }; 369 static int jz4725b_pwm_pwm3_pins[] = { 0x4d, }; 370 static int jz4725b_pwm_pwm4_pins[] = { 0x4e, }; 371 static int jz4725b_pwm_pwm5_pins[] = { 0x4f, }; 372 373 static u8 jz4725b_mmc0_4bit_funcs[] = { 1, 0, 1, }; 374 375 static const struct group_desc jz4725b_groups[] = { 376 INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit, 1), 377 INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4725b_mmc0_4bit, 378 jz4725b_mmc0_4bit_funcs), 379 INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit, 0), 380 INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit, 0), 381 INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data, 1), 382 INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit, 0), 383 INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit, 0), 384 INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit, 0), 385 INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit, 1), 386 INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special, 0), 387 INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic, 0), 388 INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1, 0), 389 INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2, 0), 390 INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3, 0), 391 INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4, 0), 392 INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale, 0), 393 INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe, 0), 394 INGENIC_PIN_GROUP("pwm0", jz4725b_pwm_pwm0, 0), 395 INGENIC_PIN_GROUP("pwm1", jz4725b_pwm_pwm1, 0), 396 INGENIC_PIN_GROUP("pwm2", jz4725b_pwm_pwm2, 0), 397 INGENIC_PIN_GROUP("pwm3", jz4725b_pwm_pwm3, 0), 398 INGENIC_PIN_GROUP("pwm4", jz4725b_pwm_pwm4, 0), 399 INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5, 0), 400 }; 401 402 static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 403 static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 404 static const char *jz4725b_uart_groups[] = { "uart-data", }; 405 static const char *jz4725b_lcd_groups[] = { 406 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 407 "lcd-special", "lcd-generic", 408 }; 409 static const char *jz4725b_nand_groups[] = { 410 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", 411 "nand-cle-ale", "nand-fre-fwe", 412 }; 413 static const char *jz4725b_pwm0_groups[] = { "pwm0", }; 414 static const char *jz4725b_pwm1_groups[] = { "pwm1", }; 415 static const char *jz4725b_pwm2_groups[] = { "pwm2", }; 416 static const char *jz4725b_pwm3_groups[] = { "pwm3", }; 417 static const char *jz4725b_pwm4_groups[] = { "pwm4", }; 418 static const char *jz4725b_pwm5_groups[] = { "pwm5", }; 419 420 static const struct function_desc jz4725b_functions[] = { 421 { "mmc0", jz4725b_mmc0_groups, ARRAY_SIZE(jz4725b_mmc0_groups), }, 422 { "mmc1", jz4725b_mmc1_groups, ARRAY_SIZE(jz4725b_mmc1_groups), }, 423 { "uart", jz4725b_uart_groups, ARRAY_SIZE(jz4725b_uart_groups), }, 424 { "nand", jz4725b_nand_groups, ARRAY_SIZE(jz4725b_nand_groups), }, 425 { "pwm0", jz4725b_pwm0_groups, ARRAY_SIZE(jz4725b_pwm0_groups), }, 426 { "pwm1", jz4725b_pwm1_groups, ARRAY_SIZE(jz4725b_pwm1_groups), }, 427 { "pwm2", jz4725b_pwm2_groups, ARRAY_SIZE(jz4725b_pwm2_groups), }, 428 { "pwm3", jz4725b_pwm3_groups, ARRAY_SIZE(jz4725b_pwm3_groups), }, 429 { "pwm4", jz4725b_pwm4_groups, ARRAY_SIZE(jz4725b_pwm4_groups), }, 430 { "pwm5", jz4725b_pwm5_groups, ARRAY_SIZE(jz4725b_pwm5_groups), }, 431 { "lcd", jz4725b_lcd_groups, ARRAY_SIZE(jz4725b_lcd_groups), }, 432 }; 433 434 static const struct ingenic_chip_info jz4725b_chip_info = { 435 .num_chips = 4, 436 .reg_offset = 0x100, 437 .version = ID_JZ4725B, 438 .groups = jz4725b_groups, 439 .num_groups = ARRAY_SIZE(jz4725b_groups), 440 .functions = jz4725b_functions, 441 .num_functions = ARRAY_SIZE(jz4725b_functions), 442 .pull_ups = jz4740_pull_ups, 443 .pull_downs = jz4740_pull_downs, 444 }; 445 446 static const u32 jz4750_pull_ups[6] = { 447 0xffffffff, 0xffffffff, 0x3fffffff, 0x7fffffff, 0x1fff3fff, 0x00ffffff, 448 }; 449 450 static const u32 jz4750_pull_downs[6] = { 451 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 452 }; 453 454 static int jz4750_uart0_data_pins[] = { 0xa4, 0xa5, }; 455 static int jz4750_uart0_hwflow_pins[] = { 0xa6, 0xa7, }; 456 static int jz4750_uart1_data_pins[] = { 0x90, 0x91, }; 457 static int jz4750_uart1_hwflow_pins[] = { 0x92, 0x93, }; 458 static int jz4750_uart2_data_pins[] = { 0x9b, 0x9a, }; 459 static int jz4750_uart3_data_pins[] = { 0xb0, 0xb1, }; 460 static int jz4750_uart3_hwflow_pins[] = { 0xb2, 0xb3, }; 461 static int jz4750_mmc0_1bit_pins[] = { 0xa8, 0xa9, 0xa0, }; 462 static int jz4750_mmc0_4bit_pins[] = { 0xa1, 0xa2, 0xa3, }; 463 static int jz4750_mmc0_8bit_pins[] = { 0xa4, 0xa5, 0xa6, 0xa7, }; 464 static int jz4750_mmc1_1bit_pins[] = { 0xae, 0xaf, 0xaa, }; 465 static int jz4750_mmc1_4bit_pins[] = { 0xab, 0xac, 0xad, }; 466 static int jz4750_i2c_pins[] = { 0x8c, 0x8d, }; 467 static int jz4750_cim_pins[] = { 468 0x89, 0x8b, 0x8a, 0x88, 469 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 470 }; 471 static int jz4750_lcd_8bit_pins[] = { 472 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 473 0x72, 0x73, 0x74, 474 }; 475 static int jz4750_lcd_16bit_pins[] = { 476 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 477 }; 478 static int jz4750_lcd_18bit_pins[] = { 0x70, 0x71, }; 479 static int jz4750_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, 0xb2, 0xb3, }; 480 static int jz4750_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 481 static int jz4750_lcd_generic_pins[] = { 0x75, }; 482 static int jz4750_nand_cs1_pins[] = { 0x55, }; 483 static int jz4750_nand_cs2_pins[] = { 0x56, }; 484 static int jz4750_nand_cs3_pins[] = { 0x57, }; 485 static int jz4750_nand_cs4_pins[] = { 0x58, }; 486 static int jz4750_nand_fre_fwe_pins[] = { 0x5c, 0x5d, }; 487 static int jz4750_pwm_pwm0_pins[] = { 0x94, }; 488 static int jz4750_pwm_pwm1_pins[] = { 0x95, }; 489 static int jz4750_pwm_pwm2_pins[] = { 0x96, }; 490 static int jz4750_pwm_pwm3_pins[] = { 0x97, }; 491 static int jz4750_pwm_pwm4_pins[] = { 0x98, }; 492 static int jz4750_pwm_pwm5_pins[] = { 0x99, }; 493 494 static const struct group_desc jz4750_groups[] = { 495 INGENIC_PIN_GROUP("uart0-data", jz4750_uart0_data, 1), 496 INGENIC_PIN_GROUP("uart0-hwflow", jz4750_uart0_hwflow, 1), 497 INGENIC_PIN_GROUP("uart1-data", jz4750_uart1_data, 0), 498 INGENIC_PIN_GROUP("uart1-hwflow", jz4750_uart1_hwflow, 0), 499 INGENIC_PIN_GROUP("uart2-data", jz4750_uart2_data, 1), 500 INGENIC_PIN_GROUP("uart3-data", jz4750_uart3_data, 0), 501 INGENIC_PIN_GROUP("uart3-hwflow", jz4750_uart3_hwflow, 0), 502 INGENIC_PIN_GROUP("mmc0-1bit", jz4750_mmc0_1bit, 0), 503 INGENIC_PIN_GROUP("mmc0-4bit", jz4750_mmc0_4bit, 0), 504 INGENIC_PIN_GROUP("mmc0-8bit", jz4750_mmc0_8bit, 0), 505 INGENIC_PIN_GROUP("mmc1-1bit", jz4750_mmc1_1bit, 0), 506 INGENIC_PIN_GROUP("mmc1-4bit", jz4750_mmc1_4bit, 0), 507 INGENIC_PIN_GROUP("i2c-data", jz4750_i2c, 0), 508 INGENIC_PIN_GROUP("cim-data", jz4750_cim, 0), 509 INGENIC_PIN_GROUP("lcd-8bit", jz4750_lcd_8bit, 0), 510 INGENIC_PIN_GROUP("lcd-16bit", jz4750_lcd_16bit, 0), 511 INGENIC_PIN_GROUP("lcd-18bit", jz4750_lcd_18bit, 0), 512 INGENIC_PIN_GROUP("lcd-24bit", jz4750_lcd_24bit, 1), 513 INGENIC_PIN_GROUP("lcd-special", jz4750_lcd_special, 0), 514 INGENIC_PIN_GROUP("lcd-generic", jz4750_lcd_generic, 0), 515 INGENIC_PIN_GROUP("nand-cs1", jz4750_nand_cs1, 0), 516 INGENIC_PIN_GROUP("nand-cs2", jz4750_nand_cs2, 0), 517 INGENIC_PIN_GROUP("nand-cs3", jz4750_nand_cs3, 0), 518 INGENIC_PIN_GROUP("nand-cs4", jz4750_nand_cs4, 0), 519 INGENIC_PIN_GROUP("nand-fre-fwe", jz4750_nand_fre_fwe, 0), 520 INGENIC_PIN_GROUP("pwm0", jz4750_pwm_pwm0, 0), 521 INGENIC_PIN_GROUP("pwm1", jz4750_pwm_pwm1, 0), 522 INGENIC_PIN_GROUP("pwm2", jz4750_pwm_pwm2, 0), 523 INGENIC_PIN_GROUP("pwm3", jz4750_pwm_pwm3, 0), 524 INGENIC_PIN_GROUP("pwm4", jz4750_pwm_pwm4, 0), 525 INGENIC_PIN_GROUP("pwm5", jz4750_pwm_pwm5, 0), 526 }; 527 528 static const char *jz4750_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 529 static const char *jz4750_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 530 static const char *jz4750_uart2_groups[] = { "uart2-data", }; 531 static const char *jz4750_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 532 static const char *jz4750_mmc0_groups[] = { 533 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", 534 }; 535 static const char *jz4750_mmc1_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 536 static const char *jz4750_i2c_groups[] = { "i2c-data", }; 537 static const char *jz4750_cim_groups[] = { "cim-data", }; 538 static const char *jz4750_lcd_groups[] = { 539 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 540 "lcd-special", "lcd-generic", 541 }; 542 static const char *jz4750_nand_groups[] = { 543 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe", 544 }; 545 static const char *jz4750_pwm0_groups[] = { "pwm0", }; 546 static const char *jz4750_pwm1_groups[] = { "pwm1", }; 547 static const char *jz4750_pwm2_groups[] = { "pwm2", }; 548 static const char *jz4750_pwm3_groups[] = { "pwm3", }; 549 static const char *jz4750_pwm4_groups[] = { "pwm4", }; 550 static const char *jz4750_pwm5_groups[] = { "pwm5", }; 551 552 static const struct function_desc jz4750_functions[] = { 553 { "uart0", jz4750_uart0_groups, ARRAY_SIZE(jz4750_uart0_groups), }, 554 { "uart1", jz4750_uart1_groups, ARRAY_SIZE(jz4750_uart1_groups), }, 555 { "uart2", jz4750_uart2_groups, ARRAY_SIZE(jz4750_uart2_groups), }, 556 { "uart3", jz4750_uart3_groups, ARRAY_SIZE(jz4750_uart3_groups), }, 557 { "mmc0", jz4750_mmc0_groups, ARRAY_SIZE(jz4750_mmc0_groups), }, 558 { "mmc1", jz4750_mmc1_groups, ARRAY_SIZE(jz4750_mmc1_groups), }, 559 { "i2c", jz4750_i2c_groups, ARRAY_SIZE(jz4750_i2c_groups), }, 560 { "cim", jz4750_cim_groups, ARRAY_SIZE(jz4750_cim_groups), }, 561 { "lcd", jz4750_lcd_groups, ARRAY_SIZE(jz4750_lcd_groups), }, 562 { "nand", jz4750_nand_groups, ARRAY_SIZE(jz4750_nand_groups), }, 563 { "pwm0", jz4750_pwm0_groups, ARRAY_SIZE(jz4750_pwm0_groups), }, 564 { "pwm1", jz4750_pwm1_groups, ARRAY_SIZE(jz4750_pwm1_groups), }, 565 { "pwm2", jz4750_pwm2_groups, ARRAY_SIZE(jz4750_pwm2_groups), }, 566 { "pwm3", jz4750_pwm3_groups, ARRAY_SIZE(jz4750_pwm3_groups), }, 567 { "pwm4", jz4750_pwm4_groups, ARRAY_SIZE(jz4750_pwm4_groups), }, 568 { "pwm5", jz4750_pwm5_groups, ARRAY_SIZE(jz4750_pwm5_groups), }, 569 }; 570 571 static const struct ingenic_chip_info jz4750_chip_info = { 572 .num_chips = 6, 573 .reg_offset = 0x100, 574 .version = ID_JZ4750, 575 .groups = jz4750_groups, 576 .num_groups = ARRAY_SIZE(jz4750_groups), 577 .functions = jz4750_functions, 578 .num_functions = ARRAY_SIZE(jz4750_functions), 579 .pull_ups = jz4750_pull_ups, 580 .pull_downs = jz4750_pull_downs, 581 }; 582 583 static const u32 jz4755_pull_ups[6] = { 584 0xffffffff, 0xffffffff, 0x0fffffff, 0xffffffff, 0x33dc3fff, 0x0000fc00, 585 }; 586 587 static const u32 jz4755_pull_downs[6] = { 588 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 589 }; 590 591 static int jz4755_uart0_data_pins[] = { 0x7c, 0x7d, }; 592 static int jz4755_uart0_hwflow_pins[] = { 0x7e, 0x7f, }; 593 static int jz4755_uart1_data_pins[] = { 0x97, 0x99, }; 594 static int jz4755_uart2_data_pins[] = { 0x9f, }; 595 static int jz4755_ssi_dt_b_pins[] = { 0x3b, }; 596 static int jz4755_ssi_dt_f_pins[] = { 0xa1, }; 597 static int jz4755_ssi_dr_b_pins[] = { 0x3c, }; 598 static int jz4755_ssi_dr_f_pins[] = { 0xa2, }; 599 static int jz4755_ssi_clk_b_pins[] = { 0x3a, }; 600 static int jz4755_ssi_clk_f_pins[] = { 0xa0, }; 601 static int jz4755_ssi_gpc_b_pins[] = { 0x3e, }; 602 static int jz4755_ssi_gpc_f_pins[] = { 0xa4, }; 603 static int jz4755_ssi_ce0_b_pins[] = { 0x3d, }; 604 static int jz4755_ssi_ce0_f_pins[] = { 0xa3, }; 605 static int jz4755_ssi_ce1_b_pins[] = { 0x3f, }; 606 static int jz4755_ssi_ce1_f_pins[] = { 0xa5, }; 607 static int jz4755_mmc0_1bit_pins[] = { 0x2f, 0x50, 0x5c, }; 608 static int jz4755_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x51, }; 609 static int jz4755_mmc1_1bit_pins[] = { 0x3a, 0x3d, 0x3c, }; 610 static int jz4755_mmc1_4bit_pins[] = { 0x3b, 0x3e, 0x3f, }; 611 static int jz4755_i2c_pins[] = { 0x8c, 0x8d, }; 612 static int jz4755_cim_pins[] = { 613 0x89, 0x8b, 0x8a, 0x88, 614 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 615 }; 616 static int jz4755_lcd_8bit_pins[] = { 617 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 618 0x72, 0x73, 0x74, 619 }; 620 static int jz4755_lcd_16bit_pins[] = { 621 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 622 }; 623 static int jz4755_lcd_18bit_pins[] = { 0x70, 0x71, }; 624 static int jz4755_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, }; 625 static int jz4755_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 626 static int jz4755_lcd_generic_pins[] = { 0x75, }; 627 static int jz4755_nand_cs1_pins[] = { 0x55, }; 628 static int jz4755_nand_cs2_pins[] = { 0x56, }; 629 static int jz4755_nand_cs3_pins[] = { 0x57, }; 630 static int jz4755_nand_cs4_pins[] = { 0x58, }; 631 static int jz4755_nand_fre_fwe_pins[] = { 0x5c, 0x5d, }; 632 static int jz4755_pwm_pwm0_pins[] = { 0x94, }; 633 static int jz4755_pwm_pwm1_pins[] = { 0xab, }; 634 static int jz4755_pwm_pwm2_pins[] = { 0x96, }; 635 static int jz4755_pwm_pwm3_pins[] = { 0x97, }; 636 static int jz4755_pwm_pwm4_pins[] = { 0x98, }; 637 static int jz4755_pwm_pwm5_pins[] = { 0x99, }; 638 639 static u8 jz4755_mmc0_1bit_funcs[] = { 2, 2, 1, }; 640 static u8 jz4755_mmc0_4bit_funcs[] = { 1, 0, 1, }; 641 static u8 jz4755_lcd_24bit_funcs[] = { 1, 1, 1, 1, 0, 0, }; 642 643 static const struct group_desc jz4755_groups[] = { 644 INGENIC_PIN_GROUP("uart0-data", jz4755_uart0_data, 0), 645 INGENIC_PIN_GROUP("uart0-hwflow", jz4755_uart0_hwflow, 0), 646 INGENIC_PIN_GROUP("uart1-data", jz4755_uart1_data, 0), 647 INGENIC_PIN_GROUP("uart2-data", jz4755_uart2_data, 1), 648 INGENIC_PIN_GROUP("ssi-dt-b", jz4755_ssi_dt_b, 0), 649 INGENIC_PIN_GROUP("ssi-dt-f", jz4755_ssi_dt_f, 0), 650 INGENIC_PIN_GROUP("ssi-dr-b", jz4755_ssi_dr_b, 0), 651 INGENIC_PIN_GROUP("ssi-dr-f", jz4755_ssi_dr_f, 0), 652 INGENIC_PIN_GROUP("ssi-clk-b", jz4755_ssi_clk_b, 0), 653 INGENIC_PIN_GROUP("ssi-clk-f", jz4755_ssi_clk_f, 0), 654 INGENIC_PIN_GROUP("ssi-gpc-b", jz4755_ssi_gpc_b, 0), 655 INGENIC_PIN_GROUP("ssi-gpc-f", jz4755_ssi_gpc_f, 0), 656 INGENIC_PIN_GROUP("ssi-ce0-b", jz4755_ssi_ce0_b, 0), 657 INGENIC_PIN_GROUP("ssi-ce0-f", jz4755_ssi_ce0_f, 0), 658 INGENIC_PIN_GROUP("ssi-ce1-b", jz4755_ssi_ce1_b, 0), 659 INGENIC_PIN_GROUP("ssi-ce1-f", jz4755_ssi_ce1_f, 0), 660 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit", jz4755_mmc0_1bit, 661 jz4755_mmc0_1bit_funcs), 662 INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4755_mmc0_4bit, 663 jz4755_mmc0_4bit_funcs), 664 INGENIC_PIN_GROUP("mmc1-1bit", jz4755_mmc1_1bit, 1), 665 INGENIC_PIN_GROUP("mmc1-4bit", jz4755_mmc1_4bit, 1), 666 INGENIC_PIN_GROUP("i2c-data", jz4755_i2c, 0), 667 INGENIC_PIN_GROUP("cim-data", jz4755_cim, 0), 668 INGENIC_PIN_GROUP("lcd-8bit", jz4755_lcd_8bit, 0), 669 INGENIC_PIN_GROUP("lcd-16bit", jz4755_lcd_16bit, 0), 670 INGENIC_PIN_GROUP("lcd-18bit", jz4755_lcd_18bit, 0), 671 INGENIC_PIN_GROUP_FUNCS("lcd-24bit", jz4755_lcd_24bit, 672 jz4755_lcd_24bit_funcs), 673 INGENIC_PIN_GROUP("lcd-special", jz4755_lcd_special, 0), 674 INGENIC_PIN_GROUP("lcd-generic", jz4755_lcd_generic, 0), 675 INGENIC_PIN_GROUP("nand-cs1", jz4755_nand_cs1, 0), 676 INGENIC_PIN_GROUP("nand-cs2", jz4755_nand_cs2, 0), 677 INGENIC_PIN_GROUP("nand-cs3", jz4755_nand_cs3, 0), 678 INGENIC_PIN_GROUP("nand-cs4", jz4755_nand_cs4, 0), 679 INGENIC_PIN_GROUP("nand-fre-fwe", jz4755_nand_fre_fwe, 0), 680 INGENIC_PIN_GROUP("pwm0", jz4755_pwm_pwm0, 0), 681 INGENIC_PIN_GROUP("pwm1", jz4755_pwm_pwm1, 1), 682 INGENIC_PIN_GROUP("pwm2", jz4755_pwm_pwm2, 0), 683 INGENIC_PIN_GROUP("pwm3", jz4755_pwm_pwm3, 0), 684 INGENIC_PIN_GROUP("pwm4", jz4755_pwm_pwm4, 0), 685 INGENIC_PIN_GROUP("pwm5", jz4755_pwm_pwm5, 0), 686 }; 687 688 static const char *jz4755_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 689 static const char *jz4755_uart1_groups[] = { "uart1-data", }; 690 static const char *jz4755_uart2_groups[] = { "uart2-data", }; 691 static const char *jz4755_ssi_groups[] = { 692 "ssi-dt-b", "ssi-dt-f", 693 "ssi-dr-b", "ssi-dr-f", 694 "ssi-clk-b", "ssi-clk-f", 695 "ssi-gpc-b", "ssi-gpc-f", 696 "ssi-ce0-b", "ssi-ce0-f", 697 "ssi-ce1-b", "ssi-ce1-f", 698 }; 699 static const char *jz4755_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 700 static const char *jz4755_mmc1_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 701 static const char *jz4755_i2c_groups[] = { "i2c-data", }; 702 static const char *jz4755_cim_groups[] = { "cim-data", }; 703 static const char *jz4755_lcd_groups[] = { 704 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 705 "lcd-special", "lcd-generic", 706 }; 707 static const char *jz4755_nand_groups[] = { 708 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe", 709 }; 710 static const char *jz4755_pwm0_groups[] = { "pwm0", }; 711 static const char *jz4755_pwm1_groups[] = { "pwm1", }; 712 static const char *jz4755_pwm2_groups[] = { "pwm2", }; 713 static const char *jz4755_pwm3_groups[] = { "pwm3", }; 714 static const char *jz4755_pwm4_groups[] = { "pwm4", }; 715 static const char *jz4755_pwm5_groups[] = { "pwm5", }; 716 717 static const struct function_desc jz4755_functions[] = { 718 { "uart0", jz4755_uart0_groups, ARRAY_SIZE(jz4755_uart0_groups), }, 719 { "uart1", jz4755_uart1_groups, ARRAY_SIZE(jz4755_uart1_groups), }, 720 { "uart2", jz4755_uart2_groups, ARRAY_SIZE(jz4755_uart2_groups), }, 721 { "ssi", jz4755_ssi_groups, ARRAY_SIZE(jz4755_ssi_groups), }, 722 { "mmc0", jz4755_mmc0_groups, ARRAY_SIZE(jz4755_mmc0_groups), }, 723 { "mmc1", jz4755_mmc1_groups, ARRAY_SIZE(jz4755_mmc1_groups), }, 724 { "i2c", jz4755_i2c_groups, ARRAY_SIZE(jz4755_i2c_groups), }, 725 { "cim", jz4755_cim_groups, ARRAY_SIZE(jz4755_cim_groups), }, 726 { "lcd", jz4755_lcd_groups, ARRAY_SIZE(jz4755_lcd_groups), }, 727 { "nand", jz4755_nand_groups, ARRAY_SIZE(jz4755_nand_groups), }, 728 { "pwm0", jz4755_pwm0_groups, ARRAY_SIZE(jz4755_pwm0_groups), }, 729 { "pwm1", jz4755_pwm1_groups, ARRAY_SIZE(jz4755_pwm1_groups), }, 730 { "pwm2", jz4755_pwm2_groups, ARRAY_SIZE(jz4755_pwm2_groups), }, 731 { "pwm3", jz4755_pwm3_groups, ARRAY_SIZE(jz4755_pwm3_groups), }, 732 { "pwm4", jz4755_pwm4_groups, ARRAY_SIZE(jz4755_pwm4_groups), }, 733 { "pwm5", jz4755_pwm5_groups, ARRAY_SIZE(jz4755_pwm5_groups), }, 734 }; 735 736 static const struct ingenic_chip_info jz4755_chip_info = { 737 .num_chips = 6, 738 .reg_offset = 0x100, 739 .version = ID_JZ4755, 740 .groups = jz4755_groups, 741 .num_groups = ARRAY_SIZE(jz4755_groups), 742 .functions = jz4755_functions, 743 .num_functions = ARRAY_SIZE(jz4755_functions), 744 .pull_ups = jz4755_pull_ups, 745 .pull_downs = jz4755_pull_downs, 746 }; 747 748 static const u32 jz4760_pull_ups[6] = { 749 0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0x0000000f, 750 }; 751 752 static const u32 jz4760_pull_downs[6] = { 753 0x00000000, 0x00030c00, 0x00000000, 0x00003000, 0x00000483, 0x00000ff0, 754 }; 755 756 static int jz4760_uart0_data_pins[] = { 0xa0, 0xa3, }; 757 static int jz4760_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; 758 static int jz4760_uart1_data_pins[] = { 0x7a, 0x7c, }; 759 static int jz4760_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; 760 static int jz4760_uart2_data_pins[] = { 0x5c, 0x5e, }; 761 static int jz4760_uart2_hwflow_pins[] = { 0x5d, 0x5f, }; 762 static int jz4760_uart3_data_pins[] = { 0x6c, 0x85, }; 763 static int jz4760_uart3_hwflow_pins[] = { 0x88, 0x89, }; 764 static int jz4760_ssi0_dt_a_pins[] = { 0x15, }; 765 static int jz4760_ssi0_dt_b_pins[] = { 0x35, }; 766 static int jz4760_ssi0_dt_d_pins[] = { 0x75, }; 767 static int jz4760_ssi0_dt_e_pins[] = { 0x91, }; 768 static int jz4760_ssi0_dr_a_pins[] = { 0x14, }; 769 static int jz4760_ssi0_dr_b_pins[] = { 0x34, }; 770 static int jz4760_ssi0_dr_d_pins[] = { 0x74, }; 771 static int jz4760_ssi0_dr_e_pins[] = { 0x8e, }; 772 static int jz4760_ssi0_clk_a_pins[] = { 0x12, }; 773 static int jz4760_ssi0_clk_b_pins[] = { 0x3c, }; 774 static int jz4760_ssi0_clk_d_pins[] = { 0x78, }; 775 static int jz4760_ssi0_clk_e_pins[] = { 0x8f, }; 776 static int jz4760_ssi0_gpc_b_pins[] = { 0x3e, }; 777 static int jz4760_ssi0_gpc_d_pins[] = { 0x76, }; 778 static int jz4760_ssi0_gpc_e_pins[] = { 0x93, }; 779 static int jz4760_ssi0_ce0_a_pins[] = { 0x13, }; 780 static int jz4760_ssi0_ce0_b_pins[] = { 0x3d, }; 781 static int jz4760_ssi0_ce0_d_pins[] = { 0x79, }; 782 static int jz4760_ssi0_ce0_e_pins[] = { 0x90, }; 783 static int jz4760_ssi0_ce1_b_pins[] = { 0x3f, }; 784 static int jz4760_ssi0_ce1_d_pins[] = { 0x77, }; 785 static int jz4760_ssi0_ce1_e_pins[] = { 0x92, }; 786 static int jz4760_ssi1_dt_b_9_pins[] = { 0x29, }; 787 static int jz4760_ssi1_dt_b_21_pins[] = { 0x35, }; 788 static int jz4760_ssi1_dt_d_12_pins[] = { 0x6c, }; 789 static int jz4760_ssi1_dt_d_21_pins[] = { 0x75, }; 790 static int jz4760_ssi1_dt_e_pins[] = { 0x91, }; 791 static int jz4760_ssi1_dt_f_pins[] = { 0xa3, }; 792 static int jz4760_ssi1_dr_b_6_pins[] = { 0x26, }; 793 static int jz4760_ssi1_dr_b_20_pins[] = { 0x34, }; 794 static int jz4760_ssi1_dr_d_13_pins[] = { 0x6d, }; 795 static int jz4760_ssi1_dr_d_20_pins[] = { 0x74, }; 796 static int jz4760_ssi1_dr_e_pins[] = { 0x8e, }; 797 static int jz4760_ssi1_dr_f_pins[] = { 0xa0, }; 798 static int jz4760_ssi1_clk_b_7_pins[] = { 0x27, }; 799 static int jz4760_ssi1_clk_b_28_pins[] = { 0x3c, }; 800 static int jz4760_ssi1_clk_d_pins[] = { 0x78, }; 801 static int jz4760_ssi1_clk_e_7_pins[] = { 0x87, }; 802 static int jz4760_ssi1_clk_e_15_pins[] = { 0x8f, }; 803 static int jz4760_ssi1_clk_f_pins[] = { 0xa2, }; 804 static int jz4760_ssi1_gpc_b_pins[] = { 0x3e, }; 805 static int jz4760_ssi1_gpc_d_pins[] = { 0x76, }; 806 static int jz4760_ssi1_gpc_e_pins[] = { 0x93, }; 807 static int jz4760_ssi1_ce0_b_8_pins[] = { 0x28, }; 808 static int jz4760_ssi1_ce0_b_29_pins[] = { 0x3d, }; 809 static int jz4760_ssi1_ce0_d_pins[] = { 0x79, }; 810 static int jz4760_ssi1_ce0_e_6_pins[] = { 0x86, }; 811 static int jz4760_ssi1_ce0_e_16_pins[] = { 0x90, }; 812 static int jz4760_ssi1_ce0_f_pins[] = { 0xa1, }; 813 static int jz4760_ssi1_ce1_b_pins[] = { 0x3f, }; 814 static int jz4760_ssi1_ce1_d_pins[] = { 0x77, }; 815 static int jz4760_ssi1_ce1_e_pins[] = { 0x92, }; 816 static int jz4760_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; 817 static int jz4760_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; 818 static int jz4760_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 819 static int jz4760_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 820 static int jz4760_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 821 static int jz4760_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; 822 static int jz4760_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; 823 static int jz4760_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 824 static int jz4760_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 825 static int jz4760_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 826 static int jz4760_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, }; 827 static int jz4760_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, }; 828 static int jz4760_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 829 static int jz4760_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 830 static int jz4760_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 831 static int jz4760_nemc_8bit_data_pins[] = { 832 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 833 }; 834 static int jz4760_nemc_16bit_data_pins[] = { 835 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 836 }; 837 static int jz4760_nemc_cle_ale_pins[] = { 0x20, 0x21, }; 838 static int jz4760_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; 839 static int jz4760_nemc_rd_we_pins[] = { 0x10, 0x11, }; 840 static int jz4760_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; 841 static int jz4760_nemc_wait_pins[] = { 0x1b, }; 842 static int jz4760_nemc_cs1_pins[] = { 0x15, }; 843 static int jz4760_nemc_cs2_pins[] = { 0x16, }; 844 static int jz4760_nemc_cs3_pins[] = { 0x17, }; 845 static int jz4760_nemc_cs4_pins[] = { 0x18, }; 846 static int jz4760_nemc_cs5_pins[] = { 0x19, }; 847 static int jz4760_nemc_cs6_pins[] = { 0x1a, }; 848 static int jz4760_i2c0_pins[] = { 0x7e, 0x7f, }; 849 static int jz4760_i2c1_pins[] = { 0x9e, 0x9f, }; 850 static int jz4760_cim_pins[] = { 851 0x26, 0x27, 0x28, 0x29, 852 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 853 }; 854 static int jz4760_lcd_8bit_pins[] = { 855 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x4c, 856 0x4d, 0x52, 0x53, 857 }; 858 static int jz4760_lcd_16bit_pins[] = { 859 0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59, 860 }; 861 static int jz4760_lcd_18bit_pins[] = { 862 0x5a, 0x5b, 863 }; 864 static int jz4760_lcd_24bit_pins[] = { 865 0x40, 0x41, 0x4a, 0x4b, 0x54, 0x55, 866 }; 867 static int jz4760_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, }; 868 static int jz4760_lcd_generic_pins[] = { 0x49, }; 869 static int jz4760_pwm_pwm0_pins[] = { 0x80, }; 870 static int jz4760_pwm_pwm1_pins[] = { 0x81, }; 871 static int jz4760_pwm_pwm2_pins[] = { 0x82, }; 872 static int jz4760_pwm_pwm3_pins[] = { 0x83, }; 873 static int jz4760_pwm_pwm4_pins[] = { 0x84, }; 874 static int jz4760_pwm_pwm5_pins[] = { 0x85, }; 875 static int jz4760_pwm_pwm6_pins[] = { 0x6a, }; 876 static int jz4760_pwm_pwm7_pins[] = { 0x6b, }; 877 static int jz4760_otg_pins[] = { 0x8a, }; 878 879 static u8 jz4760_uart3_data_funcs[] = { 0, 1, }; 880 static u8 jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, }; 881 882 static const struct group_desc jz4760_groups[] = { 883 INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data, 0), 884 INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow, 0), 885 INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data, 0), 886 INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow, 0), 887 INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data, 0), 888 INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow, 0), 889 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4760_uart3_data, 890 jz4760_uart3_data_funcs), 891 INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow, 0), 892 INGENIC_PIN_GROUP("ssi0-dt-a", jz4760_ssi0_dt_a, 2), 893 INGENIC_PIN_GROUP("ssi0-dt-b", jz4760_ssi0_dt_b, 1), 894 INGENIC_PIN_GROUP("ssi0-dt-d", jz4760_ssi0_dt_d, 1), 895 INGENIC_PIN_GROUP("ssi0-dt-e", jz4760_ssi0_dt_e, 0), 896 INGENIC_PIN_GROUP("ssi0-dr-a", jz4760_ssi0_dr_a, 1), 897 INGENIC_PIN_GROUP("ssi0-dr-b", jz4760_ssi0_dr_b, 1), 898 INGENIC_PIN_GROUP("ssi0-dr-d", jz4760_ssi0_dr_d, 1), 899 INGENIC_PIN_GROUP("ssi0-dr-e", jz4760_ssi0_dr_e, 0), 900 INGENIC_PIN_GROUP("ssi0-clk-a", jz4760_ssi0_clk_a, 2), 901 INGENIC_PIN_GROUP("ssi0-clk-b", jz4760_ssi0_clk_b, 1), 902 INGENIC_PIN_GROUP("ssi0-clk-d", jz4760_ssi0_clk_d, 1), 903 INGENIC_PIN_GROUP("ssi0-clk-e", jz4760_ssi0_clk_e, 0), 904 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4760_ssi0_gpc_b, 1), 905 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4760_ssi0_gpc_d, 1), 906 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4760_ssi0_gpc_e, 0), 907 INGENIC_PIN_GROUP("ssi0-ce0-a", jz4760_ssi0_ce0_a, 2), 908 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4760_ssi0_ce0_b, 1), 909 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4760_ssi0_ce0_d, 1), 910 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4760_ssi0_ce0_e, 0), 911 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4760_ssi0_ce1_b, 1), 912 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4760_ssi0_ce1_d, 1), 913 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4760_ssi0_ce1_e, 0), 914 INGENIC_PIN_GROUP("ssi1-dt-b-9", jz4760_ssi1_dt_b_9, 2), 915 INGENIC_PIN_GROUP("ssi1-dt-b-21", jz4760_ssi1_dt_b_21, 2), 916 INGENIC_PIN_GROUP("ssi1-dt-d-12", jz4760_ssi1_dt_d_12, 2), 917 INGENIC_PIN_GROUP("ssi1-dt-d-21", jz4760_ssi1_dt_d_21, 2), 918 INGENIC_PIN_GROUP("ssi1-dt-e", jz4760_ssi1_dt_e, 1), 919 INGENIC_PIN_GROUP("ssi1-dt-f", jz4760_ssi1_dt_f, 2), 920 INGENIC_PIN_GROUP("ssi1-dr-b-6", jz4760_ssi1_dr_b_6, 2), 921 INGENIC_PIN_GROUP("ssi1-dr-b-20", jz4760_ssi1_dr_b_20, 2), 922 INGENIC_PIN_GROUP("ssi1-dr-d-13", jz4760_ssi1_dr_d_13, 2), 923 INGENIC_PIN_GROUP("ssi1-dr-d-20", jz4760_ssi1_dr_d_20, 2), 924 INGENIC_PIN_GROUP("ssi1-dr-e", jz4760_ssi1_dr_e, 1), 925 INGENIC_PIN_GROUP("ssi1-dr-f", jz4760_ssi1_dr_f, 2), 926 INGENIC_PIN_GROUP("ssi1-clk-b-7", jz4760_ssi1_clk_b_7, 2), 927 INGENIC_PIN_GROUP("ssi1-clk-b-28", jz4760_ssi1_clk_b_28, 2), 928 INGENIC_PIN_GROUP("ssi1-clk-d", jz4760_ssi1_clk_d, 2), 929 INGENIC_PIN_GROUP("ssi1-clk-e-7", jz4760_ssi1_clk_e_7, 2), 930 INGENIC_PIN_GROUP("ssi1-clk-e-15", jz4760_ssi1_clk_e_15, 1), 931 INGENIC_PIN_GROUP("ssi1-clk-f", jz4760_ssi1_clk_f, 2), 932 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4760_ssi1_gpc_b, 2), 933 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4760_ssi1_gpc_d, 2), 934 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4760_ssi1_gpc_e, 1), 935 INGENIC_PIN_GROUP("ssi1-ce0-b-8", jz4760_ssi1_ce0_b_8, 2), 936 INGENIC_PIN_GROUP("ssi1-ce0-b-29", jz4760_ssi1_ce0_b_29, 2), 937 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4760_ssi1_ce0_d, 2), 938 INGENIC_PIN_GROUP("ssi1-ce0-e-6", jz4760_ssi1_ce0_e_6, 2), 939 INGENIC_PIN_GROUP("ssi1-ce0-e-16", jz4760_ssi1_ce0_e_16, 1), 940 INGENIC_PIN_GROUP("ssi1-ce0-f", jz4760_ssi1_ce0_f, 2), 941 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4760_ssi1_ce1_b, 2), 942 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4760_ssi1_ce1_d, 2), 943 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4760_ssi1_ce1_e, 1), 944 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4760_mmc0_1bit_a, 945 jz4760_mmc0_1bit_a_funcs), 946 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a, 1), 947 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e, 0), 948 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e, 0), 949 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e, 0), 950 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d, 0), 951 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d, 0), 952 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e, 1), 953 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e, 1), 954 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e, 1), 955 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b, 0), 956 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b, 0), 957 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e, 2), 958 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e, 2), 959 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e, 2), 960 INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data, 0), 961 INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data, 0), 962 INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale, 0), 963 INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr, 0), 964 INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we, 0), 965 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe, 0), 966 INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait, 0), 967 INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1, 0), 968 INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2, 0), 969 INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3, 0), 970 INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4, 0), 971 INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5, 0), 972 INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6, 0), 973 INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0, 0), 974 INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1, 0), 975 INGENIC_PIN_GROUP("cim-data", jz4760_cim, 0), 976 INGENIC_PIN_GROUP("lcd-8bit", jz4760_lcd_8bit, 0), 977 INGENIC_PIN_GROUP("lcd-16bit", jz4760_lcd_16bit, 0), 978 INGENIC_PIN_GROUP("lcd-18bit", jz4760_lcd_18bit, 0), 979 INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit, 0), 980 INGENIC_PIN_GROUP("lcd-special", jz4760_lcd_special, 1), 981 INGENIC_PIN_GROUP("lcd-generic", jz4760_lcd_generic, 0), 982 INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0, 0), 983 INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1, 0), 984 INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2, 0), 985 INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3, 0), 986 INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4, 0), 987 INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5, 0), 988 INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6, 0), 989 INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7, 0), 990 INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0), 991 }; 992 993 static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 994 static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 995 static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 996 static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 997 static const char *jz4760_ssi0_groups[] = { 998 "ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e", 999 "ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e", 1000 "ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e", 1001 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e", 1002 "ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e", 1003 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e", 1004 }; 1005 static const char *jz4760_ssi1_groups[] = { 1006 "ssi1-dt-b-9", "ssi1-dt-b-21", "ssi1-dt-d-12", "ssi1-dt-d-21", "ssi1-dt-e", "ssi1-dt-f", 1007 "ssi1-dr-b-6", "ssi1-dr-b-20", "ssi1-dr-d-13", "ssi1-dr-d-20", "ssi1-dr-e", "ssi1-dr-f", 1008 "ssi1-clk-b-7", "ssi1-clk-b-28", "ssi1-clk-d", "ssi1-clk-e-7", "ssi1-clk-e-15", "ssi1-clk-f", 1009 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e", 1010 "ssi1-ce0-b-8", "ssi1-ce0-b-29", "ssi1-ce0-d", "ssi1-ce0-e-6", "ssi1-ce0-e-16", "ssi1-ce0-f", 1011 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e", 1012 }; 1013 static const char *jz4760_mmc0_groups[] = { 1014 "mmc0-1bit-a", "mmc0-4bit-a", 1015 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e", 1016 }; 1017 static const char *jz4760_mmc1_groups[] = { 1018 "mmc1-1bit-d", "mmc1-4bit-d", 1019 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e", 1020 }; 1021 static const char *jz4760_mmc2_groups[] = { 1022 "mmc2-1bit-b", "mmc2-4bit-b", 1023 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e", 1024 }; 1025 static const char *jz4760_nemc_groups[] = { 1026 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale", 1027 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 1028 }; 1029 static const char *jz4760_cs1_groups[] = { "nemc-cs1", }; 1030 static const char *jz4760_cs2_groups[] = { "nemc-cs2", }; 1031 static const char *jz4760_cs3_groups[] = { "nemc-cs3", }; 1032 static const char *jz4760_cs4_groups[] = { "nemc-cs4", }; 1033 static const char *jz4760_cs5_groups[] = { "nemc-cs5", }; 1034 static const char *jz4760_cs6_groups[] = { "nemc-cs6", }; 1035 static const char *jz4760_i2c0_groups[] = { "i2c0-data", }; 1036 static const char *jz4760_i2c1_groups[] = { "i2c1-data", }; 1037 static const char *jz4760_cim_groups[] = { "cim-data", }; 1038 static const char *jz4760_lcd_groups[] = { 1039 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 1040 "lcd-special", "lcd-generic", 1041 }; 1042 static const char *jz4760_pwm0_groups[] = { "pwm0", }; 1043 static const char *jz4760_pwm1_groups[] = { "pwm1", }; 1044 static const char *jz4760_pwm2_groups[] = { "pwm2", }; 1045 static const char *jz4760_pwm3_groups[] = { "pwm3", }; 1046 static const char *jz4760_pwm4_groups[] = { "pwm4", }; 1047 static const char *jz4760_pwm5_groups[] = { "pwm5", }; 1048 static const char *jz4760_pwm6_groups[] = { "pwm6", }; 1049 static const char *jz4760_pwm7_groups[] = { "pwm7", }; 1050 static const char *jz4760_otg_groups[] = { "otg-vbus", }; 1051 1052 static const struct function_desc jz4760_functions[] = { 1053 { "uart0", jz4760_uart0_groups, ARRAY_SIZE(jz4760_uart0_groups), }, 1054 { "uart1", jz4760_uart1_groups, ARRAY_SIZE(jz4760_uart1_groups), }, 1055 { "uart2", jz4760_uart2_groups, ARRAY_SIZE(jz4760_uart2_groups), }, 1056 { "uart3", jz4760_uart3_groups, ARRAY_SIZE(jz4760_uart3_groups), }, 1057 { "ssi0", jz4760_ssi0_groups, ARRAY_SIZE(jz4760_ssi0_groups), }, 1058 { "ssi1", jz4760_ssi1_groups, ARRAY_SIZE(jz4760_ssi1_groups), }, 1059 { "mmc0", jz4760_mmc0_groups, ARRAY_SIZE(jz4760_mmc0_groups), }, 1060 { "mmc1", jz4760_mmc1_groups, ARRAY_SIZE(jz4760_mmc1_groups), }, 1061 { "mmc2", jz4760_mmc2_groups, ARRAY_SIZE(jz4760_mmc2_groups), }, 1062 { "nemc", jz4760_nemc_groups, ARRAY_SIZE(jz4760_nemc_groups), }, 1063 { "nemc-cs1", jz4760_cs1_groups, ARRAY_SIZE(jz4760_cs1_groups), }, 1064 { "nemc-cs2", jz4760_cs2_groups, ARRAY_SIZE(jz4760_cs2_groups), }, 1065 { "nemc-cs3", jz4760_cs3_groups, ARRAY_SIZE(jz4760_cs3_groups), }, 1066 { "nemc-cs4", jz4760_cs4_groups, ARRAY_SIZE(jz4760_cs4_groups), }, 1067 { "nemc-cs5", jz4760_cs5_groups, ARRAY_SIZE(jz4760_cs5_groups), }, 1068 { "nemc-cs6", jz4760_cs6_groups, ARRAY_SIZE(jz4760_cs6_groups), }, 1069 { "i2c0", jz4760_i2c0_groups, ARRAY_SIZE(jz4760_i2c0_groups), }, 1070 { "i2c1", jz4760_i2c1_groups, ARRAY_SIZE(jz4760_i2c1_groups), }, 1071 { "cim", jz4760_cim_groups, ARRAY_SIZE(jz4760_cim_groups), }, 1072 { "lcd", jz4760_lcd_groups, ARRAY_SIZE(jz4760_lcd_groups), }, 1073 { "pwm0", jz4760_pwm0_groups, ARRAY_SIZE(jz4760_pwm0_groups), }, 1074 { "pwm1", jz4760_pwm1_groups, ARRAY_SIZE(jz4760_pwm1_groups), }, 1075 { "pwm2", jz4760_pwm2_groups, ARRAY_SIZE(jz4760_pwm2_groups), }, 1076 { "pwm3", jz4760_pwm3_groups, ARRAY_SIZE(jz4760_pwm3_groups), }, 1077 { "pwm4", jz4760_pwm4_groups, ARRAY_SIZE(jz4760_pwm4_groups), }, 1078 { "pwm5", jz4760_pwm5_groups, ARRAY_SIZE(jz4760_pwm5_groups), }, 1079 { "pwm6", jz4760_pwm6_groups, ARRAY_SIZE(jz4760_pwm6_groups), }, 1080 { "pwm7", jz4760_pwm7_groups, ARRAY_SIZE(jz4760_pwm7_groups), }, 1081 { "otg", jz4760_otg_groups, ARRAY_SIZE(jz4760_otg_groups), }, 1082 }; 1083 1084 static const struct ingenic_chip_info jz4760_chip_info = { 1085 .num_chips = 6, 1086 .reg_offset = 0x100, 1087 .version = ID_JZ4760, 1088 .groups = jz4760_groups, 1089 .num_groups = ARRAY_SIZE(jz4760_groups), 1090 .functions = jz4760_functions, 1091 .num_functions = ARRAY_SIZE(jz4760_functions), 1092 .pull_ups = jz4760_pull_ups, 1093 .pull_downs = jz4760_pull_downs, 1094 }; 1095 1096 static const u32 jz4770_pull_ups[6] = { 1097 0x3fffffff, 0xfff0f3fc, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0x0024f00f, 1098 }; 1099 1100 static const u32 jz4770_pull_downs[6] = { 1101 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x005b0ff0, 1102 }; 1103 1104 static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, }; 1105 static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; 1106 static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, }; 1107 static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; 1108 static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, }; 1109 static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, }; 1110 static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, }; 1111 static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, }; 1112 static int jz4770_ssi0_dt_a_pins[] = { 0x15, }; 1113 static int jz4770_ssi0_dt_b_pins[] = { 0x35, }; 1114 static int jz4770_ssi0_dt_d_pins[] = { 0x75, }; 1115 static int jz4770_ssi0_dt_e_pins[] = { 0x91, }; 1116 static int jz4770_ssi0_dr_a_pins[] = { 0x14, }; 1117 static int jz4770_ssi0_dr_b_pins[] = { 0x34, }; 1118 static int jz4770_ssi0_dr_d_pins[] = { 0x74, }; 1119 static int jz4770_ssi0_dr_e_pins[] = { 0x8e, }; 1120 static int jz4770_ssi0_clk_a_pins[] = { 0x12, }; 1121 static int jz4770_ssi0_clk_b_pins[] = { 0x3c, }; 1122 static int jz4770_ssi0_clk_d_pins[] = { 0x78, }; 1123 static int jz4770_ssi0_clk_e_pins[] = { 0x8f, }; 1124 static int jz4770_ssi0_gpc_b_pins[] = { 0x3e, }; 1125 static int jz4770_ssi0_gpc_d_pins[] = { 0x76, }; 1126 static int jz4770_ssi0_gpc_e_pins[] = { 0x93, }; 1127 static int jz4770_ssi0_ce0_a_pins[] = { 0x13, }; 1128 static int jz4770_ssi0_ce0_b_pins[] = { 0x3d, }; 1129 static int jz4770_ssi0_ce0_d_pins[] = { 0x79, }; 1130 static int jz4770_ssi0_ce0_e_pins[] = { 0x90, }; 1131 static int jz4770_ssi0_ce1_b_pins[] = { 0x3f, }; 1132 static int jz4770_ssi0_ce1_d_pins[] = { 0x77, }; 1133 static int jz4770_ssi0_ce1_e_pins[] = { 0x92, }; 1134 static int jz4770_ssi1_dt_b_pins[] = { 0x35, }; 1135 static int jz4770_ssi1_dt_d_pins[] = { 0x75, }; 1136 static int jz4770_ssi1_dt_e_pins[] = { 0x91, }; 1137 static int jz4770_ssi1_dr_b_pins[] = { 0x34, }; 1138 static int jz4770_ssi1_dr_d_pins[] = { 0x74, }; 1139 static int jz4770_ssi1_dr_e_pins[] = { 0x8e, }; 1140 static int jz4770_ssi1_clk_b_pins[] = { 0x3c, }; 1141 static int jz4770_ssi1_clk_d_pins[] = { 0x78, }; 1142 static int jz4770_ssi1_clk_e_pins[] = { 0x8f, }; 1143 static int jz4770_ssi1_gpc_b_pins[] = { 0x3e, }; 1144 static int jz4770_ssi1_gpc_d_pins[] = { 0x76, }; 1145 static int jz4770_ssi1_gpc_e_pins[] = { 0x93, }; 1146 static int jz4770_ssi1_ce0_b_pins[] = { 0x3d, }; 1147 static int jz4770_ssi1_ce0_d_pins[] = { 0x79, }; 1148 static int jz4770_ssi1_ce0_e_pins[] = { 0x90, }; 1149 static int jz4770_ssi1_ce1_b_pins[] = { 0x3f, }; 1150 static int jz4770_ssi1_ce1_d_pins[] = { 0x77, }; 1151 static int jz4770_ssi1_ce1_e_pins[] = { 0x92, }; 1152 static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; 1153 static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; 1154 static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1155 static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1156 static int jz4770_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 1157 static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; 1158 static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; 1159 static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1160 static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1161 static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 1162 static int jz4770_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, }; 1163 static int jz4770_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, }; 1164 static int jz4770_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1165 static int jz4770_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1166 static int jz4770_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 1167 static int jz4770_nemc_8bit_data_pins[] = { 1168 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 1169 }; 1170 static int jz4770_nemc_16bit_data_pins[] = { 1171 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 1172 }; 1173 static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, }; 1174 static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; 1175 static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, }; 1176 static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; 1177 static int jz4770_nemc_wait_pins[] = { 0x1b, }; 1178 static int jz4770_nemc_cs1_pins[] = { 0x15, }; 1179 static int jz4770_nemc_cs2_pins[] = { 0x16, }; 1180 static int jz4770_nemc_cs3_pins[] = { 0x17, }; 1181 static int jz4770_nemc_cs4_pins[] = { 0x18, }; 1182 static int jz4770_nemc_cs5_pins[] = { 0x19, }; 1183 static int jz4770_nemc_cs6_pins[] = { 0x1a, }; 1184 static int jz4770_i2c0_pins[] = { 0x7e, 0x7f, }; 1185 static int jz4770_i2c1_pins[] = { 0x9e, 0x9f, }; 1186 static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, }; 1187 static int jz4770_cim_8bit_pins[] = { 1188 0x26, 0x27, 0x28, 0x29, 1189 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 1190 }; 1191 static int jz4770_cim_12bit_pins[] = { 1192 0x32, 0x33, 0xb0, 0xb1, 1193 }; 1194 static int jz4770_lcd_8bit_pins[] = { 1195 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d, 1196 0x48, 0x52, 0x53, 1197 }; 1198 static int jz4770_lcd_16bit_pins[] = { 1199 0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59, 1200 }; 1201 static int jz4770_lcd_18bit_pins[] = { 1202 0x5a, 0x5b, 1203 }; 1204 static int jz4770_lcd_24bit_pins[] = { 1205 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 1206 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 1207 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 1208 0x58, 0x59, 0x5a, 0x5b, 1209 }; 1210 static int jz4770_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, }; 1211 static int jz4770_lcd_generic_pins[] = { 0x49, }; 1212 static int jz4770_pwm_pwm0_pins[] = { 0x80, }; 1213 static int jz4770_pwm_pwm1_pins[] = { 0x81, }; 1214 static int jz4770_pwm_pwm2_pins[] = { 0x82, }; 1215 static int jz4770_pwm_pwm3_pins[] = { 0x83, }; 1216 static int jz4770_pwm_pwm4_pins[] = { 0x84, }; 1217 static int jz4770_pwm_pwm5_pins[] = { 0x85, }; 1218 static int jz4770_pwm_pwm6_pins[] = { 0x6a, }; 1219 static int jz4770_pwm_pwm7_pins[] = { 0x6b, }; 1220 static int jz4770_mac_rmii_pins[] = { 1221 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8, 1222 }; 1223 static int jz4770_mac_mii_pins[] = { 1224 0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf, 1225 }; 1226 1227 static const struct group_desc jz4770_groups[] = { 1228 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0), 1229 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0), 1230 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0), 1231 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0), 1232 INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data, 0), 1233 INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow, 0), 1234 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data, 1235 jz4760_uart3_data_funcs), 1236 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0), 1237 INGENIC_PIN_GROUP("ssi0-dt-a", jz4770_ssi0_dt_a, 2), 1238 INGENIC_PIN_GROUP("ssi0-dt-b", jz4770_ssi0_dt_b, 1), 1239 INGENIC_PIN_GROUP("ssi0-dt-d", jz4770_ssi0_dt_d, 1), 1240 INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0), 1241 INGENIC_PIN_GROUP("ssi0-dr-a", jz4770_ssi0_dr_a, 1), 1242 INGENIC_PIN_GROUP("ssi0-dr-b", jz4770_ssi0_dr_b, 1), 1243 INGENIC_PIN_GROUP("ssi0-dr-d", jz4770_ssi0_dr_d, 1), 1244 INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0), 1245 INGENIC_PIN_GROUP("ssi0-clk-a", jz4770_ssi0_clk_a, 2), 1246 INGENIC_PIN_GROUP("ssi0-clk-b", jz4770_ssi0_clk_b, 1), 1247 INGENIC_PIN_GROUP("ssi0-clk-d", jz4770_ssi0_clk_d, 1), 1248 INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0), 1249 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4770_ssi0_gpc_b, 1), 1250 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4770_ssi0_gpc_d, 1), 1251 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0), 1252 INGENIC_PIN_GROUP("ssi0-ce0-a", jz4770_ssi0_ce0_a, 2), 1253 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4770_ssi0_ce0_b, 1), 1254 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4770_ssi0_ce0_d, 1), 1255 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0), 1256 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4770_ssi0_ce1_b, 1), 1257 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4770_ssi0_ce1_d, 1), 1258 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0), 1259 INGENIC_PIN_GROUP("ssi1-dt-b", jz4770_ssi1_dt_b, 2), 1260 INGENIC_PIN_GROUP("ssi1-dt-d", jz4770_ssi1_dt_d, 2), 1261 INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1), 1262 INGENIC_PIN_GROUP("ssi1-dr-b", jz4770_ssi1_dr_b, 2), 1263 INGENIC_PIN_GROUP("ssi1-dr-d", jz4770_ssi1_dr_d, 2), 1264 INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1), 1265 INGENIC_PIN_GROUP("ssi1-clk-b", jz4770_ssi1_clk_b, 2), 1266 INGENIC_PIN_GROUP("ssi1-clk-d", jz4770_ssi1_clk_d, 2), 1267 INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1), 1268 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4770_ssi1_gpc_b, 2), 1269 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4770_ssi1_gpc_d, 2), 1270 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1), 1271 INGENIC_PIN_GROUP("ssi1-ce0-b", jz4770_ssi1_ce0_b, 2), 1272 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4770_ssi1_ce0_d, 2), 1273 INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1), 1274 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4770_ssi1_ce1_b, 2), 1275 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4770_ssi1_ce1_d, 2), 1276 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1), 1277 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a, 1278 jz4760_mmc0_1bit_a_funcs), 1279 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1), 1280 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0), 1281 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0), 1282 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e, 0), 1283 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0), 1284 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0), 1285 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1), 1286 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1), 1287 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e, 1), 1288 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0), 1289 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0), 1290 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2), 1291 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2), 1292 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e, 2), 1293 INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data, 0), 1294 INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data, 0), 1295 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0), 1296 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0), 1297 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0), 1298 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0), 1299 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0), 1300 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0), 1301 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0), 1302 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0), 1303 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0), 1304 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0), 1305 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0), 1306 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0), 1307 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0), 1308 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2), 1309 INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit, 0), 1310 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0), 1311 INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0), 1312 INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0), 1313 INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0), 1314 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0), 1315 INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1), 1316 INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0), 1317 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0), 1318 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0), 1319 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0), 1320 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0), 1321 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0), 1322 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0), 1323 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0), 1324 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0), 1325 INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii, 0), 1326 INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii, 0), 1327 INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0), 1328 }; 1329 1330 static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1331 static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 1332 static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 1333 static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 1334 static const char *jz4770_ssi0_groups[] = { 1335 "ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e", 1336 "ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e", 1337 "ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e", 1338 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e", 1339 "ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e", 1340 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e", 1341 }; 1342 static const char *jz4770_ssi1_groups[] = { 1343 "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e", 1344 "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e", 1345 "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e", 1346 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e", 1347 "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e", 1348 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e", 1349 }; 1350 static const char *jz4770_mmc0_groups[] = { 1351 "mmc0-1bit-a", "mmc0-4bit-a", 1352 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e", 1353 }; 1354 static const char *jz4770_mmc1_groups[] = { 1355 "mmc1-1bit-d", "mmc1-4bit-d", 1356 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e", 1357 }; 1358 static const char *jz4770_mmc2_groups[] = { 1359 "mmc2-1bit-b", "mmc2-4bit-b", 1360 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e", 1361 }; 1362 static const char *jz4770_nemc_groups[] = { 1363 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale", 1364 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 1365 }; 1366 static const char *jz4770_cs1_groups[] = { "nemc-cs1", }; 1367 static const char *jz4770_cs2_groups[] = { "nemc-cs2", }; 1368 static const char *jz4770_cs3_groups[] = { "nemc-cs3", }; 1369 static const char *jz4770_cs4_groups[] = { "nemc-cs4", }; 1370 static const char *jz4770_cs5_groups[] = { "nemc-cs5", }; 1371 static const char *jz4770_cs6_groups[] = { "nemc-cs6", }; 1372 static const char *jz4770_i2c0_groups[] = { "i2c0-data", }; 1373 static const char *jz4770_i2c1_groups[] = { "i2c1-data", }; 1374 static const char *jz4770_i2c2_groups[] = { "i2c2-data", }; 1375 static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", }; 1376 static const char *jz4770_lcd_groups[] = { 1377 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 1378 "lcd-special", "lcd-generic", 1379 }; 1380 static const char *jz4770_pwm0_groups[] = { "pwm0", }; 1381 static const char *jz4770_pwm1_groups[] = { "pwm1", }; 1382 static const char *jz4770_pwm2_groups[] = { "pwm2", }; 1383 static const char *jz4770_pwm3_groups[] = { "pwm3", }; 1384 static const char *jz4770_pwm4_groups[] = { "pwm4", }; 1385 static const char *jz4770_pwm5_groups[] = { "pwm5", }; 1386 static const char *jz4770_pwm6_groups[] = { "pwm6", }; 1387 static const char *jz4770_pwm7_groups[] = { "pwm7", }; 1388 static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", }; 1389 1390 static const struct function_desc jz4770_functions[] = { 1391 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), }, 1392 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), }, 1393 { "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), }, 1394 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), }, 1395 { "ssi0", jz4770_ssi0_groups, ARRAY_SIZE(jz4770_ssi0_groups), }, 1396 { "ssi1", jz4770_ssi1_groups, ARRAY_SIZE(jz4770_ssi1_groups), }, 1397 { "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), }, 1398 { "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), }, 1399 { "mmc2", jz4770_mmc2_groups, ARRAY_SIZE(jz4770_mmc2_groups), }, 1400 { "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), }, 1401 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), }, 1402 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), }, 1403 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), }, 1404 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), }, 1405 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), }, 1406 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), }, 1407 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), }, 1408 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), }, 1409 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), }, 1410 { "cim", jz4770_cim_groups, ARRAY_SIZE(jz4770_cim_groups), }, 1411 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), }, 1412 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), }, 1413 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), }, 1414 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), }, 1415 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), }, 1416 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), }, 1417 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), }, 1418 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), }, 1419 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), }, 1420 { "mac", jz4770_mac_groups, ARRAY_SIZE(jz4770_mac_groups), }, 1421 { "otg", jz4760_otg_groups, ARRAY_SIZE(jz4760_otg_groups), }, 1422 }; 1423 1424 static const struct ingenic_chip_info jz4770_chip_info = { 1425 .num_chips = 6, 1426 .reg_offset = 0x100, 1427 .version = ID_JZ4770, 1428 .groups = jz4770_groups, 1429 .num_groups = ARRAY_SIZE(jz4770_groups), 1430 .functions = jz4770_functions, 1431 .num_functions = ARRAY_SIZE(jz4770_functions), 1432 .pull_ups = jz4770_pull_ups, 1433 .pull_downs = jz4770_pull_downs, 1434 }; 1435 1436 static const u32 jz4775_pull_ups[7] = { 1437 0x28ff00ff, 0xf030f3fc, 0x0fffffff, 0xfffe4000, 0xf0f0000c, 0x0000f00f, 0x0000f3c0, 1438 }; 1439 1440 static const u32 jz4775_pull_downs[7] = { 1441 0x00000000, 0x00030c03, 0x00000000, 0x00008000, 0x00000403, 0x00000ff0, 0x00030c00, 1442 }; 1443 1444 static int jz4775_uart0_data_pins[] = { 0xa0, 0xa3, }; 1445 static int jz4775_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; 1446 static int jz4775_uart1_data_pins[] = { 0x7a, 0x7c, }; 1447 static int jz4775_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; 1448 static int jz4775_uart2_data_c_pins[] = { 0x54, 0x4a, }; 1449 static int jz4775_uart2_data_f_pins[] = { 0xa5, 0xa4, }; 1450 static int jz4775_uart3_data_pins[] = { 0x1e, 0x1f, }; 1451 static int jz4775_ssi_dt_a_pins[] = { 0x13, }; 1452 static int jz4775_ssi_dt_d_pins[] = { 0x75, }; 1453 static int jz4775_ssi_dr_a_pins[] = { 0x14, }; 1454 static int jz4775_ssi_dr_d_pins[] = { 0x74, }; 1455 static int jz4775_ssi_clk_a_pins[] = { 0x12, }; 1456 static int jz4775_ssi_clk_d_pins[] = { 0x78, }; 1457 static int jz4775_ssi_gpc_pins[] = { 0x76, }; 1458 static int jz4775_ssi_ce0_a_pins[] = { 0x17, }; 1459 static int jz4775_ssi_ce0_d_pins[] = { 0x79, }; 1460 static int jz4775_ssi_ce1_pins[] = { 0x77, }; 1461 static int jz4775_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; 1462 static int jz4775_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; 1463 static int jz4775_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, }; 1464 static int jz4775_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1465 static int jz4775_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1466 static int jz4775_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; 1467 static int jz4775_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; 1468 static int jz4775_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1469 static int jz4775_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1470 static int jz4775_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, }; 1471 static int jz4775_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, }; 1472 static int jz4775_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1473 static int jz4775_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1474 static int jz4775_nemc_8bit_data_pins[] = { 1475 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 1476 }; 1477 static int jz4775_nemc_16bit_data_pins[] = { 1478 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, 0xd0, 0xd1, 1479 }; 1480 static int jz4775_nemc_cle_ale_pins[] = { 0x20, 0x21, }; 1481 static int jz4775_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; 1482 static int jz4775_nemc_rd_we_pins[] = { 0x10, 0x11, }; 1483 static int jz4775_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; 1484 static int jz4775_nemc_wait_pins[] = { 0x1b, }; 1485 static int jz4775_nemc_cs1_pins[] = { 0x15, }; 1486 static int jz4775_nemc_cs2_pins[] = { 0x16, }; 1487 static int jz4775_nemc_cs3_pins[] = { 0x17, }; 1488 static int jz4775_i2c0_pins[] = { 0x7e, 0x7f, }; 1489 static int jz4775_i2c1_pins[] = { 0x9e, 0x9f, }; 1490 static int jz4775_i2c2_pins[] = { 0x80, 0x83, }; 1491 static int jz4775_i2s_data_tx_pins[] = { 0xa3, }; 1492 static int jz4775_i2s_data_rx_pins[] = { 0xa2, }; 1493 static int jz4775_i2s_clk_txrx_pins[] = { 0xa0, 0xa1, }; 1494 static int jz4775_i2s_sysclk_pins[] = { 0x83, }; 1495 static int jz4775_dmic_pins[] = { 0xaa, 0xab, }; 1496 static int jz4775_cim_pins[] = { 1497 0x26, 0x27, 0x28, 0x29, 1498 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 1499 }; 1500 static int jz4775_lcd_8bit_pins[] = { 1501 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d, 1502 0x48, 0x52, 0x53, 1503 }; 1504 static int jz4775_lcd_16bit_pins[] = { 1505 0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59, 1506 }; 1507 static int jz4775_lcd_18bit_pins[] = { 1508 0x5a, 0x5b, 1509 }; 1510 static int jz4775_lcd_24bit_pins[] = { 1511 0x40, 0x41, 0x4a, 0x4b, 0x54, 0x55, 1512 }; 1513 static int jz4775_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, }; 1514 static int jz4775_lcd_generic_pins[] = { 0x49, }; 1515 static int jz4775_pwm_pwm0_pins[] = { 0x80, }; 1516 static int jz4775_pwm_pwm1_pins[] = { 0x81, }; 1517 static int jz4775_pwm_pwm2_pins[] = { 0x82, }; 1518 static int jz4775_pwm_pwm3_pins[] = { 0x83, }; 1519 static int jz4775_mac_rmii_pins[] = { 1520 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8, 1521 }; 1522 static int jz4775_mac_mii_pins[] = { 1523 0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf, 1524 }; 1525 static int jz4775_mac_rgmii_pins[] = { 1526 0xa9, 0x7b, 0x7a, 0xab, 0xaa, 0xac, 0x7d, 0x7c, 0xa5, 0xa4, 1527 0xad, 0xae, 0xa7, 0xa6, 1528 }; 1529 static int jz4775_mac_gmii_pins[] = { 1530 0x31, 0x30, 0x2f, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 1531 0xa8, 0x28, 0x24, 0xaf, 1532 }; 1533 static int jz4775_otg_pins[] = { 0x8a, }; 1534 1535 static u8 jz4775_uart3_data_funcs[] = { 0, 1, }; 1536 static u8 jz4775_mac_mii_funcs[] = { 1, 1, 1, 1, 0, 1, 0, }; 1537 static u8 jz4775_mac_rgmii_funcs[] = { 1538 0, 1, 1, 0, 0, 0, 1, 1, 0, 0, 1539 0, 0, 0, 0, 1540 }; 1541 static u8 jz4775_mac_gmii_funcs[] = { 1542 1, 1, 1, 1, 1, 1, 1, 1, 1543 0, 1, 1, 0, 1544 }; 1545 1546 static const struct group_desc jz4775_groups[] = { 1547 INGENIC_PIN_GROUP("uart0-data", jz4775_uart0_data, 0), 1548 INGENIC_PIN_GROUP("uart0-hwflow", jz4775_uart0_hwflow, 0), 1549 INGENIC_PIN_GROUP("uart1-data", jz4775_uart1_data, 0), 1550 INGENIC_PIN_GROUP("uart1-hwflow", jz4775_uart1_hwflow, 0), 1551 INGENIC_PIN_GROUP("uart2-data-c", jz4775_uart2_data_c, 2), 1552 INGENIC_PIN_GROUP("uart2-data-f", jz4775_uart2_data_f, 1), 1553 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4775_uart3_data, 1554 jz4775_uart3_data_funcs), 1555 INGENIC_PIN_GROUP("ssi-dt-a", jz4775_ssi_dt_a, 2), 1556 INGENIC_PIN_GROUP("ssi-dt-d", jz4775_ssi_dt_d, 1), 1557 INGENIC_PIN_GROUP("ssi-dr-a", jz4775_ssi_dr_a, 2), 1558 INGENIC_PIN_GROUP("ssi-dr-d", jz4775_ssi_dr_d, 1), 1559 INGENIC_PIN_GROUP("ssi-clk-a", jz4775_ssi_clk_a, 2), 1560 INGENIC_PIN_GROUP("ssi-clk-d", jz4775_ssi_clk_d, 1), 1561 INGENIC_PIN_GROUP("ssi-gpc", jz4775_ssi_gpc, 1), 1562 INGENIC_PIN_GROUP("ssi-ce0-a", jz4775_ssi_ce0_a, 2), 1563 INGENIC_PIN_GROUP("ssi-ce0-d", jz4775_ssi_ce0_d, 1), 1564 INGENIC_PIN_GROUP("ssi-ce1", jz4775_ssi_ce1, 1), 1565 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4775_mmc0_1bit_a, 1), 1566 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4775_mmc0_4bit_a, 1), 1567 INGENIC_PIN_GROUP("mmc0-8bit-a", jz4775_mmc0_8bit_a, 1), 1568 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4775_mmc0_1bit_e, 0), 1569 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4775_mmc0_4bit_e, 0), 1570 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4775_mmc1_1bit_d, 0), 1571 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4775_mmc1_4bit_d, 0), 1572 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4775_mmc1_1bit_e, 1), 1573 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4775_mmc1_4bit_e, 1), 1574 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4775_mmc2_1bit_b, 0), 1575 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4775_mmc2_4bit_b, 0), 1576 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4775_mmc2_1bit_e, 2), 1577 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4775_mmc2_4bit_e, 2), 1578 INGENIC_PIN_GROUP("nemc-8bit-data", jz4775_nemc_8bit_data, 0), 1579 INGENIC_PIN_GROUP("nemc-16bit-data", jz4775_nemc_16bit_data, 1), 1580 INGENIC_PIN_GROUP("nemc-cle-ale", jz4775_nemc_cle_ale, 0), 1581 INGENIC_PIN_GROUP("nemc-addr", jz4775_nemc_addr, 0), 1582 INGENIC_PIN_GROUP("nemc-rd-we", jz4775_nemc_rd_we, 0), 1583 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4775_nemc_frd_fwe, 0), 1584 INGENIC_PIN_GROUP("nemc-wait", jz4775_nemc_wait, 0), 1585 INGENIC_PIN_GROUP("nemc-cs1", jz4775_nemc_cs1, 0), 1586 INGENIC_PIN_GROUP("nemc-cs2", jz4775_nemc_cs2, 0), 1587 INGENIC_PIN_GROUP("nemc-cs3", jz4775_nemc_cs3, 0), 1588 INGENIC_PIN_GROUP("i2c0-data", jz4775_i2c0, 0), 1589 INGENIC_PIN_GROUP("i2c1-data", jz4775_i2c1, 0), 1590 INGENIC_PIN_GROUP("i2c2-data", jz4775_i2c2, 1), 1591 INGENIC_PIN_GROUP("i2s-data-tx", jz4775_i2s_data_tx, 1), 1592 INGENIC_PIN_GROUP("i2s-data-rx", jz4775_i2s_data_rx, 1), 1593 INGENIC_PIN_GROUP("i2s-clk-txrx", jz4775_i2s_clk_txrx, 1), 1594 INGENIC_PIN_GROUP("i2s-sysclk", jz4775_i2s_sysclk, 2), 1595 INGENIC_PIN_GROUP("dmic", jz4775_dmic, 1), 1596 INGENIC_PIN_GROUP("cim-data", jz4775_cim, 0), 1597 INGENIC_PIN_GROUP("lcd-8bit", jz4775_lcd_8bit, 0), 1598 INGENIC_PIN_GROUP("lcd-16bit", jz4775_lcd_16bit, 0), 1599 INGENIC_PIN_GROUP("lcd-18bit", jz4775_lcd_18bit, 0), 1600 INGENIC_PIN_GROUP("lcd-24bit", jz4775_lcd_24bit, 0), 1601 INGENIC_PIN_GROUP("lcd-generic", jz4775_lcd_generic, 0), 1602 INGENIC_PIN_GROUP("lcd-special", jz4775_lcd_special, 1), 1603 INGENIC_PIN_GROUP("pwm0", jz4775_pwm_pwm0, 0), 1604 INGENIC_PIN_GROUP("pwm1", jz4775_pwm_pwm1, 0), 1605 INGENIC_PIN_GROUP("pwm2", jz4775_pwm_pwm2, 0), 1606 INGENIC_PIN_GROUP("pwm3", jz4775_pwm_pwm3, 0), 1607 INGENIC_PIN_GROUP("mac-rmii", jz4775_mac_rmii, 0), 1608 INGENIC_PIN_GROUP_FUNCS("mac-mii", jz4775_mac_mii, 1609 jz4775_mac_mii_funcs), 1610 INGENIC_PIN_GROUP_FUNCS("mac-rgmii", jz4775_mac_rgmii, 1611 jz4775_mac_rgmii_funcs), 1612 INGENIC_PIN_GROUP_FUNCS("mac-gmii", jz4775_mac_gmii, 1613 jz4775_mac_gmii_funcs), 1614 INGENIC_PIN_GROUP("otg-vbus", jz4775_otg, 0), 1615 }; 1616 1617 static const char *jz4775_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1618 static const char *jz4775_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 1619 static const char *jz4775_uart2_groups[] = { "uart2-data-c", "uart2-data-f", }; 1620 static const char *jz4775_uart3_groups[] = { "uart3-data", }; 1621 static const char *jz4775_ssi_groups[] = { 1622 "ssi-dt-a", "ssi-dt-d", 1623 "ssi-dr-a", "ssi-dr-d", 1624 "ssi-clk-a", "ssi-clk-d", 1625 "ssi-gpc", 1626 "ssi-ce0-a", "ssi-ce0-d", 1627 "ssi-ce1", 1628 }; 1629 static const char *jz4775_mmc0_groups[] = { 1630 "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a", 1631 "mmc0-1bit-e", "mmc0-4bit-e", 1632 }; 1633 static const char *jz4775_mmc1_groups[] = { 1634 "mmc1-1bit-d", "mmc1-4bit-d", 1635 "mmc1-1bit-e", "mmc1-4bit-e", 1636 }; 1637 static const char *jz4775_mmc2_groups[] = { 1638 "mmc2-1bit-b", "mmc2-4bit-b", 1639 "mmc2-1bit-e", "mmc2-4bit-e", 1640 }; 1641 static const char *jz4775_nemc_groups[] = { 1642 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale", 1643 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 1644 }; 1645 static const char *jz4775_cs1_groups[] = { "nemc-cs1", }; 1646 static const char *jz4775_cs2_groups[] = { "nemc-cs2", }; 1647 static const char *jz4775_cs3_groups[] = { "nemc-cs3", }; 1648 static const char *jz4775_i2c0_groups[] = { "i2c0-data", }; 1649 static const char *jz4775_i2c1_groups[] = { "i2c1-data", }; 1650 static const char *jz4775_i2c2_groups[] = { "i2c2-data", }; 1651 static const char *jz4775_i2s_groups[] = { 1652 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk", 1653 }; 1654 static const char *jz4775_dmic_groups[] = { "dmic", }; 1655 static const char *jz4775_cim_groups[] = { "cim-data", }; 1656 static const char *jz4775_lcd_groups[] = { 1657 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 1658 "lcd-special", "lcd-generic", 1659 }; 1660 static const char *jz4775_pwm0_groups[] = { "pwm0", }; 1661 static const char *jz4775_pwm1_groups[] = { "pwm1", }; 1662 static const char *jz4775_pwm2_groups[] = { "pwm2", }; 1663 static const char *jz4775_pwm3_groups[] = { "pwm3", }; 1664 static const char *jz4775_mac_groups[] = { 1665 "mac-rmii", "mac-mii", "mac-rgmii", "mac-gmii", 1666 }; 1667 static const char *jz4775_otg_groups[] = { "otg-vbus", }; 1668 1669 static const struct function_desc jz4775_functions[] = { 1670 { "uart0", jz4775_uart0_groups, ARRAY_SIZE(jz4775_uart0_groups), }, 1671 { "uart1", jz4775_uart1_groups, ARRAY_SIZE(jz4775_uart1_groups), }, 1672 { "uart2", jz4775_uart2_groups, ARRAY_SIZE(jz4775_uart2_groups), }, 1673 { "uart3", jz4775_uart3_groups, ARRAY_SIZE(jz4775_uart3_groups), }, 1674 { "ssi", jz4775_ssi_groups, ARRAY_SIZE(jz4775_ssi_groups), }, 1675 { "mmc0", jz4775_mmc0_groups, ARRAY_SIZE(jz4775_mmc0_groups), }, 1676 { "mmc1", jz4775_mmc1_groups, ARRAY_SIZE(jz4775_mmc1_groups), }, 1677 { "mmc2", jz4775_mmc2_groups, ARRAY_SIZE(jz4775_mmc2_groups), }, 1678 { "nemc", jz4775_nemc_groups, ARRAY_SIZE(jz4775_nemc_groups), }, 1679 { "nemc-cs1", jz4775_cs1_groups, ARRAY_SIZE(jz4775_cs1_groups), }, 1680 { "nemc-cs2", jz4775_cs2_groups, ARRAY_SIZE(jz4775_cs2_groups), }, 1681 { "nemc-cs3", jz4775_cs3_groups, ARRAY_SIZE(jz4775_cs3_groups), }, 1682 { "i2c0", jz4775_i2c0_groups, ARRAY_SIZE(jz4775_i2c0_groups), }, 1683 { "i2c1", jz4775_i2c1_groups, ARRAY_SIZE(jz4775_i2c1_groups), }, 1684 { "i2c2", jz4775_i2c2_groups, ARRAY_SIZE(jz4775_i2c2_groups), }, 1685 { "i2s", jz4775_i2s_groups, ARRAY_SIZE(jz4775_i2s_groups), }, 1686 { "dmic", jz4775_dmic_groups, ARRAY_SIZE(jz4775_dmic_groups), }, 1687 { "cim", jz4775_cim_groups, ARRAY_SIZE(jz4775_cim_groups), }, 1688 { "lcd", jz4775_lcd_groups, ARRAY_SIZE(jz4775_lcd_groups), }, 1689 { "pwm0", jz4775_pwm0_groups, ARRAY_SIZE(jz4775_pwm0_groups), }, 1690 { "pwm1", jz4775_pwm1_groups, ARRAY_SIZE(jz4775_pwm1_groups), }, 1691 { "pwm2", jz4775_pwm2_groups, ARRAY_SIZE(jz4775_pwm2_groups), }, 1692 { "pwm3", jz4775_pwm3_groups, ARRAY_SIZE(jz4775_pwm3_groups), }, 1693 { "mac", jz4775_mac_groups, ARRAY_SIZE(jz4775_mac_groups), }, 1694 { "otg", jz4775_otg_groups, ARRAY_SIZE(jz4775_otg_groups), }, 1695 }; 1696 1697 static const struct ingenic_chip_info jz4775_chip_info = { 1698 .num_chips = 7, 1699 .reg_offset = 0x100, 1700 .version = ID_JZ4775, 1701 .groups = jz4775_groups, 1702 .num_groups = ARRAY_SIZE(jz4775_groups), 1703 .functions = jz4775_functions, 1704 .num_functions = ARRAY_SIZE(jz4775_functions), 1705 .pull_ups = jz4775_pull_ups, 1706 .pull_downs = jz4775_pull_downs, 1707 }; 1708 1709 static const u32 jz4780_pull_ups[6] = { 1710 0x3fffffff, 0xfff0f3fc, 0x0fffffff, 0xffff4fff, 0xfffffb7c, 0x7fa7f00f, 1711 }; 1712 1713 static const u32 jz4780_pull_downs[6] = { 1714 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0, 1715 }; 1716 1717 static int jz4780_uart2_data_pins[] = { 0x66, 0x67, }; 1718 static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, }; 1719 static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, }; 1720 static int jz4780_ssi0_dt_a_19_pins[] = { 0x13, }; 1721 static int jz4780_ssi0_dt_a_21_pins[] = { 0x15, }; 1722 static int jz4780_ssi0_dt_a_28_pins[] = { 0x1c, }; 1723 static int jz4780_ssi0_dt_b_pins[] = { 0x3d, }; 1724 static int jz4780_ssi0_dt_d_pins[] = { 0x79, }; 1725 static int jz4780_ssi0_dr_a_20_pins[] = { 0x14, }; 1726 static int jz4780_ssi0_dr_a_27_pins[] = { 0x1b, }; 1727 static int jz4780_ssi0_dr_b_pins[] = { 0x34, }; 1728 static int jz4780_ssi0_dr_d_pins[] = { 0x74, }; 1729 static int jz4780_ssi0_clk_a_pins[] = { 0x12, }; 1730 static int jz4780_ssi0_clk_b_5_pins[] = { 0x25, }; 1731 static int jz4780_ssi0_clk_b_28_pins[] = { 0x3c, }; 1732 static int jz4780_ssi0_clk_d_pins[] = { 0x78, }; 1733 static int jz4780_ssi0_gpc_b_pins[] = { 0x3e, }; 1734 static int jz4780_ssi0_gpc_d_pins[] = { 0x76, }; 1735 static int jz4780_ssi0_ce0_a_23_pins[] = { 0x17, }; 1736 static int jz4780_ssi0_ce0_a_25_pins[] = { 0x19, }; 1737 static int jz4780_ssi0_ce0_b_pins[] = { 0x3f, }; 1738 static int jz4780_ssi0_ce0_d_pins[] = { 0x77, }; 1739 static int jz4780_ssi0_ce1_b_pins[] = { 0x35, }; 1740 static int jz4780_ssi0_ce1_d_pins[] = { 0x75, }; 1741 static int jz4780_ssi1_dt_b_pins[] = { 0x3d, }; 1742 static int jz4780_ssi1_dt_d_pins[] = { 0x79, }; 1743 static int jz4780_ssi1_dr_b_pins[] = { 0x34, }; 1744 static int jz4780_ssi1_dr_d_pins[] = { 0x74, }; 1745 static int jz4780_ssi1_clk_b_pins[] = { 0x3c, }; 1746 static int jz4780_ssi1_clk_d_pins[] = { 0x78, }; 1747 static int jz4780_ssi1_gpc_b_pins[] = { 0x3e, }; 1748 static int jz4780_ssi1_gpc_d_pins[] = { 0x76, }; 1749 static int jz4780_ssi1_ce0_b_pins[] = { 0x3f, }; 1750 static int jz4780_ssi1_ce0_d_pins[] = { 0x77, }; 1751 static int jz4780_ssi1_ce1_b_pins[] = { 0x35, }; 1752 static int jz4780_ssi1_ce1_d_pins[] = { 0x75, }; 1753 static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, }; 1754 static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, }; 1755 static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, }; 1756 static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, }; 1757 static int jz4780_i2s_data_tx_pins[] = { 0x87, }; 1758 static int jz4780_i2s_data_rx_pins[] = { 0x86, }; 1759 static int jz4780_i2s_clk_txrx_pins[] = { 0x6c, 0x6d, }; 1760 static int jz4780_i2s_clk_rx_pins[] = { 0x88, 0x89, }; 1761 static int jz4780_i2s_sysclk_pins[] = { 0x85, }; 1762 static int jz4780_dmic_pins[] = { 0x32, 0x33, }; 1763 static int jz4780_hdmi_ddc_pins[] = { 0xb9, 0xb8, }; 1764 1765 static u8 jz4780_i2s_clk_txrx_funcs[] = { 1, 0, }; 1766 1767 static const struct group_desc jz4780_groups[] = { 1768 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0), 1769 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0), 1770 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0), 1771 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0), 1772 INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data, 1), 1773 INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow, 1), 1774 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data, 1775 jz4760_uart3_data_funcs), 1776 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0), 1777 INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data, 2), 1778 INGENIC_PIN_GROUP("ssi0-dt-a-19", jz4780_ssi0_dt_a_19, 2), 1779 INGENIC_PIN_GROUP("ssi0-dt-a-21", jz4780_ssi0_dt_a_21, 2), 1780 INGENIC_PIN_GROUP("ssi0-dt-a-28", jz4780_ssi0_dt_a_28, 2), 1781 INGENIC_PIN_GROUP("ssi0-dt-b", jz4780_ssi0_dt_b, 1), 1782 INGENIC_PIN_GROUP("ssi0-dt-d", jz4780_ssi0_dt_d, 1), 1783 INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0), 1784 INGENIC_PIN_GROUP("ssi0-dr-a-20", jz4780_ssi0_dr_a_20, 2), 1785 INGENIC_PIN_GROUP("ssi0-dr-a-27", jz4780_ssi0_dr_a_27, 2), 1786 INGENIC_PIN_GROUP("ssi0-dr-b", jz4780_ssi0_dr_b, 1), 1787 INGENIC_PIN_GROUP("ssi0-dr-d", jz4780_ssi0_dr_d, 1), 1788 INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0), 1789 INGENIC_PIN_GROUP("ssi0-clk-a", jz4780_ssi0_clk_a, 2), 1790 INGENIC_PIN_GROUP("ssi0-clk-b-5", jz4780_ssi0_clk_b_5, 1), 1791 INGENIC_PIN_GROUP("ssi0-clk-b-28", jz4780_ssi0_clk_b_28, 1), 1792 INGENIC_PIN_GROUP("ssi0-clk-d", jz4780_ssi0_clk_d, 1), 1793 INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0), 1794 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4780_ssi0_gpc_b, 1), 1795 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4780_ssi0_gpc_d, 1), 1796 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0), 1797 INGENIC_PIN_GROUP("ssi0-ce0-a-23", jz4780_ssi0_ce0_a_23, 2), 1798 INGENIC_PIN_GROUP("ssi0-ce0-a-25", jz4780_ssi0_ce0_a_25, 2), 1799 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4780_ssi0_ce0_b, 1), 1800 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4780_ssi0_ce0_d, 1), 1801 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0), 1802 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4780_ssi0_ce1_b, 1), 1803 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4780_ssi0_ce1_d, 1), 1804 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0), 1805 INGENIC_PIN_GROUP("ssi1-dt-b", jz4780_ssi1_dt_b, 2), 1806 INGENIC_PIN_GROUP("ssi1-dt-d", jz4780_ssi1_dt_d, 2), 1807 INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1), 1808 INGENIC_PIN_GROUP("ssi1-dr-b", jz4780_ssi1_dr_b, 2), 1809 INGENIC_PIN_GROUP("ssi1-dr-d", jz4780_ssi1_dr_d, 2), 1810 INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1), 1811 INGENIC_PIN_GROUP("ssi1-clk-b", jz4780_ssi1_clk_b, 2), 1812 INGENIC_PIN_GROUP("ssi1-clk-d", jz4780_ssi1_clk_d, 2), 1813 INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1), 1814 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4780_ssi1_gpc_b, 2), 1815 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4780_ssi1_gpc_d, 2), 1816 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1), 1817 INGENIC_PIN_GROUP("ssi1-ce0-b", jz4780_ssi1_ce0_b, 2), 1818 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4780_ssi1_ce0_d, 2), 1819 INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1), 1820 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4780_ssi1_ce1_b, 2), 1821 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4780_ssi1_ce1_d, 2), 1822 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1), 1823 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a, 1824 jz4760_mmc0_1bit_a_funcs), 1825 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1), 1826 INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a, 1), 1827 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0), 1828 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0), 1829 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0), 1830 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0), 1831 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1), 1832 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1), 1833 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0), 1834 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0), 1835 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2), 1836 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2), 1837 INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data, 0), 1838 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0), 1839 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0), 1840 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0), 1841 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0), 1842 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0), 1843 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0), 1844 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0), 1845 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0), 1846 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0), 1847 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0), 1848 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0), 1849 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0), 1850 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0), 1851 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2), 1852 INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3, 1), 1853 INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e, 1), 1854 INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f, 1), 1855 INGENIC_PIN_GROUP("i2s-data-tx", jz4780_i2s_data_tx, 0), 1856 INGENIC_PIN_GROUP("i2s-data-rx", jz4780_i2s_data_rx, 0), 1857 INGENIC_PIN_GROUP_FUNCS("i2s-clk-txrx", jz4780_i2s_clk_txrx, 1858 jz4780_i2s_clk_txrx_funcs), 1859 INGENIC_PIN_GROUP("i2s-clk-rx", jz4780_i2s_clk_rx, 1), 1860 INGENIC_PIN_GROUP("i2s-sysclk", jz4780_i2s_sysclk, 2), 1861 INGENIC_PIN_GROUP("dmic", jz4780_dmic, 1), 1862 INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc, 0), 1863 INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit, 0), 1864 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0), 1865 INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0), 1866 INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0), 1867 INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0), 1868 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0), 1869 INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1), 1870 INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0), 1871 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0), 1872 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0), 1873 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0), 1874 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0), 1875 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0), 1876 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0), 1877 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0), 1878 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0), 1879 }; 1880 1881 static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 1882 static const char *jz4780_uart4_groups[] = { "uart4-data", }; 1883 static const char *jz4780_ssi0_groups[] = { 1884 "ssi0-dt-a-19", "ssi0-dt-a-21", "ssi0-dt-a-28", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e", 1885 "ssi0-dr-a-20", "ssi0-dr-a-27", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e", 1886 "ssi0-clk-a", "ssi0-clk-b-5", "ssi0-clk-b-28", "ssi0-clk-d", "ssi0-clk-e", 1887 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e", 1888 "ssi0-ce0-a-23", "ssi0-ce0-a-25", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e", 1889 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e", 1890 }; 1891 static const char *jz4780_ssi1_groups[] = { 1892 "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e", 1893 "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e", 1894 "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e", 1895 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e", 1896 "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e", 1897 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e", 1898 }; 1899 static const char *jz4780_mmc0_groups[] = { 1900 "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a", 1901 "mmc0-1bit-e", "mmc0-4bit-e", 1902 }; 1903 static const char *jz4780_mmc1_groups[] = { 1904 "mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e", 1905 }; 1906 static const char *jz4780_mmc2_groups[] = { 1907 "mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e", 1908 }; 1909 static const char *jz4780_nemc_groups[] = { 1910 "nemc-data", "nemc-cle-ale", "nemc-addr", 1911 "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 1912 }; 1913 static const char *jz4780_i2c3_groups[] = { "i2c3-data", }; 1914 static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", }; 1915 static const char *jz4780_i2s_groups[] = { 1916 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk", 1917 }; 1918 static const char *jz4780_dmic_groups[] = { "dmic", }; 1919 static const char *jz4780_cim_groups[] = { "cim-data", }; 1920 static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", }; 1921 1922 static const struct function_desc jz4780_functions[] = { 1923 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), }, 1924 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), }, 1925 { "uart2", jz4780_uart2_groups, ARRAY_SIZE(jz4780_uart2_groups), }, 1926 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), }, 1927 { "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), }, 1928 { "ssi0", jz4780_ssi0_groups, ARRAY_SIZE(jz4780_ssi0_groups), }, 1929 { "ssi1", jz4780_ssi1_groups, ARRAY_SIZE(jz4780_ssi1_groups), }, 1930 { "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), }, 1931 { "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), }, 1932 { "mmc2", jz4780_mmc2_groups, ARRAY_SIZE(jz4780_mmc2_groups), }, 1933 { "nemc", jz4780_nemc_groups, ARRAY_SIZE(jz4780_nemc_groups), }, 1934 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), }, 1935 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), }, 1936 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), }, 1937 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), }, 1938 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), }, 1939 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), }, 1940 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), }, 1941 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), }, 1942 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), }, 1943 { "i2c3", jz4780_i2c3_groups, ARRAY_SIZE(jz4780_i2c3_groups), }, 1944 { "i2c4", jz4780_i2c4_groups, ARRAY_SIZE(jz4780_i2c4_groups), }, 1945 { "i2s", jz4780_i2s_groups, ARRAY_SIZE(jz4780_i2s_groups), }, 1946 { "dmic", jz4780_dmic_groups, ARRAY_SIZE(jz4780_dmic_groups), }, 1947 { "cim", jz4780_cim_groups, ARRAY_SIZE(jz4780_cim_groups), }, 1948 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), }, 1949 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), }, 1950 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), }, 1951 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), }, 1952 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), }, 1953 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), }, 1954 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), }, 1955 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), }, 1956 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), }, 1957 { "hdmi-ddc", jz4780_hdmi_ddc_groups, 1958 ARRAY_SIZE(jz4780_hdmi_ddc_groups), }, 1959 }; 1960 1961 static const struct ingenic_chip_info jz4780_chip_info = { 1962 .num_chips = 6, 1963 .reg_offset = 0x100, 1964 .version = ID_JZ4780, 1965 .groups = jz4780_groups, 1966 .num_groups = ARRAY_SIZE(jz4780_groups), 1967 .functions = jz4780_functions, 1968 .num_functions = ARRAY_SIZE(jz4780_functions), 1969 .pull_ups = jz4780_pull_ups, 1970 .pull_downs = jz4780_pull_downs, 1971 }; 1972 1973 static const u32 x1000_pull_ups[4] = { 1974 0xffffffff, 0xfdffffff, 0x0dffffff, 0x0000003f, 1975 }; 1976 1977 static const u32 x1000_pull_downs[4] = { 1978 0x00000000, 0x02000000, 0x02000000, 0x00000000, 1979 }; 1980 1981 static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, }; 1982 static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, }; 1983 static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, }; 1984 static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, }; 1985 static int x1000_uart1_hwflow_pins[] = { 0x64, 0x65, }; 1986 static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, }; 1987 static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, }; 1988 static int x1000_sfc_data_pins[] = { 0x1d, 0x1c, 0x1e, 0x1f, }; 1989 static int x1000_sfc_clk_pins[] = { 0x1a, }; 1990 static int x1000_sfc_ce_pins[] = { 0x1b, }; 1991 static int x1000_ssi_dt_a_22_pins[] = { 0x16, }; 1992 static int x1000_ssi_dt_a_29_pins[] = { 0x1d, }; 1993 static int x1000_ssi_dt_d_pins[] = { 0x62, }; 1994 static int x1000_ssi_dr_a_23_pins[] = { 0x17, }; 1995 static int x1000_ssi_dr_a_28_pins[] = { 0x1c, }; 1996 static int x1000_ssi_dr_d_pins[] = { 0x63, }; 1997 static int x1000_ssi_clk_a_24_pins[] = { 0x18, }; 1998 static int x1000_ssi_clk_a_26_pins[] = { 0x1a, }; 1999 static int x1000_ssi_clk_d_pins[] = { 0x60, }; 2000 static int x1000_ssi_gpc_a_20_pins[] = { 0x14, }; 2001 static int x1000_ssi_gpc_a_31_pins[] = { 0x1f, }; 2002 static int x1000_ssi_ce0_a_25_pins[] = { 0x19, }; 2003 static int x1000_ssi_ce0_a_27_pins[] = { 0x1b, }; 2004 static int x1000_ssi_ce0_d_pins[] = { 0x61, }; 2005 static int x1000_ssi_ce1_a_21_pins[] = { 0x15, }; 2006 static int x1000_ssi_ce1_a_30_pins[] = { 0x1e, }; 2007 static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, }; 2008 static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, }; 2009 static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, }; 2010 static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, }; 2011 static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, }; 2012 static int x1000_emc_8bit_data_pins[] = { 2013 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 2014 }; 2015 static int x1000_emc_16bit_data_pins[] = { 2016 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 2017 }; 2018 static int x1000_emc_addr_pins[] = { 2019 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 2020 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 2021 }; 2022 static int x1000_emc_rd_we_pins[] = { 0x30, 0x31, }; 2023 static int x1000_emc_wait_pins[] = { 0x34, }; 2024 static int x1000_emc_cs1_pins[] = { 0x32, }; 2025 static int x1000_emc_cs2_pins[] = { 0x33, }; 2026 static int x1000_i2c0_pins[] = { 0x38, 0x37, }; 2027 static int x1000_i2c1_a_pins[] = { 0x01, 0x00, }; 2028 static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, }; 2029 static int x1000_i2c2_pins[] = { 0x61, 0x60, }; 2030 static int x1000_i2s_data_tx_pins[] = { 0x24, }; 2031 static int x1000_i2s_data_rx_pins[] = { 0x23, }; 2032 static int x1000_i2s_clk_txrx_pins[] = { 0x21, 0x22, }; 2033 static int x1000_i2s_sysclk_pins[] = { 0x20, }; 2034 static int x1000_dmic_if0_pins[] = { 0x35, 0x36, }; 2035 static int x1000_dmic_if1_pins[] = { 0x25, }; 2036 static int x1000_cim_pins[] = { 2037 0x08, 0x09, 0x0a, 0x0b, 2038 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 2039 }; 2040 static int x1000_lcd_8bit_pins[] = { 2041 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 2042 0x30, 0x31, 0x32, 0x33, 0x34, 2043 }; 2044 static int x1000_lcd_16bit_pins[] = { 2045 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 2046 }; 2047 static int x1000_pwm_pwm0_pins[] = { 0x59, }; 2048 static int x1000_pwm_pwm1_pins[] = { 0x5a, }; 2049 static int x1000_pwm_pwm2_pins[] = { 0x5b, }; 2050 static int x1000_pwm_pwm3_pins[] = { 0x26, }; 2051 static int x1000_pwm_pwm4_pins[] = { 0x58, }; 2052 static int x1000_mac_pins[] = { 2053 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x26, 2054 }; 2055 2056 static const struct group_desc x1000_groups[] = { 2057 INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data, 0), 2058 INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow, 0), 2059 INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a, 2), 2060 INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d, 1), 2061 INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow, 1), 2062 INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a, 2), 2063 INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d, 0), 2064 INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1), 2065 INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1), 2066 INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1), 2067 INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22, 2), 2068 INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29, 2), 2069 INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d, 0), 2070 INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23, 2), 2071 INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28, 2), 2072 INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d, 0), 2073 INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24, 2), 2074 INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26, 2), 2075 INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d, 0), 2076 INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20, 2), 2077 INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31, 2), 2078 INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25, 2), 2079 INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27, 2), 2080 INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d, 0), 2081 INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21, 2), 2082 INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30, 2), 2083 INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit, 1), 2084 INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit, 1), 2085 INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit, 1), 2086 INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit, 0), 2087 INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit, 0), 2088 INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data, 0), 2089 INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data, 0), 2090 INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr, 0), 2091 INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we, 0), 2092 INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait, 0), 2093 INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1, 0), 2094 INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2, 0), 2095 INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0, 0), 2096 INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a, 2), 2097 INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c, 0), 2098 INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2, 1), 2099 INGENIC_PIN_GROUP("i2s-data-tx", x1000_i2s_data_tx, 1), 2100 INGENIC_PIN_GROUP("i2s-data-rx", x1000_i2s_data_rx, 1), 2101 INGENIC_PIN_GROUP("i2s-clk-txrx", x1000_i2s_clk_txrx, 1), 2102 INGENIC_PIN_GROUP("i2s-sysclk", x1000_i2s_sysclk, 1), 2103 INGENIC_PIN_GROUP("dmic-if0", x1000_dmic_if0, 0), 2104 INGENIC_PIN_GROUP("dmic-if1", x1000_dmic_if1, 1), 2105 INGENIC_PIN_GROUP("cim-data", x1000_cim, 2), 2106 INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit, 1), 2107 INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit, 1), 2108 INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0, 0), 2109 INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1, 1), 2110 INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2, 1), 2111 INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3, 2), 2112 INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4, 0), 2113 INGENIC_PIN_GROUP("mac", x1000_mac, 1), 2114 }; 2115 2116 static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 2117 static const char *x1000_uart1_groups[] = { 2118 "uart1-data-a", "uart1-data-d", "uart1-hwflow", 2119 }; 2120 static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; 2121 static const char *x1000_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", }; 2122 static const char *x1000_ssi_groups[] = { 2123 "ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d", 2124 "ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d", 2125 "ssi-clk-a-24", "ssi-clk-a-26", "ssi-clk-d", 2126 "ssi-gpc-a-20", "ssi-gpc-a-31", 2127 "ssi-ce0-a-25", "ssi-ce0-a-27", "ssi-ce0-d", 2128 "ssi-ce1-a-21", "ssi-ce1-a-30", 2129 }; 2130 static const char *x1000_mmc0_groups[] = { 2131 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", 2132 }; 2133 static const char *x1000_mmc1_groups[] = { 2134 "mmc1-1bit", "mmc1-4bit", 2135 }; 2136 static const char *x1000_emc_groups[] = { 2137 "emc-8bit-data", "emc-16bit-data", 2138 "emc-addr", "emc-rd-we", "emc-wait", 2139 }; 2140 static const char *x1000_cs1_groups[] = { "emc-cs1", }; 2141 static const char *x1000_cs2_groups[] = { "emc-cs2", }; 2142 static const char *x1000_i2c0_groups[] = { "i2c0-data", }; 2143 static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; 2144 static const char *x1000_i2c2_groups[] = { "i2c2-data", }; 2145 static const char *x1000_i2s_groups[] = { 2146 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk", 2147 }; 2148 static const char *x1000_dmic_groups[] = { "dmic-if0", "dmic-if1", }; 2149 static const char *x1000_cim_groups[] = { "cim-data", }; 2150 static const char *x1000_lcd_groups[] = { "lcd-8bit", "lcd-16bit", }; 2151 static const char *x1000_pwm0_groups[] = { "pwm0", }; 2152 static const char *x1000_pwm1_groups[] = { "pwm1", }; 2153 static const char *x1000_pwm2_groups[] = { "pwm2", }; 2154 static const char *x1000_pwm3_groups[] = { "pwm3", }; 2155 static const char *x1000_pwm4_groups[] = { "pwm4", }; 2156 static const char *x1000_mac_groups[] = { "mac", }; 2157 2158 static const struct function_desc x1000_functions[] = { 2159 { "uart0", x1000_uart0_groups, ARRAY_SIZE(x1000_uart0_groups), }, 2160 { "uart1", x1000_uart1_groups, ARRAY_SIZE(x1000_uart1_groups), }, 2161 { "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), }, 2162 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), }, 2163 { "ssi", x1000_ssi_groups, ARRAY_SIZE(x1000_ssi_groups), }, 2164 { "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), }, 2165 { "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), }, 2166 { "emc", x1000_emc_groups, ARRAY_SIZE(x1000_emc_groups), }, 2167 { "emc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), }, 2168 { "emc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), }, 2169 { "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), }, 2170 { "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), }, 2171 { "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), }, 2172 { "i2s", x1000_i2s_groups, ARRAY_SIZE(x1000_i2s_groups), }, 2173 { "dmic", x1000_dmic_groups, ARRAY_SIZE(x1000_dmic_groups), }, 2174 { "cim", x1000_cim_groups, ARRAY_SIZE(x1000_cim_groups), }, 2175 { "lcd", x1000_lcd_groups, ARRAY_SIZE(x1000_lcd_groups), }, 2176 { "pwm0", x1000_pwm0_groups, ARRAY_SIZE(x1000_pwm0_groups), }, 2177 { "pwm1", x1000_pwm1_groups, ARRAY_SIZE(x1000_pwm1_groups), }, 2178 { "pwm2", x1000_pwm2_groups, ARRAY_SIZE(x1000_pwm2_groups), }, 2179 { "pwm3", x1000_pwm3_groups, ARRAY_SIZE(x1000_pwm3_groups), }, 2180 { "pwm4", x1000_pwm4_groups, ARRAY_SIZE(x1000_pwm4_groups), }, 2181 { "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), }, 2182 }; 2183 2184 static const struct regmap_range x1000_access_ranges[] = { 2185 regmap_reg_range(0x000, 0x400 - 4), 2186 regmap_reg_range(0x700, 0x800 - 4), 2187 }; 2188 2189 /* shared with X1500 */ 2190 static const struct regmap_access_table x1000_access_table = { 2191 .yes_ranges = x1000_access_ranges, 2192 .n_yes_ranges = ARRAY_SIZE(x1000_access_ranges), 2193 }; 2194 2195 static const struct ingenic_chip_info x1000_chip_info = { 2196 .num_chips = 4, 2197 .reg_offset = 0x100, 2198 .version = ID_X1000, 2199 .groups = x1000_groups, 2200 .num_groups = ARRAY_SIZE(x1000_groups), 2201 .functions = x1000_functions, 2202 .num_functions = ARRAY_SIZE(x1000_functions), 2203 .pull_ups = x1000_pull_ups, 2204 .pull_downs = x1000_pull_downs, 2205 .access_table = &x1000_access_table, 2206 }; 2207 2208 static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, }; 2209 static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, }; 2210 static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, }; 2211 static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, }; 2212 static int x1500_uart1_hwflow_pins[] = { 0x64, 0x65, }; 2213 static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, }; 2214 static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, }; 2215 static int x1500_mmc_1bit_pins[] = { 0x18, 0x19, 0x17, }; 2216 static int x1500_mmc_4bit_pins[] = { 0x16, 0x15, 0x14, }; 2217 static int x1500_i2c0_pins[] = { 0x38, 0x37, }; 2218 static int x1500_i2c1_a_pins[] = { 0x01, 0x00, }; 2219 static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, }; 2220 static int x1500_i2c2_pins[] = { 0x61, 0x60, }; 2221 static int x1500_i2s_data_tx_pins[] = { 0x24, }; 2222 static int x1500_i2s_data_rx_pins[] = { 0x23, }; 2223 static int x1500_i2s_clk_txrx_pins[] = { 0x21, 0x22, }; 2224 static int x1500_i2s_sysclk_pins[] = { 0x20, }; 2225 static int x1500_dmic_if0_pins[] = { 0x35, 0x36, }; 2226 static int x1500_dmic_if1_pins[] = { 0x25, }; 2227 static int x1500_cim_pins[] = { 2228 0x08, 0x09, 0x0a, 0x0b, 2229 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 2230 }; 2231 static int x1500_pwm_pwm0_pins[] = { 0x59, }; 2232 static int x1500_pwm_pwm1_pins[] = { 0x5a, }; 2233 static int x1500_pwm_pwm2_pins[] = { 0x5b, }; 2234 static int x1500_pwm_pwm3_pins[] = { 0x26, }; 2235 static int x1500_pwm_pwm4_pins[] = { 0x58, }; 2236 2237 static const struct group_desc x1500_groups[] = { 2238 INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data, 0), 2239 INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow, 0), 2240 INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a, 2), 2241 INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d, 1), 2242 INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow, 1), 2243 INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a, 2), 2244 INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d, 0), 2245 INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1), 2246 INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1), 2247 INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1), 2248 INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit, 1), 2249 INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit, 1), 2250 INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0, 0), 2251 INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a, 2), 2252 INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c, 0), 2253 INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2, 1), 2254 INGENIC_PIN_GROUP("i2s-data-tx", x1500_i2s_data_tx, 1), 2255 INGENIC_PIN_GROUP("i2s-data-rx", x1500_i2s_data_rx, 1), 2256 INGENIC_PIN_GROUP("i2s-clk-txrx", x1500_i2s_clk_txrx, 1), 2257 INGENIC_PIN_GROUP("i2s-sysclk", x1500_i2s_sysclk, 1), 2258 INGENIC_PIN_GROUP("dmic-if0", x1500_dmic_if0, 0), 2259 INGENIC_PIN_GROUP("dmic-if1", x1500_dmic_if1, 1), 2260 INGENIC_PIN_GROUP("cim-data", x1500_cim, 2), 2261 INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0, 0), 2262 INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1, 1), 2263 INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2, 1), 2264 INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3, 2), 2265 INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4, 0), 2266 }; 2267 2268 static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 2269 static const char *x1500_uart1_groups[] = { 2270 "uart1-data-a", "uart1-data-d", "uart1-hwflow", 2271 }; 2272 static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; 2273 static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; 2274 static const char *x1500_i2c0_groups[] = { "i2c0-data", }; 2275 static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; 2276 static const char *x1500_i2c2_groups[] = { "i2c2-data", }; 2277 static const char *x1500_i2s_groups[] = { 2278 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk", 2279 }; 2280 static const char *x1500_dmic_groups[] = { "dmic-if0", "dmic-if1", }; 2281 static const char *x1500_cim_groups[] = { "cim-data", }; 2282 static const char *x1500_pwm0_groups[] = { "pwm0", }; 2283 static const char *x1500_pwm1_groups[] = { "pwm1", }; 2284 static const char *x1500_pwm2_groups[] = { "pwm2", }; 2285 static const char *x1500_pwm3_groups[] = { "pwm3", }; 2286 static const char *x1500_pwm4_groups[] = { "pwm4", }; 2287 2288 static const struct function_desc x1500_functions[] = { 2289 { "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), }, 2290 { "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), }, 2291 { "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), }, 2292 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), }, 2293 { "mmc", x1500_mmc_groups, ARRAY_SIZE(x1500_mmc_groups), }, 2294 { "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), }, 2295 { "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), }, 2296 { "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), }, 2297 { "i2s", x1500_i2s_groups, ARRAY_SIZE(x1500_i2s_groups), }, 2298 { "dmic", x1500_dmic_groups, ARRAY_SIZE(x1500_dmic_groups), }, 2299 { "cim", x1500_cim_groups, ARRAY_SIZE(x1500_cim_groups), }, 2300 { "pwm0", x1500_pwm0_groups, ARRAY_SIZE(x1500_pwm0_groups), }, 2301 { "pwm1", x1500_pwm1_groups, ARRAY_SIZE(x1500_pwm1_groups), }, 2302 { "pwm2", x1500_pwm2_groups, ARRAY_SIZE(x1500_pwm2_groups), }, 2303 { "pwm3", x1500_pwm3_groups, ARRAY_SIZE(x1500_pwm3_groups), }, 2304 { "pwm4", x1500_pwm4_groups, ARRAY_SIZE(x1500_pwm4_groups), }, 2305 }; 2306 2307 static const struct ingenic_chip_info x1500_chip_info = { 2308 .num_chips = 4, 2309 .reg_offset = 0x100, 2310 .version = ID_X1500, 2311 .groups = x1500_groups, 2312 .num_groups = ARRAY_SIZE(x1500_groups), 2313 .functions = x1500_functions, 2314 .num_functions = ARRAY_SIZE(x1500_functions), 2315 .pull_ups = x1000_pull_ups, 2316 .pull_downs = x1000_pull_downs, 2317 .access_table = &x1000_access_table, 2318 }; 2319 2320 static const u32 x1830_pull_ups[4] = { 2321 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc, 2322 }; 2323 2324 static const u32 x1830_pull_downs[4] = { 2325 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc, 2326 }; 2327 2328 static int x1830_uart0_data_pins[] = { 0x33, 0x36, }; 2329 static int x1830_uart0_hwflow_pins[] = { 0x34, 0x35, }; 2330 static int x1830_uart1_data_pins[] = { 0x38, 0x37, }; 2331 static int x1830_sfc_data_pins[] = { 0x17, 0x18, 0x1a, 0x19, }; 2332 static int x1830_sfc_clk_pins[] = { 0x1b, }; 2333 static int x1830_sfc_ce_pins[] = { 0x1c, }; 2334 static int x1830_ssi0_dt_pins[] = { 0x4c, }; 2335 static int x1830_ssi0_dr_pins[] = { 0x4b, }; 2336 static int x1830_ssi0_clk_pins[] = { 0x4f, }; 2337 static int x1830_ssi0_gpc_pins[] = { 0x4d, }; 2338 static int x1830_ssi0_ce0_pins[] = { 0x50, }; 2339 static int x1830_ssi0_ce1_pins[] = { 0x4e, }; 2340 static int x1830_ssi1_dt_c_pins[] = { 0x53, }; 2341 static int x1830_ssi1_dt_d_pins[] = { 0x62, }; 2342 static int x1830_ssi1_dr_c_pins[] = { 0x54, }; 2343 static int x1830_ssi1_dr_d_pins[] = { 0x63, }; 2344 static int x1830_ssi1_clk_c_pins[] = { 0x57, }; 2345 static int x1830_ssi1_clk_d_pins[] = { 0x66, }; 2346 static int x1830_ssi1_gpc_c_pins[] = { 0x55, }; 2347 static int x1830_ssi1_gpc_d_pins[] = { 0x64, }; 2348 static int x1830_ssi1_ce0_c_pins[] = { 0x58, }; 2349 static int x1830_ssi1_ce0_d_pins[] = { 0x67, }; 2350 static int x1830_ssi1_ce1_c_pins[] = { 0x56, }; 2351 static int x1830_ssi1_ce1_d_pins[] = { 0x65, }; 2352 static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, }; 2353 static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, }; 2354 static int x1830_mmc1_1bit_pins[] = { 0x42, 0x43, 0x44, }; 2355 static int x1830_mmc1_4bit_pins[] = { 0x45, 0x46, 0x47, }; 2356 static int x1830_i2c0_pins[] = { 0x0c, 0x0d, }; 2357 static int x1830_i2c1_pins[] = { 0x39, 0x3a, }; 2358 static int x1830_i2c2_pins[] = { 0x5b, 0x5c, }; 2359 static int x1830_i2s_data_tx_pins[] = { 0x53, }; 2360 static int x1830_i2s_data_rx_pins[] = { 0x54, }; 2361 static int x1830_i2s_clk_txrx_pins[] = { 0x58, 0x52, }; 2362 static int x1830_i2s_clk_rx_pins[] = { 0x56, 0x55, }; 2363 static int x1830_i2s_sysclk_pins[] = { 0x57, }; 2364 static int x1830_dmic_if0_pins[] = { 0x48, 0x59, }; 2365 static int x1830_dmic_if1_pins[] = { 0x5a, }; 2366 static int x1830_lcd_tft_8bit_pins[] = { 2367 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 2368 0x68, 0x73, 0x72, 0x69, 2369 }; 2370 static int x1830_lcd_tft_24bit_pins[] = { 2371 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71, 2372 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, 2373 }; 2374 static int x1830_lcd_slcd_8bit_pins[] = { 2375 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x6c, 0x6d, 2376 0x69, 0x72, 0x73, 0x7b, 0x7a, 2377 }; 2378 static int x1830_lcd_slcd_16bit_pins[] = { 2379 0x6e, 0x6f, 0x70, 0x71, 0x76, 0x77, 0x78, 0x79, 2380 }; 2381 static int x1830_pwm_pwm0_b_pins[] = { 0x31, }; 2382 static int x1830_pwm_pwm0_c_pins[] = { 0x4b, }; 2383 static int x1830_pwm_pwm1_b_pins[] = { 0x32, }; 2384 static int x1830_pwm_pwm1_c_pins[] = { 0x4c, }; 2385 static int x1830_pwm_pwm2_c_8_pins[] = { 0x48, }; 2386 static int x1830_pwm_pwm2_c_13_pins[] = { 0x4d, }; 2387 static int x1830_pwm_pwm3_c_9_pins[] = { 0x49, }; 2388 static int x1830_pwm_pwm3_c_14_pins[] = { 0x4e, }; 2389 static int x1830_pwm_pwm4_c_15_pins[] = { 0x4f, }; 2390 static int x1830_pwm_pwm4_c_25_pins[] = { 0x59, }; 2391 static int x1830_pwm_pwm5_c_16_pins[] = { 0x50, }; 2392 static int x1830_pwm_pwm5_c_26_pins[] = { 0x5a, }; 2393 static int x1830_pwm_pwm6_c_17_pins[] = { 0x51, }; 2394 static int x1830_pwm_pwm6_c_27_pins[] = { 0x5b, }; 2395 static int x1830_pwm_pwm7_c_18_pins[] = { 0x52, }; 2396 static int x1830_pwm_pwm7_c_28_pins[] = { 0x5c, }; 2397 static int x1830_mac_pins[] = { 2398 0x29, 0x30, 0x2f, 0x28, 0x2e, 0x2d, 0x2a, 0x2b, 0x26, 0x27, 2399 }; 2400 2401 static const struct group_desc x1830_groups[] = { 2402 INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data, 0), 2403 INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow, 0), 2404 INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data, 0), 2405 INGENIC_PIN_GROUP("sfc-data", x1830_sfc_data, 1), 2406 INGENIC_PIN_GROUP("sfc-clk", x1830_sfc_clk, 1), 2407 INGENIC_PIN_GROUP("sfc-ce", x1830_sfc_ce, 1), 2408 INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt, 0), 2409 INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr, 0), 2410 INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk, 0), 2411 INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc, 0), 2412 INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0, 0), 2413 INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1, 0), 2414 INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c, 1), 2415 INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c, 1), 2416 INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c, 1), 2417 INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c, 1), 2418 INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c, 1), 2419 INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c, 1), 2420 INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d, 2), 2421 INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d, 2), 2422 INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d, 2), 2423 INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d, 2), 2424 INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d, 2), 2425 INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d, 2), 2426 INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit, 0), 2427 INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit, 0), 2428 INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit, 0), 2429 INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit, 0), 2430 INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0, 1), 2431 INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1, 0), 2432 INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2, 1), 2433 INGENIC_PIN_GROUP("i2s-data-tx", x1830_i2s_data_tx, 0), 2434 INGENIC_PIN_GROUP("i2s-data-rx", x1830_i2s_data_rx, 0), 2435 INGENIC_PIN_GROUP("i2s-clk-txrx", x1830_i2s_clk_txrx, 0), 2436 INGENIC_PIN_GROUP("i2s-clk-rx", x1830_i2s_clk_rx, 0), 2437 INGENIC_PIN_GROUP("i2s-sysclk", x1830_i2s_sysclk, 0), 2438 INGENIC_PIN_GROUP("dmic-if0", x1830_dmic_if0, 2), 2439 INGENIC_PIN_GROUP("dmic-if1", x1830_dmic_if1, 2), 2440 INGENIC_PIN_GROUP("lcd-tft-8bit", x1830_lcd_tft_8bit, 0), 2441 INGENIC_PIN_GROUP("lcd-tft-24bit", x1830_lcd_tft_24bit, 0), 2442 INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit, 1), 2443 INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit, 1), 2444 INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b, 0), 2445 INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c, 1), 2446 INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b, 0), 2447 INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c, 1), 2448 INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8, 0), 2449 INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13, 1), 2450 INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9, 0), 2451 INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14, 1), 2452 INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15, 1), 2453 INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25, 0), 2454 INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16, 1), 2455 INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26, 0), 2456 INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17, 1), 2457 INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27, 0), 2458 INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18, 1), 2459 INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28, 0), 2460 INGENIC_PIN_GROUP("mac", x1830_mac, 0), 2461 }; 2462 2463 static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 2464 static const char *x1830_uart1_groups[] = { "uart1-data", }; 2465 static const char *x1830_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", }; 2466 static const char *x1830_ssi0_groups[] = { 2467 "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1", 2468 }; 2469 static const char *x1830_ssi1_groups[] = { 2470 "ssi1-dt-c", "ssi1-dt-d", 2471 "ssi1-dr-c", "ssi1-dr-d", 2472 "ssi1-clk-c", "ssi1-clk-d", 2473 "ssi1-gpc-c", "ssi1-gpc-d", 2474 "ssi1-ce0-c", "ssi1-ce0-d", 2475 "ssi1-ce1-c", "ssi1-ce1-d", 2476 }; 2477 static const char *x1830_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 2478 static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 2479 static const char *x1830_i2c0_groups[] = { "i2c0-data", }; 2480 static const char *x1830_i2c1_groups[] = { "i2c1-data", }; 2481 static const char *x1830_i2c2_groups[] = { "i2c2-data", }; 2482 static const char *x1830_i2s_groups[] = { 2483 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk", 2484 }; 2485 static const char *x1830_dmic_groups[] = { "dmic-if0", "dmic-if1", }; 2486 static const char *x1830_lcd_groups[] = { 2487 "lcd-tft-8bit", "lcd-tft-24bit", "lcd-slcd-8bit", "lcd-slcd-16bit", 2488 }; 2489 static const char *x1830_pwm0_groups[] = { "pwm0-b", "pwm0-c", }; 2490 static const char *x1830_pwm1_groups[] = { "pwm1-b", "pwm1-c", }; 2491 static const char *x1830_pwm2_groups[] = { "pwm2-c-8", "pwm2-c-13", }; 2492 static const char *x1830_pwm3_groups[] = { "pwm3-c-9", "pwm3-c-14", }; 2493 static const char *x1830_pwm4_groups[] = { "pwm4-c-15", "pwm4-c-25", }; 2494 static const char *x1830_pwm5_groups[] = { "pwm5-c-16", "pwm5-c-26", }; 2495 static const char *x1830_pwm6_groups[] = { "pwm6-c-17", "pwm6-c-27", }; 2496 static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", }; 2497 static const char *x1830_mac_groups[] = { "mac", }; 2498 2499 static const struct function_desc x1830_functions[] = { 2500 { "uart0", x1830_uart0_groups, ARRAY_SIZE(x1830_uart0_groups), }, 2501 { "uart1", x1830_uart1_groups, ARRAY_SIZE(x1830_uart1_groups), }, 2502 { "sfc", x1830_sfc_groups, ARRAY_SIZE(x1830_sfc_groups), }, 2503 { "ssi0", x1830_ssi0_groups, ARRAY_SIZE(x1830_ssi0_groups), }, 2504 { "ssi1", x1830_ssi1_groups, ARRAY_SIZE(x1830_ssi1_groups), }, 2505 { "mmc0", x1830_mmc0_groups, ARRAY_SIZE(x1830_mmc0_groups), }, 2506 { "mmc1", x1830_mmc1_groups, ARRAY_SIZE(x1830_mmc1_groups), }, 2507 { "i2c0", x1830_i2c0_groups, ARRAY_SIZE(x1830_i2c0_groups), }, 2508 { "i2c1", x1830_i2c1_groups, ARRAY_SIZE(x1830_i2c1_groups), }, 2509 { "i2c2", x1830_i2c2_groups, ARRAY_SIZE(x1830_i2c2_groups), }, 2510 { "i2s", x1830_i2s_groups, ARRAY_SIZE(x1830_i2s_groups), }, 2511 { "dmic", x1830_dmic_groups, ARRAY_SIZE(x1830_dmic_groups), }, 2512 { "lcd", x1830_lcd_groups, ARRAY_SIZE(x1830_lcd_groups), }, 2513 { "pwm0", x1830_pwm0_groups, ARRAY_SIZE(x1830_pwm0_groups), }, 2514 { "pwm1", x1830_pwm1_groups, ARRAY_SIZE(x1830_pwm1_groups), }, 2515 { "pwm2", x1830_pwm2_groups, ARRAY_SIZE(x1830_pwm2_groups), }, 2516 { "pwm3", x1830_pwm3_groups, ARRAY_SIZE(x1830_pwm3_groups), }, 2517 { "pwm4", x1830_pwm4_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 2518 { "pwm5", x1830_pwm5_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 2519 { "pwm6", x1830_pwm6_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 2520 { "pwm7", x1830_pwm7_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 2521 { "mac", x1830_mac_groups, ARRAY_SIZE(x1830_mac_groups), }, 2522 }; 2523 2524 static const struct regmap_range x1830_access_ranges[] = { 2525 regmap_reg_range(0x0000, 0x4000 - 4), 2526 regmap_reg_range(0x7000, 0x8000 - 4), 2527 }; 2528 2529 static const struct regmap_access_table x1830_access_table = { 2530 .yes_ranges = x1830_access_ranges, 2531 .n_yes_ranges = ARRAY_SIZE(x1830_access_ranges), 2532 }; 2533 2534 static const struct ingenic_chip_info x1830_chip_info = { 2535 .num_chips = 4, 2536 .reg_offset = 0x1000, 2537 .version = ID_X1830, 2538 .groups = x1830_groups, 2539 .num_groups = ARRAY_SIZE(x1830_groups), 2540 .functions = x1830_functions, 2541 .num_functions = ARRAY_SIZE(x1830_functions), 2542 .pull_ups = x1830_pull_ups, 2543 .pull_downs = x1830_pull_downs, 2544 .access_table = &x1830_access_table, 2545 }; 2546 2547 static const u32 x2000_pull_ups[5] = { 2548 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0xc7fe3f3f, 0x8fff003f, 2549 }; 2550 2551 static const u32 x2000_pull_downs[5] = { 2552 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0x00000000, 0x8fff003f, 2553 }; 2554 2555 static int x2000_uart0_data_pins[] = { 0x77, 0x78, }; 2556 static int x2000_uart0_hwflow_pins[] = { 0x79, 0x7a, }; 2557 static int x2000_uart1_data_pins[] = { 0x57, 0x58, }; 2558 static int x2000_uart1_hwflow_pins[] = { 0x55, 0x56, }; 2559 static int x2000_uart2_data_pins[] = { 0x7e, 0x7f, }; 2560 static int x2000_uart3_data_c_pins[] = { 0x59, 0x5a, }; 2561 static int x2000_uart3_data_d_pins[] = { 0x62, 0x63, }; 2562 static int x2000_uart3_hwflow_c_pins[] = { 0x5b, 0x5c, }; 2563 static int x2000_uart3_hwflow_d_pins[] = { 0x60, 0x61, }; 2564 static int x2000_uart4_data_a_pins[] = { 0x02, 0x03, }; 2565 static int x2000_uart4_data_c_pins[] = { 0x4b, 0x4c, }; 2566 static int x2000_uart4_hwflow_a_pins[] = { 0x00, 0x01, }; 2567 static int x2000_uart4_hwflow_c_pins[] = { 0x49, 0x4a, }; 2568 static int x2000_uart5_data_a_pins[] = { 0x04, 0x05, }; 2569 static int x2000_uart5_data_c_pins[] = { 0x45, 0x46, }; 2570 static int x2000_uart6_data_a_pins[] = { 0x06, 0x07, }; 2571 static int x2000_uart6_data_c_pins[] = { 0x47, 0x48, }; 2572 static int x2000_uart7_data_a_pins[] = { 0x08, 0x09, }; 2573 static int x2000_uart7_data_c_pins[] = { 0x41, 0x42, }; 2574 static int x2000_uart8_data_pins[] = { 0x3c, 0x3d, }; 2575 static int x2000_uart9_data_pins[] = { 0x3e, 0x3f, }; 2576 static int x2000_sfc_data_if0_d_pins[] = { 0x73, 0x74, 0x75, 0x76, }; 2577 static int x2000_sfc_data_if0_e_pins[] = { 0x92, 0x93, 0x94, 0x95, }; 2578 static int x2000_sfc_data_if1_pins[] = { 0x77, 0x78, 0x79, 0x7a, }; 2579 static int x2000_sfc_clk_d_pins[] = { 0x71, }; 2580 static int x2000_sfc_clk_e_pins[] = { 0x90, }; 2581 static int x2000_sfc_ce_d_pins[] = { 0x72, }; 2582 static int x2000_sfc_ce_e_pins[] = { 0x91, }; 2583 static int x2000_ssi0_dt_b_pins[] = { 0x3e, }; 2584 static int x2000_ssi0_dt_d_pins[] = { 0x69, }; 2585 static int x2000_ssi0_dr_b_pins[] = { 0x3d, }; 2586 static int x2000_ssi0_dr_d_pins[] = { 0x6a, }; 2587 static int x2000_ssi0_clk_b_pins[] = { 0x3f, }; 2588 static int x2000_ssi0_clk_d_pins[] = { 0x68, }; 2589 static int x2000_ssi0_ce_b_pins[] = { 0x3c, }; 2590 static int x2000_ssi0_ce_d_pins[] = { 0x6d, }; 2591 static int x2000_ssi1_dt_c_pins[] = { 0x4b, }; 2592 static int x2000_ssi1_dt_d_pins[] = { 0x72, }; 2593 static int x2000_ssi1_dt_e_pins[] = { 0x91, }; 2594 static int x2000_ssi1_dr_c_pins[] = { 0x4a, }; 2595 static int x2000_ssi1_dr_d_pins[] = { 0x73, }; 2596 static int x2000_ssi1_dr_e_pins[] = { 0x92, }; 2597 static int x2000_ssi1_clk_c_pins[] = { 0x4c, }; 2598 static int x2000_ssi1_clk_d_pins[] = { 0x71, }; 2599 static int x2000_ssi1_clk_e_pins[] = { 0x90, }; 2600 static int x2000_ssi1_ce_c_pins[] = { 0x49, }; 2601 static int x2000_ssi1_ce_d_pins[] = { 0x76, }; 2602 static int x2000_ssi1_ce_e_pins[] = { 0x95, }; 2603 static int x2000_mmc0_1bit_pins[] = { 0x71, 0x72, 0x73, }; 2604 static int x2000_mmc0_4bit_pins[] = { 0x74, 0x75, 0x75, }; 2605 static int x2000_mmc0_8bit_pins[] = { 0x77, 0x78, 0x79, 0x7a, }; 2606 static int x2000_mmc1_1bit_pins[] = { 0x68, 0x69, 0x6a, }; 2607 static int x2000_mmc1_4bit_pins[] = { 0x6b, 0x6c, 0x6d, }; 2608 static int x2000_mmc2_1bit_pins[] = { 0x80, 0x81, 0x82, }; 2609 static int x2000_mmc2_4bit_pins[] = { 0x83, 0x84, 0x85, }; 2610 static int x2000_emc_8bit_data_pins[] = { 2611 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 2612 }; 2613 static int x2000_emc_16bit_data_pins[] = { 2614 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, 2615 }; 2616 static int x2000_emc_addr_pins[] = { 2617 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 2618 0x28, 0x29, 0x2a, 0x2b, 0x2c, 2619 }; 2620 static int x2000_emc_rd_we_pins[] = { 0x2d, 0x2e, }; 2621 static int x2000_emc_wait_pins[] = { 0x2f, }; 2622 static int x2000_emc_cs1_pins[] = { 0x57, }; 2623 static int x2000_emc_cs2_pins[] = { 0x58, }; 2624 static int x2000_i2c0_pins[] = { 0x4e, 0x4d, }; 2625 static int x2000_i2c1_c_pins[] = { 0x58, 0x57, }; 2626 static int x2000_i2c1_d_pins[] = { 0x6c, 0x6b, }; 2627 static int x2000_i2c2_b_pins[] = { 0x37, 0x36, }; 2628 static int x2000_i2c2_d_pins[] = { 0x75, 0x74, }; 2629 static int x2000_i2c2_e_pins[] = { 0x94, 0x93, }; 2630 static int x2000_i2c3_a_pins[] = { 0x11, 0x10, }; 2631 static int x2000_i2c3_d_pins[] = { 0x7f, 0x7e, }; 2632 static int x2000_i2c4_c_pins[] = { 0x5a, 0x59, }; 2633 static int x2000_i2c4_d_pins[] = { 0x61, 0x60, }; 2634 static int x2000_i2c5_c_pins[] = { 0x5c, 0x5b, }; 2635 static int x2000_i2c5_d_pins[] = { 0x65, 0x64, }; 2636 static int x2000_i2s1_data_tx_pins[] = { 0x47, }; 2637 static int x2000_i2s1_data_rx_pins[] = { 0x44, }; 2638 static int x2000_i2s1_clk_tx_pins[] = { 0x45, 0x46, }; 2639 static int x2000_i2s1_clk_rx_pins[] = { 0x42, 0x43, }; 2640 static int x2000_i2s1_sysclk_tx_pins[] = { 0x48, }; 2641 static int x2000_i2s1_sysclk_rx_pins[] = { 0x41, }; 2642 static int x2000_i2s2_data_rx0_pins[] = { 0x0a, }; 2643 static int x2000_i2s2_data_rx1_pins[] = { 0x0b, }; 2644 static int x2000_i2s2_data_rx2_pins[] = { 0x0c, }; 2645 static int x2000_i2s2_data_rx3_pins[] = { 0x0d, }; 2646 static int x2000_i2s2_clk_rx_pins[] = { 0x11, 0x09, }; 2647 static int x2000_i2s2_sysclk_rx_pins[] = { 0x07, }; 2648 static int x2000_i2s3_data_tx0_pins[] = { 0x03, }; 2649 static int x2000_i2s3_data_tx1_pins[] = { 0x04, }; 2650 static int x2000_i2s3_data_tx2_pins[] = { 0x05, }; 2651 static int x2000_i2s3_data_tx3_pins[] = { 0x06, }; 2652 static int x2000_i2s3_clk_tx_pins[] = { 0x10, 0x02, }; 2653 static int x2000_i2s3_sysclk_tx_pins[] = { 0x00, }; 2654 static int x2000_dmic_if0_pins[] = { 0x54, 0x55, }; 2655 static int x2000_dmic_if1_pins[] = { 0x56, }; 2656 static int x2000_dmic_if2_pins[] = { 0x57, }; 2657 static int x2000_dmic_if3_pins[] = { 0x58, }; 2658 static int x2000_cim_8bit_pins[] = { 2659 0x0e, 0x0c, 0x0d, 0x4f, 2660 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 2661 }; 2662 static int x2000_cim_12bit_pins[] = { 0x08, 0x09, 0x0a, 0x0b, }; 2663 static int x2000_lcd_tft_8bit_pins[] = { 2664 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 2665 0x38, 0x3a, 0x39, 0x3b, 2666 }; 2667 static int x2000_lcd_tft_16bit_pins[] = { 2668 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 2669 }; 2670 static int x2000_lcd_tft_18bit_pins[] = { 2671 0x30, 0x31, 2672 }; 2673 static int x2000_lcd_tft_24bit_pins[] = { 2674 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 2675 }; 2676 static int x2000_lcd_slcd_8bit_pins[] = { 2677 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 2678 0x3a, 0x38, 0x3b, 0x30, 0x39, 2679 }; 2680 static int x2000_pwm_pwm0_c_pins[] = { 0x40, }; 2681 static int x2000_pwm_pwm0_d_pins[] = { 0x7e, }; 2682 static int x2000_pwm_pwm1_c_pins[] = { 0x41, }; 2683 static int x2000_pwm_pwm1_d_pins[] = { 0x7f, }; 2684 static int x2000_pwm_pwm2_c_pins[] = { 0x42, }; 2685 static int x2000_pwm_pwm2_e_pins[] = { 0x80, }; 2686 static int x2000_pwm_pwm3_c_pins[] = { 0x43, }; 2687 static int x2000_pwm_pwm3_e_pins[] = { 0x81, }; 2688 static int x2000_pwm_pwm4_c_pins[] = { 0x44, }; 2689 static int x2000_pwm_pwm4_e_pins[] = { 0x82, }; 2690 static int x2000_pwm_pwm5_c_pins[] = { 0x45, }; 2691 static int x2000_pwm_pwm5_e_pins[] = { 0x83, }; 2692 static int x2000_pwm_pwm6_c_pins[] = { 0x46, }; 2693 static int x2000_pwm_pwm6_e_pins[] = { 0x84, }; 2694 static int x2000_pwm_pwm7_c_pins[] = { 0x47, }; 2695 static int x2000_pwm_pwm7_e_pins[] = { 0x85, }; 2696 static int x2000_pwm_pwm8_pins[] = { 0x48, }; 2697 static int x2000_pwm_pwm9_pins[] = { 0x49, }; 2698 static int x2000_pwm_pwm10_pins[] = { 0x4a, }; 2699 static int x2000_pwm_pwm11_pins[] = { 0x4b, }; 2700 static int x2000_pwm_pwm12_pins[] = { 0x4c, }; 2701 static int x2000_pwm_pwm13_pins[] = { 0x4d, }; 2702 static int x2000_pwm_pwm14_pins[] = { 0x4e, }; 2703 static int x2000_pwm_pwm15_pins[] = { 0x4f, }; 2704 static int x2000_mac0_rmii_pins[] = { 2705 0x4b, 0x47, 0x46, 0x4a, 0x43, 0x42, 0x4c, 0x4d, 0x4e, 0x41, 2706 }; 2707 static int x2000_mac0_rgmii_pins[] = { 2708 0x4b, 0x49, 0x48, 0x47, 0x46, 0x4a, 0x45, 0x44, 0x43, 0x42, 2709 0x4c, 0x4d, 0x4f, 0x4e, 0x41, 2710 }; 2711 static int x2000_mac1_rmii_pins[] = { 2712 0x32, 0x2d, 0x2c, 0x31, 0x29, 0x28, 0x33, 0x34, 0x35, 0x37, 2713 }; 2714 static int x2000_mac1_rgmii_pins[] = { 2715 0x32, 0x2f, 0x2e, 0x2d, 0x2c, 0x31, 0x2b, 0x2a, 0x29, 0x28, 2716 0x33, 0x34, 0x36, 0x35, 0x37, 2717 }; 2718 static int x2000_otg_pins[] = { 0x96, }; 2719 2720 static u8 x2000_cim_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, }; 2721 2722 static const struct group_desc x2000_groups[] = { 2723 INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2), 2724 INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2), 2725 INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1), 2726 INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1), 2727 INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0), 2728 INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0), 2729 INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1), 2730 INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0), 2731 INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1), 2732 INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1), 2733 INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3), 2734 INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1), 2735 INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3), 2736 INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1), 2737 INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3), 2738 INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1), 2739 INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3), 2740 INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1), 2741 INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3), 2742 INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3), 2743 INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3), 2744 INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1), 2745 INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0), 2746 INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1), 2747 INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1), 2748 INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0), 2749 INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1), 2750 INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0), 2751 INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1), 2752 INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1), 2753 INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1), 2754 INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1), 2755 INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1), 2756 INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1), 2757 INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1), 2758 INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1), 2759 INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2), 2760 INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2), 2761 INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1), 2762 INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2), 2763 INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2), 2764 INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1), 2765 INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2), 2766 INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2), 2767 INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1), 2768 INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2), 2769 INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2), 2770 INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1), 2771 INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0), 2772 INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0), 2773 INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0), 2774 INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0), 2775 INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0), 2776 INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0), 2777 INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0), 2778 INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0), 2779 INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0), 2780 INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0), 2781 INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0), 2782 INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0), 2783 INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3), 2784 INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3), 2785 INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3), 2786 INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2), 2787 INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1), 2788 INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2), 2789 INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2), 2790 INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1), 2791 INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0), 2792 INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1), 2793 INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1), 2794 INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2), 2795 INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1), 2796 INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1), 2797 INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2), 2798 INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2), 2799 INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2), 2800 INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2), 2801 INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2), 2802 INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2), 2803 INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2), 2804 INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2), 2805 INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2), 2806 INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2), 2807 INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2), 2808 INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2), 2809 INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2), 2810 INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2), 2811 INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2), 2812 INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2), 2813 INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2), 2814 INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2), 2815 INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0), 2816 INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0), 2817 INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0), 2818 INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0), 2819 INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit, 2820 x2000_cim_8bit_funcs), 2821 INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0), 2822 INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1), 2823 INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1), 2824 INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1), 2825 INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1), 2826 INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2), 2827 INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2), 2828 INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0), 2829 INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2), 2830 INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0), 2831 INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2), 2832 INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0), 2833 INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1), 2834 INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0), 2835 INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1), 2836 INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0), 2837 INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1), 2838 INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0), 2839 INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1), 2840 INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0), 2841 INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1), 2842 INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0), 2843 INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1), 2844 INGENIC_PIN_GROUP("pwm8", x2000_pwm_pwm8, 0), 2845 INGENIC_PIN_GROUP("pwm9", x2000_pwm_pwm9, 0), 2846 INGENIC_PIN_GROUP("pwm10", x2000_pwm_pwm10, 0), 2847 INGENIC_PIN_GROUP("pwm11", x2000_pwm_pwm11, 0), 2848 INGENIC_PIN_GROUP("pwm12", x2000_pwm_pwm12, 0), 2849 INGENIC_PIN_GROUP("pwm13", x2000_pwm_pwm13, 0), 2850 INGENIC_PIN_GROUP("pwm14", x2000_pwm_pwm14, 0), 2851 INGENIC_PIN_GROUP("pwm15", x2000_pwm_pwm15, 0), 2852 INGENIC_PIN_GROUP("mac0-rmii", x2000_mac0_rmii, 1), 2853 INGENIC_PIN_GROUP("mac0-rgmii", x2000_mac0_rgmii, 1), 2854 INGENIC_PIN_GROUP("mac1-rmii", x2000_mac1_rmii, 3), 2855 INGENIC_PIN_GROUP("mac1-rgmii", x2000_mac1_rgmii, 3), 2856 INGENIC_PIN_GROUP("otg-vbus", x2000_otg, 0), 2857 }; 2858 2859 static const char *x2000_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 2860 static const char *x2000_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 2861 static const char *x2000_uart2_groups[] = { "uart2-data", }; 2862 static const char *x2000_uart3_groups[] = { 2863 "uart3-data-c", "uart3-data-d", "uart3-hwflow-c", "uart3-hwflow-d", 2864 }; 2865 static const char *x2000_uart4_groups[] = { 2866 "uart4-data-a", "uart4-data-c", "uart4-hwflow-a", "uart4-hwflow-c", 2867 }; 2868 static const char *x2000_uart5_groups[] = { "uart5-data-a", "uart5-data-c", }; 2869 static const char *x2000_uart6_groups[] = { "uart6-data-a", "uart6-data-c", }; 2870 static const char *x2000_uart7_groups[] = { "uart7-data-a", "uart7-data-c", }; 2871 static const char *x2000_uart8_groups[] = { "uart8-data", }; 2872 static const char *x2000_uart9_groups[] = { "uart9-data", }; 2873 static const char *x2000_sfc_groups[] = { 2874 "sfc-data-if0-d", "sfc-data-if0-e", "sfc-data-if1", 2875 "sfc-clk-d", "sfc-clk-e", "sfc-ce-d", "sfc-ce-e", 2876 }; 2877 static const char *x2000_ssi0_groups[] = { 2878 "ssi0-dt-b", "ssi0-dt-d", 2879 "ssi0-dr-b", "ssi0-dr-d", 2880 "ssi0-clk-b", "ssi0-clk-d", 2881 "ssi0-ce-b", "ssi0-ce-d", 2882 }; 2883 static const char *x2000_ssi1_groups[] = { 2884 "ssi1-dt-c", "ssi1-dt-d", "ssi1-dt-e", 2885 "ssi1-dr-c", "ssi1-dr-d", "ssi1-dr-e", 2886 "ssi1-clk-c", "ssi1-clk-d", "ssi1-clk-e", 2887 "ssi1-ce-c", "ssi1-ce-d", "ssi1-ce-e", 2888 }; 2889 static const char *x2000_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", }; 2890 static const char *x2000_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 2891 static const char *x2000_mmc2_groups[] = { "mmc2-1bit", "mmc2-4bit", }; 2892 static const char *x2000_emc_groups[] = { 2893 "emc-8bit-data", "emc-16bit-data", 2894 "emc-addr", "emc-rd-we", "emc-wait", 2895 }; 2896 static const char *x2000_cs1_groups[] = { "emc-cs1", }; 2897 static const char *x2000_cs2_groups[] = { "emc-cs2", }; 2898 static const char *x2000_i2c0_groups[] = { "i2c0-data", }; 2899 static const char *x2000_i2c1_groups[] = { "i2c1-data-c", "i2c1-data-d", }; 2900 static const char *x2000_i2c2_groups[] = { "i2c2-data-b", "i2c2-data-d", }; 2901 static const char *x2000_i2c3_groups[] = { "i2c3-data-a", "i2c3-data-d", }; 2902 static const char *x2000_i2c4_groups[] = { "i2c4-data-c", "i2c4-data-d", }; 2903 static const char *x2000_i2c5_groups[] = { "i2c5-data-c", "i2c5-data-d", }; 2904 static const char *x2000_i2s1_groups[] = { 2905 "i2s1-data-tx", "i2s1-data-rx", 2906 "i2s1-clk-tx", "i2s1-clk-rx", 2907 "i2s1-sysclk-tx", "i2s1-sysclk-rx", 2908 }; 2909 static const char *x2000_i2s2_groups[] = { 2910 "i2s2-data-rx0", "i2s2-data-rx1", "i2s2-data-rx2", "i2s2-data-rx3", 2911 "i2s2-clk-rx", "i2s2-sysclk-rx", 2912 }; 2913 static const char *x2000_i2s3_groups[] = { 2914 "i2s3-data-tx0", "i2s3-data-tx1", "i2s3-data-tx2", "i2s3-data-tx3", 2915 "i2s3-clk-tx", "i2s3-sysclk-tx", 2916 }; 2917 static const char *x2000_dmic_groups[] = { 2918 "dmic-if0", "dmic-if1", "dmic-if2", "dmic-if3", 2919 }; 2920 static const char *x2000_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", }; 2921 static const char *x2000_lcd_groups[] = { 2922 "lcd-tft-8bit", "lcd-tft-16bit", "lcd-tft-18bit", "lcd-tft-24bit", 2923 "lcd-slcd-8bit", "lcd-slcd-16bit", 2924 }; 2925 static const char *x2000_pwm0_groups[] = { "pwm0-c", "pwm0-d", }; 2926 static const char *x2000_pwm1_groups[] = { "pwm1-c", "pwm1-d", }; 2927 static const char *x2000_pwm2_groups[] = { "pwm2-c", "pwm2-e", }; 2928 static const char *x2000_pwm3_groups[] = { "pwm3-c", "pwm3-r", }; 2929 static const char *x2000_pwm4_groups[] = { "pwm4-c", "pwm4-e", }; 2930 static const char *x2000_pwm5_groups[] = { "pwm5-c", "pwm5-e", }; 2931 static const char *x2000_pwm6_groups[] = { "pwm6-c", "pwm6-e", }; 2932 static const char *x2000_pwm7_groups[] = { "pwm7-c", "pwm7-e", }; 2933 static const char *x2000_pwm8_groups[] = { "pwm8", }; 2934 static const char *x2000_pwm9_groups[] = { "pwm9", }; 2935 static const char *x2000_pwm10_groups[] = { "pwm10", }; 2936 static const char *x2000_pwm11_groups[] = { "pwm11", }; 2937 static const char *x2000_pwm12_groups[] = { "pwm12", }; 2938 static const char *x2000_pwm13_groups[] = { "pwm13", }; 2939 static const char *x2000_pwm14_groups[] = { "pwm14", }; 2940 static const char *x2000_pwm15_groups[] = { "pwm15", }; 2941 static const char *x2000_mac0_groups[] = { "mac0-rmii", "mac0-rgmii", }; 2942 static const char *x2000_mac1_groups[] = { "mac1-rmii", "mac1-rgmii", }; 2943 static const char *x2000_otg_groups[] = { "otg-vbus", }; 2944 2945 static const struct function_desc x2000_functions[] = { 2946 { "uart0", x2000_uart0_groups, ARRAY_SIZE(x2000_uart0_groups), }, 2947 { "uart1", x2000_uart1_groups, ARRAY_SIZE(x2000_uart1_groups), }, 2948 { "uart2", x2000_uart2_groups, ARRAY_SIZE(x2000_uart2_groups), }, 2949 { "uart3", x2000_uart3_groups, ARRAY_SIZE(x2000_uart3_groups), }, 2950 { "uart4", x2000_uart4_groups, ARRAY_SIZE(x2000_uart4_groups), }, 2951 { "uart5", x2000_uart5_groups, ARRAY_SIZE(x2000_uart5_groups), }, 2952 { "uart6", x2000_uart6_groups, ARRAY_SIZE(x2000_uart6_groups), }, 2953 { "uart7", x2000_uart7_groups, ARRAY_SIZE(x2000_uart7_groups), }, 2954 { "uart8", x2000_uart8_groups, ARRAY_SIZE(x2000_uart8_groups), }, 2955 { "uart9", x2000_uart9_groups, ARRAY_SIZE(x2000_uart9_groups), }, 2956 { "sfc", x2000_sfc_groups, ARRAY_SIZE(x2000_sfc_groups), }, 2957 { "ssi0", x2000_ssi0_groups, ARRAY_SIZE(x2000_ssi0_groups), }, 2958 { "ssi1", x2000_ssi1_groups, ARRAY_SIZE(x2000_ssi1_groups), }, 2959 { "mmc0", x2000_mmc0_groups, ARRAY_SIZE(x2000_mmc0_groups), }, 2960 { "mmc1", x2000_mmc1_groups, ARRAY_SIZE(x2000_mmc1_groups), }, 2961 { "mmc2", x2000_mmc2_groups, ARRAY_SIZE(x2000_mmc2_groups), }, 2962 { "emc", x2000_emc_groups, ARRAY_SIZE(x2000_emc_groups), }, 2963 { "emc-cs1", x2000_cs1_groups, ARRAY_SIZE(x2000_cs1_groups), }, 2964 { "emc-cs2", x2000_cs2_groups, ARRAY_SIZE(x2000_cs2_groups), }, 2965 { "i2c0", x2000_i2c0_groups, ARRAY_SIZE(x2000_i2c0_groups), }, 2966 { "i2c1", x2000_i2c1_groups, ARRAY_SIZE(x2000_i2c1_groups), }, 2967 { "i2c2", x2000_i2c2_groups, ARRAY_SIZE(x2000_i2c2_groups), }, 2968 { "i2c3", x2000_i2c3_groups, ARRAY_SIZE(x2000_i2c3_groups), }, 2969 { "i2c4", x2000_i2c4_groups, ARRAY_SIZE(x2000_i2c4_groups), }, 2970 { "i2c5", x2000_i2c5_groups, ARRAY_SIZE(x2000_i2c5_groups), }, 2971 { "i2s1", x2000_i2s1_groups, ARRAY_SIZE(x2000_i2s1_groups), }, 2972 { "i2s2", x2000_i2s2_groups, ARRAY_SIZE(x2000_i2s2_groups), }, 2973 { "i2s3", x2000_i2s3_groups, ARRAY_SIZE(x2000_i2s3_groups), }, 2974 { "dmic", x2000_dmic_groups, ARRAY_SIZE(x2000_dmic_groups), }, 2975 { "cim", x2000_cim_groups, ARRAY_SIZE(x2000_cim_groups), }, 2976 { "lcd", x2000_lcd_groups, ARRAY_SIZE(x2000_lcd_groups), }, 2977 { "pwm0", x2000_pwm0_groups, ARRAY_SIZE(x2000_pwm0_groups), }, 2978 { "pwm1", x2000_pwm1_groups, ARRAY_SIZE(x2000_pwm1_groups), }, 2979 { "pwm2", x2000_pwm2_groups, ARRAY_SIZE(x2000_pwm2_groups), }, 2980 { "pwm3", x2000_pwm3_groups, ARRAY_SIZE(x2000_pwm3_groups), }, 2981 { "pwm4", x2000_pwm4_groups, ARRAY_SIZE(x2000_pwm4_groups), }, 2982 { "pwm5", x2000_pwm5_groups, ARRAY_SIZE(x2000_pwm5_groups), }, 2983 { "pwm6", x2000_pwm6_groups, ARRAY_SIZE(x2000_pwm6_groups), }, 2984 { "pwm7", x2000_pwm7_groups, ARRAY_SIZE(x2000_pwm7_groups), }, 2985 { "pwm8", x2000_pwm8_groups, ARRAY_SIZE(x2000_pwm8_groups), }, 2986 { "pwm9", x2000_pwm9_groups, ARRAY_SIZE(x2000_pwm9_groups), }, 2987 { "pwm10", x2000_pwm10_groups, ARRAY_SIZE(x2000_pwm10_groups), }, 2988 { "pwm11", x2000_pwm11_groups, ARRAY_SIZE(x2000_pwm11_groups), }, 2989 { "pwm12", x2000_pwm12_groups, ARRAY_SIZE(x2000_pwm12_groups), }, 2990 { "pwm13", x2000_pwm13_groups, ARRAY_SIZE(x2000_pwm13_groups), }, 2991 { "pwm14", x2000_pwm14_groups, ARRAY_SIZE(x2000_pwm14_groups), }, 2992 { "pwm15", x2000_pwm15_groups, ARRAY_SIZE(x2000_pwm15_groups), }, 2993 { "mac0", x2000_mac0_groups, ARRAY_SIZE(x2000_mac0_groups), }, 2994 { "mac1", x2000_mac1_groups, ARRAY_SIZE(x2000_mac1_groups), }, 2995 { "otg", x2000_otg_groups, ARRAY_SIZE(x2000_otg_groups), }, 2996 }; 2997 2998 static const struct regmap_range x2000_access_ranges[] = { 2999 regmap_reg_range(0x000, 0x500 - 4), 3000 regmap_reg_range(0x700, 0x800 - 4), 3001 }; 3002 3003 /* shared with X2100 */ 3004 static const struct regmap_access_table x2000_access_table = { 3005 .yes_ranges = x2000_access_ranges, 3006 .n_yes_ranges = ARRAY_SIZE(x2000_access_ranges), 3007 }; 3008 3009 static const struct ingenic_chip_info x2000_chip_info = { 3010 .num_chips = 5, 3011 .reg_offset = 0x100, 3012 .version = ID_X2000, 3013 .groups = x2000_groups, 3014 .num_groups = ARRAY_SIZE(x2000_groups), 3015 .functions = x2000_functions, 3016 .num_functions = ARRAY_SIZE(x2000_functions), 3017 .pull_ups = x2000_pull_ups, 3018 .pull_downs = x2000_pull_downs, 3019 .access_table = &x2000_access_table, 3020 }; 3021 3022 static const u32 x2100_pull_ups[5] = { 3023 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0xc7fe3f3f, 0x0fbf003f, 3024 }; 3025 3026 static const u32 x2100_pull_downs[5] = { 3027 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0x00000000, 0x0fbf003f, 3028 }; 3029 3030 static int x2100_mac_pins[] = { 3031 0x4b, 0x47, 0x46, 0x4a, 0x43, 0x42, 0x4c, 0x4d, 0x4f, 0x41, 3032 }; 3033 3034 static const struct group_desc x2100_groups[] = { 3035 INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2), 3036 INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2), 3037 INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1), 3038 INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1), 3039 INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0), 3040 INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0), 3041 INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1), 3042 INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0), 3043 INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1), 3044 INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1), 3045 INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3), 3046 INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1), 3047 INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3), 3048 INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1), 3049 INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3), 3050 INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1), 3051 INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3), 3052 INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1), 3053 INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3), 3054 INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3), 3055 INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3), 3056 INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1), 3057 INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0), 3058 INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1), 3059 INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1), 3060 INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0), 3061 INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1), 3062 INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0), 3063 INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1), 3064 INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1), 3065 INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1), 3066 INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1), 3067 INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1), 3068 INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1), 3069 INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1), 3070 INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1), 3071 INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2), 3072 INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2), 3073 INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1), 3074 INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2), 3075 INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2), 3076 INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1), 3077 INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2), 3078 INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2), 3079 INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1), 3080 INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2), 3081 INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2), 3082 INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1), 3083 INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0), 3084 INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0), 3085 INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0), 3086 INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0), 3087 INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0), 3088 INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0), 3089 INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0), 3090 INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0), 3091 INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0), 3092 INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0), 3093 INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0), 3094 INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0), 3095 INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3), 3096 INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3), 3097 INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3), 3098 INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2), 3099 INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1), 3100 INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2), 3101 INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2), 3102 INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1), 3103 INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0), 3104 INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1), 3105 INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1), 3106 INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2), 3107 INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1), 3108 INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1), 3109 INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2), 3110 INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2), 3111 INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2), 3112 INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2), 3113 INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2), 3114 INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2), 3115 INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2), 3116 INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2), 3117 INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2), 3118 INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2), 3119 INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2), 3120 INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2), 3121 INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2), 3122 INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2), 3123 INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2), 3124 INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2), 3125 INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2), 3126 INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2), 3127 INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0), 3128 INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0), 3129 INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0), 3130 INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0), 3131 INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit, 3132 x2000_cim_8bit_funcs), 3133 INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0), 3134 INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1), 3135 INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1), 3136 INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1), 3137 INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1), 3138 INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2), 3139 INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2), 3140 INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0), 3141 INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2), 3142 INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0), 3143 INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2), 3144 INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0), 3145 INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1), 3146 INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0), 3147 INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1), 3148 INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0), 3149 INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1), 3150 INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0), 3151 INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1), 3152 INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0), 3153 INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1), 3154 INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0), 3155 INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1), 3156 INGENIC_PIN_GROUP("pwm8", x2000_pwm_pwm8, 0), 3157 INGENIC_PIN_GROUP("pwm9", x2000_pwm_pwm9, 0), 3158 INGENIC_PIN_GROUP("pwm10", x2000_pwm_pwm10, 0), 3159 INGENIC_PIN_GROUP("pwm11", x2000_pwm_pwm11, 0), 3160 INGENIC_PIN_GROUP("pwm12", x2000_pwm_pwm12, 0), 3161 INGENIC_PIN_GROUP("pwm13", x2000_pwm_pwm13, 0), 3162 INGENIC_PIN_GROUP("pwm14", x2000_pwm_pwm14, 0), 3163 INGENIC_PIN_GROUP("pwm15", x2000_pwm_pwm15, 0), 3164 INGENIC_PIN_GROUP("mac", x2100_mac, 1), 3165 }; 3166 3167 static const char *x2100_mac_groups[] = { "mac", }; 3168 3169 static const struct function_desc x2100_functions[] = { 3170 { "uart0", x2000_uart0_groups, ARRAY_SIZE(x2000_uart0_groups), }, 3171 { "uart1", x2000_uart1_groups, ARRAY_SIZE(x2000_uart1_groups), }, 3172 { "uart2", x2000_uart2_groups, ARRAY_SIZE(x2000_uart2_groups), }, 3173 { "uart3", x2000_uart3_groups, ARRAY_SIZE(x2000_uart3_groups), }, 3174 { "uart4", x2000_uart4_groups, ARRAY_SIZE(x2000_uart4_groups), }, 3175 { "uart5", x2000_uart5_groups, ARRAY_SIZE(x2000_uart5_groups), }, 3176 { "uart6", x2000_uart6_groups, ARRAY_SIZE(x2000_uart6_groups), }, 3177 { "uart7", x2000_uart7_groups, ARRAY_SIZE(x2000_uart7_groups), }, 3178 { "uart8", x2000_uart8_groups, ARRAY_SIZE(x2000_uart8_groups), }, 3179 { "uart9", x2000_uart9_groups, ARRAY_SIZE(x2000_uart9_groups), }, 3180 { "sfc", x2000_sfc_groups, ARRAY_SIZE(x2000_sfc_groups), }, 3181 { "ssi0", x2000_ssi0_groups, ARRAY_SIZE(x2000_ssi0_groups), }, 3182 { "ssi1", x2000_ssi1_groups, ARRAY_SIZE(x2000_ssi1_groups), }, 3183 { "mmc0", x2000_mmc0_groups, ARRAY_SIZE(x2000_mmc0_groups), }, 3184 { "mmc1", x2000_mmc1_groups, ARRAY_SIZE(x2000_mmc1_groups), }, 3185 { "mmc2", x2000_mmc2_groups, ARRAY_SIZE(x2000_mmc2_groups), }, 3186 { "emc", x2000_emc_groups, ARRAY_SIZE(x2000_emc_groups), }, 3187 { "emc-cs1", x2000_cs1_groups, ARRAY_SIZE(x2000_cs1_groups), }, 3188 { "emc-cs2", x2000_cs2_groups, ARRAY_SIZE(x2000_cs2_groups), }, 3189 { "i2c0", x2000_i2c0_groups, ARRAY_SIZE(x2000_i2c0_groups), }, 3190 { "i2c1", x2000_i2c1_groups, ARRAY_SIZE(x2000_i2c1_groups), }, 3191 { "i2c2", x2000_i2c2_groups, ARRAY_SIZE(x2000_i2c2_groups), }, 3192 { "i2c3", x2000_i2c3_groups, ARRAY_SIZE(x2000_i2c3_groups), }, 3193 { "i2c4", x2000_i2c4_groups, ARRAY_SIZE(x2000_i2c4_groups), }, 3194 { "i2c5", x2000_i2c5_groups, ARRAY_SIZE(x2000_i2c5_groups), }, 3195 { "i2s1", x2000_i2s1_groups, ARRAY_SIZE(x2000_i2s1_groups), }, 3196 { "i2s2", x2000_i2s2_groups, ARRAY_SIZE(x2000_i2s2_groups), }, 3197 { "i2s3", x2000_i2s3_groups, ARRAY_SIZE(x2000_i2s3_groups), }, 3198 { "dmic", x2000_dmic_groups, ARRAY_SIZE(x2000_dmic_groups), }, 3199 { "cim", x2000_cim_groups, ARRAY_SIZE(x2000_cim_groups), }, 3200 { "lcd", x2000_lcd_groups, ARRAY_SIZE(x2000_lcd_groups), }, 3201 { "pwm0", x2000_pwm0_groups, ARRAY_SIZE(x2000_pwm0_groups), }, 3202 { "pwm1", x2000_pwm1_groups, ARRAY_SIZE(x2000_pwm1_groups), }, 3203 { "pwm2", x2000_pwm2_groups, ARRAY_SIZE(x2000_pwm2_groups), }, 3204 { "pwm3", x2000_pwm3_groups, ARRAY_SIZE(x2000_pwm3_groups), }, 3205 { "pwm4", x2000_pwm4_groups, ARRAY_SIZE(x2000_pwm4_groups), }, 3206 { "pwm5", x2000_pwm5_groups, ARRAY_SIZE(x2000_pwm5_groups), }, 3207 { "pwm6", x2000_pwm6_groups, ARRAY_SIZE(x2000_pwm6_groups), }, 3208 { "pwm7", x2000_pwm7_groups, ARRAY_SIZE(x2000_pwm7_groups), }, 3209 { "pwm8", x2000_pwm8_groups, ARRAY_SIZE(x2000_pwm8_groups), }, 3210 { "pwm9", x2000_pwm9_groups, ARRAY_SIZE(x2000_pwm9_groups), }, 3211 { "pwm10", x2000_pwm10_groups, ARRAY_SIZE(x2000_pwm10_groups), }, 3212 { "pwm11", x2000_pwm11_groups, ARRAY_SIZE(x2000_pwm11_groups), }, 3213 { "pwm12", x2000_pwm12_groups, ARRAY_SIZE(x2000_pwm12_groups), }, 3214 { "pwm13", x2000_pwm13_groups, ARRAY_SIZE(x2000_pwm13_groups), }, 3215 { "pwm14", x2000_pwm14_groups, ARRAY_SIZE(x2000_pwm14_groups), }, 3216 { "pwm15", x2000_pwm15_groups, ARRAY_SIZE(x2000_pwm15_groups), }, 3217 { "mac", x2100_mac_groups, ARRAY_SIZE(x2100_mac_groups), }, 3218 }; 3219 3220 static const struct ingenic_chip_info x2100_chip_info = { 3221 .num_chips = 5, 3222 .reg_offset = 0x100, 3223 .version = ID_X2100, 3224 .groups = x2100_groups, 3225 .num_groups = ARRAY_SIZE(x2100_groups), 3226 .functions = x2100_functions, 3227 .num_functions = ARRAY_SIZE(x2100_functions), 3228 .pull_ups = x2100_pull_ups, 3229 .pull_downs = x2100_pull_downs, 3230 .access_table = &x2000_access_table, 3231 }; 3232 3233 static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg) 3234 { 3235 unsigned int val; 3236 3237 regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val); 3238 3239 return (u32) val; 3240 } 3241 3242 static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc, 3243 u8 reg, u8 offset, bool set) 3244 { 3245 if (jzgc->jzpc->info->version == ID_JZ4730) { 3246 regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg, 3247 BIT(offset), set ? BIT(offset) : 0); 3248 return; 3249 } 3250 3251 if (set) 3252 reg = REG_SET(reg); 3253 else 3254 reg = REG_CLEAR(reg); 3255 3256 regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset)); 3257 } 3258 3259 static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc, 3260 u8 reg, u8 offset, bool set) 3261 { 3262 if (set) 3263 reg = REG_SET(reg); 3264 else 3265 reg = REG_CLEAR(reg); 3266 3267 regmap_write(jzgc->jzpc->map, REG_PZ_BASE( 3268 jzgc->jzpc->info->reg_offset) + reg, BIT(offset)); 3269 } 3270 3271 static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc) 3272 { 3273 regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD( 3274 jzgc->jzpc->info->reg_offset), 3275 jzgc->gc.base / PINS_PER_GPIO_CHIP); 3276 } 3277 3278 static void jz4730_gpio_set_bits(struct ingenic_gpio_chip *jzgc, 3279 u8 reg_upper, u8 reg_lower, u8 offset, u8 value) 3280 { 3281 /* 3282 * JZ4730 function and IRQ registers support two-bits-per-pin 3283 * definitions, split into two groups of 16. 3284 */ 3285 u8 reg = offset < JZ4730_PINS_PER_PAIRED_REG ? reg_lower : reg_upper; 3286 unsigned int idx = offset % JZ4730_PINS_PER_PAIRED_REG; 3287 unsigned int mask = GENMASK(1, 0) << idx * 2; 3288 3289 regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg, mask, value << (idx * 2)); 3290 } 3291 3292 static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc, 3293 u8 offset) 3294 { 3295 unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN); 3296 3297 return !!(val & BIT(offset)); 3298 } 3299 3300 static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc, 3301 u8 offset, int value) 3302 { 3303 if (jzgc->jzpc->info->version >= ID_JZ4770) 3304 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value); 3305 else if (jzgc->jzpc->info->version >= ID_JZ4740) 3306 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value); 3307 else 3308 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_DATA, offset, !!value); 3309 } 3310 3311 static void irq_set_type(struct ingenic_gpio_chip *jzgc, 3312 u8 offset, unsigned int type) 3313 { 3314 u8 reg1, reg2; 3315 bool val1, val2, val3; 3316 3317 switch (type) { 3318 case IRQ_TYPE_EDGE_BOTH: 3319 val1 = val2 = false; 3320 val3 = true; 3321 break; 3322 case IRQ_TYPE_EDGE_RISING: 3323 val1 = val2 = true; 3324 val3 = false; 3325 break; 3326 case IRQ_TYPE_EDGE_FALLING: 3327 val1 = val3 = false; 3328 val2 = true; 3329 break; 3330 case IRQ_TYPE_LEVEL_HIGH: 3331 val1 = true; 3332 val2 = val3 = false; 3333 break; 3334 case IRQ_TYPE_LEVEL_LOW: 3335 default: 3336 val1 = val2 = val3 = false; 3337 break; 3338 } 3339 3340 if (jzgc->jzpc->info->version >= ID_JZ4770) { 3341 reg1 = JZ4770_GPIO_PAT1; 3342 reg2 = JZ4770_GPIO_PAT0; 3343 } else if (jzgc->jzpc->info->version >= ID_JZ4740) { 3344 reg1 = JZ4740_GPIO_TRIG; 3345 reg2 = JZ4740_GPIO_DIR; 3346 } else { 3347 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPDIR, offset, false); 3348 jz4730_gpio_set_bits(jzgc, JZ4730_GPIO_GPIDUR, 3349 JZ4730_GPIO_GPIDLR, offset, (val2 << 1) | val1); 3350 return; 3351 } 3352 3353 if (jzgc->jzpc->info->version >= ID_X2000) { 3354 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1); 3355 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2); 3356 ingenic_gpio_shadow_set_bit_load(jzgc); 3357 ingenic_gpio_set_bit(jzgc, X2000_GPIO_EDG, offset, val3); 3358 } else if (jzgc->jzpc->info->version >= ID_X1000) { 3359 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1); 3360 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2); 3361 ingenic_gpio_shadow_set_bit_load(jzgc); 3362 } else { 3363 ingenic_gpio_set_bit(jzgc, reg2, offset, val1); 3364 ingenic_gpio_set_bit(jzgc, reg1, offset, val2); 3365 } 3366 } 3367 3368 static void ingenic_gpio_irq_mask(struct irq_data *irqd) 3369 { 3370 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 3371 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3372 int irq = irqd->hwirq; 3373 3374 if (jzgc->jzpc->info->version >= ID_JZ4740) 3375 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, true); 3376 else 3377 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, true); 3378 } 3379 3380 static void ingenic_gpio_irq_unmask(struct irq_data *irqd) 3381 { 3382 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 3383 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3384 int irq = irqd->hwirq; 3385 3386 if (jzgc->jzpc->info->version >= ID_JZ4740) 3387 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, false); 3388 else 3389 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, false); 3390 } 3391 3392 static void ingenic_gpio_irq_enable(struct irq_data *irqd) 3393 { 3394 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 3395 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3396 int irq = irqd->hwirq; 3397 3398 if (jzgc->jzpc->info->version >= ID_JZ4770) 3399 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, true); 3400 else if (jzgc->jzpc->info->version >= ID_JZ4740) 3401 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true); 3402 else 3403 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, true); 3404 3405 ingenic_gpio_irq_unmask(irqd); 3406 } 3407 3408 static void ingenic_gpio_irq_disable(struct irq_data *irqd) 3409 { 3410 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 3411 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3412 int irq = irqd->hwirq; 3413 3414 ingenic_gpio_irq_mask(irqd); 3415 3416 if (jzgc->jzpc->info->version >= ID_JZ4770) 3417 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, false); 3418 else if (jzgc->jzpc->info->version >= ID_JZ4740) 3419 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false); 3420 else 3421 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, false); 3422 } 3423 3424 static void ingenic_gpio_irq_ack(struct irq_data *irqd) 3425 { 3426 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 3427 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3428 int irq = irqd->hwirq; 3429 bool high; 3430 3431 if ((irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) && 3432 (jzgc->jzpc->info->version < ID_X2000)) { 3433 /* 3434 * Switch to an interrupt for the opposite edge to the one that 3435 * triggered the interrupt being ACKed. 3436 */ 3437 high = ingenic_gpio_get_value(jzgc, irq); 3438 if (high) 3439 irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_LOW); 3440 else 3441 irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_HIGH); 3442 } 3443 3444 if (jzgc->jzpc->info->version >= ID_JZ4770) 3445 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false); 3446 else if (jzgc->jzpc->info->version >= ID_JZ4740) 3447 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true); 3448 else 3449 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPFR, irq, false); 3450 } 3451 3452 static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) 3453 { 3454 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 3455 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3456 3457 switch (type) { 3458 case IRQ_TYPE_EDGE_BOTH: 3459 case IRQ_TYPE_EDGE_RISING: 3460 case IRQ_TYPE_EDGE_FALLING: 3461 irq_set_handler_locked(irqd, handle_edge_irq); 3462 break; 3463 case IRQ_TYPE_LEVEL_HIGH: 3464 case IRQ_TYPE_LEVEL_LOW: 3465 irq_set_handler_locked(irqd, handle_level_irq); 3466 break; 3467 default: 3468 irq_set_handler_locked(irqd, handle_bad_irq); 3469 } 3470 3471 if ((type == IRQ_TYPE_EDGE_BOTH) && (jzgc->jzpc->info->version < ID_X2000)) { 3472 /* 3473 * The hardware does not support interrupts on both edges. The 3474 * best we can do is to set up a single-edge interrupt and then 3475 * switch to the opposing edge when ACKing the interrupt. 3476 */ 3477 bool high = ingenic_gpio_get_value(jzgc, irqd->hwirq); 3478 3479 type = high ? IRQ_TYPE_LEVEL_LOW : IRQ_TYPE_LEVEL_HIGH; 3480 } 3481 3482 irq_set_type(jzgc, irqd->hwirq, type); 3483 return 0; 3484 } 3485 3486 static int ingenic_gpio_irq_set_wake(struct irq_data *irqd, unsigned int on) 3487 { 3488 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 3489 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3490 3491 return irq_set_irq_wake(jzgc->irq, on); 3492 } 3493 3494 static void ingenic_gpio_irq_handler(struct irq_desc *desc) 3495 { 3496 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 3497 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3498 struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data); 3499 unsigned long flag, i; 3500 3501 chained_irq_enter(irq_chip, desc); 3502 3503 if (jzgc->jzpc->info->version >= ID_JZ4770) 3504 flag = ingenic_gpio_read_reg(jzgc, JZ4770_GPIO_FLAG); 3505 else if (jzgc->jzpc->info->version >= ID_JZ4740) 3506 flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG); 3507 else 3508 flag = ingenic_gpio_read_reg(jzgc, JZ4730_GPIO_GPFR); 3509 3510 for_each_set_bit(i, &flag, 32) 3511 generic_handle_domain_irq(gc->irq.domain, i); 3512 chained_irq_exit(irq_chip, desc); 3513 } 3514 3515 static void ingenic_gpio_set(struct gpio_chip *gc, 3516 unsigned int offset, int value) 3517 { 3518 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3519 3520 ingenic_gpio_set_value(jzgc, offset, value); 3521 } 3522 3523 static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset) 3524 { 3525 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3526 3527 return (int) ingenic_gpio_get_value(jzgc, offset); 3528 } 3529 3530 static int ingenic_gpio_direction_input(struct gpio_chip *gc, 3531 unsigned int offset) 3532 { 3533 return pinctrl_gpio_direction_input(gc->base + offset); 3534 } 3535 3536 static int ingenic_gpio_direction_output(struct gpio_chip *gc, 3537 unsigned int offset, int value) 3538 { 3539 ingenic_gpio_set(gc, offset, value); 3540 return pinctrl_gpio_direction_output(gc->base + offset); 3541 } 3542 3543 static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc, 3544 unsigned int pin, unsigned int reg, bool set) 3545 { 3546 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3547 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3548 3549 if (set) { 3550 if (jzpc->info->version >= ID_JZ4740) 3551 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 3552 REG_SET(reg), BIT(idx)); 3553 else 3554 regmap_set_bits(jzpc->map, offt * jzpc->info->reg_offset + 3555 reg, BIT(idx)); 3556 } else { 3557 if (jzpc->info->version >= ID_JZ4740) 3558 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 3559 REG_CLEAR(reg), BIT(idx)); 3560 else 3561 regmap_clear_bits(jzpc->map, offt * jzpc->info->reg_offset + 3562 reg, BIT(idx)); 3563 } 3564 } 3565 3566 static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc, 3567 unsigned int pin, u8 reg, bool set) 3568 { 3569 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3570 3571 regmap_write(jzpc->map, REG_PZ_BASE(jzpc->info->reg_offset) + 3572 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); 3573 } 3574 3575 static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc, 3576 unsigned int pin) 3577 { 3578 regmap_write(jzpc->map, REG_PZ_GID2LD(jzpc->info->reg_offset), 3579 pin / PINS_PER_GPIO_CHIP); 3580 } 3581 3582 static inline void jz4730_config_pin_function(struct ingenic_pinctrl *jzpc, 3583 unsigned int pin, u8 reg_upper, u8 reg_lower, u8 value) 3584 { 3585 /* 3586 * JZ4730 function and IRQ registers support two-bits-per-pin 3587 * definitions, split into two groups of 16. 3588 */ 3589 unsigned int idx = pin % JZ4730_PINS_PER_PAIRED_REG; 3590 unsigned int mask = GENMASK(1, 0) << idx * 2; 3591 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3592 u8 reg = (pin % PINS_PER_GPIO_CHIP) < JZ4730_PINS_PER_PAIRED_REG ? reg_lower : reg_upper; 3593 3594 regmap_update_bits(jzpc->map, offt * jzpc->info->reg_offset + reg, 3595 mask, value << (idx * 2)); 3596 } 3597 3598 static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc, 3599 unsigned int pin, unsigned int reg) 3600 { 3601 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3602 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3603 unsigned int val; 3604 3605 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + reg, &val); 3606 3607 return val & BIT(idx); 3608 } 3609 3610 static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 3611 { 3612 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3613 struct ingenic_pinctrl *jzpc = jzgc->jzpc; 3614 unsigned int pin = gc->base + offset; 3615 3616 if (jzpc->info->version >= ID_JZ4770) { 3617 if (ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_INT) || 3618 ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PAT1)) 3619 return GPIO_LINE_DIRECTION_IN; 3620 return GPIO_LINE_DIRECTION_OUT; 3621 } else if (jzpc->info->version == ID_JZ4730) { 3622 if (!ingenic_get_pin_config(jzpc, pin, JZ4730_GPIO_GPDIR)) 3623 return GPIO_LINE_DIRECTION_IN; 3624 return GPIO_LINE_DIRECTION_OUT; 3625 } 3626 3627 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT)) 3628 return GPIO_LINE_DIRECTION_IN; 3629 3630 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_DIR)) 3631 return GPIO_LINE_DIRECTION_OUT; 3632 3633 return GPIO_LINE_DIRECTION_IN; 3634 } 3635 3636 static const struct pinctrl_ops ingenic_pctlops = { 3637 .get_groups_count = pinctrl_generic_get_group_count, 3638 .get_group_name = pinctrl_generic_get_group_name, 3639 .get_group_pins = pinctrl_generic_get_group_pins, 3640 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 3641 .dt_free_map = pinconf_generic_dt_free_map, 3642 }; 3643 3644 static int ingenic_gpio_irq_request(struct irq_data *data) 3645 { 3646 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 3647 int ret; 3648 3649 ret = ingenic_gpio_direction_input(gpio_chip, data->hwirq); 3650 if (ret) 3651 return ret; 3652 3653 return gpiochip_reqres_irq(gpio_chip, data->hwirq); 3654 } 3655 3656 static void ingenic_gpio_irq_release(struct irq_data *data) 3657 { 3658 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 3659 3660 return gpiochip_relres_irq(gpio_chip, data->hwirq); 3661 } 3662 3663 static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc, 3664 int pin, int func) 3665 { 3666 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3667 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3668 3669 dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n", 3670 'A' + offt, idx, func); 3671 3672 if (jzpc->info->version >= ID_X1000) { 3673 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_INT, false); 3674 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false); 3675 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2); 3676 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1); 3677 ingenic_shadow_config_pin_load(jzpc, pin); 3678 } else if (jzpc->info->version >= ID_JZ4770) { 3679 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false); 3680 ingenic_config_pin(jzpc, pin, GPIO_MSK, false); 3681 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2); 3682 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1); 3683 } else if (jzpc->info->version >= ID_JZ4740) { 3684 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true); 3685 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2); 3686 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func & 0x1); 3687 } else { 3688 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPIER, false); 3689 jz4730_config_pin_function(jzpc, pin, JZ4730_GPIO_GPAUR, JZ4730_GPIO_GPALR, func); 3690 } 3691 3692 return 0; 3693 } 3694 3695 static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev, 3696 unsigned int selector, unsigned int group) 3697 { 3698 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 3699 struct function_desc *func; 3700 struct group_desc *grp; 3701 unsigned int i; 3702 uintptr_t mode; 3703 u8 *pin_modes; 3704 3705 func = pinmux_generic_get_function(pctldev, selector); 3706 if (!func) 3707 return -EINVAL; 3708 3709 grp = pinctrl_generic_get_group(pctldev, group); 3710 if (!grp) 3711 return -EINVAL; 3712 3713 dev_dbg(pctldev->dev, "enable function %s group %s\n", 3714 func->name, grp->name); 3715 3716 mode = (uintptr_t)grp->data; 3717 if (mode <= 3) { 3718 for (i = 0; i < grp->num_pins; i++) 3719 ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], mode); 3720 } else { 3721 pin_modes = grp->data; 3722 3723 for (i = 0; i < grp->num_pins; i++) 3724 ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]); 3725 } 3726 3727 return 0; 3728 } 3729 3730 static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, 3731 struct pinctrl_gpio_range *range, 3732 unsigned int pin, bool input) 3733 { 3734 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 3735 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3736 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3737 3738 dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n", 3739 'A' + offt, idx, input ? "in" : "out"); 3740 3741 if (jzpc->info->version >= ID_X1000) { 3742 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_INT, false); 3743 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true); 3744 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input); 3745 ingenic_shadow_config_pin_load(jzpc, pin); 3746 } else if (jzpc->info->version >= ID_JZ4770) { 3747 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false); 3748 ingenic_config_pin(jzpc, pin, GPIO_MSK, true); 3749 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input); 3750 } else if (jzpc->info->version >= ID_JZ4740) { 3751 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false); 3752 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input); 3753 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false); 3754 } else { 3755 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPIER, false); 3756 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPDIR, !input); 3757 jz4730_config_pin_function(jzpc, pin, JZ4730_GPIO_GPAUR, JZ4730_GPIO_GPALR, 0); 3758 } 3759 3760 return 0; 3761 } 3762 3763 static const struct pinmux_ops ingenic_pmxops = { 3764 .get_functions_count = pinmux_generic_get_function_count, 3765 .get_function_name = pinmux_generic_get_function_name, 3766 .get_function_groups = pinmux_generic_get_function_groups, 3767 .set_mux = ingenic_pinmux_set_mux, 3768 .gpio_set_direction = ingenic_pinmux_gpio_set_direction, 3769 }; 3770 3771 static int ingenic_pinconf_get(struct pinctrl_dev *pctldev, 3772 unsigned int pin, unsigned long *config) 3773 { 3774 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 3775 enum pin_config_param param = pinconf_to_config_param(*config); 3776 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3777 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3778 unsigned int arg = 1; 3779 unsigned int bias, reg; 3780 bool pull, pullup, pulldown; 3781 3782 if (jzpc->info->version >= ID_X2000) { 3783 pullup = ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPU) && 3784 !ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPD) && 3785 (jzpc->info->pull_ups[offt] & BIT(idx)); 3786 pulldown = ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPD) && 3787 !ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPU) && 3788 (jzpc->info->pull_downs[offt] & BIT(idx)); 3789 3790 } else if (jzpc->info->version >= ID_X1830) { 3791 unsigned int half = PINS_PER_GPIO_CHIP / 2; 3792 unsigned int idxh = (pin % half) * 2; 3793 3794 if (idx < half) 3795 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + 3796 X1830_GPIO_PEL, &bias); 3797 else 3798 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + 3799 X1830_GPIO_PEH, &bias); 3800 3801 bias = (bias >> idxh) & (GPIO_PULL_UP | GPIO_PULL_DOWN); 3802 3803 pullup = (bias == GPIO_PULL_UP) && (jzpc->info->pull_ups[offt] & BIT(idx)); 3804 pulldown = (bias == GPIO_PULL_DOWN) && (jzpc->info->pull_downs[offt] & BIT(idx)); 3805 3806 } else { 3807 if (jzpc->info->version >= ID_JZ4770) 3808 pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN); 3809 else if (jzpc->info->version >= ID_JZ4740) 3810 pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS); 3811 else 3812 pull = ingenic_get_pin_config(jzpc, pin, JZ4730_GPIO_GPPUR); 3813 3814 pullup = pull && (jzpc->info->pull_ups[offt] & BIT(idx)); 3815 pulldown = pull && (jzpc->info->pull_downs[offt] & BIT(idx)); 3816 } 3817 3818 switch (param) { 3819 case PIN_CONFIG_BIAS_DISABLE: 3820 if (pullup || pulldown) 3821 return -EINVAL; 3822 3823 break; 3824 3825 case PIN_CONFIG_BIAS_PULL_UP: 3826 if (!pullup) 3827 return -EINVAL; 3828 3829 break; 3830 3831 case PIN_CONFIG_BIAS_PULL_DOWN: 3832 if (!pulldown) 3833 return -EINVAL; 3834 3835 break; 3836 3837 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 3838 if (jzpc->info->version >= ID_X2000) 3839 reg = X2000_GPIO_SMT; 3840 else if (jzpc->info->version >= ID_X1830) 3841 reg = X1830_GPIO_SMT; 3842 else 3843 return -EINVAL; 3844 3845 arg = !!ingenic_get_pin_config(jzpc, pin, reg); 3846 break; 3847 3848 case PIN_CONFIG_SLEW_RATE: 3849 if (jzpc->info->version >= ID_X2000) 3850 reg = X2000_GPIO_SR; 3851 else if (jzpc->info->version >= ID_X1830) 3852 reg = X1830_GPIO_SR; 3853 else 3854 return -EINVAL; 3855 3856 arg = !!ingenic_get_pin_config(jzpc, pin, reg); 3857 break; 3858 3859 default: 3860 return -ENOTSUPP; 3861 } 3862 3863 *config = pinconf_to_config_packed(param, arg); 3864 return 0; 3865 } 3866 3867 static void ingenic_set_bias(struct ingenic_pinctrl *jzpc, 3868 unsigned int pin, unsigned int bias) 3869 { 3870 if (jzpc->info->version >= ID_X2000) { 3871 switch (bias) { 3872 case GPIO_PULL_UP: 3873 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false); 3874 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, true); 3875 break; 3876 3877 case GPIO_PULL_DOWN: 3878 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, false); 3879 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, true); 3880 break; 3881 3882 case GPIO_PULL_DIS: 3883 default: 3884 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, false); 3885 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false); 3886 } 3887 3888 } else if (jzpc->info->version >= ID_X1830) { 3889 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3890 unsigned int half = PINS_PER_GPIO_CHIP / 2; 3891 unsigned int idxh = (pin % half) * 2; 3892 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3893 3894 if (idx < half) { 3895 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 3896 REG_CLEAR(X1830_GPIO_PEL), 3 << idxh); 3897 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 3898 REG_SET(X1830_GPIO_PEL), bias << idxh); 3899 } else { 3900 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 3901 REG_CLEAR(X1830_GPIO_PEH), 3 << idxh); 3902 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 3903 REG_SET(X1830_GPIO_PEH), bias << idxh); 3904 } 3905 3906 } else if (jzpc->info->version >= ID_JZ4770) { 3907 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PEN, !bias); 3908 } else if (jzpc->info->version >= ID_JZ4740) { 3909 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !bias); 3910 } else { 3911 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPPUR, bias); 3912 } 3913 } 3914 3915 static void ingenic_set_schmitt_trigger(struct ingenic_pinctrl *jzpc, 3916 unsigned int pin, bool enable) 3917 { 3918 if (jzpc->info->version >= ID_X2000) 3919 ingenic_config_pin(jzpc, pin, X2000_GPIO_SMT, enable); 3920 else 3921 ingenic_config_pin(jzpc, pin, X1830_GPIO_SMT, enable); 3922 } 3923 3924 static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc, 3925 unsigned int pin, bool high) 3926 { 3927 if (jzpc->info->version >= ID_JZ4770) 3928 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, high); 3929 else if (jzpc->info->version >= ID_JZ4740) 3930 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DATA, high); 3931 else 3932 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_DATA, high); 3933 } 3934 3935 static void ingenic_set_slew_rate(struct ingenic_pinctrl *jzpc, 3936 unsigned int pin, unsigned int slew) 3937 { 3938 if (jzpc->info->version >= ID_X2000) 3939 ingenic_config_pin(jzpc, pin, X2000_GPIO_SR, slew); 3940 else 3941 ingenic_config_pin(jzpc, pin, X1830_GPIO_SR, slew); 3942 } 3943 3944 static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 3945 unsigned long *configs, unsigned int num_configs) 3946 { 3947 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 3948 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3949 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3950 unsigned int cfg, arg; 3951 int ret; 3952 3953 for (cfg = 0; cfg < num_configs; cfg++) { 3954 switch (pinconf_to_config_param(configs[cfg])) { 3955 case PIN_CONFIG_BIAS_DISABLE: 3956 case PIN_CONFIG_BIAS_PULL_UP: 3957 case PIN_CONFIG_BIAS_PULL_DOWN: 3958 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 3959 case PIN_CONFIG_OUTPUT: 3960 case PIN_CONFIG_SLEW_RATE: 3961 continue; 3962 default: 3963 return -ENOTSUPP; 3964 } 3965 } 3966 3967 for (cfg = 0; cfg < num_configs; cfg++) { 3968 arg = pinconf_to_config_argument(configs[cfg]); 3969 3970 switch (pinconf_to_config_param(configs[cfg])) { 3971 case PIN_CONFIG_BIAS_DISABLE: 3972 dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n", 3973 'A' + offt, idx); 3974 ingenic_set_bias(jzpc, pin, GPIO_PULL_DIS); 3975 break; 3976 3977 case PIN_CONFIG_BIAS_PULL_UP: 3978 if (!(jzpc->info->pull_ups[offt] & BIT(idx))) 3979 return -EINVAL; 3980 dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n", 3981 'A' + offt, idx); 3982 ingenic_set_bias(jzpc, pin, GPIO_PULL_UP); 3983 break; 3984 3985 case PIN_CONFIG_BIAS_PULL_DOWN: 3986 if (!(jzpc->info->pull_downs[offt] & BIT(idx))) 3987 return -EINVAL; 3988 dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n", 3989 'A' + offt, idx); 3990 ingenic_set_bias(jzpc, pin, GPIO_PULL_DOWN); 3991 break; 3992 3993 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 3994 if (jzpc->info->version < ID_X1830) 3995 return -EINVAL; 3996 3997 ingenic_set_schmitt_trigger(jzpc, pin, arg); 3998 break; 3999 4000 case PIN_CONFIG_OUTPUT: 4001 ret = pinctrl_gpio_direction_output(pin); 4002 if (ret) 4003 return ret; 4004 4005 ingenic_set_output_level(jzpc, pin, arg); 4006 break; 4007 4008 case PIN_CONFIG_SLEW_RATE: 4009 if (jzpc->info->version < ID_X1830) 4010 return -EINVAL; 4011 4012 ingenic_set_slew_rate(jzpc, pin, arg); 4013 break; 4014 4015 default: 4016 /* unreachable */ 4017 break; 4018 } 4019 } 4020 4021 return 0; 4022 } 4023 4024 static int ingenic_pinconf_group_get(struct pinctrl_dev *pctldev, 4025 unsigned int group, unsigned long *config) 4026 { 4027 const unsigned int *pins; 4028 unsigned int i, npins, old = 0; 4029 int ret; 4030 4031 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 4032 if (ret) 4033 return ret; 4034 4035 for (i = 0; i < npins; i++) { 4036 if (ingenic_pinconf_get(pctldev, pins[i], config)) 4037 return -ENOTSUPP; 4038 4039 /* configs do not match between two pins */ 4040 if (i && (old != *config)) 4041 return -ENOTSUPP; 4042 4043 old = *config; 4044 } 4045 4046 return 0; 4047 } 4048 4049 static int ingenic_pinconf_group_set(struct pinctrl_dev *pctldev, 4050 unsigned int group, unsigned long *configs, 4051 unsigned int num_configs) 4052 { 4053 const unsigned int *pins; 4054 unsigned int i, npins; 4055 int ret; 4056 4057 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 4058 if (ret) 4059 return ret; 4060 4061 for (i = 0; i < npins; i++) { 4062 ret = ingenic_pinconf_set(pctldev, 4063 pins[i], configs, num_configs); 4064 if (ret) 4065 return ret; 4066 } 4067 4068 return 0; 4069 } 4070 4071 static const struct pinconf_ops ingenic_confops = { 4072 .is_generic = true, 4073 .pin_config_get = ingenic_pinconf_get, 4074 .pin_config_set = ingenic_pinconf_set, 4075 .pin_config_group_get = ingenic_pinconf_group_get, 4076 .pin_config_group_set = ingenic_pinconf_group_set, 4077 }; 4078 4079 static const struct regmap_config ingenic_pinctrl_regmap_config = { 4080 .reg_bits = 32, 4081 .val_bits = 32, 4082 .reg_stride = 4, 4083 }; 4084 4085 static const struct of_device_id ingenic_gpio_of_matches[] __initconst = { 4086 { .compatible = "ingenic,jz4730-gpio" }, 4087 { .compatible = "ingenic,jz4740-gpio" }, 4088 { .compatible = "ingenic,jz4725b-gpio" }, 4089 { .compatible = "ingenic,jz4750-gpio" }, 4090 { .compatible = "ingenic,jz4755-gpio" }, 4091 { .compatible = "ingenic,jz4760-gpio" }, 4092 { .compatible = "ingenic,jz4770-gpio" }, 4093 { .compatible = "ingenic,jz4775-gpio" }, 4094 { .compatible = "ingenic,jz4780-gpio" }, 4095 { .compatible = "ingenic,x1000-gpio" }, 4096 { .compatible = "ingenic,x1830-gpio" }, 4097 { .compatible = "ingenic,x2000-gpio" }, 4098 { .compatible = "ingenic,x2100-gpio" }, 4099 {}, 4100 }; 4101 4102 static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc, 4103 struct device_node *node) 4104 { 4105 struct ingenic_gpio_chip *jzgc; 4106 struct device *dev = jzpc->dev; 4107 struct gpio_irq_chip *girq; 4108 unsigned int bank; 4109 int err; 4110 4111 err = of_property_read_u32(node, "reg", &bank); 4112 if (err) { 4113 dev_err(dev, "Cannot read \"reg\" property: %i\n", err); 4114 return err; 4115 } 4116 4117 jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL); 4118 if (!jzgc) 4119 return -ENOMEM; 4120 4121 jzgc->jzpc = jzpc; 4122 jzgc->reg_base = bank * jzpc->info->reg_offset; 4123 4124 jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank); 4125 if (!jzgc->gc.label) 4126 return -ENOMEM; 4127 4128 /* DO NOT EXPAND THIS: FOR BACKWARD GPIO NUMBERSPACE COMPATIBIBILITY 4129 * ONLY: WORK TO TRANSITION CONSUMERS TO USE THE GPIO DESCRIPTOR API IN 4130 * <linux/gpio/consumer.h> INSTEAD. 4131 */ 4132 jzgc->gc.base = bank * 32; 4133 4134 jzgc->gc.ngpio = 32; 4135 jzgc->gc.parent = dev; 4136 jzgc->gc.of_node = node; 4137 jzgc->gc.owner = THIS_MODULE; 4138 4139 jzgc->gc.set = ingenic_gpio_set; 4140 jzgc->gc.get = ingenic_gpio_get; 4141 jzgc->gc.direction_input = ingenic_gpio_direction_input; 4142 jzgc->gc.direction_output = ingenic_gpio_direction_output; 4143 jzgc->gc.get_direction = ingenic_gpio_get_direction; 4144 jzgc->gc.request = gpiochip_generic_request; 4145 jzgc->gc.free = gpiochip_generic_free; 4146 4147 jzgc->irq = irq_of_parse_and_map(node, 0); 4148 if (!jzgc->irq) 4149 return -EINVAL; 4150 4151 jzgc->irq_chip.name = jzgc->gc.label; 4152 jzgc->irq_chip.irq_enable = ingenic_gpio_irq_enable; 4153 jzgc->irq_chip.irq_disable = ingenic_gpio_irq_disable; 4154 jzgc->irq_chip.irq_unmask = ingenic_gpio_irq_unmask; 4155 jzgc->irq_chip.irq_mask = ingenic_gpio_irq_mask; 4156 jzgc->irq_chip.irq_ack = ingenic_gpio_irq_ack; 4157 jzgc->irq_chip.irq_set_type = ingenic_gpio_irq_set_type; 4158 jzgc->irq_chip.irq_set_wake = ingenic_gpio_irq_set_wake; 4159 jzgc->irq_chip.irq_request_resources = ingenic_gpio_irq_request; 4160 jzgc->irq_chip.irq_release_resources = ingenic_gpio_irq_release; 4161 jzgc->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND; 4162 4163 girq = &jzgc->gc.irq; 4164 girq->chip = &jzgc->irq_chip; 4165 girq->parent_handler = ingenic_gpio_irq_handler; 4166 girq->num_parents = 1; 4167 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), 4168 GFP_KERNEL); 4169 if (!girq->parents) 4170 return -ENOMEM; 4171 4172 girq->parents[0] = jzgc->irq; 4173 girq->default_type = IRQ_TYPE_NONE; 4174 girq->handler = handle_level_irq; 4175 4176 err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc); 4177 if (err) 4178 return err; 4179 4180 return 0; 4181 } 4182 4183 static int __init ingenic_pinctrl_probe(struct platform_device *pdev) 4184 { 4185 struct device *dev = &pdev->dev; 4186 struct ingenic_pinctrl *jzpc; 4187 struct pinctrl_desc *pctl_desc; 4188 void __iomem *base; 4189 const struct ingenic_chip_info *chip_info; 4190 struct device_node *node; 4191 struct regmap_config regmap_config; 4192 unsigned int i; 4193 int err; 4194 4195 chip_info = of_device_get_match_data(dev); 4196 if (!chip_info) { 4197 dev_err(dev, "Unsupported SoC\n"); 4198 return -EINVAL; 4199 } 4200 4201 jzpc = devm_kzalloc(dev, sizeof(*jzpc), GFP_KERNEL); 4202 if (!jzpc) 4203 return -ENOMEM; 4204 4205 base = devm_platform_ioremap_resource(pdev, 0); 4206 if (IS_ERR(base)) 4207 return PTR_ERR(base); 4208 4209 regmap_config = ingenic_pinctrl_regmap_config; 4210 if (chip_info->access_table) { 4211 regmap_config.rd_table = chip_info->access_table; 4212 regmap_config.wr_table = chip_info->access_table; 4213 } else { 4214 regmap_config.max_register = chip_info->num_chips * chip_info->reg_offset - 4; 4215 } 4216 4217 jzpc->map = devm_regmap_init_mmio(dev, base, ®map_config); 4218 if (IS_ERR(jzpc->map)) { 4219 dev_err(dev, "Failed to create regmap\n"); 4220 return PTR_ERR(jzpc->map); 4221 } 4222 4223 jzpc->dev = dev; 4224 jzpc->info = chip_info; 4225 4226 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL); 4227 if (!pctl_desc) 4228 return -ENOMEM; 4229 4230 /* fill in pinctrl_desc structure */ 4231 pctl_desc->name = dev_name(dev); 4232 pctl_desc->owner = THIS_MODULE; 4233 pctl_desc->pctlops = &ingenic_pctlops; 4234 pctl_desc->pmxops = &ingenic_pmxops; 4235 pctl_desc->confops = &ingenic_confops; 4236 pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP; 4237 pctl_desc->pins = jzpc->pdesc = devm_kcalloc(&pdev->dev, 4238 pctl_desc->npins, sizeof(*jzpc->pdesc), GFP_KERNEL); 4239 if (!jzpc->pdesc) 4240 return -ENOMEM; 4241 4242 for (i = 0; i < pctl_desc->npins; i++) { 4243 jzpc->pdesc[i].number = i; 4244 jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d", 4245 'A' + (i / PINS_PER_GPIO_CHIP), 4246 i % PINS_PER_GPIO_CHIP); 4247 } 4248 4249 jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc); 4250 if (IS_ERR(jzpc->pctl)) { 4251 dev_err(dev, "Failed to register pinctrl\n"); 4252 return PTR_ERR(jzpc->pctl); 4253 } 4254 4255 for (i = 0; i < chip_info->num_groups; i++) { 4256 const struct group_desc *group = &chip_info->groups[i]; 4257 4258 err = pinctrl_generic_add_group(jzpc->pctl, group->name, 4259 group->pins, group->num_pins, group->data); 4260 if (err < 0) { 4261 dev_err(dev, "Failed to register group %s\n", 4262 group->name); 4263 return err; 4264 } 4265 } 4266 4267 for (i = 0; i < chip_info->num_functions; i++) { 4268 const struct function_desc *func = &chip_info->functions[i]; 4269 4270 err = pinmux_generic_add_function(jzpc->pctl, func->name, 4271 func->group_names, func->num_group_names, 4272 func->data); 4273 if (err < 0) { 4274 dev_err(dev, "Failed to register function %s\n", 4275 func->name); 4276 return err; 4277 } 4278 } 4279 4280 dev_set_drvdata(dev, jzpc->map); 4281 4282 for_each_child_of_node(dev->of_node, node) { 4283 if (of_match_node(ingenic_gpio_of_matches, node)) { 4284 err = ingenic_gpio_probe(jzpc, node); 4285 if (err) { 4286 of_node_put(node); 4287 return err; 4288 } 4289 } 4290 } 4291 4292 return 0; 4293 } 4294 4295 #define IF_ENABLED(cfg, ptr) PTR_IF(IS_ENABLED(cfg), (ptr)) 4296 4297 static const struct of_device_id ingenic_pinctrl_of_matches[] = { 4298 { 4299 .compatible = "ingenic,jz4730-pinctrl", 4300 .data = IF_ENABLED(CONFIG_MACH_JZ4730, &jz4730_chip_info) 4301 }, 4302 { 4303 .compatible = "ingenic,jz4740-pinctrl", 4304 .data = IF_ENABLED(CONFIG_MACH_JZ4740, &jz4740_chip_info) 4305 }, 4306 { 4307 .compatible = "ingenic,jz4725b-pinctrl", 4308 .data = IF_ENABLED(CONFIG_MACH_JZ4725B, &jz4725b_chip_info) 4309 }, 4310 { 4311 .compatible = "ingenic,jz4750-pinctrl", 4312 .data = IF_ENABLED(CONFIG_MACH_JZ4750, &jz4750_chip_info) 4313 }, 4314 { 4315 .compatible = "ingenic,jz4755-pinctrl", 4316 .data = IF_ENABLED(CONFIG_MACH_JZ4755, &jz4755_chip_info) 4317 }, 4318 { 4319 .compatible = "ingenic,jz4760-pinctrl", 4320 .data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info) 4321 }, 4322 { 4323 .compatible = "ingenic,jz4760b-pinctrl", 4324 .data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info) 4325 }, 4326 { 4327 .compatible = "ingenic,jz4770-pinctrl", 4328 .data = IF_ENABLED(CONFIG_MACH_JZ4770, &jz4770_chip_info) 4329 }, 4330 { 4331 .compatible = "ingenic,jz4775-pinctrl", 4332 .data = IF_ENABLED(CONFIG_MACH_JZ4775, &jz4775_chip_info) 4333 }, 4334 { 4335 .compatible = "ingenic,jz4780-pinctrl", 4336 .data = IF_ENABLED(CONFIG_MACH_JZ4780, &jz4780_chip_info) 4337 }, 4338 { 4339 .compatible = "ingenic,x1000-pinctrl", 4340 .data = IF_ENABLED(CONFIG_MACH_X1000, &x1000_chip_info) 4341 }, 4342 { 4343 .compatible = "ingenic,x1000e-pinctrl", 4344 .data = IF_ENABLED(CONFIG_MACH_X1000, &x1000_chip_info) 4345 }, 4346 { 4347 .compatible = "ingenic,x1500-pinctrl", 4348 .data = IF_ENABLED(CONFIG_MACH_X1500, &x1500_chip_info) 4349 }, 4350 { 4351 .compatible = "ingenic,x1830-pinctrl", 4352 .data = IF_ENABLED(CONFIG_MACH_X1830, &x1830_chip_info) 4353 }, 4354 { 4355 .compatible = "ingenic,x2000-pinctrl", 4356 .data = IF_ENABLED(CONFIG_MACH_X2000, &x2000_chip_info) 4357 }, 4358 { 4359 .compatible = "ingenic,x2000e-pinctrl", 4360 .data = IF_ENABLED(CONFIG_MACH_X2000, &x2000_chip_info) 4361 }, 4362 { 4363 .compatible = "ingenic,x2100-pinctrl", 4364 .data = IF_ENABLED(CONFIG_MACH_X2100, &x2100_chip_info) 4365 }, 4366 { /* sentinel */ }, 4367 }; 4368 4369 static struct platform_driver ingenic_pinctrl_driver = { 4370 .driver = { 4371 .name = "pinctrl-ingenic", 4372 .of_match_table = ingenic_pinctrl_of_matches, 4373 }, 4374 }; 4375 4376 static int __init ingenic_pinctrl_drv_register(void) 4377 { 4378 return platform_driver_probe(&ingenic_pinctrl_driver, 4379 ingenic_pinctrl_probe); 4380 } 4381 subsys_initcall(ingenic_pinctrl_drv_register); 4382