1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  *  linux/drivers/pinctrl/pinmux-falcon.c
4  *  based on linux/drivers/pinctrl/pinmux-pxa910.c
5  *
6  *  Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>
7  *  Copyright (C) 2012 John Crispin <john@phrozen.org>
8  */
9 
10 #include <linux/err.h>
11 #include <linux/export.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/interrupt.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/of_gpio.h>
18 #include <linux/of_platform.h>
19 #include <linux/platform_device.h>
20 #include <linux/seq_file.h>
21 #include <linux/slab.h>
22 
23 #include "pinctrl-lantiq.h"
24 
25 #include <lantiq_soc.h>
26 
27 /* Multiplexer Control Register */
28 #define LTQ_PADC_MUX(x)         (x * 0x4)
29 /* Pull Up Enable Register */
30 #define LTQ_PADC_PUEN		0x80
31 /* Pull Down Enable Register */
32 #define LTQ_PADC_PDEN		0x84
33 /* Slew Rate Control Register */
34 #define LTQ_PADC_SRC		0x88
35 /* Drive Current Control Register */
36 #define LTQ_PADC_DCC		0x8C
37 /* Pad Control Availability Register */
38 #define LTQ_PADC_AVAIL          0xF0
39 
40 #define pad_r32(p, reg)		ltq_r32(p + reg)
41 #define pad_w32(p, val, reg)	ltq_w32(val, p + reg)
42 #define pad_w32_mask(c, clear, set, reg) \
43 		pad_w32(c, (pad_r32(c, reg) & ~(clear)) | (set), reg)
44 
45 #define pad_getbit(m, r, p)	(!!(ltq_r32(m + r) & (1 << p)))
46 
47 #define PORTS			5
48 #define PINS			32
49 #define PORT(x)                 (x / PINS)
50 #define PORT_PIN(x)             (x % PINS)
51 
52 #define MFP_FALCON(a, f0, f1, f2, f3)		\
53 {						\
54 	.name = #a,				\
55 	.pin = a,				\
56 	.func = {				\
57 		FALCON_MUX_##f0,		\
58 		FALCON_MUX_##f1,		\
59 		FALCON_MUX_##f2,		\
60 		FALCON_MUX_##f3,		\
61 	},					\
62 }
63 
64 #define GRP_MUX(a, m, p)	\
65 {				\
66 	.name = a,		\
67 	.mux = FALCON_MUX_##m,	\
68 	.pins = p,		\
69 	.npins = ARRAY_SIZE(p),	\
70 }
71 
72 enum falcon_mux {
73 	FALCON_MUX_GPIO = 0,
74 	FALCON_MUX_RST,
75 	FALCON_MUX_NTR,
76 	FALCON_MUX_PPS,
77 	FALCON_MUX_MDIO,
78 	FALCON_MUX_LED,
79 	FALCON_MUX_SPI,
80 	FALCON_MUX_ASC,
81 	FALCON_MUX_I2C,
82 	FALCON_MUX_HOSTIF,
83 	FALCON_MUX_SLIC,
84 	FALCON_MUX_JTAG,
85 	FALCON_MUX_PCM,
86 	FALCON_MUX_MII,
87 	FALCON_MUX_PHY,
88 	FALCON_MUX_NONE = 0xffff,
89 };
90 
91 static struct pinctrl_pin_desc falcon_pads[PORTS * PINS];
92 static int pad_count[PORTS];
93 
94 static void lantiq_load_pin_desc(struct pinctrl_pin_desc *d, int bank, int len)
95 {
96 	int base = bank * PINS;
97 	int i;
98 
99 	for (i = 0; i < len; i++) {
100 		d[i].number = base + i;
101 		d[i].name = kasprintf(GFP_KERNEL, "io%d", base + i);
102 	}
103 	pad_count[bank] = len;
104 }
105 
106 static struct ltq_mfp_pin falcon_mfp[] = {
107 	/*	pin		f0	f1	f2	f3 */
108 	MFP_FALCON(GPIO0,	RST,	GPIO,   NONE,   NONE),
109 	MFP_FALCON(GPIO1,	GPIO,	GPIO,   NONE,   NONE),
110 	MFP_FALCON(GPIO2,	GPIO,	GPIO,   NONE,   NONE),
111 	MFP_FALCON(GPIO3,	GPIO,	GPIO,   NONE,   NONE),
112 	MFP_FALCON(GPIO4,	NTR,	GPIO,   NONE,   NONE),
113 	MFP_FALCON(GPIO5,	NTR,	GPIO,   PPS,    NONE),
114 	MFP_FALCON(GPIO6,	RST,	GPIO,   NONE,   NONE),
115 	MFP_FALCON(GPIO7,	MDIO,	GPIO,   NONE,   NONE),
116 	MFP_FALCON(GPIO8,	MDIO,	GPIO,   NONE,   NONE),
117 	MFP_FALCON(GPIO9,	LED,	GPIO,   NONE,   NONE),
118 	MFP_FALCON(GPIO10,	LED,	GPIO,   NONE,   NONE),
119 	MFP_FALCON(GPIO11,	LED,	GPIO,   NONE,   NONE),
120 	MFP_FALCON(GPIO12,	LED,	GPIO,   NONE,   NONE),
121 	MFP_FALCON(GPIO13,	LED,	GPIO,   NONE,   NONE),
122 	MFP_FALCON(GPIO14,	LED,	GPIO,   NONE,   NONE),
123 	MFP_FALCON(GPIO32,	ASC,	GPIO,   NONE,   NONE),
124 	MFP_FALCON(GPIO33,	ASC,	GPIO,   NONE,   NONE),
125 	MFP_FALCON(GPIO34,	SPI,	GPIO,	NONE,	NONE),
126 	MFP_FALCON(GPIO35,	SPI,	GPIO,	NONE,	NONE),
127 	MFP_FALCON(GPIO36,	SPI,	GPIO,	NONE,	NONE),
128 	MFP_FALCON(GPIO37,	SPI,	GPIO,	NONE,	NONE),
129 	MFP_FALCON(GPIO38,	SPI,	GPIO,	NONE,	NONE),
130 	MFP_FALCON(GPIO39,	I2C,	GPIO,	NONE,	NONE),
131 	MFP_FALCON(GPIO40,	I2C,	GPIO,	NONE,	NONE),
132 	MFP_FALCON(GPIO41,	HOSTIF,	GPIO,	HOSTIF,	JTAG),
133 	MFP_FALCON(GPIO42,	HOSTIF,	GPIO,	HOSTIF,	NONE),
134 	MFP_FALCON(GPIO43,	SLIC,	GPIO,	NONE,	NONE),
135 	MFP_FALCON(GPIO44,	SLIC,	GPIO,	PCM,	ASC),
136 	MFP_FALCON(GPIO45,	SLIC,	GPIO,	PCM,	ASC),
137 	MFP_FALCON(GPIO64,	MII,	GPIO,	NONE,	NONE),
138 	MFP_FALCON(GPIO65,	MII,	GPIO,	NONE,	NONE),
139 	MFP_FALCON(GPIO66,	MII,	GPIO,	NONE,	NONE),
140 	MFP_FALCON(GPIO67,	MII,	GPIO,	NONE,	NONE),
141 	MFP_FALCON(GPIO68,	MII,	GPIO,	NONE,	NONE),
142 	MFP_FALCON(GPIO69,	MII,	GPIO,	NONE,	NONE),
143 	MFP_FALCON(GPIO70,	MII,	GPIO,	NONE,	NONE),
144 	MFP_FALCON(GPIO71,	MII,	GPIO,	NONE,	NONE),
145 	MFP_FALCON(GPIO72,	MII,	GPIO,	NONE,	NONE),
146 	MFP_FALCON(GPIO73,	MII,	GPIO,	NONE,	NONE),
147 	MFP_FALCON(GPIO74,	MII,	GPIO,	NONE,	NONE),
148 	MFP_FALCON(GPIO75,	MII,	GPIO,	NONE,	NONE),
149 	MFP_FALCON(GPIO76,	MII,	GPIO,	NONE,	NONE),
150 	MFP_FALCON(GPIO77,	MII,	GPIO,	NONE,	NONE),
151 	MFP_FALCON(GPIO78,	MII,	GPIO,	NONE,	NONE),
152 	MFP_FALCON(GPIO79,	MII,	GPIO,	NONE,	NONE),
153 	MFP_FALCON(GPIO80,	MII,	GPIO,	NONE,	NONE),
154 	MFP_FALCON(GPIO81,	MII,	GPIO,	NONE,	NONE),
155 	MFP_FALCON(GPIO82,	MII,	GPIO,	NONE,	NONE),
156 	MFP_FALCON(GPIO83,	MII,	GPIO,	NONE,	NONE),
157 	MFP_FALCON(GPIO84,	MII,	GPIO,	NONE,	NONE),
158 	MFP_FALCON(GPIO85,	MII,	GPIO,	NONE,	NONE),
159 	MFP_FALCON(GPIO86,	MII,	GPIO,	NONE,	NONE),
160 	MFP_FALCON(GPIO87,	MII,	GPIO,	NONE,	NONE),
161 	MFP_FALCON(GPIO88,	PHY,	GPIO,	NONE,	NONE),
162 };
163 
164 static const unsigned pins_por[] = {GPIO0};
165 static const unsigned pins_ntr[] = {GPIO4};
166 static const unsigned pins_ntr8k[] = {GPIO5};
167 static const unsigned pins_pps[] = {GPIO5};
168 static const unsigned pins_hrst[] = {GPIO6};
169 static const unsigned pins_mdio[] = {GPIO7, GPIO8};
170 static const unsigned pins_bled[] = {GPIO9, GPIO10, GPIO11,
171 					GPIO12, GPIO13, GPIO14};
172 static const unsigned pins_asc0[] = {GPIO32, GPIO33};
173 static const unsigned pins_spi[] = {GPIO34, GPIO35, GPIO36};
174 static const unsigned pins_spi_cs0[] = {GPIO37};
175 static const unsigned pins_spi_cs1[] = {GPIO38};
176 static const unsigned pins_i2c[] = {GPIO39, GPIO40};
177 static const unsigned pins_jtag[] = {GPIO41};
178 static const unsigned pins_slic[] = {GPIO43, GPIO44, GPIO45};
179 static const unsigned pins_pcm[] = {GPIO44, GPIO45};
180 static const unsigned pins_asc1[] = {GPIO44, GPIO45};
181 
182 static struct ltq_pin_group falcon_grps[] = {
183 	GRP_MUX("por", RST, pins_por),
184 	GRP_MUX("ntr", NTR, pins_ntr),
185 	GRP_MUX("ntr8k", NTR, pins_ntr8k),
186 	GRP_MUX("pps", PPS, pins_pps),
187 	GRP_MUX("hrst", RST, pins_hrst),
188 	GRP_MUX("mdio", MDIO, pins_mdio),
189 	GRP_MUX("bootled", LED, pins_bled),
190 	GRP_MUX("asc0", ASC, pins_asc0),
191 	GRP_MUX("spi", SPI, pins_spi),
192 	GRP_MUX("spi cs0", SPI, pins_spi_cs0),
193 	GRP_MUX("spi cs1", SPI, pins_spi_cs1),
194 	GRP_MUX("i2c", I2C, pins_i2c),
195 	GRP_MUX("jtag", JTAG, pins_jtag),
196 	GRP_MUX("slic", SLIC, pins_slic),
197 	GRP_MUX("pcm", PCM, pins_pcm),
198 	GRP_MUX("asc1", ASC, pins_asc1),
199 };
200 
201 static const char * const ltq_rst_grps[] = {"por", "hrst"};
202 static const char * const ltq_ntr_grps[] = {"ntr", "ntr8k", "pps"};
203 static const char * const ltq_mdio_grps[] = {"mdio"};
204 static const char * const ltq_bled_grps[] = {"bootled"};
205 static const char * const ltq_asc_grps[] = {"asc0", "asc1"};
206 static const char * const ltq_spi_grps[] = {"spi", "spi cs0", "spi cs1"};
207 static const char * const ltq_i2c_grps[] = {"i2c"};
208 static const char * const ltq_jtag_grps[] = {"jtag"};
209 static const char * const ltq_slic_grps[] = {"slic"};
210 static const char * const ltq_pcm_grps[] = {"pcm"};
211 
212 static struct ltq_pmx_func falcon_funcs[] = {
213 	{"rst",		ARRAY_AND_SIZE(ltq_rst_grps)},
214 	{"ntr",		ARRAY_AND_SIZE(ltq_ntr_grps)},
215 	{"mdio",	ARRAY_AND_SIZE(ltq_mdio_grps)},
216 	{"led",		ARRAY_AND_SIZE(ltq_bled_grps)},
217 	{"asc",		ARRAY_AND_SIZE(ltq_asc_grps)},
218 	{"spi",		ARRAY_AND_SIZE(ltq_spi_grps)},
219 	{"i2c",		ARRAY_AND_SIZE(ltq_i2c_grps)},
220 	{"jtag",	ARRAY_AND_SIZE(ltq_jtag_grps)},
221 	{"slic",	ARRAY_AND_SIZE(ltq_slic_grps)},
222 	{"pcm",		ARRAY_AND_SIZE(ltq_pcm_grps)},
223 };
224 
225 
226 
227 
228 /* ---------  pinconf related code --------- */
229 static int falcon_pinconf_group_get(struct pinctrl_dev *pctrldev,
230 				unsigned group, unsigned long *config)
231 {
232 	return -ENOTSUPP;
233 }
234 
235 static int falcon_pinconf_group_set(struct pinctrl_dev *pctrldev,
236 				unsigned group, unsigned long *configs,
237 				unsigned num_configs)
238 {
239 	return -ENOTSUPP;
240 }
241 
242 static int falcon_pinconf_get(struct pinctrl_dev *pctrldev,
243 				unsigned pin, unsigned long *config)
244 {
245 	struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
246 	enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(*config);
247 	void __iomem *mem = info->membase[PORT(pin)];
248 
249 	switch (param) {
250 	case LTQ_PINCONF_PARAM_DRIVE_CURRENT:
251 		*config = LTQ_PINCONF_PACK(param,
252 			!!pad_getbit(mem, LTQ_PADC_DCC, PORT_PIN(pin)));
253 		break;
254 
255 	case LTQ_PINCONF_PARAM_SLEW_RATE:
256 		*config = LTQ_PINCONF_PACK(param,
257 			!!pad_getbit(mem, LTQ_PADC_SRC, PORT_PIN(pin)));
258 		break;
259 
260 	case LTQ_PINCONF_PARAM_PULL:
261 		if (pad_getbit(mem, LTQ_PADC_PDEN, PORT_PIN(pin)))
262 			*config = LTQ_PINCONF_PACK(param, 1);
263 		else if (pad_getbit(mem, LTQ_PADC_PUEN, PORT_PIN(pin)))
264 			*config = LTQ_PINCONF_PACK(param, 2);
265 		else
266 			*config = LTQ_PINCONF_PACK(param, 0);
267 
268 		break;
269 
270 	default:
271 		return -ENOTSUPP;
272 	}
273 
274 	return 0;
275 }
276 
277 static int falcon_pinconf_set(struct pinctrl_dev *pctrldev,
278 			unsigned pin, unsigned long *configs,
279 			unsigned num_configs)
280 {
281 	enum ltq_pinconf_param param;
282 	int arg;
283 	struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
284 	void __iomem *mem = info->membase[PORT(pin)];
285 	u32 reg;
286 	int i;
287 
288 	for (i = 0; i < num_configs; i++) {
289 		param = LTQ_PINCONF_UNPACK_PARAM(configs[i]);
290 		arg = LTQ_PINCONF_UNPACK_ARG(configs[i]);
291 
292 		switch (param) {
293 		case LTQ_PINCONF_PARAM_DRIVE_CURRENT:
294 			reg = LTQ_PADC_DCC;
295 			break;
296 
297 		case LTQ_PINCONF_PARAM_SLEW_RATE:
298 			reg = LTQ_PADC_SRC;
299 			break;
300 
301 		case LTQ_PINCONF_PARAM_PULL:
302 			if (arg == 1)
303 				reg = LTQ_PADC_PDEN;
304 			else
305 				reg = LTQ_PADC_PUEN;
306 			break;
307 
308 		default:
309 			pr_err("%s: Invalid config param %04x\n",
310 			pinctrl_dev_get_name(pctrldev), param);
311 			return -ENOTSUPP;
312 		}
313 
314 		pad_w32(mem, BIT(PORT_PIN(pin)), reg);
315 		if (!(pad_r32(mem, reg) & BIT(PORT_PIN(pin))))
316 			return -ENOTSUPP;
317 	} /* for each config */
318 
319 	return 0;
320 }
321 
322 static void falcon_pinconf_dbg_show(struct pinctrl_dev *pctrldev,
323 			struct seq_file *s, unsigned offset)
324 {
325 	unsigned long config;
326 	struct pin_desc *desc;
327 
328 	struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
329 	int port = PORT(offset);
330 
331 	seq_printf(s, " (port %d) mux %d -- ", port,
332 		pad_r32(info->membase[port], LTQ_PADC_MUX(PORT_PIN(offset))));
333 
334 	config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_PULL, 0);
335 	if (!falcon_pinconf_get(pctrldev, offset, &config))
336 		seq_printf(s, "pull %d ",
337 			(int)LTQ_PINCONF_UNPACK_ARG(config));
338 
339 	config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_DRIVE_CURRENT, 0);
340 	if (!falcon_pinconf_get(pctrldev, offset, &config))
341 		seq_printf(s, "drive-current %d ",
342 			(int)LTQ_PINCONF_UNPACK_ARG(config));
343 
344 	config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_SLEW_RATE, 0);
345 	if (!falcon_pinconf_get(pctrldev, offset, &config))
346 		seq_printf(s, "slew-rate %d ",
347 			(int)LTQ_PINCONF_UNPACK_ARG(config));
348 
349 	desc = pin_desc_get(pctrldev, offset);
350 	if (desc) {
351 		if (desc->gpio_owner)
352 			seq_printf(s, " owner: %s", desc->gpio_owner);
353 	} else {
354 		seq_printf(s, " not registered");
355 	}
356 }
357 
358 static void falcon_pinconf_group_dbg_show(struct pinctrl_dev *pctrldev,
359 			struct seq_file *s, unsigned selector)
360 {
361 }
362 
363 static const struct pinconf_ops falcon_pinconf_ops = {
364 	.pin_config_get			= falcon_pinconf_get,
365 	.pin_config_set			= falcon_pinconf_set,
366 	.pin_config_group_get		= falcon_pinconf_group_get,
367 	.pin_config_group_set		= falcon_pinconf_group_set,
368 	.pin_config_dbg_show		= falcon_pinconf_dbg_show,
369 	.pin_config_group_dbg_show	= falcon_pinconf_group_dbg_show,
370 };
371 
372 static struct pinctrl_desc falcon_pctrl_desc = {
373 	.owner		= THIS_MODULE,
374 	.pins		= falcon_pads,
375 	.confops	= &falcon_pinconf_ops,
376 };
377 
378 static inline int falcon_mux_apply(struct pinctrl_dev *pctrldev,
379 			int mfp, int mux)
380 {
381 	struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
382 	int port = PORT(info->mfp[mfp].pin);
383 
384 	if ((port >= PORTS) || (!info->membase[port]))
385 		return -ENODEV;
386 
387 	pad_w32(info->membase[port], mux,
388 		LTQ_PADC_MUX(PORT_PIN(info->mfp[mfp].pin)));
389 	return 0;
390 }
391 
392 static const struct ltq_cfg_param falcon_cfg_params[] = {
393 	{"lantiq,pull",			LTQ_PINCONF_PARAM_PULL},
394 	{"lantiq,drive-current",	LTQ_PINCONF_PARAM_DRIVE_CURRENT},
395 	{"lantiq,slew-rate",		LTQ_PINCONF_PARAM_SLEW_RATE},
396 };
397 
398 static struct ltq_pinmux_info falcon_info = {
399 	.desc		= &falcon_pctrl_desc,
400 	.apply_mux	= falcon_mux_apply,
401 	.params		= falcon_cfg_params,
402 	.num_params	= ARRAY_SIZE(falcon_cfg_params),
403 };
404 
405 
406 
407 
408 /* --------- register the pinctrl layer --------- */
409 
410 int pinctrl_falcon_get_range_size(int id)
411 {
412 	u32 avail;
413 
414 	if ((id >= PORTS) || (!falcon_info.membase[id]))
415 		return -EINVAL;
416 
417 	avail = pad_r32(falcon_info.membase[id], LTQ_PADC_AVAIL);
418 
419 	return fls(avail);
420 }
421 
422 void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range)
423 {
424 	pinctrl_add_gpio_range(falcon_info.pctrl, range);
425 }
426 
427 static int pinctrl_falcon_probe(struct platform_device *pdev)
428 {
429 	struct device_node *np;
430 	int pad_count = 0;
431 	int ret = 0;
432 
433 	/* load and remap the pad resources of the different banks */
434 	for_each_compatible_node(np, NULL, "lantiq,pad-falcon") {
435 		const __be32 *bank = of_get_property(np, "lantiq,bank", NULL);
436 		struct resource res;
437 		struct platform_device *ppdev;
438 		u32 avail;
439 		int pins;
440 
441 		if (!of_device_is_available(np))
442 			continue;
443 
444 		if (!bank || *bank >= PORTS)
445 			continue;
446 		if (of_address_to_resource(np, 0, &res))
447 			continue;
448 
449 		ppdev = of_find_device_by_node(np);
450 		if (!ppdev) {
451 			dev_err(&pdev->dev, "failed to find pad pdev\n");
452 			continue;
453 		}
454 
455 		falcon_info.clk[*bank] = clk_get(&ppdev->dev, NULL);
456 		put_device(&ppdev->dev);
457 		if (IS_ERR(falcon_info.clk[*bank])) {
458 			dev_err(&ppdev->dev, "failed to get clock\n");
459 			of_node_put(np);
460 			return PTR_ERR(falcon_info.clk[*bank]);
461 		}
462 		falcon_info.membase[*bank] = devm_ioremap_resource(&pdev->dev,
463 								   &res);
464 		if (IS_ERR(falcon_info.membase[*bank])) {
465 			of_node_put(np);
466 			return PTR_ERR(falcon_info.membase[*bank]);
467 		}
468 
469 		avail = pad_r32(falcon_info.membase[*bank],
470 					LTQ_PADC_AVAIL);
471 		pins = fls(avail);
472 		lantiq_load_pin_desc(&falcon_pads[pad_count], *bank, pins);
473 		pad_count += pins;
474 		clk_enable(falcon_info.clk[*bank]);
475 		dev_dbg(&pdev->dev, "found %s with %d pads\n",
476 				res.name, pins);
477 	}
478 	dev_dbg(&pdev->dev, "found a total of %d pads\n", pad_count);
479 	falcon_pctrl_desc.name	= dev_name(&pdev->dev);
480 	falcon_pctrl_desc.npins	= pad_count;
481 
482 	falcon_info.mfp		= falcon_mfp;
483 	falcon_info.num_mfp	= ARRAY_SIZE(falcon_mfp);
484 	falcon_info.grps	= falcon_grps;
485 	falcon_info.num_grps	= ARRAY_SIZE(falcon_grps);
486 	falcon_info.funcs	= falcon_funcs;
487 	falcon_info.num_funcs	= ARRAY_SIZE(falcon_funcs);
488 
489 	ret = ltq_pinctrl_register(pdev, &falcon_info);
490 	if (!ret)
491 		dev_info(&pdev->dev, "Init done\n");
492 	return ret;
493 }
494 
495 static const struct of_device_id falcon_match[] = {
496 	{ .compatible = "lantiq,pinctrl-falcon" },
497 	{},
498 };
499 MODULE_DEVICE_TABLE(of, falcon_match);
500 
501 static struct platform_driver pinctrl_falcon_driver = {
502 	.probe = pinctrl_falcon_probe,
503 	.driver = {
504 		.name = "pinctrl-falcon",
505 		.of_match_table = falcon_match,
506 	},
507 };
508 
509 int __init pinctrl_falcon_init(void)
510 {
511 	return platform_driver_register(&pinctrl_falcon_driver);
512 }
513 
514 core_initcall_sync(pinctrl_falcon_init);
515