1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/drivers/pinctrl/pinmux-falcon.c 4 * based on linux/drivers/pinctrl/pinmux-pxa910.c 5 * 6 * Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com> 7 * Copyright (C) 2012 John Crispin <john@phrozen.org> 8 */ 9 10 #include <linux/gpio/driver.h> 11 #include <linux/interrupt.h> 12 #include <linux/slab.h> 13 #include <linux/export.h> 14 #include <linux/err.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/of_platform.h> 18 #include <linux/of_address.h> 19 #include <linux/of_gpio.h> 20 #include <linux/platform_device.h> 21 22 #include "pinctrl-lantiq.h" 23 24 #include <lantiq_soc.h> 25 26 /* Multiplexer Control Register */ 27 #define LTQ_PADC_MUX(x) (x * 0x4) 28 /* Pull Up Enable Register */ 29 #define LTQ_PADC_PUEN 0x80 30 /* Pull Down Enable Register */ 31 #define LTQ_PADC_PDEN 0x84 32 /* Slew Rate Control Register */ 33 #define LTQ_PADC_SRC 0x88 34 /* Drive Current Control Register */ 35 #define LTQ_PADC_DCC 0x8C 36 /* Pad Control Availability Register */ 37 #define LTQ_PADC_AVAIL 0xF0 38 39 #define pad_r32(p, reg) ltq_r32(p + reg) 40 #define pad_w32(p, val, reg) ltq_w32(val, p + reg) 41 #define pad_w32_mask(c, clear, set, reg) \ 42 pad_w32(c, (pad_r32(c, reg) & ~(clear)) | (set), reg) 43 44 #define pad_getbit(m, r, p) (!!(ltq_r32(m + r) & (1 << p))) 45 46 #define PORTS 5 47 #define PINS 32 48 #define PORT(x) (x / PINS) 49 #define PORT_PIN(x) (x % PINS) 50 51 #define MFP_FALCON(a, f0, f1, f2, f3) \ 52 { \ 53 .name = #a, \ 54 .pin = a, \ 55 .func = { \ 56 FALCON_MUX_##f0, \ 57 FALCON_MUX_##f1, \ 58 FALCON_MUX_##f2, \ 59 FALCON_MUX_##f3, \ 60 }, \ 61 } 62 63 #define GRP_MUX(a, m, p) \ 64 { \ 65 .name = a, \ 66 .mux = FALCON_MUX_##m, \ 67 .pins = p, \ 68 .npins = ARRAY_SIZE(p), \ 69 } 70 71 enum falcon_mux { 72 FALCON_MUX_GPIO = 0, 73 FALCON_MUX_RST, 74 FALCON_MUX_NTR, 75 FALCON_MUX_PPS, 76 FALCON_MUX_MDIO, 77 FALCON_MUX_LED, 78 FALCON_MUX_SPI, 79 FALCON_MUX_ASC, 80 FALCON_MUX_I2C, 81 FALCON_MUX_HOSTIF, 82 FALCON_MUX_SLIC, 83 FALCON_MUX_JTAG, 84 FALCON_MUX_PCM, 85 FALCON_MUX_MII, 86 FALCON_MUX_PHY, 87 FALCON_MUX_NONE = 0xffff, 88 }; 89 90 static struct pinctrl_pin_desc falcon_pads[PORTS * PINS]; 91 static int pad_count[PORTS]; 92 93 static void lantiq_load_pin_desc(struct pinctrl_pin_desc *d, int bank, int len) 94 { 95 int base = bank * PINS; 96 int i; 97 98 for (i = 0; i < len; i++) { 99 /* strlen("ioXYZ") + 1 = 6 */ 100 char *name = kzalloc(6, GFP_KERNEL); 101 102 snprintf(name, 6, "io%d", base + i); 103 d[i].number = base + i; 104 d[i].name = name; 105 } 106 pad_count[bank] = len; 107 } 108 109 static struct ltq_mfp_pin falcon_mfp[] = { 110 /* pin f0 f1 f2 f3 */ 111 MFP_FALCON(GPIO0, RST, GPIO, NONE, NONE), 112 MFP_FALCON(GPIO1, GPIO, GPIO, NONE, NONE), 113 MFP_FALCON(GPIO2, GPIO, GPIO, NONE, NONE), 114 MFP_FALCON(GPIO3, GPIO, GPIO, NONE, NONE), 115 MFP_FALCON(GPIO4, NTR, GPIO, NONE, NONE), 116 MFP_FALCON(GPIO5, NTR, GPIO, PPS, NONE), 117 MFP_FALCON(GPIO6, RST, GPIO, NONE, NONE), 118 MFP_FALCON(GPIO7, MDIO, GPIO, NONE, NONE), 119 MFP_FALCON(GPIO8, MDIO, GPIO, NONE, NONE), 120 MFP_FALCON(GPIO9, LED, GPIO, NONE, NONE), 121 MFP_FALCON(GPIO10, LED, GPIO, NONE, NONE), 122 MFP_FALCON(GPIO11, LED, GPIO, NONE, NONE), 123 MFP_FALCON(GPIO12, LED, GPIO, NONE, NONE), 124 MFP_FALCON(GPIO13, LED, GPIO, NONE, NONE), 125 MFP_FALCON(GPIO14, LED, GPIO, NONE, NONE), 126 MFP_FALCON(GPIO32, ASC, GPIO, NONE, NONE), 127 MFP_FALCON(GPIO33, ASC, GPIO, NONE, NONE), 128 MFP_FALCON(GPIO34, SPI, GPIO, NONE, NONE), 129 MFP_FALCON(GPIO35, SPI, GPIO, NONE, NONE), 130 MFP_FALCON(GPIO36, SPI, GPIO, NONE, NONE), 131 MFP_FALCON(GPIO37, SPI, GPIO, NONE, NONE), 132 MFP_FALCON(GPIO38, SPI, GPIO, NONE, NONE), 133 MFP_FALCON(GPIO39, I2C, GPIO, NONE, NONE), 134 MFP_FALCON(GPIO40, I2C, GPIO, NONE, NONE), 135 MFP_FALCON(GPIO41, HOSTIF, GPIO, HOSTIF, JTAG), 136 MFP_FALCON(GPIO42, HOSTIF, GPIO, HOSTIF, NONE), 137 MFP_FALCON(GPIO43, SLIC, GPIO, NONE, NONE), 138 MFP_FALCON(GPIO44, SLIC, GPIO, PCM, ASC), 139 MFP_FALCON(GPIO45, SLIC, GPIO, PCM, ASC), 140 MFP_FALCON(GPIO64, MII, GPIO, NONE, NONE), 141 MFP_FALCON(GPIO65, MII, GPIO, NONE, NONE), 142 MFP_FALCON(GPIO66, MII, GPIO, NONE, NONE), 143 MFP_FALCON(GPIO67, MII, GPIO, NONE, NONE), 144 MFP_FALCON(GPIO68, MII, GPIO, NONE, NONE), 145 MFP_FALCON(GPIO69, MII, GPIO, NONE, NONE), 146 MFP_FALCON(GPIO70, MII, GPIO, NONE, NONE), 147 MFP_FALCON(GPIO71, MII, GPIO, NONE, NONE), 148 MFP_FALCON(GPIO72, MII, GPIO, NONE, NONE), 149 MFP_FALCON(GPIO73, MII, GPIO, NONE, NONE), 150 MFP_FALCON(GPIO74, MII, GPIO, NONE, NONE), 151 MFP_FALCON(GPIO75, MII, GPIO, NONE, NONE), 152 MFP_FALCON(GPIO76, MII, GPIO, NONE, NONE), 153 MFP_FALCON(GPIO77, MII, GPIO, NONE, NONE), 154 MFP_FALCON(GPIO78, MII, GPIO, NONE, NONE), 155 MFP_FALCON(GPIO79, MII, GPIO, NONE, NONE), 156 MFP_FALCON(GPIO80, MII, GPIO, NONE, NONE), 157 MFP_FALCON(GPIO81, MII, GPIO, NONE, NONE), 158 MFP_FALCON(GPIO82, MII, GPIO, NONE, NONE), 159 MFP_FALCON(GPIO83, MII, GPIO, NONE, NONE), 160 MFP_FALCON(GPIO84, MII, GPIO, NONE, NONE), 161 MFP_FALCON(GPIO85, MII, GPIO, NONE, NONE), 162 MFP_FALCON(GPIO86, MII, GPIO, NONE, NONE), 163 MFP_FALCON(GPIO87, MII, GPIO, NONE, NONE), 164 MFP_FALCON(GPIO88, PHY, GPIO, NONE, NONE), 165 }; 166 167 static const unsigned pins_por[] = {GPIO0}; 168 static const unsigned pins_ntr[] = {GPIO4}; 169 static const unsigned pins_ntr8k[] = {GPIO5}; 170 static const unsigned pins_pps[] = {GPIO5}; 171 static const unsigned pins_hrst[] = {GPIO6}; 172 static const unsigned pins_mdio[] = {GPIO7, GPIO8}; 173 static const unsigned pins_bled[] = {GPIO9, GPIO10, GPIO11, 174 GPIO12, GPIO13, GPIO14}; 175 static const unsigned pins_asc0[] = {GPIO32, GPIO33}; 176 static const unsigned pins_spi[] = {GPIO34, GPIO35, GPIO36}; 177 static const unsigned pins_spi_cs0[] = {GPIO37}; 178 static const unsigned pins_spi_cs1[] = {GPIO38}; 179 static const unsigned pins_i2c[] = {GPIO39, GPIO40}; 180 static const unsigned pins_jtag[] = {GPIO41}; 181 static const unsigned pins_slic[] = {GPIO43, GPIO44, GPIO45}; 182 static const unsigned pins_pcm[] = {GPIO44, GPIO45}; 183 static const unsigned pins_asc1[] = {GPIO44, GPIO45}; 184 185 static struct ltq_pin_group falcon_grps[] = { 186 GRP_MUX("por", RST, pins_por), 187 GRP_MUX("ntr", NTR, pins_ntr), 188 GRP_MUX("ntr8k", NTR, pins_ntr8k), 189 GRP_MUX("pps", PPS, pins_pps), 190 GRP_MUX("hrst", RST, pins_hrst), 191 GRP_MUX("mdio", MDIO, pins_mdio), 192 GRP_MUX("bootled", LED, pins_bled), 193 GRP_MUX("asc0", ASC, pins_asc0), 194 GRP_MUX("spi", SPI, pins_spi), 195 GRP_MUX("spi cs0", SPI, pins_spi_cs0), 196 GRP_MUX("spi cs1", SPI, pins_spi_cs1), 197 GRP_MUX("i2c", I2C, pins_i2c), 198 GRP_MUX("jtag", JTAG, pins_jtag), 199 GRP_MUX("slic", SLIC, pins_slic), 200 GRP_MUX("pcm", PCM, pins_pcm), 201 GRP_MUX("asc1", ASC, pins_asc1), 202 }; 203 204 static const char * const ltq_rst_grps[] = {"por", "hrst"}; 205 static const char * const ltq_ntr_grps[] = {"ntr", "ntr8k", "pps"}; 206 static const char * const ltq_mdio_grps[] = {"mdio"}; 207 static const char * const ltq_bled_grps[] = {"bootled"}; 208 static const char * const ltq_asc_grps[] = {"asc0", "asc1"}; 209 static const char * const ltq_spi_grps[] = {"spi", "spi cs0", "spi cs1"}; 210 static const char * const ltq_i2c_grps[] = {"i2c"}; 211 static const char * const ltq_jtag_grps[] = {"jtag"}; 212 static const char * const ltq_slic_grps[] = {"slic"}; 213 static const char * const ltq_pcm_grps[] = {"pcm"}; 214 215 static struct ltq_pmx_func falcon_funcs[] = { 216 {"rst", ARRAY_AND_SIZE(ltq_rst_grps)}, 217 {"ntr", ARRAY_AND_SIZE(ltq_ntr_grps)}, 218 {"mdio", ARRAY_AND_SIZE(ltq_mdio_grps)}, 219 {"led", ARRAY_AND_SIZE(ltq_bled_grps)}, 220 {"asc", ARRAY_AND_SIZE(ltq_asc_grps)}, 221 {"spi", ARRAY_AND_SIZE(ltq_spi_grps)}, 222 {"i2c", ARRAY_AND_SIZE(ltq_i2c_grps)}, 223 {"jtag", ARRAY_AND_SIZE(ltq_jtag_grps)}, 224 {"slic", ARRAY_AND_SIZE(ltq_slic_grps)}, 225 {"pcm", ARRAY_AND_SIZE(ltq_pcm_grps)}, 226 }; 227 228 229 230 231 /* --------- pinconf related code --------- */ 232 static int falcon_pinconf_group_get(struct pinctrl_dev *pctrldev, 233 unsigned group, unsigned long *config) 234 { 235 return -ENOTSUPP; 236 } 237 238 static int falcon_pinconf_group_set(struct pinctrl_dev *pctrldev, 239 unsigned group, unsigned long *configs, 240 unsigned num_configs) 241 { 242 return -ENOTSUPP; 243 } 244 245 static int falcon_pinconf_get(struct pinctrl_dev *pctrldev, 246 unsigned pin, unsigned long *config) 247 { 248 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); 249 enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(*config); 250 void __iomem *mem = info->membase[PORT(pin)]; 251 252 switch (param) { 253 case LTQ_PINCONF_PARAM_DRIVE_CURRENT: 254 *config = LTQ_PINCONF_PACK(param, 255 !!pad_getbit(mem, LTQ_PADC_DCC, PORT_PIN(pin))); 256 break; 257 258 case LTQ_PINCONF_PARAM_SLEW_RATE: 259 *config = LTQ_PINCONF_PACK(param, 260 !!pad_getbit(mem, LTQ_PADC_SRC, PORT_PIN(pin))); 261 break; 262 263 case LTQ_PINCONF_PARAM_PULL: 264 if (pad_getbit(mem, LTQ_PADC_PDEN, PORT_PIN(pin))) 265 *config = LTQ_PINCONF_PACK(param, 1); 266 else if (pad_getbit(mem, LTQ_PADC_PUEN, PORT_PIN(pin))) 267 *config = LTQ_PINCONF_PACK(param, 2); 268 else 269 *config = LTQ_PINCONF_PACK(param, 0); 270 271 break; 272 273 default: 274 return -ENOTSUPP; 275 } 276 277 return 0; 278 } 279 280 static int falcon_pinconf_set(struct pinctrl_dev *pctrldev, 281 unsigned pin, unsigned long *configs, 282 unsigned num_configs) 283 { 284 enum ltq_pinconf_param param; 285 int arg; 286 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); 287 void __iomem *mem = info->membase[PORT(pin)]; 288 u32 reg; 289 int i; 290 291 for (i = 0; i < num_configs; i++) { 292 param = LTQ_PINCONF_UNPACK_PARAM(configs[i]); 293 arg = LTQ_PINCONF_UNPACK_ARG(configs[i]); 294 295 switch (param) { 296 case LTQ_PINCONF_PARAM_DRIVE_CURRENT: 297 reg = LTQ_PADC_DCC; 298 break; 299 300 case LTQ_PINCONF_PARAM_SLEW_RATE: 301 reg = LTQ_PADC_SRC; 302 break; 303 304 case LTQ_PINCONF_PARAM_PULL: 305 if (arg == 1) 306 reg = LTQ_PADC_PDEN; 307 else 308 reg = LTQ_PADC_PUEN; 309 break; 310 311 default: 312 pr_err("%s: Invalid config param %04x\n", 313 pinctrl_dev_get_name(pctrldev), param); 314 return -ENOTSUPP; 315 } 316 317 pad_w32(mem, BIT(PORT_PIN(pin)), reg); 318 if (!(pad_r32(mem, reg) & BIT(PORT_PIN(pin)))) 319 return -ENOTSUPP; 320 } /* for each config */ 321 322 return 0; 323 } 324 325 static void falcon_pinconf_dbg_show(struct pinctrl_dev *pctrldev, 326 struct seq_file *s, unsigned offset) 327 { 328 unsigned long config; 329 struct pin_desc *desc; 330 331 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); 332 int port = PORT(offset); 333 334 seq_printf(s, " (port %d) mux %d -- ", port, 335 pad_r32(info->membase[port], LTQ_PADC_MUX(PORT_PIN(offset)))); 336 337 config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_PULL, 0); 338 if (!falcon_pinconf_get(pctrldev, offset, &config)) 339 seq_printf(s, "pull %d ", 340 (int)LTQ_PINCONF_UNPACK_ARG(config)); 341 342 config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_DRIVE_CURRENT, 0); 343 if (!falcon_pinconf_get(pctrldev, offset, &config)) 344 seq_printf(s, "drive-current %d ", 345 (int)LTQ_PINCONF_UNPACK_ARG(config)); 346 347 config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_SLEW_RATE, 0); 348 if (!falcon_pinconf_get(pctrldev, offset, &config)) 349 seq_printf(s, "slew-rate %d ", 350 (int)LTQ_PINCONF_UNPACK_ARG(config)); 351 352 desc = pin_desc_get(pctrldev, offset); 353 if (desc) { 354 if (desc->gpio_owner) 355 seq_printf(s, " owner: %s", desc->gpio_owner); 356 } else { 357 seq_printf(s, " not registered"); 358 } 359 } 360 361 static void falcon_pinconf_group_dbg_show(struct pinctrl_dev *pctrldev, 362 struct seq_file *s, unsigned selector) 363 { 364 } 365 366 static const struct pinconf_ops falcon_pinconf_ops = { 367 .pin_config_get = falcon_pinconf_get, 368 .pin_config_set = falcon_pinconf_set, 369 .pin_config_group_get = falcon_pinconf_group_get, 370 .pin_config_group_set = falcon_pinconf_group_set, 371 .pin_config_dbg_show = falcon_pinconf_dbg_show, 372 .pin_config_group_dbg_show = falcon_pinconf_group_dbg_show, 373 }; 374 375 static struct pinctrl_desc falcon_pctrl_desc = { 376 .owner = THIS_MODULE, 377 .pins = falcon_pads, 378 .confops = &falcon_pinconf_ops, 379 }; 380 381 static inline int falcon_mux_apply(struct pinctrl_dev *pctrldev, 382 int mfp, int mux) 383 { 384 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); 385 int port = PORT(info->mfp[mfp].pin); 386 387 if ((port >= PORTS) || (!info->membase[port])) 388 return -ENODEV; 389 390 pad_w32(info->membase[port], mux, 391 LTQ_PADC_MUX(PORT_PIN(info->mfp[mfp].pin))); 392 return 0; 393 } 394 395 static const struct ltq_cfg_param falcon_cfg_params[] = { 396 {"lantiq,pull", LTQ_PINCONF_PARAM_PULL}, 397 {"lantiq,drive-current", LTQ_PINCONF_PARAM_DRIVE_CURRENT}, 398 {"lantiq,slew-rate", LTQ_PINCONF_PARAM_SLEW_RATE}, 399 }; 400 401 static struct ltq_pinmux_info falcon_info = { 402 .desc = &falcon_pctrl_desc, 403 .apply_mux = falcon_mux_apply, 404 .params = falcon_cfg_params, 405 .num_params = ARRAY_SIZE(falcon_cfg_params), 406 }; 407 408 409 410 411 /* --------- register the pinctrl layer --------- */ 412 413 int pinctrl_falcon_get_range_size(int id) 414 { 415 u32 avail; 416 417 if ((id >= PORTS) || (!falcon_info.membase[id])) 418 return -EINVAL; 419 420 avail = pad_r32(falcon_info.membase[id], LTQ_PADC_AVAIL); 421 422 return fls(avail); 423 } 424 425 void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range) 426 { 427 pinctrl_add_gpio_range(falcon_info.pctrl, range); 428 } 429 430 static int pinctrl_falcon_probe(struct platform_device *pdev) 431 { 432 struct device_node *np; 433 int pad_count = 0; 434 int ret = 0; 435 436 /* load and remap the pad resources of the different banks */ 437 for_each_compatible_node(np, NULL, "lantiq,pad-falcon") { 438 struct platform_device *ppdev = of_find_device_by_node(np); 439 const __be32 *bank = of_get_property(np, "lantiq,bank", NULL); 440 struct resource res; 441 u32 avail; 442 int pins; 443 444 if (!of_device_is_available(np)) 445 continue; 446 447 if (!ppdev) { 448 dev_err(&pdev->dev, "failed to find pad pdev\n"); 449 continue; 450 } 451 if (!bank || *bank >= PORTS) 452 continue; 453 if (of_address_to_resource(np, 0, &res)) 454 continue; 455 falcon_info.clk[*bank] = clk_get(&ppdev->dev, NULL); 456 if (IS_ERR(falcon_info.clk[*bank])) { 457 dev_err(&ppdev->dev, "failed to get clock\n"); 458 return PTR_ERR(falcon_info.clk[*bank]); 459 } 460 falcon_info.membase[*bank] = devm_ioremap_resource(&pdev->dev, 461 &res); 462 if (IS_ERR(falcon_info.membase[*bank])) 463 return PTR_ERR(falcon_info.membase[*bank]); 464 465 avail = pad_r32(falcon_info.membase[*bank], 466 LTQ_PADC_AVAIL); 467 pins = fls(avail); 468 lantiq_load_pin_desc(&falcon_pads[pad_count], *bank, pins); 469 pad_count += pins; 470 clk_enable(falcon_info.clk[*bank]); 471 dev_dbg(&pdev->dev, "found %s with %d pads\n", 472 res.name, pins); 473 } 474 dev_dbg(&pdev->dev, "found a total of %d pads\n", pad_count); 475 falcon_pctrl_desc.name = dev_name(&pdev->dev); 476 falcon_pctrl_desc.npins = pad_count; 477 478 falcon_info.mfp = falcon_mfp; 479 falcon_info.num_mfp = ARRAY_SIZE(falcon_mfp); 480 falcon_info.grps = falcon_grps; 481 falcon_info.num_grps = ARRAY_SIZE(falcon_grps); 482 falcon_info.funcs = falcon_funcs; 483 falcon_info.num_funcs = ARRAY_SIZE(falcon_funcs); 484 485 ret = ltq_pinctrl_register(pdev, &falcon_info); 486 if (!ret) 487 dev_info(&pdev->dev, "Init done\n"); 488 return ret; 489 } 490 491 static const struct of_device_id falcon_match[] = { 492 { .compatible = "lantiq,pinctrl-falcon" }, 493 {}, 494 }; 495 MODULE_DEVICE_TABLE(of, falcon_match); 496 497 static struct platform_driver pinctrl_falcon_driver = { 498 .probe = pinctrl_falcon_probe, 499 .driver = { 500 .name = "pinctrl-falcon", 501 .of_match_table = falcon_match, 502 }, 503 }; 504 505 int __init pinctrl_falcon_init(void) 506 { 507 return platform_driver_register(&pinctrl_falcon_driver); 508 } 509 510 core_initcall_sync(pinctrl_falcon_init); 511