1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * CY8C95X0 20/40/60 pin I2C GPIO port expander with interrupt support
4  *
5  * Copyright (C) 2022 9elements GmbH
6  * Authors: Patrick Rudolph <patrick.rudolph@9elements.com>
7  *	    Naresh Solanki <Naresh.Solanki@9elements.com>
8  */
9 
10 #include <linux/acpi.h>
11 #include <linux/bitmap.h>
12 #include <linux/dmi.h>
13 #include <linux/gpio/driver.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/i2c.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/mod_devicetable.h>
19 #include <linux/module.h>
20 #include <linux/property.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/seq_file.h>
24 
25 #include <linux/pinctrl/consumer.h>
26 #include <linux/pinctrl/pinconf.h>
27 #include <linux/pinctrl/pinconf-generic.h>
28 #include <linux/pinctrl/pinctrl.h>
29 #include <linux/pinctrl/pinmux.h>
30 
31 /* Fast access registers */
32 #define CY8C95X0_INPUT		0x00
33 #define CY8C95X0_OUTPUT		0x08
34 #define CY8C95X0_INTSTATUS	0x10
35 
36 #define CY8C95X0_INPUT_(x)	(CY8C95X0_INPUT + (x))
37 #define CY8C95X0_OUTPUT_(x)	(CY8C95X0_OUTPUT + (x))
38 #define CY8C95X0_INTSTATUS_(x)	(CY8C95X0_INTSTATUS + (x))
39 
40 /* Port Select configures the port */
41 #define CY8C95X0_PORTSEL	0x18
42 /* Port settings, write PORTSEL first */
43 #define CY8C95X0_INTMASK	0x19
44 #define CY8C95X0_PWMSEL		0x1A
45 #define CY8C95X0_INVERT		0x1B
46 #define CY8C95X0_DIRECTION	0x1C
47 /* Drive mode register change state on writing '1' */
48 #define CY8C95X0_DRV_PU		0x1D
49 #define CY8C95X0_DRV_PD		0x1E
50 #define CY8C95X0_DRV_ODH	0x1F
51 #define CY8C95X0_DRV_ODL	0x20
52 #define CY8C95X0_DRV_PP_FAST	0x21
53 #define CY8C95X0_DRV_PP_SLOW	0x22
54 #define CY8C95X0_DRV_HIZ	0x23
55 #define CY8C95X0_DEVID		0x2E
56 #define CY8C95X0_WATCHDOG	0x2F
57 #define CY8C95X0_COMMAND	0x30
58 
59 #define CY8C95X0_PIN_TO_OFFSET(x) (((x) >= 20) ? ((x) + 4) : (x))
60 
61 static const struct i2c_device_id cy8c95x0_id[] = {
62 	{ "cy8c9520", 20, },
63 	{ "cy8c9540", 40, },
64 	{ "cy8c9560", 60, },
65 	{ }
66 };
67 MODULE_DEVICE_TABLE(i2c, cy8c95x0_id);
68 
69 #define OF_CY8C95X(__nrgpio) ((void *)(__nrgpio))
70 
71 static const struct of_device_id cy8c95x0_dt_ids[] = {
72 	{ .compatible = "cypress,cy8c9520", .data = OF_CY8C95X(20), },
73 	{ .compatible = "cypress,cy8c9540", .data = OF_CY8C95X(40), },
74 	{ .compatible = "cypress,cy8c9560", .data = OF_CY8C95X(60), },
75 	{ }
76 };
77 MODULE_DEVICE_TABLE(of, cy8c95x0_dt_ids);
78 
79 static const struct acpi_gpio_params cy8c95x0_irq_gpios = { 0, 0, true };
80 
81 static const struct acpi_gpio_mapping cy8c95x0_acpi_irq_gpios[] = {
82 	{ "irq-gpios", &cy8c95x0_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER },
83 	{ }
84 };
85 
86 static int cy8c95x0_acpi_get_irq(struct device *dev)
87 {
88 	int ret;
89 
90 	ret = devm_acpi_dev_add_driver_gpios(dev, cy8c95x0_acpi_irq_gpios);
91 	if (ret)
92 		dev_warn(dev, "can't add GPIO ACPI mapping\n");
93 
94 	ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq-gpios", 0);
95 	if (ret < 0)
96 		return ret;
97 
98 	dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret);
99 	return ret;
100 }
101 
102 static const struct dmi_system_id cy8c95x0_dmi_acpi_irq_info[] = {
103 	{
104 		/*
105 		 * On Intel Galileo Gen 1 board the IRQ pin is provided
106 		 * as an absolute number instead of being relative.
107 		 * Since first controller (gpio-sch.c) and second
108 		 * (gpio-dwapb.c) are at the fixed bases, we may safely
109 		 * refer to the number in the global space to get an IRQ
110 		 * out of it.
111 		 */
112 		.matches = {
113 			DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"),
114 		},
115 	},
116 	{}
117 };
118 
119 #define MAX_BANK 8
120 #define BANK_SZ 8
121 #define MAX_LINE	(MAX_BANK * BANK_SZ)
122 
123 #define CY8C95X0_GPIO_MASK		GENMASK(7, 0)
124 
125 /**
126  * struct cy8c95x0_pinctrl - driver data
127  * @regmap:         Device's regmap
128  * @irq_lock:       IRQ bus lock
129  * @i2c_lock:       Mutex for the device internal mux register
130  * @irq_mask:       I/O bits affected by interrupts
131  * @irq_trig_raise: I/O bits affected by raising voltage level
132  * @irq_trig_fall:  I/O bits affected by falling voltage level
133  * @irq_trig_low:   I/O bits affected by a low voltage level
134  * @irq_trig_high:  I/O bits affected by a high voltage level
135  * @push_pull:      I/O bits configured as push pull driver
136  * @shiftmask:      Mask used to compensate for Gport2 width
137  * @nport:          Number of Gports in this chip
138  * @gpio_chip:      gpiolib chip
139  * @driver_data:    private driver data
140  * @regulator:      Pointer to the regulator for the IC
141  * @dev:            struct device
142  * @pctldev:        pin controller device
143  * @pinctrl_desc:   pin controller description
144  * @name:           Chip controller name
145  * @tpin:           Total number of pins
146  */
147 struct cy8c95x0_pinctrl {
148 	struct regmap *regmap;
149 	struct mutex irq_lock;
150 	struct mutex i2c_lock;
151 	DECLARE_BITMAP(irq_mask, MAX_LINE);
152 	DECLARE_BITMAP(irq_trig_raise, MAX_LINE);
153 	DECLARE_BITMAP(irq_trig_fall, MAX_LINE);
154 	DECLARE_BITMAP(irq_trig_low, MAX_LINE);
155 	DECLARE_BITMAP(irq_trig_high, MAX_LINE);
156 	DECLARE_BITMAP(push_pull, MAX_LINE);
157 	DECLARE_BITMAP(shiftmask, MAX_LINE);
158 	int nport;
159 	struct gpio_chip gpio_chip;
160 	unsigned long driver_data;
161 	struct regulator *regulator;
162 	struct device *dev;
163 	struct pinctrl_dev *pctldev;
164 	struct pinctrl_desc pinctrl_desc;
165 	char name[32];
166 	unsigned int tpin;
167 	struct gpio_desc *gpio_reset;
168 };
169 
170 static const struct pinctrl_pin_desc cy8c9560_pins[] = {
171 	PINCTRL_PIN(0, "gp00"),
172 	PINCTRL_PIN(1, "gp01"),
173 	PINCTRL_PIN(2, "gp02"),
174 	PINCTRL_PIN(3, "gp03"),
175 	PINCTRL_PIN(4, "gp04"),
176 	PINCTRL_PIN(5, "gp05"),
177 	PINCTRL_PIN(6, "gp06"),
178 	PINCTRL_PIN(7, "gp07"),
179 
180 	PINCTRL_PIN(8, "gp10"),
181 	PINCTRL_PIN(9, "gp11"),
182 	PINCTRL_PIN(10, "gp12"),
183 	PINCTRL_PIN(11, "gp13"),
184 	PINCTRL_PIN(12, "gp14"),
185 	PINCTRL_PIN(13, "gp15"),
186 	PINCTRL_PIN(14, "gp16"),
187 	PINCTRL_PIN(15, "gp17"),
188 
189 	PINCTRL_PIN(16, "gp20"),
190 	PINCTRL_PIN(17, "gp21"),
191 	PINCTRL_PIN(18, "gp22"),
192 	PINCTRL_PIN(19, "gp23"),
193 
194 	PINCTRL_PIN(20, "gp30"),
195 	PINCTRL_PIN(21, "gp31"),
196 	PINCTRL_PIN(22, "gp32"),
197 	PINCTRL_PIN(23, "gp33"),
198 	PINCTRL_PIN(24, "gp34"),
199 	PINCTRL_PIN(25, "gp35"),
200 	PINCTRL_PIN(26, "gp36"),
201 	PINCTRL_PIN(27, "gp37"),
202 
203 	PINCTRL_PIN(28, "gp40"),
204 	PINCTRL_PIN(29, "gp41"),
205 	PINCTRL_PIN(30, "gp42"),
206 	PINCTRL_PIN(31, "gp43"),
207 	PINCTRL_PIN(32, "gp44"),
208 	PINCTRL_PIN(33, "gp45"),
209 	PINCTRL_PIN(34, "gp46"),
210 	PINCTRL_PIN(35, "gp47"),
211 
212 	PINCTRL_PIN(36, "gp50"),
213 	PINCTRL_PIN(37, "gp51"),
214 	PINCTRL_PIN(38, "gp52"),
215 	PINCTRL_PIN(39, "gp53"),
216 	PINCTRL_PIN(40, "gp54"),
217 	PINCTRL_PIN(41, "gp55"),
218 	PINCTRL_PIN(42, "gp56"),
219 	PINCTRL_PIN(43, "gp57"),
220 
221 	PINCTRL_PIN(44, "gp60"),
222 	PINCTRL_PIN(45, "gp61"),
223 	PINCTRL_PIN(46, "gp62"),
224 	PINCTRL_PIN(47, "gp63"),
225 	PINCTRL_PIN(48, "gp64"),
226 	PINCTRL_PIN(49, "gp65"),
227 	PINCTRL_PIN(50, "gp66"),
228 	PINCTRL_PIN(51, "gp67"),
229 
230 	PINCTRL_PIN(52, "gp70"),
231 	PINCTRL_PIN(53, "gp71"),
232 	PINCTRL_PIN(54, "gp72"),
233 	PINCTRL_PIN(55, "gp73"),
234 	PINCTRL_PIN(56, "gp74"),
235 	PINCTRL_PIN(57, "gp75"),
236 	PINCTRL_PIN(58, "gp76"),
237 	PINCTRL_PIN(59, "gp77"),
238 };
239 
240 static const char * const cy8c95x0_groups[] = {
241 	"gp00",
242 	"gp01",
243 	"gp02",
244 	"gp03",
245 	"gp04",
246 	"gp05",
247 	"gp06",
248 	"gp07",
249 
250 	"gp10",
251 	"gp11",
252 	"gp12",
253 	"gp13",
254 	"gp14",
255 	"gp15",
256 	"gp16",
257 	"gp17",
258 
259 	"gp20",
260 	"gp21",
261 	"gp22",
262 	"gp23",
263 
264 	"gp30",
265 	"gp31",
266 	"gp32",
267 	"gp33",
268 	"gp34",
269 	"gp35",
270 	"gp36",
271 	"gp37",
272 
273 	"gp40",
274 	"gp41",
275 	"gp42",
276 	"gp43",
277 	"gp44",
278 	"gp45",
279 	"gp46",
280 	"gp47",
281 
282 	"gp50",
283 	"gp51",
284 	"gp52",
285 	"gp53",
286 	"gp54",
287 	"gp55",
288 	"gp56",
289 	"gp57",
290 
291 	"gp60",
292 	"gp61",
293 	"gp62",
294 	"gp63",
295 	"gp64",
296 	"gp65",
297 	"gp66",
298 	"gp67",
299 
300 	"gp70",
301 	"gp71",
302 	"gp72",
303 	"gp73",
304 	"gp74",
305 	"gp75",
306 	"gp76",
307 	"gp77",
308 };
309 
310 static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip,
311 				     unsigned int pin, bool input);
312 
313 static inline u8 cypress_get_port(struct cy8c95x0_pinctrl *chip, unsigned int pin)
314 {
315 	/* Account for GPORT2 which only has 4 bits */
316 	return CY8C95X0_PIN_TO_OFFSET(pin) / BANK_SZ;
317 }
318 
319 static int cypress_get_pin_mask(struct cy8c95x0_pinctrl *chip, unsigned int pin)
320 {
321 	/* Account for GPORT2 which only has 4 bits */
322 	return BIT(CY8C95X0_PIN_TO_OFFSET(pin) % BANK_SZ);
323 }
324 
325 static bool cy8c95x0_readable_register(struct device *dev, unsigned int reg)
326 {
327 	switch (reg) {
328 	case 0x24 ... 0x27:
329 		return false;
330 	default:
331 		return true;
332 	}
333 }
334 
335 static bool cy8c95x0_writeable_register(struct device *dev, unsigned int reg)
336 {
337 	switch (reg) {
338 	case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):
339 		return false;
340 	case CY8C95X0_DEVID:
341 		return false;
342 	case 0x24 ... 0x27:
343 		return false;
344 	default:
345 		return true;
346 	}
347 }
348 
349 static bool cy8c95x0_volatile_register(struct device *dev, unsigned int reg)
350 {
351 	switch (reg) {
352 	case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):
353 	case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7):
354 	case CY8C95X0_INTMASK:
355 	case CY8C95X0_INVERT:
356 	case CY8C95X0_PWMSEL:
357 	case CY8C95X0_DIRECTION:
358 	case CY8C95X0_DRV_PU:
359 	case CY8C95X0_DRV_PD:
360 	case CY8C95X0_DRV_ODH:
361 	case CY8C95X0_DRV_ODL:
362 	case CY8C95X0_DRV_PP_FAST:
363 	case CY8C95X0_DRV_PP_SLOW:
364 	case CY8C95X0_DRV_HIZ:
365 		return true;
366 	default:
367 		return false;
368 	}
369 }
370 
371 static bool cy8c95x0_precious_register(struct device *dev, unsigned int reg)
372 {
373 	switch (reg) {
374 	case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7):
375 		return true;
376 	default:
377 		return false;
378 	}
379 }
380 
381 static const struct reg_default cy8c95x0_reg_defaults[] = {
382 	{ CY8C95X0_OUTPUT_(0), GENMASK(7, 0) },
383 	{ CY8C95X0_OUTPUT_(1), GENMASK(7, 0) },
384 	{ CY8C95X0_OUTPUT_(2), GENMASK(7, 0) },
385 	{ CY8C95X0_OUTPUT_(3), GENMASK(7, 0) },
386 	{ CY8C95X0_OUTPUT_(4), GENMASK(7, 0) },
387 	{ CY8C95X0_OUTPUT_(5), GENMASK(7, 0) },
388 	{ CY8C95X0_OUTPUT_(6), GENMASK(7, 0) },
389 	{ CY8C95X0_OUTPUT_(7), GENMASK(7, 0) },
390 	{ CY8C95X0_PORTSEL, 0 },
391 	{ CY8C95X0_PWMSEL, 0 },
392 };
393 
394 static const struct regmap_config cy8c95x0_i2c_regmap = {
395 	.reg_bits = 8,
396 	.val_bits = 8,
397 
398 	.reg_defaults = cy8c95x0_reg_defaults,
399 	.num_reg_defaults = ARRAY_SIZE(cy8c95x0_reg_defaults),
400 
401 	.readable_reg = cy8c95x0_readable_register,
402 	.writeable_reg = cy8c95x0_writeable_register,
403 	.volatile_reg = cy8c95x0_volatile_register,
404 	.precious_reg = cy8c95x0_precious_register,
405 
406 	.cache_type = REGCACHE_FLAT,
407 	.max_register = CY8C95X0_COMMAND,
408 };
409 
410 static int cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl *chip, int reg,
411 				    unsigned long *val, unsigned long *mask)
412 {
413 	DECLARE_BITMAP(tmask, MAX_LINE);
414 	DECLARE_BITMAP(tval, MAX_LINE);
415 	int write_val;
416 	int ret = 0;
417 	int i, off = 0;
418 	u8 bits;
419 
420 	/* Add the 4 bit gap of Gport2 */
421 	bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE);
422 	bitmap_shift_left(tmask, tmask, 4, MAX_LINE);
423 	bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3);
424 
425 	bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE);
426 	bitmap_shift_left(tval, tval, 4, MAX_LINE);
427 	bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3);
428 
429 	mutex_lock(&chip->i2c_lock);
430 	for (i = 0; i < chip->nport; i++) {
431 		/* Skip over unused banks */
432 		bits = bitmap_get_value8(tmask, i * BANK_SZ);
433 		if (!bits)
434 			continue;
435 
436 		switch (reg) {
437 		/* Muxed registers */
438 		case CY8C95X0_INTMASK:
439 		case CY8C95X0_PWMSEL:
440 		case CY8C95X0_INVERT:
441 		case CY8C95X0_DIRECTION:
442 		case CY8C95X0_DRV_PU:
443 		case CY8C95X0_DRV_PD:
444 		case CY8C95X0_DRV_ODH:
445 		case CY8C95X0_DRV_ODL:
446 		case CY8C95X0_DRV_PP_FAST:
447 		case CY8C95X0_DRV_PP_SLOW:
448 		case CY8C95X0_DRV_HIZ:
449 			ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, i);
450 			if (ret < 0)
451 				goto out;
452 			off = reg;
453 			break;
454 		/* Direct access registers */
455 		case CY8C95X0_INPUT:
456 		case CY8C95X0_OUTPUT:
457 		case CY8C95X0_INTSTATUS:
458 			off = reg + i;
459 			break;
460 		default:
461 			ret = -EINVAL;
462 			goto out;
463 		}
464 
465 		write_val = bitmap_get_value8(tval, i * BANK_SZ);
466 
467 		ret = regmap_update_bits(chip->regmap, off, bits, write_val);
468 		if (ret < 0)
469 			goto out;
470 	}
471 out:
472 	mutex_unlock(&chip->i2c_lock);
473 
474 	if (ret < 0)
475 		dev_err(chip->dev, "failed writing register %d: err %d\n", off, ret);
476 
477 	return ret;
478 }
479 
480 static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg,
481 				   unsigned long *val, unsigned long *mask)
482 {
483 	DECLARE_BITMAP(tmask, MAX_LINE);
484 	DECLARE_BITMAP(tval, MAX_LINE);
485 	DECLARE_BITMAP(tmp, MAX_LINE);
486 	int read_val;
487 	int ret = 0;
488 	int i, off = 0;
489 	u8 bits;
490 
491 	/* Add the 4 bit gap of Gport2 */
492 	bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE);
493 	bitmap_shift_left(tmask, tmask, 4, MAX_LINE);
494 	bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3);
495 
496 	bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE);
497 	bitmap_shift_left(tval, tval, 4, MAX_LINE);
498 	bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3);
499 
500 	mutex_lock(&chip->i2c_lock);
501 	for (i = 0; i < chip->nport; i++) {
502 		/* Skip over unused banks */
503 		bits = bitmap_get_value8(tmask, i * BANK_SZ);
504 		if (!bits)
505 			continue;
506 
507 		switch (reg) {
508 		/* Muxed registers */
509 		case CY8C95X0_INTMASK:
510 		case CY8C95X0_PWMSEL:
511 		case CY8C95X0_INVERT:
512 		case CY8C95X0_DIRECTION:
513 		case CY8C95X0_DRV_PU:
514 		case CY8C95X0_DRV_PD:
515 		case CY8C95X0_DRV_ODH:
516 		case CY8C95X0_DRV_ODL:
517 		case CY8C95X0_DRV_PP_FAST:
518 		case CY8C95X0_DRV_PP_SLOW:
519 		case CY8C95X0_DRV_HIZ:
520 			ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, i);
521 			if (ret < 0)
522 				goto out;
523 			off = reg;
524 			break;
525 		/* Direct access registers */
526 		case CY8C95X0_INPUT:
527 		case CY8C95X0_OUTPUT:
528 		case CY8C95X0_INTSTATUS:
529 			off = reg + i;
530 			break;
531 		default:
532 			ret = -EINVAL;
533 			goto out;
534 		}
535 
536 		ret = regmap_read(chip->regmap, off, &read_val);
537 		if (ret < 0)
538 			goto out;
539 
540 		read_val &= bits;
541 		read_val |= bitmap_get_value8(tval, i * BANK_SZ) & ~bits;
542 		bitmap_set_value8(tval, read_val, i * BANK_SZ);
543 	}
544 
545 	/* Fill the 4 bit gap of Gport2 */
546 	bitmap_shift_right(tmp, tval, 4, MAX_LINE);
547 	bitmap_replace(val, tmp, tval, chip->shiftmask, MAX_LINE);
548 
549 out:
550 	mutex_unlock(&chip->i2c_lock);
551 
552 	if (ret < 0)
553 		dev_err(chip->dev, "failed reading register %d: err %d\n", off, ret);
554 
555 	return ret;
556 }
557 
558 static int cy8c95x0_gpio_direction_input(struct gpio_chip *gc, unsigned int off)
559 {
560 	return pinctrl_gpio_direction_input(gc->base + off);
561 }
562 
563 static int cy8c95x0_gpio_direction_output(struct gpio_chip *gc,
564 					  unsigned int off, int val)
565 {
566 	struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
567 	u8 port = cypress_get_port(chip, off);
568 	u8 outreg = CY8C95X0_OUTPUT_(port);
569 	u8 bit = cypress_get_pin_mask(chip, off);
570 	int ret;
571 
572 	/* Set output level */
573 	ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
574 	if (ret)
575 		return ret;
576 
577 	return pinctrl_gpio_direction_output(gc->base + off);
578 }
579 
580 static int cy8c95x0_gpio_get_value(struct gpio_chip *gc, unsigned int off)
581 {
582 	struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
583 	u8 inreg = CY8C95X0_INPUT_(cypress_get_port(chip, off));
584 	u8 bit = cypress_get_pin_mask(chip, off);
585 	u32 reg_val;
586 	int ret;
587 
588 	ret = regmap_read(chip->regmap, inreg, &reg_val);
589 	if (ret < 0) {
590 		/*
591 		 * NOTE:
592 		 * Diagnostic already emitted; that's all we should
593 		 * do unless gpio_*_value_cansleep() calls become different
594 		 * from their nonsleeping siblings (and report faults).
595 		 */
596 		return 0;
597 	}
598 
599 	return !!(reg_val & bit);
600 }
601 
602 static void cy8c95x0_gpio_set_value(struct gpio_chip *gc, unsigned int off,
603 				    int val)
604 {
605 	struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
606 	u8 outreg = CY8C95X0_OUTPUT_(cypress_get_port(chip, off));
607 	u8 bit = cypress_get_pin_mask(chip, off);
608 
609 	regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
610 }
611 
612 static int cy8c95x0_gpio_get_direction(struct gpio_chip *gc, unsigned int off)
613 {
614 	struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
615 	u8 port = cypress_get_port(chip, off);
616 	u8 bit = cypress_get_pin_mask(chip, off);
617 	u32 reg_val;
618 	int ret;
619 
620 	mutex_lock(&chip->i2c_lock);
621 
622 	ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
623 	if (ret < 0)
624 		goto out;
625 
626 	ret = regmap_read(chip->regmap, CY8C95X0_DIRECTION, &reg_val);
627 	if (ret < 0)
628 		goto out;
629 
630 	mutex_unlock(&chip->i2c_lock);
631 
632 	if (reg_val & bit)
633 		return GPIO_LINE_DIRECTION_IN;
634 
635 	return GPIO_LINE_DIRECTION_OUT;
636 out:
637 	mutex_unlock(&chip->i2c_lock);
638 	return ret;
639 }
640 
641 static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip,
642 				    unsigned int off,
643 				    unsigned long *config)
644 {
645 	enum pin_config_param param = pinconf_to_config_param(*config);
646 	u8 port = cypress_get_port(chip, off);
647 	u8 bit = cypress_get_pin_mask(chip, off);
648 	unsigned int reg;
649 	u32 reg_val;
650 	u16 arg = 0;
651 	int ret;
652 
653 	mutex_lock(&chip->i2c_lock);
654 
655 	/* Select port */
656 	ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
657 	if (ret < 0)
658 		goto out;
659 
660 	switch (param) {
661 	case PIN_CONFIG_BIAS_PULL_UP:
662 		reg = CY8C95X0_DRV_PU;
663 		break;
664 	case PIN_CONFIG_BIAS_PULL_DOWN:
665 		reg = CY8C95X0_DRV_PD;
666 		break;
667 	case PIN_CONFIG_BIAS_DISABLE:
668 		reg = CY8C95X0_DRV_HIZ;
669 		break;
670 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
671 		reg = CY8C95X0_DRV_ODL;
672 		break;
673 	case PIN_CONFIG_DRIVE_OPEN_SOURCE:
674 		reg = CY8C95X0_DRV_ODH;
675 		break;
676 	case PIN_CONFIG_DRIVE_PUSH_PULL:
677 		reg = CY8C95X0_DRV_PP_FAST;
678 		break;
679 	case PIN_CONFIG_INPUT_ENABLE:
680 		reg = CY8C95X0_DIRECTION;
681 		break;
682 	case PIN_CONFIG_MODE_PWM:
683 		reg = CY8C95X0_PWMSEL;
684 		break;
685 	case PIN_CONFIG_OUTPUT:
686 		reg = CY8C95X0_OUTPUT_(port);
687 		break;
688 	case PIN_CONFIG_OUTPUT_ENABLE:
689 		reg = CY8C95X0_DIRECTION;
690 		break;
691 
692 	case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
693 	case PIN_CONFIG_BIAS_BUS_HOLD:
694 	case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
695 	case PIN_CONFIG_DRIVE_STRENGTH:
696 	case PIN_CONFIG_DRIVE_STRENGTH_UA:
697 	case PIN_CONFIG_INPUT_DEBOUNCE:
698 	case PIN_CONFIG_INPUT_SCHMITT:
699 	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
700 	case PIN_CONFIG_MODE_LOW_POWER:
701 	case PIN_CONFIG_PERSIST_STATE:
702 	case PIN_CONFIG_POWER_SOURCE:
703 	case PIN_CONFIG_SKEW_DELAY:
704 	case PIN_CONFIG_SLEEP_HARDWARE_STATE:
705 	case PIN_CONFIG_SLEW_RATE:
706 	default:
707 		ret = -ENOTSUPP;
708 		goto out;
709 	}
710 	/*
711 	 * Writing 1 to one of the drive mode registers will automatically
712 	 * clear conflicting set bits in the other drive mode registers.
713 	 */
714 	ret = regmap_read(chip->regmap, reg, &reg_val);
715 	if (reg_val & bit)
716 		arg = 1;
717 	if (param == PIN_CONFIG_OUTPUT_ENABLE)
718 		arg = !arg;
719 
720 	*config = pinconf_to_config_packed(param, (u16)arg);
721 out:
722 	mutex_unlock(&chip->i2c_lock);
723 
724 	return ret;
725 }
726 
727 static int cy8c95x0_gpio_set_pincfg(struct cy8c95x0_pinctrl *chip,
728 				    unsigned int off,
729 				    unsigned long config)
730 {
731 	u8 port = cypress_get_port(chip, off);
732 	u8 bit = cypress_get_pin_mask(chip, off);
733 	unsigned long param = pinconf_to_config_param(config);
734 	unsigned long arg = pinconf_to_config_argument(config);
735 	unsigned int reg;
736 	int ret;
737 
738 	mutex_lock(&chip->i2c_lock);
739 
740 	/* Select port */
741 	ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
742 	if (ret < 0)
743 		goto out;
744 
745 	switch (param) {
746 	case PIN_CONFIG_BIAS_PULL_UP:
747 		__clear_bit(off, chip->push_pull);
748 		reg = CY8C95X0_DRV_PU;
749 		break;
750 	case PIN_CONFIG_BIAS_PULL_DOWN:
751 		__clear_bit(off, chip->push_pull);
752 		reg = CY8C95X0_DRV_PD;
753 		break;
754 	case PIN_CONFIG_BIAS_DISABLE:
755 		__clear_bit(off, chip->push_pull);
756 		reg = CY8C95X0_DRV_HIZ;
757 		break;
758 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
759 		__clear_bit(off, chip->push_pull);
760 		reg = CY8C95X0_DRV_ODL;
761 		break;
762 	case PIN_CONFIG_DRIVE_OPEN_SOURCE:
763 		__clear_bit(off, chip->push_pull);
764 		reg = CY8C95X0_DRV_ODH;
765 		break;
766 	case PIN_CONFIG_DRIVE_PUSH_PULL:
767 		__set_bit(off, chip->push_pull);
768 		reg = CY8C95X0_DRV_PP_FAST;
769 		break;
770 	case PIN_CONFIG_MODE_PWM:
771 		reg = CY8C95X0_PWMSEL;
772 		break;
773 	case PIN_CONFIG_OUTPUT_ENABLE:
774 		ret = cy8c95x0_pinmux_direction(chip, off, !arg);
775 		goto out;
776 	case PIN_CONFIG_INPUT_ENABLE:
777 		ret = cy8c95x0_pinmux_direction(chip, off, arg);
778 		goto out;
779 	default:
780 		ret = -ENOTSUPP;
781 		goto out;
782 	}
783 	/*
784 	 * Writing 1 to one of the drive mode registers will automatically
785 	 * clear conflicting set bits in the other drive mode registers.
786 	 */
787 	ret = regmap_write_bits(chip->regmap, reg, bit, bit);
788 
789 out:
790 	mutex_unlock(&chip->i2c_lock);
791 	return ret;
792 }
793 
794 static int cy8c95x0_gpio_get_multiple(struct gpio_chip *gc,
795 				      unsigned long *mask, unsigned long *bits)
796 {
797 	struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
798 
799 	return cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, bits, mask);
800 }
801 
802 static void cy8c95x0_gpio_set_multiple(struct gpio_chip *gc,
803 				       unsigned long *mask, unsigned long *bits)
804 {
805 	struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
806 
807 	cy8c95x0_write_regs_mask(chip, CY8C95X0_OUTPUT, bits, mask);
808 }
809 
810 static int cy8c95x0_add_pin_ranges(struct gpio_chip *gc)
811 {
812 	struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
813 	struct device *dev = chip->dev;
814 	int ret;
815 
816 	ret = gpiochip_add_pin_range(gc, dev_name(dev), 0, 0, chip->tpin);
817 	if (ret)
818 		dev_err(dev, "failed to add GPIO pin range\n");
819 
820 	return ret;
821 }
822 
823 static int cy8c95x0_setup_gpiochip(struct cy8c95x0_pinctrl *chip)
824 {
825 	struct gpio_chip *gc = &chip->gpio_chip;
826 
827 	gc->request = gpiochip_generic_request;
828 	gc->free = gpiochip_generic_free;
829 	gc->direction_input  = cy8c95x0_gpio_direction_input;
830 	gc->direction_output = cy8c95x0_gpio_direction_output;
831 	gc->get = cy8c95x0_gpio_get_value;
832 	gc->set = cy8c95x0_gpio_set_value;
833 	gc->get_direction = cy8c95x0_gpio_get_direction;
834 	gc->get_multiple = cy8c95x0_gpio_get_multiple;
835 	gc->set_multiple = cy8c95x0_gpio_set_multiple;
836 	gc->set_config = gpiochip_generic_config;
837 	gc->can_sleep = true;
838 	gc->add_pin_ranges = cy8c95x0_add_pin_ranges;
839 
840 	gc->base = -1;
841 	gc->ngpio = chip->tpin;
842 
843 	gc->parent = chip->dev;
844 	gc->owner = THIS_MODULE;
845 	gc->names = NULL;
846 
847 	gc->label = dev_name(chip->dev);
848 
849 	return devm_gpiochip_add_data(chip->dev, gc, chip);
850 }
851 
852 static void cy8c95x0_irq_mask(struct irq_data *d)
853 {
854 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
855 	struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
856 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
857 
858 	set_bit(hwirq, chip->irq_mask);
859 	gpiochip_disable_irq(gc, hwirq);
860 }
861 
862 static void cy8c95x0_irq_unmask(struct irq_data *d)
863 {
864 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
865 	struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
866 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
867 
868 	gpiochip_enable_irq(gc, hwirq);
869 	clear_bit(hwirq, chip->irq_mask);
870 }
871 
872 static void cy8c95x0_irq_bus_lock(struct irq_data *d)
873 {
874 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
875 	struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
876 
877 	mutex_lock(&chip->irq_lock);
878 }
879 
880 static void cy8c95x0_irq_bus_sync_unlock(struct irq_data *d)
881 {
882 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
883 	struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
884 	DECLARE_BITMAP(ones, MAX_LINE);
885 	DECLARE_BITMAP(irq_mask, MAX_LINE);
886 	DECLARE_BITMAP(reg_direction, MAX_LINE);
887 
888 	bitmap_fill(ones, MAX_LINE);
889 
890 	cy8c95x0_write_regs_mask(chip, CY8C95X0_INTMASK, chip->irq_mask, ones);
891 
892 	/* Switch direction to input if needed */
893 	cy8c95x0_read_regs_mask(chip, CY8C95X0_DIRECTION, reg_direction, chip->irq_mask);
894 	bitmap_or(irq_mask, chip->irq_mask, reg_direction, MAX_LINE);
895 	bitmap_complement(irq_mask, irq_mask, MAX_LINE);
896 
897 	/* Look for any newly setup interrupt */
898 	cy8c95x0_write_regs_mask(chip, CY8C95X0_DIRECTION, ones, irq_mask);
899 
900 	mutex_unlock(&chip->irq_lock);
901 }
902 
903 static int cy8c95x0_irq_set_type(struct irq_data *d, unsigned int type)
904 {
905 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
906 	struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
907 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
908 	unsigned int trig_type;
909 
910 	switch (type) {
911 	case IRQ_TYPE_EDGE_RISING:
912 	case IRQ_TYPE_EDGE_FALLING:
913 	case IRQ_TYPE_EDGE_BOTH:
914 		trig_type = type;
915 		break;
916 	case IRQ_TYPE_LEVEL_HIGH:
917 		trig_type = IRQ_TYPE_EDGE_RISING;
918 		break;
919 	case IRQ_TYPE_LEVEL_LOW:
920 		trig_type = IRQ_TYPE_EDGE_FALLING;
921 		break;
922 	default:
923 		dev_err(chip->dev, "irq %d: unsupported type %d\n", d->irq, type);
924 		return -EINVAL;
925 	}
926 
927 	assign_bit(hwirq, chip->irq_trig_fall, trig_type & IRQ_TYPE_EDGE_FALLING);
928 	assign_bit(hwirq, chip->irq_trig_raise, trig_type & IRQ_TYPE_EDGE_RISING);
929 	assign_bit(hwirq, chip->irq_trig_low, type == IRQ_TYPE_LEVEL_LOW);
930 	assign_bit(hwirq, chip->irq_trig_high, type == IRQ_TYPE_LEVEL_HIGH);
931 
932 	return 0;
933 }
934 
935 static void cy8c95x0_irq_shutdown(struct irq_data *d)
936 {
937 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
938 	struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
939 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
940 
941 	clear_bit(hwirq, chip->irq_trig_raise);
942 	clear_bit(hwirq, chip->irq_trig_fall);
943 	clear_bit(hwirq, chip->irq_trig_low);
944 	clear_bit(hwirq, chip->irq_trig_high);
945 }
946 
947 static const struct irq_chip cy8c95x0_irqchip = {
948 	.name = "cy8c95x0-irq",
949 	.irq_mask = cy8c95x0_irq_mask,
950 	.irq_unmask = cy8c95x0_irq_unmask,
951 	.irq_bus_lock = cy8c95x0_irq_bus_lock,
952 	.irq_bus_sync_unlock = cy8c95x0_irq_bus_sync_unlock,
953 	.irq_set_type = cy8c95x0_irq_set_type,
954 	.irq_shutdown = cy8c95x0_irq_shutdown,
955 	.flags = IRQCHIP_IMMUTABLE,
956 	GPIOCHIP_IRQ_RESOURCE_HELPERS,
957 };
958 
959 static bool cy8c95x0_irq_pending(struct cy8c95x0_pinctrl *chip, unsigned long *pending)
960 {
961 	DECLARE_BITMAP(ones, MAX_LINE);
962 	DECLARE_BITMAP(cur_stat, MAX_LINE);
963 	DECLARE_BITMAP(new_stat, MAX_LINE);
964 	DECLARE_BITMAP(trigger, MAX_LINE);
965 
966 	bitmap_fill(ones, MAX_LINE);
967 
968 	/* Read the current interrupt status from the device */
969 	if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INTSTATUS, trigger, ones))
970 		return false;
971 
972 	/* Check latched inputs */
973 	if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, cur_stat, trigger))
974 		return false;
975 
976 	/* Apply filter for rising/falling edge selection */
977 	bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise,
978 		       cur_stat, MAX_LINE);
979 
980 	bitmap_and(pending, new_stat, trigger, MAX_LINE);
981 
982 	return !bitmap_empty(pending, MAX_LINE);
983 }
984 
985 static irqreturn_t cy8c95x0_irq_handler(int irq, void *devid)
986 {
987 	struct cy8c95x0_pinctrl *chip = devid;
988 	struct gpio_chip *gc = &chip->gpio_chip;
989 	DECLARE_BITMAP(pending, MAX_LINE);
990 	int nested_irq, level;
991 	bool ret;
992 
993 	ret = cy8c95x0_irq_pending(chip, pending);
994 	if (!ret)
995 		return IRQ_RETVAL(0);
996 
997 	ret = 0;
998 	for_each_set_bit(level, pending, MAX_LINE) {
999 		/* Already accounted for 4bit gap in GPort2 */
1000 		nested_irq = irq_find_mapping(gc->irq.domain, level);
1001 
1002 		if (unlikely(nested_irq <= 0)) {
1003 			dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level);
1004 			continue;
1005 		}
1006 
1007 		if (test_bit(level, chip->irq_trig_low))
1008 			while (!cy8c95x0_gpio_get_value(gc, level))
1009 				handle_nested_irq(nested_irq);
1010 		else if (test_bit(level, chip->irq_trig_high))
1011 			while (cy8c95x0_gpio_get_value(gc, level))
1012 				handle_nested_irq(nested_irq);
1013 		else
1014 			handle_nested_irq(nested_irq);
1015 
1016 		ret = 1;
1017 	}
1018 
1019 	return IRQ_RETVAL(ret);
1020 }
1021 
1022 static int cy8c95x0_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
1023 {
1024 	struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1025 
1026 	return chip->tpin;
1027 }
1028 
1029 static const char *cy8c95x0_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
1030 						   unsigned int group)
1031 {
1032 	return cy8c95x0_groups[group];
1033 }
1034 
1035 static int cy8c95x0_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
1036 					   unsigned int group,
1037 					   const unsigned int **pins,
1038 					   unsigned int *num_pins)
1039 {
1040 	*pins = &cy8c9560_pins[group].number;
1041 	*num_pins = 1;
1042 	return 0;
1043 }
1044 
1045 static const char *cy8c95x0_get_fname(unsigned int selector)
1046 {
1047 	if (selector == 0)
1048 		return "gpio";
1049 	else
1050 		return "pwm";
1051 }
1052 
1053 static void cy8c95x0_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1054 				  unsigned int pin)
1055 {
1056 	struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1057 	DECLARE_BITMAP(mask, MAX_LINE);
1058 	DECLARE_BITMAP(pwm, MAX_LINE);
1059 
1060 	bitmap_zero(mask, MAX_LINE);
1061 	__set_bit(pin, mask);
1062 
1063 	if (cy8c95x0_read_regs_mask(chip, CY8C95X0_PWMSEL, pwm, mask)) {
1064 		seq_puts(s, "not available");
1065 		return;
1066 	}
1067 
1068 	seq_printf(s, "MODE:%s", cy8c95x0_get_fname(test_bit(pin, pwm)));
1069 }
1070 
1071 static const struct pinctrl_ops cy8c95x0_pinctrl_ops = {
1072 	.get_groups_count = cy8c95x0_pinctrl_get_groups_count,
1073 	.get_group_name = cy8c95x0_pinctrl_get_group_name,
1074 	.get_group_pins = cy8c95x0_pinctrl_get_group_pins,
1075 #ifdef CONFIG_OF
1076 	.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1077 	.dt_free_map = pinconf_generic_dt_free_map,
1078 #endif
1079 	.pin_dbg_show = cy8c95x0_pin_dbg_show,
1080 };
1081 
1082 static const char *cy8c95x0_get_function_name(struct pinctrl_dev *pctldev, unsigned int selector)
1083 {
1084 	return cy8c95x0_get_fname(selector);
1085 }
1086 
1087 static int cy8c95x0_get_functions_count(struct pinctrl_dev *pctldev)
1088 {
1089 	return 2;
1090 }
1091 
1092 static int cy8c95x0_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector,
1093 					const char * const **groups,
1094 					unsigned int * const num_groups)
1095 {
1096 	struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1097 
1098 	*groups = cy8c95x0_groups;
1099 	*num_groups = chip->tpin;
1100 	return 0;
1101 }
1102 
1103 static int cy8c95x0_set_mode(struct cy8c95x0_pinctrl *chip, unsigned int off, bool mode)
1104 {
1105 	u8 port = cypress_get_port(chip, off);
1106 	u8 bit = cypress_get_pin_mask(chip, off);
1107 	int ret;
1108 
1109 	/* Select port */
1110 	ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
1111 	if (ret < 0)
1112 		return ret;
1113 
1114 	return regmap_write_bits(chip->regmap, CY8C95X0_PWMSEL, bit, mode ? bit : 0);
1115 }
1116 
1117 static int cy8c95x0_pinmux_mode(struct cy8c95x0_pinctrl *chip,
1118 				unsigned int selector, unsigned int group)
1119 {
1120 	u8 port = cypress_get_port(chip, group);
1121 	u8 bit = cypress_get_pin_mask(chip, group);
1122 	int ret;
1123 
1124 	ret = cy8c95x0_set_mode(chip, group, selector);
1125 	if (ret < 0)
1126 		return ret;
1127 
1128 	if (selector == 0)
1129 		return 0;
1130 
1131 	/* Set direction to output & set output to 1 so that PWM can work */
1132 	ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, bit);
1133 	if (ret < 0)
1134 		return ret;
1135 
1136 	return regmap_write_bits(chip->regmap, CY8C95X0_OUTPUT_(port), bit, bit);
1137 }
1138 
1139 static int cy8c95x0_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
1140 			    unsigned int group)
1141 {
1142 	struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1143 	int ret;
1144 
1145 	mutex_lock(&chip->i2c_lock);
1146 	ret = cy8c95x0_pinmux_mode(chip, selector, group);
1147 	mutex_unlock(&chip->i2c_lock);
1148 
1149 	return ret;
1150 }
1151 
1152 static int cy8c95x0_gpio_request_enable(struct pinctrl_dev *pctldev,
1153 					struct pinctrl_gpio_range *range,
1154 					unsigned int pin)
1155 {
1156 	struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1157 	int ret;
1158 
1159 	mutex_lock(&chip->i2c_lock);
1160 	ret = cy8c95x0_set_mode(chip, pin, false);
1161 	mutex_unlock(&chip->i2c_lock);
1162 
1163 	return ret;
1164 }
1165 
1166 static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip,
1167 				     unsigned int pin, bool input)
1168 {
1169 	u8 port = cypress_get_port(chip, pin);
1170 	u8 bit = cypress_get_pin_mask(chip, pin);
1171 	int ret;
1172 
1173 	/* Select port... */
1174 	ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
1175 	if (ret)
1176 		return ret;
1177 
1178 	/* ...then direction */
1179 	ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, input ? bit : 0);
1180 	if (ret)
1181 		return ret;
1182 
1183 	/*
1184 	 * Disable driving the pin by forcing it to HighZ. Only setting
1185 	 * the direction register isn't sufficient in Push-Pull mode.
1186 	 */
1187 	if (input && test_bit(pin, chip->push_pull)) {
1188 		ret = regmap_write_bits(chip->regmap, CY8C95X0_DRV_HIZ, bit, bit);
1189 		if (ret)
1190 			return ret;
1191 
1192 		__clear_bit(pin, chip->push_pull);
1193 	}
1194 
1195 	return 0;
1196 }
1197 
1198 static int cy8c95x0_gpio_set_direction(struct pinctrl_dev *pctldev,
1199 				       struct pinctrl_gpio_range *range,
1200 				       unsigned int pin, bool input)
1201 {
1202 	struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1203 	int ret;
1204 
1205 	mutex_lock(&chip->i2c_lock);
1206 	ret = cy8c95x0_pinmux_direction(chip, pin, input);
1207 	mutex_unlock(&chip->i2c_lock);
1208 
1209 	return ret;
1210 }
1211 
1212 static const struct pinmux_ops cy8c95x0_pmxops = {
1213 	.get_functions_count = cy8c95x0_get_functions_count,
1214 	.get_function_name = cy8c95x0_get_function_name,
1215 	.get_function_groups = cy8c95x0_get_function_groups,
1216 	.set_mux = cy8c95x0_set_mux,
1217 	.gpio_request_enable = cy8c95x0_gpio_request_enable,
1218 	.gpio_set_direction = cy8c95x0_gpio_set_direction,
1219 	.strict = true,
1220 };
1221 
1222 static int cy8c95x0_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1223 				unsigned long *config)
1224 {
1225 	struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1226 
1227 	return cy8c95x0_gpio_get_pincfg(chip, pin, config);
1228 }
1229 
1230 static int cy8c95x0_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1231 				unsigned long *configs, unsigned int num_configs)
1232 {
1233 	struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1234 	int ret = 0;
1235 	int i;
1236 
1237 	for (i = 0; i < num_configs; i++) {
1238 		ret = cy8c95x0_gpio_set_pincfg(chip, pin, configs[i]);
1239 		if (ret)
1240 			return ret;
1241 	}
1242 
1243 	return ret;
1244 }
1245 
1246 static const struct pinconf_ops cy8c95x0_pinconf_ops = {
1247 	.pin_config_get = cy8c95x0_pinconf_get,
1248 	.pin_config_set = cy8c95x0_pinconf_set,
1249 	.is_generic = true,
1250 };
1251 
1252 static int cy8c95x0_irq_setup(struct cy8c95x0_pinctrl *chip, int irq)
1253 {
1254 	struct gpio_irq_chip *girq = &chip->gpio_chip.irq;
1255 	DECLARE_BITMAP(pending_irqs, MAX_LINE);
1256 	int ret;
1257 
1258 	mutex_init(&chip->irq_lock);
1259 
1260 	bitmap_zero(pending_irqs, MAX_LINE);
1261 
1262 	/* Read IRQ status register to clear all pending interrupts */
1263 	ret = cy8c95x0_irq_pending(chip, pending_irqs);
1264 	if (ret) {
1265 		dev_err(chip->dev, "failed to clear irq status register\n");
1266 		return ret;
1267 	}
1268 
1269 	/* Mask all interrupts */
1270 	bitmap_fill(chip->irq_mask, MAX_LINE);
1271 
1272 	gpio_irq_chip_set_chip(girq, &cy8c95x0_irqchip);
1273 
1274 	/* This will let us handle the parent IRQ in the driver */
1275 	girq->parent_handler = NULL;
1276 	girq->num_parents = 0;
1277 	girq->parents = NULL;
1278 	girq->default_type = IRQ_TYPE_NONE;
1279 	girq->handler = handle_simple_irq;
1280 	girq->threaded = true;
1281 
1282 	ret = devm_request_threaded_irq(chip->dev, irq,
1283 					NULL, cy8c95x0_irq_handler,
1284 					IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_HIGH,
1285 					dev_name(chip->dev), chip);
1286 	if (ret) {
1287 		dev_err(chip->dev, "failed to request irq %d\n", irq);
1288 		return ret;
1289 	}
1290 	dev_info(chip->dev, "Registered threaded IRQ\n");
1291 
1292 	return 0;
1293 }
1294 
1295 static int cy8c95x0_setup_pinctrl(struct cy8c95x0_pinctrl *chip)
1296 {
1297 	struct pinctrl_desc *pd = &chip->pinctrl_desc;
1298 
1299 	pd->pctlops = &cy8c95x0_pinctrl_ops;
1300 	pd->confops = &cy8c95x0_pinconf_ops;
1301 	pd->pmxops = &cy8c95x0_pmxops;
1302 	pd->name = dev_name(chip->dev);
1303 	pd->pins = cy8c9560_pins;
1304 	pd->npins = chip->tpin;
1305 	pd->owner = THIS_MODULE;
1306 
1307 	chip->pctldev = devm_pinctrl_register(chip->dev, pd, chip);
1308 	if (IS_ERR(chip->pctldev))
1309 		return dev_err_probe(chip->dev, PTR_ERR(chip->pctldev),
1310 			"can't register controller\n");
1311 
1312 	return 0;
1313 }
1314 
1315 static int cy8c95x0_detect(struct i2c_client *client,
1316 			   struct i2c_board_info *info)
1317 {
1318 	struct i2c_adapter *adapter = client->adapter;
1319 	int ret;
1320 	const char *name;
1321 
1322 	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1323 		return -ENODEV;
1324 
1325 	ret = i2c_smbus_read_byte_data(client, CY8C95X0_DEVID);
1326 	if (ret < 0)
1327 		return ret;
1328 	switch (ret & GENMASK(7, 4)) {
1329 	case 0x20:
1330 		name = cy8c95x0_id[0].name;
1331 		break;
1332 	case 0x40:
1333 		name = cy8c95x0_id[1].name;
1334 		break;
1335 	case 0x60:
1336 		name = cy8c95x0_id[2].name;
1337 		break;
1338 	default:
1339 		return -ENODEV;
1340 	}
1341 
1342 	dev_info(&client->dev, "Found a %s chip at 0x%02x.\n", name, client->addr);
1343 	strscpy(info->type, name, I2C_NAME_SIZE);
1344 
1345 	return 0;
1346 }
1347 
1348 static int cy8c95x0_probe(struct i2c_client *client)
1349 {
1350 	struct cy8c95x0_pinctrl *chip;
1351 	struct regulator *reg;
1352 	int ret;
1353 
1354 	chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
1355 	if (!chip)
1356 		return -ENOMEM;
1357 
1358 	chip->dev = &client->dev;
1359 
1360 	/* Set the device type */
1361 	chip->driver_data = (unsigned long)device_get_match_data(&client->dev);
1362 	if (!chip->driver_data)
1363 		chip->driver_data = i2c_match_id(cy8c95x0_id, client)->driver_data;
1364 	if (!chip->driver_data)
1365 		return -ENODEV;
1366 
1367 	i2c_set_clientdata(client, chip);
1368 
1369 	chip->tpin = chip->driver_data & CY8C95X0_GPIO_MASK;
1370 	chip->nport = DIV_ROUND_UP(CY8C95X0_PIN_TO_OFFSET(chip->tpin), BANK_SZ);
1371 
1372 	switch (chip->tpin) {
1373 	case 20:
1374 		strscpy(chip->name, cy8c95x0_id[0].name, I2C_NAME_SIZE);
1375 		break;
1376 	case 40:
1377 		strscpy(chip->name, cy8c95x0_id[1].name, I2C_NAME_SIZE);
1378 		break;
1379 	case 60:
1380 		strscpy(chip->name, cy8c95x0_id[2].name, I2C_NAME_SIZE);
1381 		break;
1382 	default:
1383 		return -ENODEV;
1384 	}
1385 
1386 	reg = devm_regulator_get(&client->dev, "vdd");
1387 	if (IS_ERR(reg)) {
1388 		if (PTR_ERR(reg) == -EPROBE_DEFER)
1389 			return -EPROBE_DEFER;
1390 	} else {
1391 		ret = regulator_enable(reg);
1392 		if (ret) {
1393 			dev_err(&client->dev, "failed to enable regulator vdd: %d\n", ret);
1394 			return ret;
1395 		}
1396 		chip->regulator = reg;
1397 	}
1398 
1399 	/* bring the chip out of reset if reset pin is provided */
1400 	chip->gpio_reset = devm_gpiod_get_optional(&client->dev, "reset", GPIOD_OUT_HIGH);
1401 	if (IS_ERR(chip->gpio_reset)) {
1402 		ret = dev_err_probe(chip->dev, PTR_ERR(chip->gpio_reset),
1403 				    "Failed to get GPIO 'reset'\n");
1404 		goto err_exit;
1405 	} else if (chip->gpio_reset) {
1406 		usleep_range(1000, 2000);
1407 		gpiod_set_value_cansleep(chip->gpio_reset, 0);
1408 		usleep_range(250000, 300000);
1409 
1410 		gpiod_set_consumer_name(chip->gpio_reset, "CY8C95X0 RESET");
1411 	}
1412 
1413 	chip->regmap = devm_regmap_init_i2c(client, &cy8c95x0_i2c_regmap);
1414 	if (IS_ERR(chip->regmap)) {
1415 		ret = PTR_ERR(chip->regmap);
1416 		goto err_exit;
1417 	}
1418 
1419 	bitmap_zero(chip->push_pull, MAX_LINE);
1420 	bitmap_zero(chip->shiftmask, MAX_LINE);
1421 	bitmap_set(chip->shiftmask, 0, 20);
1422 	mutex_init(&chip->i2c_lock);
1423 
1424 	if (dmi_first_match(cy8c95x0_dmi_acpi_irq_info)) {
1425 		ret = cy8c95x0_acpi_get_irq(&client->dev);
1426 		if (ret > 0)
1427 			client->irq = ret;
1428 	}
1429 
1430 	if (client->irq) {
1431 		ret = cy8c95x0_irq_setup(chip, client->irq);
1432 		if (ret)
1433 			goto err_exit;
1434 	}
1435 
1436 	ret = cy8c95x0_setup_pinctrl(chip);
1437 	if (ret)
1438 		goto err_exit;
1439 
1440 	ret = cy8c95x0_setup_gpiochip(chip);
1441 	if (ret)
1442 		goto err_exit;
1443 
1444 	return 0;
1445 
1446 err_exit:
1447 	if (!IS_ERR_OR_NULL(chip->regulator))
1448 		regulator_disable(chip->regulator);
1449 	return ret;
1450 }
1451 
1452 static void cy8c95x0_remove(struct i2c_client *client)
1453 {
1454 	struct cy8c95x0_pinctrl *chip = i2c_get_clientdata(client);
1455 
1456 	if (!IS_ERR_OR_NULL(chip->regulator))
1457 		regulator_disable(chip->regulator);
1458 }
1459 
1460 static const struct acpi_device_id cy8c95x0_acpi_ids[] = {
1461 	{ "INT3490", 40, },
1462 	{ }
1463 };
1464 MODULE_DEVICE_TABLE(acpi, cy8c95x0_acpi_ids);
1465 
1466 static struct i2c_driver cy8c95x0_driver = {
1467 	.driver = {
1468 		.name	= "cy8c95x0-pinctrl",
1469 		.of_match_table = cy8c95x0_dt_ids,
1470 		.acpi_match_table = cy8c95x0_acpi_ids,
1471 	},
1472 	.probe		= cy8c95x0_probe,
1473 	.remove		= cy8c95x0_remove,
1474 	.id_table	= cy8c95x0_id,
1475 	.detect		= cy8c95x0_detect,
1476 };
1477 module_i2c_driver(cy8c95x0_driver);
1478 
1479 MODULE_AUTHOR("Patrick Rudolph <patrick.rudolph@9elements.com>");
1480 MODULE_AUTHOR("Naresh Solanki <naresh.solanki@9elements.com>");
1481 MODULE_DESCRIPTION("Pinctrl driver for CY8C95X0");
1482 MODULE_LICENSE("GPL");
1483