1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * CY8C95X0 20/40/60 pin I2C GPIO port expander with interrupt support 4 * 5 * Copyright (C) 2022 9elements GmbH 6 * Authors: Patrick Rudolph <patrick.rudolph@9elements.com> 7 * Naresh Solanki <Naresh.Solanki@9elements.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/bitmap.h> 12 #include <linux/dmi.h> 13 #include <linux/gpio/driver.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/i2c.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/mod_devicetable.h> 19 #include <linux/module.h> 20 #include <linux/property.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/seq_file.h> 24 25 #include <linux/pinctrl/consumer.h> 26 #include <linux/pinctrl/pinconf.h> 27 #include <linux/pinctrl/pinconf-generic.h> 28 #include <linux/pinctrl/pinctrl.h> 29 #include <linux/pinctrl/pinmux.h> 30 31 /* Fast access registers */ 32 #define CY8C95X0_INPUT 0x00 33 #define CY8C95X0_OUTPUT 0x08 34 #define CY8C95X0_INTSTATUS 0x10 35 36 #define CY8C95X0_INPUT_(x) (CY8C95X0_INPUT + (x)) 37 #define CY8C95X0_OUTPUT_(x) (CY8C95X0_OUTPUT + (x)) 38 #define CY8C95X0_INTSTATUS_(x) (CY8C95X0_INTSTATUS + (x)) 39 40 /* Port Select configures the port */ 41 #define CY8C95X0_PORTSEL 0x18 42 /* Port settings, write PORTSEL first */ 43 #define CY8C95X0_INTMASK 0x19 44 #define CY8C95X0_PWMSEL 0x1A 45 #define CY8C95X0_INVERT 0x1B 46 #define CY8C95X0_DIRECTION 0x1C 47 /* Drive mode register change state on writing '1' */ 48 #define CY8C95X0_DRV_PU 0x1D 49 #define CY8C95X0_DRV_PD 0x1E 50 #define CY8C95X0_DRV_ODH 0x1F 51 #define CY8C95X0_DRV_ODL 0x20 52 #define CY8C95X0_DRV_PP_FAST 0x21 53 #define CY8C95X0_DRV_PP_SLOW 0x22 54 #define CY8C95X0_DRV_HIZ 0x23 55 #define CY8C95X0_DEVID 0x2E 56 #define CY8C95X0_WATCHDOG 0x2F 57 #define CY8C95X0_COMMAND 0x30 58 59 #define CY8C95X0_PIN_TO_OFFSET(x) (((x) >= 20) ? ((x) + 4) : (x)) 60 61 static const struct i2c_device_id cy8c95x0_id[] = { 62 { "cy8c9520", 20, }, 63 { "cy8c9540", 40, }, 64 { "cy8c9560", 60, }, 65 { } 66 }; 67 MODULE_DEVICE_TABLE(i2c, cy8c95x0_id); 68 69 #define OF_CY8C95X(__nrgpio) ((void *)(__nrgpio)) 70 71 static const struct of_device_id cy8c95x0_dt_ids[] = { 72 { .compatible = "cypress,cy8c9520", .data = OF_CY8C95X(20), }, 73 { .compatible = "cypress,cy8c9540", .data = OF_CY8C95X(40), }, 74 { .compatible = "cypress,cy8c9560", .data = OF_CY8C95X(60), }, 75 { } 76 }; 77 MODULE_DEVICE_TABLE(of, cy8c95x0_dt_ids); 78 79 static const struct acpi_gpio_params cy8c95x0_irq_gpios = { 0, 0, true }; 80 81 static const struct acpi_gpio_mapping cy8c95x0_acpi_irq_gpios[] = { 82 { "irq-gpios", &cy8c95x0_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER }, 83 { } 84 }; 85 86 static int cy8c95x0_acpi_get_irq(struct device *dev) 87 { 88 int ret; 89 90 ret = devm_acpi_dev_add_driver_gpios(dev, cy8c95x0_acpi_irq_gpios); 91 if (ret) 92 dev_warn(dev, "can't add GPIO ACPI mapping\n"); 93 94 ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq-gpios", 0); 95 if (ret < 0) 96 return ret; 97 98 dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret); 99 return ret; 100 } 101 102 static const struct dmi_system_id cy8c95x0_dmi_acpi_irq_info[] = { 103 { 104 /* 105 * On Intel Galileo Gen 1 board the IRQ pin is provided 106 * as an absolute number instead of being relative. 107 * Since first controller (gpio-sch.c) and second 108 * (gpio-dwapb.c) are at the fixed bases, we may safely 109 * refer to the number in the global space to get an IRQ 110 * out of it. 111 */ 112 .matches = { 113 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"), 114 }, 115 }, 116 {} 117 }; 118 119 #define MAX_BANK 8 120 #define BANK_SZ 8 121 #define MAX_LINE (MAX_BANK * BANK_SZ) 122 123 #define CY8C95X0_GPIO_MASK GENMASK(7, 0) 124 125 /** 126 * struct cy8c95x0_pinctrl - driver data 127 * @regmap: Device's regmap 128 * @irq_lock: IRQ bus lock 129 * @i2c_lock: Mutex for the device internal mux register 130 * @irq_mask: I/O bits affected by interrupts 131 * @irq_trig_raise: I/O bits affected by raising voltage level 132 * @irq_trig_fall: I/O bits affected by falling voltage level 133 * @irq_trig_low: I/O bits affected by a low voltage level 134 * @irq_trig_high: I/O bits affected by a high voltage level 135 * @push_pull: I/O bits configured as push pull driver 136 * @shiftmask: Mask used to compensate for Gport2 width 137 * @nport: Number of Gports in this chip 138 * @gpio_chip: gpiolib chip 139 * @driver_data: private driver data 140 * @regulator: Pointer to the regulator for the IC 141 * @dev: struct device 142 * @pctldev: pin controller device 143 * @pinctrl_desc: pin controller description 144 * @name: Chip controller name 145 * @tpin: Total number of pins 146 */ 147 struct cy8c95x0_pinctrl { 148 struct regmap *regmap; 149 struct mutex irq_lock; 150 struct mutex i2c_lock; 151 DECLARE_BITMAP(irq_mask, MAX_LINE); 152 DECLARE_BITMAP(irq_trig_raise, MAX_LINE); 153 DECLARE_BITMAP(irq_trig_fall, MAX_LINE); 154 DECLARE_BITMAP(irq_trig_low, MAX_LINE); 155 DECLARE_BITMAP(irq_trig_high, MAX_LINE); 156 DECLARE_BITMAP(push_pull, MAX_LINE); 157 DECLARE_BITMAP(shiftmask, MAX_LINE); 158 int nport; 159 struct gpio_chip gpio_chip; 160 unsigned long driver_data; 161 struct regulator *regulator; 162 struct device *dev; 163 struct pinctrl_dev *pctldev; 164 struct pinctrl_desc pinctrl_desc; 165 char name[32]; 166 unsigned int tpin; 167 }; 168 169 static const struct pinctrl_pin_desc cy8c9560_pins[] = { 170 PINCTRL_PIN(0, "gp00"), 171 PINCTRL_PIN(1, "gp01"), 172 PINCTRL_PIN(2, "gp02"), 173 PINCTRL_PIN(3, "gp03"), 174 PINCTRL_PIN(4, "gp04"), 175 PINCTRL_PIN(5, "gp05"), 176 PINCTRL_PIN(6, "gp06"), 177 PINCTRL_PIN(7, "gp07"), 178 179 PINCTRL_PIN(8, "gp10"), 180 PINCTRL_PIN(9, "gp11"), 181 PINCTRL_PIN(10, "gp12"), 182 PINCTRL_PIN(11, "gp13"), 183 PINCTRL_PIN(12, "gp14"), 184 PINCTRL_PIN(13, "gp15"), 185 PINCTRL_PIN(14, "gp16"), 186 PINCTRL_PIN(15, "gp17"), 187 188 PINCTRL_PIN(16, "gp20"), 189 PINCTRL_PIN(17, "gp21"), 190 PINCTRL_PIN(18, "gp22"), 191 PINCTRL_PIN(19, "gp23"), 192 193 PINCTRL_PIN(20, "gp30"), 194 PINCTRL_PIN(21, "gp31"), 195 PINCTRL_PIN(22, "gp32"), 196 PINCTRL_PIN(23, "gp33"), 197 PINCTRL_PIN(24, "gp34"), 198 PINCTRL_PIN(25, "gp35"), 199 PINCTRL_PIN(26, "gp36"), 200 PINCTRL_PIN(27, "gp37"), 201 202 PINCTRL_PIN(28, "gp40"), 203 PINCTRL_PIN(29, "gp41"), 204 PINCTRL_PIN(30, "gp42"), 205 PINCTRL_PIN(31, "gp43"), 206 PINCTRL_PIN(32, "gp44"), 207 PINCTRL_PIN(33, "gp45"), 208 PINCTRL_PIN(34, "gp46"), 209 PINCTRL_PIN(35, "gp47"), 210 211 PINCTRL_PIN(36, "gp50"), 212 PINCTRL_PIN(37, "gp51"), 213 PINCTRL_PIN(38, "gp52"), 214 PINCTRL_PIN(39, "gp53"), 215 PINCTRL_PIN(40, "gp54"), 216 PINCTRL_PIN(41, "gp55"), 217 PINCTRL_PIN(42, "gp56"), 218 PINCTRL_PIN(43, "gp57"), 219 220 PINCTRL_PIN(44, "gp60"), 221 PINCTRL_PIN(45, "gp61"), 222 PINCTRL_PIN(46, "gp62"), 223 PINCTRL_PIN(47, "gp63"), 224 PINCTRL_PIN(48, "gp64"), 225 PINCTRL_PIN(49, "gp65"), 226 PINCTRL_PIN(50, "gp66"), 227 PINCTRL_PIN(51, "gp67"), 228 229 PINCTRL_PIN(52, "gp70"), 230 PINCTRL_PIN(53, "gp71"), 231 PINCTRL_PIN(54, "gp72"), 232 PINCTRL_PIN(55, "gp73"), 233 PINCTRL_PIN(56, "gp74"), 234 PINCTRL_PIN(57, "gp75"), 235 PINCTRL_PIN(58, "gp76"), 236 PINCTRL_PIN(59, "gp77"), 237 }; 238 239 static const char * const cy8c95x0_groups[] = { 240 "gp00", 241 "gp01", 242 "gp02", 243 "gp03", 244 "gp04", 245 "gp05", 246 "gp06", 247 "gp07", 248 249 "gp10", 250 "gp11", 251 "gp12", 252 "gp13", 253 "gp14", 254 "gp15", 255 "gp16", 256 "gp17", 257 258 "gp20", 259 "gp21", 260 "gp22", 261 "gp23", 262 263 "gp30", 264 "gp31", 265 "gp32", 266 "gp33", 267 "gp34", 268 "gp35", 269 "gp36", 270 "gp37", 271 272 "gp40", 273 "gp41", 274 "gp42", 275 "gp43", 276 "gp44", 277 "gp45", 278 "gp46", 279 "gp47", 280 281 "gp50", 282 "gp51", 283 "gp52", 284 "gp53", 285 "gp54", 286 "gp55", 287 "gp56", 288 "gp57", 289 290 "gp60", 291 "gp61", 292 "gp62", 293 "gp63", 294 "gp64", 295 "gp65", 296 "gp66", 297 "gp67", 298 299 "gp70", 300 "gp71", 301 "gp72", 302 "gp73", 303 "gp74", 304 "gp75", 305 "gp76", 306 "gp77", 307 }; 308 309 static inline u8 cypress_get_port(struct cy8c95x0_pinctrl *chip, unsigned int pin) 310 { 311 /* Account for GPORT2 which only has 4 bits */ 312 return CY8C95X0_PIN_TO_OFFSET(pin) / BANK_SZ; 313 } 314 315 static int cypress_get_pin_mask(struct cy8c95x0_pinctrl *chip, unsigned int pin) 316 { 317 /* Account for GPORT2 which only has 4 bits */ 318 return BIT(CY8C95X0_PIN_TO_OFFSET(pin) % BANK_SZ); 319 } 320 321 static bool cy8c95x0_readable_register(struct device *dev, unsigned int reg) 322 { 323 switch (reg) { 324 case 0x24 ... 0x27: 325 return false; 326 default: 327 return true; 328 } 329 } 330 331 static bool cy8c95x0_writeable_register(struct device *dev, unsigned int reg) 332 { 333 switch (reg) { 334 case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7): 335 return false; 336 case CY8C95X0_DEVID: 337 return false; 338 case 0x24 ... 0x27: 339 return false; 340 default: 341 return true; 342 } 343 } 344 345 static bool cy8c95x0_volatile_register(struct device *dev, unsigned int reg) 346 { 347 switch (reg) { 348 case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7): 349 case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7): 350 case CY8C95X0_INTMASK: 351 case CY8C95X0_INVERT: 352 case CY8C95X0_PWMSEL: 353 case CY8C95X0_DIRECTION: 354 case CY8C95X0_DRV_PU: 355 case CY8C95X0_DRV_PD: 356 case CY8C95X0_DRV_ODH: 357 case CY8C95X0_DRV_ODL: 358 case CY8C95X0_DRV_PP_FAST: 359 case CY8C95X0_DRV_PP_SLOW: 360 case CY8C95X0_DRV_HIZ: 361 return true; 362 default: 363 return false; 364 } 365 } 366 367 static bool cy8c95x0_precious_register(struct device *dev, unsigned int reg) 368 { 369 switch (reg) { 370 case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7): 371 return true; 372 default: 373 return false; 374 } 375 } 376 377 static const struct reg_default cy8c95x0_reg_defaults[] = { 378 { CY8C95X0_OUTPUT_(0), GENMASK(7, 0) }, 379 { CY8C95X0_OUTPUT_(1), GENMASK(7, 0) }, 380 { CY8C95X0_OUTPUT_(2), GENMASK(7, 0) }, 381 { CY8C95X0_OUTPUT_(3), GENMASK(7, 0) }, 382 { CY8C95X0_OUTPUT_(4), GENMASK(7, 0) }, 383 { CY8C95X0_OUTPUT_(5), GENMASK(7, 0) }, 384 { CY8C95X0_OUTPUT_(6), GENMASK(7, 0) }, 385 { CY8C95X0_OUTPUT_(7), GENMASK(7, 0) }, 386 { CY8C95X0_PORTSEL, 0 }, 387 { CY8C95X0_PWMSEL, 0 }, 388 }; 389 390 static const struct regmap_config cy8c95x0_i2c_regmap = { 391 .reg_bits = 8, 392 .val_bits = 8, 393 394 .reg_defaults = cy8c95x0_reg_defaults, 395 .num_reg_defaults = ARRAY_SIZE(cy8c95x0_reg_defaults), 396 397 .readable_reg = cy8c95x0_readable_register, 398 .writeable_reg = cy8c95x0_writeable_register, 399 .volatile_reg = cy8c95x0_volatile_register, 400 .precious_reg = cy8c95x0_precious_register, 401 402 .cache_type = REGCACHE_FLAT, 403 .max_register = CY8C95X0_COMMAND, 404 }; 405 406 static int cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, 407 unsigned long *val, unsigned long *mask) 408 { 409 DECLARE_BITMAP(tmask, MAX_LINE); 410 DECLARE_BITMAP(tval, MAX_LINE); 411 int write_val; 412 int ret = 0; 413 int i, off = 0; 414 u8 bits; 415 416 /* Add the 4 bit gap of Gport2 */ 417 bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE); 418 bitmap_shift_left(tmask, tmask, 4, MAX_LINE); 419 bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3); 420 421 bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE); 422 bitmap_shift_left(tval, tval, 4, MAX_LINE); 423 bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3); 424 425 mutex_lock(&chip->i2c_lock); 426 for (i = 0; i < chip->nport; i++) { 427 /* Skip over unused banks */ 428 bits = bitmap_get_value8(tmask, i * BANK_SZ); 429 if (!bits) 430 continue; 431 432 switch (reg) { 433 /* Muxed registers */ 434 case CY8C95X0_INTMASK: 435 case CY8C95X0_PWMSEL: 436 case CY8C95X0_INVERT: 437 case CY8C95X0_DIRECTION: 438 case CY8C95X0_DRV_PU: 439 case CY8C95X0_DRV_PD: 440 case CY8C95X0_DRV_ODH: 441 case CY8C95X0_DRV_ODL: 442 case CY8C95X0_DRV_PP_FAST: 443 case CY8C95X0_DRV_PP_SLOW: 444 case CY8C95X0_DRV_HIZ: 445 ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, i); 446 if (ret < 0) 447 goto out; 448 off = reg; 449 break; 450 /* Direct access registers */ 451 case CY8C95X0_INPUT: 452 case CY8C95X0_OUTPUT: 453 case CY8C95X0_INTSTATUS: 454 off = reg + i; 455 break; 456 default: 457 ret = -EINVAL; 458 goto out; 459 } 460 461 write_val = bitmap_get_value8(tval, i * BANK_SZ); 462 463 ret = regmap_update_bits(chip->regmap, off, bits, write_val); 464 if (ret < 0) 465 goto out; 466 } 467 out: 468 mutex_unlock(&chip->i2c_lock); 469 470 if (ret < 0) 471 dev_err(chip->dev, "failed writing register %d: err %d\n", off, ret); 472 473 return ret; 474 } 475 476 static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, 477 unsigned long *val, unsigned long *mask) 478 { 479 DECLARE_BITMAP(tmask, MAX_LINE); 480 DECLARE_BITMAP(tval, MAX_LINE); 481 DECLARE_BITMAP(tmp, MAX_LINE); 482 int read_val; 483 int ret = 0; 484 int i, off = 0; 485 u8 bits; 486 487 /* Add the 4 bit gap of Gport2 */ 488 bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE); 489 bitmap_shift_left(tmask, tmask, 4, MAX_LINE); 490 bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3); 491 492 bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE); 493 bitmap_shift_left(tval, tval, 4, MAX_LINE); 494 bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3); 495 496 mutex_lock(&chip->i2c_lock); 497 for (i = 0; i < chip->nport; i++) { 498 /* Skip over unused banks */ 499 bits = bitmap_get_value8(tmask, i * BANK_SZ); 500 if (!bits) 501 continue; 502 503 switch (reg) { 504 /* Muxed registers */ 505 case CY8C95X0_INTMASK: 506 case CY8C95X0_PWMSEL: 507 case CY8C95X0_INVERT: 508 case CY8C95X0_DIRECTION: 509 case CY8C95X0_DRV_PU: 510 case CY8C95X0_DRV_PD: 511 case CY8C95X0_DRV_ODH: 512 case CY8C95X0_DRV_ODL: 513 case CY8C95X0_DRV_PP_FAST: 514 case CY8C95X0_DRV_PP_SLOW: 515 case CY8C95X0_DRV_HIZ: 516 ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, i); 517 if (ret < 0) 518 goto out; 519 off = reg; 520 break; 521 /* Direct access registers */ 522 case CY8C95X0_INPUT: 523 case CY8C95X0_OUTPUT: 524 case CY8C95X0_INTSTATUS: 525 off = reg + i; 526 break; 527 default: 528 ret = -EINVAL; 529 goto out; 530 } 531 532 ret = regmap_read(chip->regmap, off, &read_val); 533 if (ret < 0) 534 goto out; 535 536 read_val &= bits; 537 read_val |= bitmap_get_value8(tval, i * BANK_SZ) & ~bits; 538 bitmap_set_value8(tval, read_val, i * BANK_SZ); 539 } 540 541 /* Fill the 4 bit gap of Gport2 */ 542 bitmap_shift_right(tmp, tval, 4, MAX_LINE); 543 bitmap_replace(val, tmp, tval, chip->shiftmask, MAX_LINE); 544 545 out: 546 mutex_unlock(&chip->i2c_lock); 547 548 if (ret < 0) 549 dev_err(chip->dev, "failed reading register %d: err %d\n", off, ret); 550 551 return ret; 552 } 553 554 static int cy8c95x0_gpio_direction_input(struct gpio_chip *gc, unsigned int off) 555 { 556 return pinctrl_gpio_direction_input(gc->base + off); 557 } 558 559 static int cy8c95x0_gpio_direction_output(struct gpio_chip *gc, 560 unsigned int off, int val) 561 { 562 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 563 u8 port = cypress_get_port(chip, off); 564 u8 outreg = CY8C95X0_OUTPUT_(port); 565 u8 bit = cypress_get_pin_mask(chip, off); 566 int ret; 567 568 /* Set output level */ 569 ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); 570 if (ret) 571 return ret; 572 573 return pinctrl_gpio_direction_output(gc->base + off); 574 } 575 576 static int cy8c95x0_gpio_get_value(struct gpio_chip *gc, unsigned int off) 577 { 578 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 579 u8 inreg = CY8C95X0_INPUT_(cypress_get_port(chip, off)); 580 u8 bit = cypress_get_pin_mask(chip, off); 581 u32 reg_val; 582 int ret; 583 584 ret = regmap_read(chip->regmap, inreg, ®_val); 585 if (ret < 0) { 586 /* 587 * NOTE: 588 * Diagnostic already emitted; that's all we should 589 * do unless gpio_*_value_cansleep() calls become different 590 * from their nonsleeping siblings (and report faults). 591 */ 592 return 0; 593 } 594 595 return !!(reg_val & bit); 596 } 597 598 static void cy8c95x0_gpio_set_value(struct gpio_chip *gc, unsigned int off, 599 int val) 600 { 601 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 602 u8 outreg = CY8C95X0_OUTPUT_(cypress_get_port(chip, off)); 603 u8 bit = cypress_get_pin_mask(chip, off); 604 605 regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); 606 } 607 608 static int cy8c95x0_gpio_get_direction(struct gpio_chip *gc, unsigned int off) 609 { 610 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 611 u8 port = cypress_get_port(chip, off); 612 u8 bit = cypress_get_pin_mask(chip, off); 613 u32 reg_val; 614 int ret; 615 616 mutex_lock(&chip->i2c_lock); 617 618 ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port); 619 if (ret < 0) 620 goto out; 621 622 ret = regmap_read(chip->regmap, CY8C95X0_DIRECTION, ®_val); 623 if (ret < 0) 624 goto out; 625 626 mutex_unlock(&chip->i2c_lock); 627 628 if (reg_val & bit) 629 return GPIO_LINE_DIRECTION_IN; 630 631 return GPIO_LINE_DIRECTION_OUT; 632 out: 633 mutex_unlock(&chip->i2c_lock); 634 return ret; 635 } 636 637 static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip, 638 unsigned int off, 639 unsigned long *config) 640 { 641 enum pin_config_param param = pinconf_to_config_param(*config); 642 u8 port = cypress_get_port(chip, off); 643 u8 bit = cypress_get_pin_mask(chip, off); 644 unsigned int reg; 645 u32 reg_val; 646 u16 arg = 0; 647 int ret; 648 649 mutex_lock(&chip->i2c_lock); 650 651 /* Select port */ 652 ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port); 653 if (ret < 0) 654 goto out; 655 656 switch (param) { 657 case PIN_CONFIG_BIAS_PULL_UP: 658 reg = CY8C95X0_DRV_PU; 659 break; 660 case PIN_CONFIG_BIAS_PULL_DOWN: 661 reg = CY8C95X0_DRV_PD; 662 break; 663 case PIN_CONFIG_BIAS_DISABLE: 664 reg = CY8C95X0_DRV_HIZ; 665 break; 666 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 667 reg = CY8C95X0_DRV_ODL; 668 break; 669 case PIN_CONFIG_DRIVE_OPEN_SOURCE: 670 reg = CY8C95X0_DRV_ODH; 671 break; 672 case PIN_CONFIG_DRIVE_PUSH_PULL: 673 reg = CY8C95X0_DRV_PP_FAST; 674 break; 675 case PIN_CONFIG_INPUT_ENABLE: 676 reg = CY8C95X0_DIRECTION; 677 break; 678 case PIN_CONFIG_MODE_PWM: 679 reg = CY8C95X0_PWMSEL; 680 break; 681 case PIN_CONFIG_OUTPUT: 682 reg = CY8C95X0_OUTPUT_(port); 683 break; 684 case PIN_CONFIG_OUTPUT_ENABLE: 685 reg = CY8C95X0_DIRECTION; 686 break; 687 688 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 689 case PIN_CONFIG_BIAS_BUS_HOLD: 690 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 691 case PIN_CONFIG_DRIVE_STRENGTH: 692 case PIN_CONFIG_DRIVE_STRENGTH_UA: 693 case PIN_CONFIG_INPUT_DEBOUNCE: 694 case PIN_CONFIG_INPUT_SCHMITT: 695 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 696 case PIN_CONFIG_MODE_LOW_POWER: 697 case PIN_CONFIG_PERSIST_STATE: 698 case PIN_CONFIG_POWER_SOURCE: 699 case PIN_CONFIG_SKEW_DELAY: 700 case PIN_CONFIG_SLEEP_HARDWARE_STATE: 701 case PIN_CONFIG_SLEW_RATE: 702 default: 703 ret = -ENOTSUPP; 704 goto out; 705 } 706 /* 707 * Writing 1 to one of the drive mode registers will automatically 708 * clear conflicting set bits in the other drive mode registers. 709 */ 710 ret = regmap_read(chip->regmap, reg, ®_val); 711 if (reg_val & bit) 712 arg = 1; 713 714 *config = pinconf_to_config_packed(param, (u16)arg); 715 out: 716 mutex_unlock(&chip->i2c_lock); 717 718 return ret; 719 } 720 721 static int cy8c95x0_gpio_set_pincfg(struct cy8c95x0_pinctrl *chip, 722 unsigned int off, 723 unsigned long config) 724 { 725 u8 port = cypress_get_port(chip, off); 726 u8 bit = cypress_get_pin_mask(chip, off); 727 unsigned long param = pinconf_to_config_param(config); 728 unsigned int reg; 729 int ret; 730 731 mutex_lock(&chip->i2c_lock); 732 733 /* Select port */ 734 ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port); 735 if (ret < 0) 736 goto out; 737 738 switch (param) { 739 case PIN_CONFIG_BIAS_PULL_UP: 740 __clear_bit(off, chip->push_pull); 741 reg = CY8C95X0_DRV_PU; 742 break; 743 case PIN_CONFIG_BIAS_PULL_DOWN: 744 __clear_bit(off, chip->push_pull); 745 reg = CY8C95X0_DRV_PD; 746 break; 747 case PIN_CONFIG_BIAS_DISABLE: 748 __clear_bit(off, chip->push_pull); 749 reg = CY8C95X0_DRV_HIZ; 750 break; 751 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 752 __clear_bit(off, chip->push_pull); 753 reg = CY8C95X0_DRV_ODL; 754 break; 755 case PIN_CONFIG_DRIVE_OPEN_SOURCE: 756 __clear_bit(off, chip->push_pull); 757 reg = CY8C95X0_DRV_ODH; 758 break; 759 case PIN_CONFIG_DRIVE_PUSH_PULL: 760 __set_bit(off, chip->push_pull); 761 reg = CY8C95X0_DRV_PP_FAST; 762 break; 763 case PIN_CONFIG_MODE_PWM: 764 reg = CY8C95X0_PWMSEL; 765 break; 766 default: 767 ret = -ENOTSUPP; 768 goto out; 769 } 770 /* 771 * Writing 1 to one of the drive mode registers will automatically 772 * clear conflicting set bits in the other drive mode registers. 773 */ 774 ret = regmap_write_bits(chip->regmap, reg, bit, bit); 775 776 out: 777 mutex_unlock(&chip->i2c_lock); 778 return ret; 779 } 780 781 static int cy8c95x0_gpio_get_multiple(struct gpio_chip *gc, 782 unsigned long *mask, unsigned long *bits) 783 { 784 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 785 786 return cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, bits, mask); 787 } 788 789 static void cy8c95x0_gpio_set_multiple(struct gpio_chip *gc, 790 unsigned long *mask, unsigned long *bits) 791 { 792 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 793 794 cy8c95x0_write_regs_mask(chip, CY8C95X0_OUTPUT, bits, mask); 795 } 796 797 static int cy8c95x0_add_pin_ranges(struct gpio_chip *gc) 798 { 799 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 800 struct device *dev = chip->dev; 801 int ret; 802 803 ret = gpiochip_add_pin_range(gc, dev_name(dev), 0, 0, chip->tpin); 804 if (ret) 805 dev_err(dev, "failed to add GPIO pin range\n"); 806 807 return ret; 808 } 809 810 static int cy8c95x0_setup_gpiochip(struct cy8c95x0_pinctrl *chip) 811 { 812 struct gpio_chip *gc = &chip->gpio_chip; 813 814 gc->request = gpiochip_generic_request; 815 gc->free = gpiochip_generic_free; 816 gc->direction_input = cy8c95x0_gpio_direction_input; 817 gc->direction_output = cy8c95x0_gpio_direction_output; 818 gc->get = cy8c95x0_gpio_get_value; 819 gc->set = cy8c95x0_gpio_set_value; 820 gc->get_direction = cy8c95x0_gpio_get_direction; 821 gc->get_multiple = cy8c95x0_gpio_get_multiple; 822 gc->set_multiple = cy8c95x0_gpio_set_multiple; 823 gc->set_config = gpiochip_generic_config, 824 gc->can_sleep = true; 825 gc->add_pin_ranges = cy8c95x0_add_pin_ranges; 826 827 gc->base = -1; 828 gc->ngpio = chip->tpin; 829 830 gc->parent = chip->dev; 831 gc->owner = THIS_MODULE; 832 gc->names = NULL; 833 834 gc->label = dev_name(chip->dev); 835 836 return devm_gpiochip_add_data(chip->dev, gc, chip); 837 } 838 839 static void cy8c95x0_irq_mask(struct irq_data *d) 840 { 841 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 842 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 843 irq_hw_number_t hwirq = irqd_to_hwirq(d); 844 845 set_bit(hwirq, chip->irq_mask); 846 gpiochip_disable_irq(gc, hwirq); 847 } 848 849 static void cy8c95x0_irq_unmask(struct irq_data *d) 850 { 851 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 852 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 853 irq_hw_number_t hwirq = irqd_to_hwirq(d); 854 855 gpiochip_enable_irq(gc, hwirq); 856 clear_bit(hwirq, chip->irq_mask); 857 } 858 859 static void cy8c95x0_irq_bus_lock(struct irq_data *d) 860 { 861 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 862 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 863 864 mutex_lock(&chip->irq_lock); 865 } 866 867 static void cy8c95x0_irq_bus_sync_unlock(struct irq_data *d) 868 { 869 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 870 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 871 DECLARE_BITMAP(ones, MAX_LINE); 872 DECLARE_BITMAP(irq_mask, MAX_LINE); 873 DECLARE_BITMAP(reg_direction, MAX_LINE); 874 875 bitmap_fill(ones, MAX_LINE); 876 877 cy8c95x0_write_regs_mask(chip, CY8C95X0_INTMASK, chip->irq_mask, ones); 878 879 /* Switch direction to input if needed */ 880 cy8c95x0_read_regs_mask(chip, CY8C95X0_DIRECTION, reg_direction, chip->irq_mask); 881 bitmap_or(irq_mask, chip->irq_mask, reg_direction, MAX_LINE); 882 bitmap_complement(irq_mask, irq_mask, MAX_LINE); 883 884 /* Look for any newly setup interrupt */ 885 cy8c95x0_write_regs_mask(chip, CY8C95X0_DIRECTION, ones, irq_mask); 886 887 mutex_unlock(&chip->irq_lock); 888 } 889 890 static int cy8c95x0_irq_set_type(struct irq_data *d, unsigned int type) 891 { 892 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 893 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 894 irq_hw_number_t hwirq = irqd_to_hwirq(d); 895 unsigned int trig_type; 896 897 switch (type) { 898 case IRQ_TYPE_EDGE_RISING: 899 case IRQ_TYPE_EDGE_FALLING: 900 case IRQ_TYPE_EDGE_BOTH: 901 trig_type = type; 902 break; 903 case IRQ_TYPE_LEVEL_HIGH: 904 trig_type = IRQ_TYPE_EDGE_RISING; 905 break; 906 case IRQ_TYPE_LEVEL_LOW: 907 trig_type = IRQ_TYPE_EDGE_FALLING; 908 break; 909 default: 910 dev_err(chip->dev, "irq %d: unsupported type %d\n", d->irq, type); 911 return -EINVAL; 912 } 913 914 assign_bit(hwirq, chip->irq_trig_fall, trig_type & IRQ_TYPE_EDGE_FALLING); 915 assign_bit(hwirq, chip->irq_trig_raise, trig_type & IRQ_TYPE_EDGE_RISING); 916 assign_bit(hwirq, chip->irq_trig_low, type == IRQ_TYPE_LEVEL_LOW); 917 assign_bit(hwirq, chip->irq_trig_high, type == IRQ_TYPE_LEVEL_HIGH); 918 919 return 0; 920 } 921 922 static void cy8c95x0_irq_shutdown(struct irq_data *d) 923 { 924 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 925 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 926 irq_hw_number_t hwirq = irqd_to_hwirq(d); 927 928 clear_bit(hwirq, chip->irq_trig_raise); 929 clear_bit(hwirq, chip->irq_trig_fall); 930 clear_bit(hwirq, chip->irq_trig_low); 931 clear_bit(hwirq, chip->irq_trig_high); 932 } 933 934 static const struct irq_chip cy8c95x0_irqchip = { 935 .name = "cy8c95x0-irq", 936 .irq_mask = cy8c95x0_irq_mask, 937 .irq_unmask = cy8c95x0_irq_unmask, 938 .irq_bus_lock = cy8c95x0_irq_bus_lock, 939 .irq_bus_sync_unlock = cy8c95x0_irq_bus_sync_unlock, 940 .irq_set_type = cy8c95x0_irq_set_type, 941 .irq_shutdown = cy8c95x0_irq_shutdown, 942 .flags = IRQCHIP_IMMUTABLE, 943 GPIOCHIP_IRQ_RESOURCE_HELPERS, 944 }; 945 946 static bool cy8c95x0_irq_pending(struct cy8c95x0_pinctrl *chip, unsigned long *pending) 947 { 948 DECLARE_BITMAP(ones, MAX_LINE); 949 DECLARE_BITMAP(cur_stat, MAX_LINE); 950 DECLARE_BITMAP(new_stat, MAX_LINE); 951 DECLARE_BITMAP(trigger, MAX_LINE); 952 953 bitmap_fill(ones, MAX_LINE); 954 955 /* Read the current interrupt status from the device */ 956 if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INTSTATUS, trigger, ones)) 957 return false; 958 959 /* Check latched inputs */ 960 if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, cur_stat, trigger)) 961 return false; 962 963 /* Apply filter for rising/falling edge selection */ 964 bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise, 965 cur_stat, MAX_LINE); 966 967 bitmap_and(pending, new_stat, trigger, MAX_LINE); 968 969 return !bitmap_empty(pending, MAX_LINE); 970 } 971 972 static irqreturn_t cy8c95x0_irq_handler(int irq, void *devid) 973 { 974 struct cy8c95x0_pinctrl *chip = devid; 975 struct gpio_chip *gc = &chip->gpio_chip; 976 DECLARE_BITMAP(pending, MAX_LINE); 977 int nested_irq, level; 978 bool ret; 979 980 ret = cy8c95x0_irq_pending(chip, pending); 981 if (!ret) 982 return IRQ_RETVAL(0); 983 984 ret = 0; 985 for_each_set_bit(level, pending, MAX_LINE) { 986 /* Already accounted for 4bit gap in GPort2 */ 987 nested_irq = irq_find_mapping(gc->irq.domain, level); 988 989 if (unlikely(nested_irq <= 0)) { 990 dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level); 991 continue; 992 } 993 994 if (test_bit(level, chip->irq_trig_low)) 995 while (!cy8c95x0_gpio_get_value(gc, level)) 996 handle_nested_irq(nested_irq); 997 else if (test_bit(level, chip->irq_trig_high)) 998 while (cy8c95x0_gpio_get_value(gc, level)) 999 handle_nested_irq(nested_irq); 1000 else 1001 handle_nested_irq(nested_irq); 1002 1003 ret = 1; 1004 } 1005 1006 return IRQ_RETVAL(ret); 1007 } 1008 1009 static int cy8c95x0_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 1010 { 1011 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1012 1013 return chip->tpin; 1014 } 1015 1016 static const char *cy8c95x0_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 1017 unsigned int group) 1018 { 1019 return cy8c95x0_groups[group]; 1020 } 1021 1022 static int cy8c95x0_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, 1023 unsigned int group, 1024 const unsigned int **pins, 1025 unsigned int *num_pins) 1026 { 1027 *pins = &cy8c9560_pins[group].number; 1028 *num_pins = 1; 1029 return 0; 1030 } 1031 1032 static const char *cy8c95x0_get_fname(unsigned int selector) 1033 { 1034 if (selector == 0) 1035 return "gpio"; 1036 else 1037 return "pwm"; 1038 } 1039 1040 static void cy8c95x0_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 1041 unsigned int pin) 1042 { 1043 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1044 DECLARE_BITMAP(mask, MAX_LINE); 1045 DECLARE_BITMAP(pwm, MAX_LINE); 1046 1047 bitmap_zero(mask, MAX_LINE); 1048 __set_bit(pin, mask); 1049 1050 if (cy8c95x0_read_regs_mask(chip, CY8C95X0_PWMSEL, pwm, mask)) { 1051 seq_puts(s, "not available"); 1052 return; 1053 } 1054 1055 seq_printf(s, "MODE:%s", cy8c95x0_get_fname(test_bit(pin, pwm))); 1056 } 1057 1058 static const struct pinctrl_ops cy8c95x0_pinctrl_ops = { 1059 .get_groups_count = cy8c95x0_pinctrl_get_groups_count, 1060 .get_group_name = cy8c95x0_pinctrl_get_group_name, 1061 .get_group_pins = cy8c95x0_pinctrl_get_group_pins, 1062 #ifdef CONFIG_OF 1063 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 1064 .dt_free_map = pinconf_generic_dt_free_map, 1065 #endif 1066 .pin_dbg_show = cy8c95x0_pin_dbg_show, 1067 }; 1068 1069 static const char *cy8c95x0_get_function_name(struct pinctrl_dev *pctldev, unsigned int selector) 1070 { 1071 return cy8c95x0_get_fname(selector); 1072 } 1073 1074 static int cy8c95x0_get_functions_count(struct pinctrl_dev *pctldev) 1075 { 1076 return 2; 1077 } 1078 1079 static int cy8c95x0_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector, 1080 const char * const **groups, 1081 unsigned int * const num_groups) 1082 { 1083 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1084 1085 *groups = cy8c95x0_groups; 1086 *num_groups = chip->tpin; 1087 return 0; 1088 } 1089 1090 static int cy8c95x0_set_mode(struct cy8c95x0_pinctrl *chip, unsigned int off, bool mode) 1091 { 1092 u8 port = cypress_get_port(chip, off); 1093 u8 bit = cypress_get_pin_mask(chip, off); 1094 int ret; 1095 1096 /* Select port */ 1097 ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port); 1098 if (ret < 0) 1099 return ret; 1100 1101 return regmap_write_bits(chip->regmap, CY8C95X0_PWMSEL, bit, mode ? bit : 0); 1102 } 1103 1104 static int cy8c95x0_pinmux_mode(struct cy8c95x0_pinctrl *chip, 1105 unsigned int selector, unsigned int group) 1106 { 1107 u8 port = cypress_get_port(chip, group); 1108 u8 bit = cypress_get_pin_mask(chip, group); 1109 int ret; 1110 1111 ret = cy8c95x0_set_mode(chip, group, selector); 1112 if (ret < 0) 1113 return ret; 1114 1115 if (selector == 0) 1116 return 0; 1117 1118 /* Set direction to output & set output to 1 so that PWM can work */ 1119 ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, bit); 1120 if (ret < 0) 1121 return ret; 1122 1123 return regmap_write_bits(chip->regmap, CY8C95X0_OUTPUT_(port), bit, bit); 1124 } 1125 1126 static int cy8c95x0_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, 1127 unsigned int group) 1128 { 1129 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1130 int ret; 1131 1132 mutex_lock(&chip->i2c_lock); 1133 ret = cy8c95x0_pinmux_mode(chip, selector, group); 1134 mutex_unlock(&chip->i2c_lock); 1135 1136 return ret; 1137 } 1138 1139 static int cy8c95x0_gpio_request_enable(struct pinctrl_dev *pctldev, 1140 struct pinctrl_gpio_range *range, 1141 unsigned int pin) 1142 { 1143 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1144 int ret; 1145 1146 mutex_lock(&chip->i2c_lock); 1147 ret = cy8c95x0_set_mode(chip, pin, false); 1148 mutex_unlock(&chip->i2c_lock); 1149 1150 return ret; 1151 } 1152 1153 static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip, 1154 unsigned int pin, bool input) 1155 { 1156 u8 port = cypress_get_port(chip, pin); 1157 u8 bit = cypress_get_pin_mask(chip, pin); 1158 int ret; 1159 1160 /* Select port... */ 1161 ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port); 1162 if (ret) 1163 return ret; 1164 1165 /* ...then direction */ 1166 ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, input ? bit : 0); 1167 if (ret) 1168 return ret; 1169 1170 /* 1171 * Disable driving the pin by forcing it to HighZ. Only setting 1172 * the direction register isn't sufficient in Push-Pull mode. 1173 */ 1174 if (input && test_bit(pin, chip->push_pull)) { 1175 ret = regmap_write_bits(chip->regmap, CY8C95X0_DRV_HIZ, bit, bit); 1176 if (ret) 1177 return ret; 1178 1179 __clear_bit(pin, chip->push_pull); 1180 } 1181 1182 return 0; 1183 } 1184 1185 static int cy8c95x0_gpio_set_direction(struct pinctrl_dev *pctldev, 1186 struct pinctrl_gpio_range *range, 1187 unsigned int pin, bool input) 1188 { 1189 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1190 int ret; 1191 1192 mutex_lock(&chip->i2c_lock); 1193 ret = cy8c95x0_pinmux_direction(chip, pin, input); 1194 mutex_unlock(&chip->i2c_lock); 1195 1196 return ret; 1197 } 1198 1199 static const struct pinmux_ops cy8c95x0_pmxops = { 1200 .get_functions_count = cy8c95x0_get_functions_count, 1201 .get_function_name = cy8c95x0_get_function_name, 1202 .get_function_groups = cy8c95x0_get_function_groups, 1203 .set_mux = cy8c95x0_set_mux, 1204 .gpio_request_enable = cy8c95x0_gpio_request_enable, 1205 .gpio_set_direction = cy8c95x0_gpio_set_direction, 1206 .strict = true, 1207 }; 1208 1209 static int cy8c95x0_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 1210 unsigned long *config) 1211 { 1212 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1213 1214 return cy8c95x0_gpio_get_pincfg(chip, pin, config); 1215 } 1216 1217 static int cy8c95x0_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 1218 unsigned long *configs, unsigned int num_configs) 1219 { 1220 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1221 int ret = 0; 1222 int i; 1223 1224 for (i = 0; i < num_configs; i++) { 1225 ret = cy8c95x0_gpio_set_pincfg(chip, pin, configs[i]); 1226 if (ret) 1227 return ret; 1228 } 1229 1230 return ret; 1231 } 1232 1233 static const struct pinconf_ops cy8c95x0_pinconf_ops = { 1234 .pin_config_get = cy8c95x0_pinconf_get, 1235 .pin_config_set = cy8c95x0_pinconf_set, 1236 .is_generic = true, 1237 }; 1238 1239 static int cy8c95x0_irq_setup(struct cy8c95x0_pinctrl *chip, int irq) 1240 { 1241 struct gpio_irq_chip *girq = &chip->gpio_chip.irq; 1242 DECLARE_BITMAP(pending_irqs, MAX_LINE); 1243 int ret; 1244 1245 mutex_init(&chip->irq_lock); 1246 1247 bitmap_zero(pending_irqs, MAX_LINE); 1248 1249 /* Read IRQ status register to clear all pending interrupts */ 1250 ret = cy8c95x0_irq_pending(chip, pending_irqs); 1251 if (ret) { 1252 dev_err(chip->dev, "failed to clear irq status register\n"); 1253 return ret; 1254 } 1255 1256 /* Mask all interrupts */ 1257 bitmap_fill(chip->irq_mask, MAX_LINE); 1258 1259 gpio_irq_chip_set_chip(girq, &cy8c95x0_irqchip); 1260 1261 /* This will let us handle the parent IRQ in the driver */ 1262 girq->parent_handler = NULL; 1263 girq->num_parents = 0; 1264 girq->parents = NULL; 1265 girq->default_type = IRQ_TYPE_NONE; 1266 girq->handler = handle_simple_irq; 1267 girq->threaded = true; 1268 1269 ret = devm_request_threaded_irq(chip->dev, irq, 1270 NULL, cy8c95x0_irq_handler, 1271 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_HIGH, 1272 dev_name(chip->dev), chip); 1273 if (ret) { 1274 dev_err(chip->dev, "failed to request irq %d\n", irq); 1275 return ret; 1276 } 1277 dev_info(chip->dev, "Registered threaded IRQ\n"); 1278 1279 return 0; 1280 } 1281 1282 static int cy8c95x0_setup_pinctrl(struct cy8c95x0_pinctrl *chip) 1283 { 1284 struct pinctrl_desc *pd = &chip->pinctrl_desc; 1285 1286 pd->pctlops = &cy8c95x0_pinctrl_ops; 1287 pd->confops = &cy8c95x0_pinconf_ops; 1288 pd->pmxops = &cy8c95x0_pmxops; 1289 pd->name = dev_name(chip->dev); 1290 pd->pins = cy8c9560_pins; 1291 pd->npins = chip->tpin; 1292 pd->owner = THIS_MODULE; 1293 1294 chip->pctldev = devm_pinctrl_register(chip->dev, pd, chip); 1295 if (IS_ERR(chip->pctldev)) 1296 return dev_err_probe(chip->dev, PTR_ERR(chip->pctldev), 1297 "can't register controller\n"); 1298 1299 return 0; 1300 } 1301 1302 static int cy8c95x0_detect(struct i2c_client *client, 1303 struct i2c_board_info *info) 1304 { 1305 struct i2c_adapter *adapter = client->adapter; 1306 int ret; 1307 const char *name; 1308 1309 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 1310 return -ENODEV; 1311 1312 ret = i2c_smbus_read_byte_data(client, CY8C95X0_DEVID); 1313 if (ret < 0) 1314 return ret; 1315 switch (ret & GENMASK(7, 4)) { 1316 case 0x20: 1317 name = cy8c95x0_id[0].name; 1318 break; 1319 case 0x40: 1320 name = cy8c95x0_id[1].name; 1321 break; 1322 case 0x60: 1323 name = cy8c95x0_id[2].name; 1324 break; 1325 default: 1326 return -ENODEV; 1327 } 1328 1329 dev_info(&client->dev, "Found a %s chip at 0x%02x.\n", name, client->addr); 1330 strscpy(info->type, name, I2C_NAME_SIZE); 1331 1332 return 0; 1333 } 1334 1335 static int cy8c95x0_probe(struct i2c_client *client) 1336 { 1337 struct cy8c95x0_pinctrl *chip; 1338 struct regulator *reg; 1339 int ret; 1340 1341 chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); 1342 if (!chip) 1343 return -ENOMEM; 1344 1345 chip->dev = &client->dev; 1346 1347 /* Set the device type */ 1348 chip->driver_data = (unsigned long)device_get_match_data(&client->dev); 1349 if (!chip->driver_data) 1350 chip->driver_data = i2c_match_id(cy8c95x0_id, client)->driver_data; 1351 if (!chip->driver_data) 1352 return -ENODEV; 1353 1354 i2c_set_clientdata(client, chip); 1355 1356 chip->tpin = chip->driver_data & CY8C95X0_GPIO_MASK; 1357 chip->nport = DIV_ROUND_UP(CY8C95X0_PIN_TO_OFFSET(chip->tpin), BANK_SZ); 1358 1359 switch (chip->tpin) { 1360 case 20: 1361 strscpy(chip->name, cy8c95x0_id[0].name, I2C_NAME_SIZE); 1362 break; 1363 case 40: 1364 strscpy(chip->name, cy8c95x0_id[1].name, I2C_NAME_SIZE); 1365 break; 1366 case 60: 1367 strscpy(chip->name, cy8c95x0_id[2].name, I2C_NAME_SIZE); 1368 break; 1369 default: 1370 return -ENODEV; 1371 } 1372 1373 reg = devm_regulator_get(&client->dev, "vdd"); 1374 if (IS_ERR(reg)) { 1375 if (PTR_ERR(reg) == -EPROBE_DEFER) 1376 return -EPROBE_DEFER; 1377 } else { 1378 ret = regulator_enable(reg); 1379 if (ret) { 1380 dev_err(&client->dev, "failed to enable regulator vdd: %d\n", ret); 1381 return ret; 1382 } 1383 chip->regulator = reg; 1384 } 1385 1386 chip->regmap = devm_regmap_init_i2c(client, &cy8c95x0_i2c_regmap); 1387 if (IS_ERR(chip->regmap)) { 1388 ret = PTR_ERR(chip->regmap); 1389 goto err_exit; 1390 } 1391 1392 bitmap_zero(chip->push_pull, MAX_LINE); 1393 bitmap_zero(chip->shiftmask, MAX_LINE); 1394 bitmap_set(chip->shiftmask, 0, 20); 1395 mutex_init(&chip->i2c_lock); 1396 1397 if (dmi_first_match(cy8c95x0_dmi_acpi_irq_info)) { 1398 ret = cy8c95x0_acpi_get_irq(&client->dev); 1399 if (ret > 0) 1400 client->irq = ret; 1401 } 1402 1403 if (client->irq) { 1404 ret = cy8c95x0_irq_setup(chip, client->irq); 1405 if (ret) 1406 goto err_exit; 1407 } 1408 1409 ret = cy8c95x0_setup_pinctrl(chip); 1410 if (ret) 1411 goto err_exit; 1412 1413 ret = cy8c95x0_setup_gpiochip(chip); 1414 if (ret) 1415 goto err_exit; 1416 1417 return 0; 1418 1419 err_exit: 1420 if (!IS_ERR_OR_NULL(chip->regulator)) 1421 regulator_disable(chip->regulator); 1422 return ret; 1423 } 1424 1425 static void cy8c95x0_remove(struct i2c_client *client) 1426 { 1427 struct cy8c95x0_pinctrl *chip = i2c_get_clientdata(client); 1428 1429 if (!IS_ERR_OR_NULL(chip->regulator)) 1430 regulator_disable(chip->regulator); 1431 } 1432 1433 static const struct acpi_device_id cy8c95x0_acpi_ids[] = { 1434 { "INT3490", 40, }, 1435 { } 1436 }; 1437 MODULE_DEVICE_TABLE(acpi, cy8c95x0_acpi_ids); 1438 1439 static struct i2c_driver cy8c95x0_driver = { 1440 .driver = { 1441 .name = "cy8c95x0-pinctrl", 1442 .of_match_table = cy8c95x0_dt_ids, 1443 .acpi_match_table = cy8c95x0_acpi_ids, 1444 }, 1445 .probe = cy8c95x0_probe, 1446 .remove = cy8c95x0_remove, 1447 .id_table = cy8c95x0_id, 1448 .detect = cy8c95x0_detect, 1449 }; 1450 module_i2c_driver(cy8c95x0_driver); 1451 1452 MODULE_AUTHOR("Patrick Rudolph <patrick.rudolph@9elements.com>"); 1453 MODULE_AUTHOR("Naresh Solanki <naresh.solanki@9elements.com>"); 1454 MODULE_DESCRIPTION("Pinctrl driver for CY8C95X0"); 1455 MODULE_LICENSE("GPL"); 1456