1 /* 2 * at91 pinctrl driver based on at91 pinmux core 3 * 4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 5 * 6 * Under GPLv2 only 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/err.h> 11 #include <linux/init.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_device.h> 15 #include <linux/of_address.h> 16 #include <linux/of_irq.h> 17 #include <linux/slab.h> 18 #include <linux/interrupt.h> 19 #include <linux/io.h> 20 #include <linux/gpio.h> 21 #include <linux/pinctrl/machine.h> 22 #include <linux/pinctrl/pinconf.h> 23 #include <linux/pinctrl/pinctrl.h> 24 #include <linux/pinctrl/pinmux.h> 25 /* Since we request GPIOs from ourself */ 26 #include <linux/pinctrl/consumer.h> 27 28 #include "pinctrl-at91.h" 29 #include "core.h" 30 31 #define MAX_GPIO_BANKS 5 32 #define MAX_NB_GPIO_PER_BANK 32 33 34 struct at91_pinctrl_mux_ops; 35 36 struct at91_gpio_chip { 37 struct gpio_chip chip; 38 struct pinctrl_gpio_range range; 39 struct at91_gpio_chip *next; /* Bank sharing same clock */ 40 int pioc_hwirq; /* PIO bank interrupt identifier on AIC */ 41 int pioc_virq; /* PIO bank Linux virtual interrupt */ 42 int pioc_idx; /* PIO bank index */ 43 void __iomem *regbase; /* PIO bank virtual address */ 44 struct clk *clock; /* associated clock */ 45 struct at91_pinctrl_mux_ops *ops; /* ops */ 46 }; 47 48 #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip) 49 50 static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS]; 51 52 static int gpio_banks; 53 54 #define PULL_UP (1 << 0) 55 #define MULTI_DRIVE (1 << 1) 56 #define DEGLITCH (1 << 2) 57 #define PULL_DOWN (1 << 3) 58 #define DIS_SCHMIT (1 << 4) 59 #define DRIVE_STRENGTH_SHIFT 5 60 #define DRIVE_STRENGTH_MASK 0x3 61 #define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT) 62 #define DEBOUNCE (1 << 16) 63 #define DEBOUNCE_VAL_SHIFT 17 64 #define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT) 65 66 /** 67 * These defines will translated the dt binding settings to our internal 68 * settings. They are not necessarily the same value as the register setting. 69 * The actual drive strength current of low, medium and high must be looked up 70 * from the corresponding device datasheet. This value is different for pins 71 * that are even in the same banks. It is also dependent on VCC. 72 * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive 73 * strength when there is no dt config for it. 74 */ 75 #define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT) 76 #define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT) 77 #define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT) 78 #define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT) 79 80 /** 81 * struct at91_pmx_func - describes AT91 pinmux functions 82 * @name: the name of this specific function 83 * @groups: corresponding pin groups 84 * @ngroups: the number of groups 85 */ 86 struct at91_pmx_func { 87 const char *name; 88 const char **groups; 89 unsigned ngroups; 90 }; 91 92 enum at91_mux { 93 AT91_MUX_GPIO = 0, 94 AT91_MUX_PERIPH_A = 1, 95 AT91_MUX_PERIPH_B = 2, 96 AT91_MUX_PERIPH_C = 3, 97 AT91_MUX_PERIPH_D = 4, 98 }; 99 100 /** 101 * struct at91_pmx_pin - describes an At91 pin mux 102 * @bank: the bank of the pin 103 * @pin: the pin number in the @bank 104 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function. 105 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc... 106 */ 107 struct at91_pmx_pin { 108 uint32_t bank; 109 uint32_t pin; 110 enum at91_mux mux; 111 unsigned long conf; 112 }; 113 114 /** 115 * struct at91_pin_group - describes an At91 pin group 116 * @name: the name of this specific pin group 117 * @pins_conf: the mux mode for each pin in this group. The size of this 118 * array is the same as pins. 119 * @pins: an array of discrete physical pins used in this group, taken 120 * from the driver-local pin enumeration space 121 * @npins: the number of pins in this group array, i.e. the number of 122 * elements in .pins so we can iterate over that array 123 */ 124 struct at91_pin_group { 125 const char *name; 126 struct at91_pmx_pin *pins_conf; 127 unsigned int *pins; 128 unsigned npins; 129 }; 130 131 /** 132 * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group 133 * on new IP with support for periph C and D the way to mux in 134 * periph A and B has changed 135 * So provide the right call back 136 * if not present means the IP does not support it 137 * @get_periph: return the periph mode configured 138 * @mux_A_periph: mux as periph A 139 * @mux_B_periph: mux as periph B 140 * @mux_C_periph: mux as periph C 141 * @mux_D_periph: mux as periph D 142 * @get_deglitch: get deglitch status 143 * @set_deglitch: enable/disable deglitch 144 * @get_debounce: get debounce status 145 * @set_debounce: enable/disable debounce 146 * @get_pulldown: get pulldown status 147 * @set_pulldown: enable/disable pulldown 148 * @get_schmitt_trig: get schmitt trigger status 149 * @disable_schmitt_trig: disable schmitt trigger 150 * @irq_type: return irq type 151 */ 152 struct at91_pinctrl_mux_ops { 153 enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask); 154 void (*mux_A_periph)(void __iomem *pio, unsigned mask); 155 void (*mux_B_periph)(void __iomem *pio, unsigned mask); 156 void (*mux_C_periph)(void __iomem *pio, unsigned mask); 157 void (*mux_D_periph)(void __iomem *pio, unsigned mask); 158 bool (*get_deglitch)(void __iomem *pio, unsigned pin); 159 void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on); 160 bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div); 161 void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div); 162 bool (*get_pulldown)(void __iomem *pio, unsigned pin); 163 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on); 164 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin); 165 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask); 166 unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin); 167 void (*set_drivestrength)(void __iomem *pio, unsigned pin, 168 u32 strength); 169 /* irq */ 170 int (*irq_type)(struct irq_data *d, unsigned type); 171 }; 172 173 static int gpio_irq_type(struct irq_data *d, unsigned type); 174 static int alt_gpio_irq_type(struct irq_data *d, unsigned type); 175 176 struct at91_pinctrl { 177 struct device *dev; 178 struct pinctrl_dev *pctl; 179 180 int nbanks; 181 182 uint32_t *mux_mask; 183 int nmux; 184 185 struct at91_pmx_func *functions; 186 int nfunctions; 187 188 struct at91_pin_group *groups; 189 int ngroups; 190 191 struct at91_pinctrl_mux_ops *ops; 192 }; 193 194 static const inline struct at91_pin_group *at91_pinctrl_find_group_by_name( 195 const struct at91_pinctrl *info, 196 const char *name) 197 { 198 const struct at91_pin_group *grp = NULL; 199 int i; 200 201 for (i = 0; i < info->ngroups; i++) { 202 if (strcmp(info->groups[i].name, name)) 203 continue; 204 205 grp = &info->groups[i]; 206 dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]); 207 break; 208 } 209 210 return grp; 211 } 212 213 static int at91_get_groups_count(struct pinctrl_dev *pctldev) 214 { 215 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 216 217 return info->ngroups; 218 } 219 220 static const char *at91_get_group_name(struct pinctrl_dev *pctldev, 221 unsigned selector) 222 { 223 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 224 225 return info->groups[selector].name; 226 } 227 228 static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, 229 const unsigned **pins, 230 unsigned *npins) 231 { 232 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 233 234 if (selector >= info->ngroups) 235 return -EINVAL; 236 237 *pins = info->groups[selector].pins; 238 *npins = info->groups[selector].npins; 239 240 return 0; 241 } 242 243 static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 244 unsigned offset) 245 { 246 seq_printf(s, "%s", dev_name(pctldev->dev)); 247 } 248 249 static int at91_dt_node_to_map(struct pinctrl_dev *pctldev, 250 struct device_node *np, 251 struct pinctrl_map **map, unsigned *num_maps) 252 { 253 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 254 const struct at91_pin_group *grp; 255 struct pinctrl_map *new_map; 256 struct device_node *parent; 257 int map_num = 1; 258 int i; 259 260 /* 261 * first find the group of this node and check if we need to create 262 * config maps for pins 263 */ 264 grp = at91_pinctrl_find_group_by_name(info, np->name); 265 if (!grp) { 266 dev_err(info->dev, "unable to find group for node %s\n", 267 np->name); 268 return -EINVAL; 269 } 270 271 map_num += grp->npins; 272 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, GFP_KERNEL); 273 if (!new_map) 274 return -ENOMEM; 275 276 *map = new_map; 277 *num_maps = map_num; 278 279 /* create mux map */ 280 parent = of_get_parent(np); 281 if (!parent) { 282 devm_kfree(pctldev->dev, new_map); 283 return -EINVAL; 284 } 285 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 286 new_map[0].data.mux.function = parent->name; 287 new_map[0].data.mux.group = np->name; 288 of_node_put(parent); 289 290 /* create config map */ 291 new_map++; 292 for (i = 0; i < grp->npins; i++) { 293 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 294 new_map[i].data.configs.group_or_pin = 295 pin_get_name(pctldev, grp->pins[i]); 296 new_map[i].data.configs.configs = &grp->pins_conf[i].conf; 297 new_map[i].data.configs.num_configs = 1; 298 } 299 300 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 301 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 302 303 return 0; 304 } 305 306 static void at91_dt_free_map(struct pinctrl_dev *pctldev, 307 struct pinctrl_map *map, unsigned num_maps) 308 { 309 } 310 311 static const struct pinctrl_ops at91_pctrl_ops = { 312 .get_groups_count = at91_get_groups_count, 313 .get_group_name = at91_get_group_name, 314 .get_group_pins = at91_get_group_pins, 315 .pin_dbg_show = at91_pin_dbg_show, 316 .dt_node_to_map = at91_dt_node_to_map, 317 .dt_free_map = at91_dt_free_map, 318 }; 319 320 static void __iomem *pin_to_controller(struct at91_pinctrl *info, 321 unsigned int bank) 322 { 323 return gpio_chips[bank]->regbase; 324 } 325 326 static inline int pin_to_bank(unsigned pin) 327 { 328 return pin /= MAX_NB_GPIO_PER_BANK; 329 } 330 331 static unsigned pin_to_mask(unsigned int pin) 332 { 333 return 1 << pin; 334 } 335 336 static unsigned two_bit_pin_value_shift_amount(unsigned int pin) 337 { 338 /* return the shift value for a pin for "two bit" per pin registers, 339 * i.e. drive strength */ 340 return 2*((pin >= MAX_NB_GPIO_PER_BANK/2) 341 ? pin - MAX_NB_GPIO_PER_BANK/2 : pin); 342 } 343 344 static unsigned sama5d3_get_drive_register(unsigned int pin) 345 { 346 /* drive strength is split between two registers 347 * with two bits per pin */ 348 return (pin >= MAX_NB_GPIO_PER_BANK/2) 349 ? SAMA5D3_PIO_DRIVER2 : SAMA5D3_PIO_DRIVER1; 350 } 351 352 static unsigned at91sam9x5_get_drive_register(unsigned int pin) 353 { 354 /* drive strength is split between two registers 355 * with two bits per pin */ 356 return (pin >= MAX_NB_GPIO_PER_BANK/2) 357 ? AT91SAM9X5_PIO_DRIVER2 : AT91SAM9X5_PIO_DRIVER1; 358 } 359 360 static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask) 361 { 362 writel_relaxed(mask, pio + PIO_IDR); 363 } 364 365 static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin) 366 { 367 return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1); 368 } 369 370 static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on) 371 { 372 if (on) 373 writel_relaxed(mask, pio + PIO_PPDDR); 374 375 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR)); 376 } 377 378 static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin) 379 { 380 return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1; 381 } 382 383 static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on) 384 { 385 writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR)); 386 } 387 388 static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask) 389 { 390 writel_relaxed(mask, pio + PIO_ASR); 391 } 392 393 static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask) 394 { 395 writel_relaxed(mask, pio + PIO_BSR); 396 } 397 398 static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask) 399 { 400 401 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, 402 pio + PIO_ABCDSR1); 403 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, 404 pio + PIO_ABCDSR2); 405 } 406 407 static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask) 408 { 409 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, 410 pio + PIO_ABCDSR1); 411 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, 412 pio + PIO_ABCDSR2); 413 } 414 415 static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask) 416 { 417 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1); 418 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); 419 } 420 421 static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask) 422 { 423 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1); 424 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); 425 } 426 427 static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask) 428 { 429 unsigned select; 430 431 if (readl_relaxed(pio + PIO_PSR) & mask) 432 return AT91_MUX_GPIO; 433 434 select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask); 435 select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1); 436 437 return select + 1; 438 } 439 440 static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask) 441 { 442 unsigned select; 443 444 if (readl_relaxed(pio + PIO_PSR) & mask) 445 return AT91_MUX_GPIO; 446 447 select = readl_relaxed(pio + PIO_ABSR) & mask; 448 449 return select + 1; 450 } 451 452 static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin) 453 { 454 return (__raw_readl(pio + PIO_IFSR) >> pin) & 0x1; 455 } 456 457 static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) 458 { 459 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); 460 } 461 462 static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin) 463 { 464 if ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1) 465 return !((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1); 466 467 return false; 468 } 469 470 static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) 471 { 472 if (is_on) 473 __raw_writel(mask, pio + PIO_IFSCDR); 474 at91_mux_set_deglitch(pio, mask, is_on); 475 } 476 477 static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div) 478 { 479 *div = __raw_readl(pio + PIO_SCDR); 480 481 return ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1) && 482 ((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1); 483 } 484 485 static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask, 486 bool is_on, u32 div) 487 { 488 if (is_on) { 489 __raw_writel(mask, pio + PIO_IFSCER); 490 __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR); 491 __raw_writel(mask, pio + PIO_IFER); 492 } else 493 __raw_writel(mask, pio + PIO_IFSCDR); 494 } 495 496 static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin) 497 { 498 return !((__raw_readl(pio + PIO_PPDSR) >> pin) & 0x1); 499 } 500 501 static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on) 502 { 503 if (is_on) 504 __raw_writel(mask, pio + PIO_PUDR); 505 506 __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR)); 507 } 508 509 static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask) 510 { 511 __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT); 512 } 513 514 static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin) 515 { 516 return (__raw_readl(pio + PIO_SCHMITT) >> pin) & 0x1; 517 } 518 519 static inline u32 read_drive_strength(void __iomem *reg, unsigned pin) 520 { 521 unsigned tmp = __raw_readl(reg); 522 523 tmp = tmp >> two_bit_pin_value_shift_amount(pin); 524 525 return tmp & DRIVE_STRENGTH_MASK; 526 } 527 528 static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio, 529 unsigned pin) 530 { 531 unsigned tmp = read_drive_strength(pio + 532 sama5d3_get_drive_register(pin), pin); 533 534 /* SAMA5 strength is 1:1 with our defines, 535 * except 0 is equivalent to low per datasheet */ 536 if (!tmp) 537 tmp = DRIVE_STRENGTH_LOW; 538 539 return tmp; 540 } 541 542 static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio, 543 unsigned pin) 544 { 545 unsigned tmp = read_drive_strength(pio + 546 at91sam9x5_get_drive_register(pin), pin); 547 548 /* strength is inverse in SAM9x5s hardware with the pinctrl defines 549 * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */ 550 tmp = DRIVE_STRENGTH_HI - tmp; 551 552 return tmp; 553 } 554 555 static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength) 556 { 557 unsigned tmp = __raw_readl(reg); 558 unsigned shift = two_bit_pin_value_shift_amount(pin); 559 560 tmp &= ~(DRIVE_STRENGTH_MASK << shift); 561 tmp |= strength << shift; 562 563 __raw_writel(tmp, reg); 564 } 565 566 static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin, 567 u32 setting) 568 { 569 /* do nothing if setting is zero */ 570 if (!setting) 571 return; 572 573 /* strength is 1 to 1 with setting for SAMA5 */ 574 set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting); 575 } 576 577 static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin, 578 u32 setting) 579 { 580 /* do nothing if setting is zero */ 581 if (!setting) 582 return; 583 584 /* strength is inverse on SAM9x5s with our defines 585 * 0 = hi, 1 = med, 2 = low, 3 = rsvd */ 586 setting = DRIVE_STRENGTH_HI - setting; 587 588 set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin, 589 setting); 590 } 591 592 static struct at91_pinctrl_mux_ops at91rm9200_ops = { 593 .get_periph = at91_mux_get_periph, 594 .mux_A_periph = at91_mux_set_A_periph, 595 .mux_B_periph = at91_mux_set_B_periph, 596 .get_deglitch = at91_mux_get_deglitch, 597 .set_deglitch = at91_mux_set_deglitch, 598 .irq_type = gpio_irq_type, 599 }; 600 601 static struct at91_pinctrl_mux_ops at91sam9x5_ops = { 602 .get_periph = at91_mux_pio3_get_periph, 603 .mux_A_periph = at91_mux_pio3_set_A_periph, 604 .mux_B_periph = at91_mux_pio3_set_B_periph, 605 .mux_C_periph = at91_mux_pio3_set_C_periph, 606 .mux_D_periph = at91_mux_pio3_set_D_periph, 607 .get_deglitch = at91_mux_pio3_get_deglitch, 608 .set_deglitch = at91_mux_pio3_set_deglitch, 609 .get_debounce = at91_mux_pio3_get_debounce, 610 .set_debounce = at91_mux_pio3_set_debounce, 611 .get_pulldown = at91_mux_pio3_get_pulldown, 612 .set_pulldown = at91_mux_pio3_set_pulldown, 613 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig, 614 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig, 615 .get_drivestrength = at91_mux_sam9x5_get_drivestrength, 616 .set_drivestrength = at91_mux_sam9x5_set_drivestrength, 617 .irq_type = alt_gpio_irq_type, 618 }; 619 620 static struct at91_pinctrl_mux_ops sama5d3_ops = { 621 .get_periph = at91_mux_pio3_get_periph, 622 .mux_A_periph = at91_mux_pio3_set_A_periph, 623 .mux_B_periph = at91_mux_pio3_set_B_periph, 624 .mux_C_periph = at91_mux_pio3_set_C_periph, 625 .mux_D_periph = at91_mux_pio3_set_D_periph, 626 .get_deglitch = at91_mux_pio3_get_deglitch, 627 .set_deglitch = at91_mux_pio3_set_deglitch, 628 .get_debounce = at91_mux_pio3_get_debounce, 629 .set_debounce = at91_mux_pio3_set_debounce, 630 .get_pulldown = at91_mux_pio3_get_pulldown, 631 .set_pulldown = at91_mux_pio3_set_pulldown, 632 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig, 633 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig, 634 .get_drivestrength = at91_mux_sama5d3_get_drivestrength, 635 .set_drivestrength = at91_mux_sama5d3_set_drivestrength, 636 .irq_type = alt_gpio_irq_type, 637 }; 638 639 static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin) 640 { 641 if (pin->mux) { 642 dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lx\n", 643 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf); 644 } else { 645 dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lx\n", 646 pin->bank + 'A', pin->pin, pin->conf); 647 } 648 } 649 650 static int pin_check_config(struct at91_pinctrl *info, const char *name, 651 int index, const struct at91_pmx_pin *pin) 652 { 653 int mux; 654 655 /* check if it's a valid config */ 656 if (pin->bank >= info->nbanks) { 657 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n", 658 name, index, pin->bank, info->nbanks); 659 return -EINVAL; 660 } 661 662 if (pin->pin >= MAX_NB_GPIO_PER_BANK) { 663 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n", 664 name, index, pin->pin, MAX_NB_GPIO_PER_BANK); 665 return -EINVAL; 666 } 667 668 if (!pin->mux) 669 return 0; 670 671 mux = pin->mux - 1; 672 673 if (mux >= info->nmux) { 674 dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n", 675 name, index, mux, info->nmux); 676 return -EINVAL; 677 } 678 679 if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) { 680 dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n", 681 name, index, mux, pin->bank + 'A', pin->pin); 682 return -EINVAL; 683 } 684 685 return 0; 686 } 687 688 static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask) 689 { 690 writel_relaxed(mask, pio + PIO_PDR); 691 } 692 693 static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input) 694 { 695 writel_relaxed(mask, pio + PIO_PER); 696 writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER)); 697 } 698 699 static int at91_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 700 unsigned group) 701 { 702 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 703 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf; 704 const struct at91_pmx_pin *pin; 705 uint32_t npins = info->groups[group].npins; 706 int i, ret; 707 unsigned mask; 708 void __iomem *pio; 709 710 dev_dbg(info->dev, "enable function %s group %s\n", 711 info->functions[selector].name, info->groups[group].name); 712 713 /* first check that all the pins of the group are valid with a valid 714 * parameter */ 715 for (i = 0; i < npins; i++) { 716 pin = &pins_conf[i]; 717 ret = pin_check_config(info, info->groups[group].name, i, pin); 718 if (ret) 719 return ret; 720 } 721 722 for (i = 0; i < npins; i++) { 723 pin = &pins_conf[i]; 724 at91_pin_dbg(info->dev, pin); 725 pio = pin_to_controller(info, pin->bank); 726 mask = pin_to_mask(pin->pin); 727 at91_mux_disable_interrupt(pio, mask); 728 switch (pin->mux) { 729 case AT91_MUX_GPIO: 730 at91_mux_gpio_enable(pio, mask, 1); 731 break; 732 case AT91_MUX_PERIPH_A: 733 info->ops->mux_A_periph(pio, mask); 734 break; 735 case AT91_MUX_PERIPH_B: 736 info->ops->mux_B_periph(pio, mask); 737 break; 738 case AT91_MUX_PERIPH_C: 739 if (!info->ops->mux_C_periph) 740 return -EINVAL; 741 info->ops->mux_C_periph(pio, mask); 742 break; 743 case AT91_MUX_PERIPH_D: 744 if (!info->ops->mux_D_periph) 745 return -EINVAL; 746 info->ops->mux_D_periph(pio, mask); 747 break; 748 } 749 if (pin->mux) 750 at91_mux_gpio_disable(pio, mask); 751 } 752 753 return 0; 754 } 755 756 static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 757 { 758 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 759 760 return info->nfunctions; 761 } 762 763 static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev, 764 unsigned selector) 765 { 766 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 767 768 return info->functions[selector].name; 769 } 770 771 static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, 772 const char * const **groups, 773 unsigned * const num_groups) 774 { 775 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 776 777 *groups = info->functions[selector].groups; 778 *num_groups = info->functions[selector].ngroups; 779 780 return 0; 781 } 782 783 static int at91_gpio_request_enable(struct pinctrl_dev *pctldev, 784 struct pinctrl_gpio_range *range, 785 unsigned offset) 786 { 787 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 788 struct at91_gpio_chip *at91_chip; 789 struct gpio_chip *chip; 790 unsigned mask; 791 792 if (!range) { 793 dev_err(npct->dev, "invalid range\n"); 794 return -EINVAL; 795 } 796 if (!range->gc) { 797 dev_err(npct->dev, "missing GPIO chip in range\n"); 798 return -EINVAL; 799 } 800 chip = range->gc; 801 at91_chip = container_of(chip, struct at91_gpio_chip, chip); 802 803 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); 804 805 mask = 1 << (offset - chip->base); 806 807 dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n", 808 offset, 'A' + range->id, offset - chip->base, mask); 809 810 writel_relaxed(mask, at91_chip->regbase + PIO_PER); 811 812 return 0; 813 } 814 815 static void at91_gpio_disable_free(struct pinctrl_dev *pctldev, 816 struct pinctrl_gpio_range *range, 817 unsigned offset) 818 { 819 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 820 821 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); 822 /* Set the pin to some default state, GPIO is usually default */ 823 } 824 825 static const struct pinmux_ops at91_pmx_ops = { 826 .get_functions_count = at91_pmx_get_funcs_count, 827 .get_function_name = at91_pmx_get_func_name, 828 .get_function_groups = at91_pmx_get_groups, 829 .set_mux = at91_pmx_set, 830 .gpio_request_enable = at91_gpio_request_enable, 831 .gpio_disable_free = at91_gpio_disable_free, 832 }; 833 834 static int at91_pinconf_get(struct pinctrl_dev *pctldev, 835 unsigned pin_id, unsigned long *config) 836 { 837 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 838 void __iomem *pio; 839 unsigned pin; 840 int div; 841 842 *config = 0; 843 dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id); 844 pio = pin_to_controller(info, pin_to_bank(pin_id)); 845 pin = pin_id % MAX_NB_GPIO_PER_BANK; 846 847 if (at91_mux_get_multidrive(pio, pin)) 848 *config |= MULTI_DRIVE; 849 850 if (at91_mux_get_pullup(pio, pin)) 851 *config |= PULL_UP; 852 853 if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin)) 854 *config |= DEGLITCH; 855 if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div)) 856 *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT); 857 if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin)) 858 *config |= PULL_DOWN; 859 if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin)) 860 *config |= DIS_SCHMIT; 861 if (info->ops->get_drivestrength) 862 *config |= (info->ops->get_drivestrength(pio, pin) 863 << DRIVE_STRENGTH_SHIFT); 864 865 return 0; 866 } 867 868 static int at91_pinconf_set(struct pinctrl_dev *pctldev, 869 unsigned pin_id, unsigned long *configs, 870 unsigned num_configs) 871 { 872 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 873 unsigned mask; 874 void __iomem *pio; 875 int i; 876 unsigned long config; 877 unsigned pin; 878 879 for (i = 0; i < num_configs; i++) { 880 config = configs[i]; 881 882 dev_dbg(info->dev, 883 "%s:%d, pin_id=%d, config=0x%lx", 884 __func__, __LINE__, pin_id, config); 885 pio = pin_to_controller(info, pin_to_bank(pin_id)); 886 pin = pin_id % MAX_NB_GPIO_PER_BANK; 887 mask = pin_to_mask(pin); 888 889 if (config & PULL_UP && config & PULL_DOWN) 890 return -EINVAL; 891 892 at91_mux_set_pullup(pio, mask, config & PULL_UP); 893 at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE); 894 if (info->ops->set_deglitch) 895 info->ops->set_deglitch(pio, mask, config & DEGLITCH); 896 if (info->ops->set_debounce) 897 info->ops->set_debounce(pio, mask, config & DEBOUNCE, 898 (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT); 899 if (info->ops->set_pulldown) 900 info->ops->set_pulldown(pio, mask, config & PULL_DOWN); 901 if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT) 902 info->ops->disable_schmitt_trig(pio, mask); 903 if (info->ops->set_drivestrength) 904 info->ops->set_drivestrength(pio, pin, 905 (config & DRIVE_STRENGTH) 906 >> DRIVE_STRENGTH_SHIFT); 907 908 } /* for each config */ 909 910 return 0; 911 } 912 913 #define DBG_SHOW_FLAG(flag) do { \ 914 if (config & flag) { \ 915 if (num_conf) \ 916 seq_puts(s, "|"); \ 917 seq_puts(s, #flag); \ 918 num_conf++; \ 919 } \ 920 } while (0) 921 922 #define DBG_SHOW_FLAG_MASKED(mask,flag) do { \ 923 if ((config & mask) == flag) { \ 924 if (num_conf) \ 925 seq_puts(s, "|"); \ 926 seq_puts(s, #flag); \ 927 num_conf++; \ 928 } \ 929 } while (0) 930 931 static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev, 932 struct seq_file *s, unsigned pin_id) 933 { 934 unsigned long config; 935 int val, num_conf = 0; 936 937 at91_pinconf_get(pctldev, pin_id, &config); 938 939 DBG_SHOW_FLAG(MULTI_DRIVE); 940 DBG_SHOW_FLAG(PULL_UP); 941 DBG_SHOW_FLAG(PULL_DOWN); 942 DBG_SHOW_FLAG(DIS_SCHMIT); 943 DBG_SHOW_FLAG(DEGLITCH); 944 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW); 945 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED); 946 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI); 947 DBG_SHOW_FLAG(DEBOUNCE); 948 if (config & DEBOUNCE) { 949 val = config >> DEBOUNCE_VAL_SHIFT; 950 seq_printf(s, "(%d)", val); 951 } 952 953 return; 954 } 955 956 static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 957 struct seq_file *s, unsigned group) 958 { 959 } 960 961 static const struct pinconf_ops at91_pinconf_ops = { 962 .pin_config_get = at91_pinconf_get, 963 .pin_config_set = at91_pinconf_set, 964 .pin_config_dbg_show = at91_pinconf_dbg_show, 965 .pin_config_group_dbg_show = at91_pinconf_group_dbg_show, 966 }; 967 968 static struct pinctrl_desc at91_pinctrl_desc = { 969 .pctlops = &at91_pctrl_ops, 970 .pmxops = &at91_pmx_ops, 971 .confops = &at91_pinconf_ops, 972 .owner = THIS_MODULE, 973 }; 974 975 static const char *gpio_compat = "atmel,at91rm9200-gpio"; 976 977 static void at91_pinctrl_child_count(struct at91_pinctrl *info, 978 struct device_node *np) 979 { 980 struct device_node *child; 981 982 for_each_child_of_node(np, child) { 983 if (of_device_is_compatible(child, gpio_compat)) { 984 info->nbanks++; 985 } else { 986 info->nfunctions++; 987 info->ngroups += of_get_child_count(child); 988 } 989 } 990 } 991 992 static int at91_pinctrl_mux_mask(struct at91_pinctrl *info, 993 struct device_node *np) 994 { 995 int ret = 0; 996 int size; 997 const __be32 *list; 998 999 list = of_get_property(np, "atmel,mux-mask", &size); 1000 if (!list) { 1001 dev_err(info->dev, "can not read the mux-mask of %d\n", size); 1002 return -EINVAL; 1003 } 1004 1005 size /= sizeof(*list); 1006 if (!size || size % info->nbanks) { 1007 dev_err(info->dev, "wrong mux mask array should be by %d\n", info->nbanks); 1008 return -EINVAL; 1009 } 1010 info->nmux = size / info->nbanks; 1011 1012 info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL); 1013 if (!info->mux_mask) { 1014 dev_err(info->dev, "could not alloc mux_mask\n"); 1015 return -ENOMEM; 1016 } 1017 1018 ret = of_property_read_u32_array(np, "atmel,mux-mask", 1019 info->mux_mask, size); 1020 if (ret) 1021 dev_err(info->dev, "can not read the mux-mask of %d\n", size); 1022 return ret; 1023 } 1024 1025 static int at91_pinctrl_parse_groups(struct device_node *np, 1026 struct at91_pin_group *grp, 1027 struct at91_pinctrl *info, u32 index) 1028 { 1029 struct at91_pmx_pin *pin; 1030 int size; 1031 const __be32 *list; 1032 int i, j; 1033 1034 dev_dbg(info->dev, "group(%d): %s\n", index, np->name); 1035 1036 /* Initialise group */ 1037 grp->name = np->name; 1038 1039 /* 1040 * the binding format is atmel,pins = <bank pin mux CONFIG ...>, 1041 * do sanity check and calculate pins number 1042 */ 1043 list = of_get_property(np, "atmel,pins", &size); 1044 /* we do not check return since it's safe node passed down */ 1045 size /= sizeof(*list); 1046 if (!size || size % 4) { 1047 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); 1048 return -EINVAL; 1049 } 1050 1051 grp->npins = size / 4; 1052 pin = grp->pins_conf = devm_kzalloc(info->dev, grp->npins * sizeof(struct at91_pmx_pin), 1053 GFP_KERNEL); 1054 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), 1055 GFP_KERNEL); 1056 if (!grp->pins_conf || !grp->pins) 1057 return -ENOMEM; 1058 1059 for (i = 0, j = 0; i < size; i += 4, j++) { 1060 pin->bank = be32_to_cpu(*list++); 1061 pin->pin = be32_to_cpu(*list++); 1062 grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin; 1063 pin->mux = be32_to_cpu(*list++); 1064 pin->conf = be32_to_cpu(*list++); 1065 1066 at91_pin_dbg(info->dev, pin); 1067 pin++; 1068 } 1069 1070 return 0; 1071 } 1072 1073 static int at91_pinctrl_parse_functions(struct device_node *np, 1074 struct at91_pinctrl *info, u32 index) 1075 { 1076 struct device_node *child; 1077 struct at91_pmx_func *func; 1078 struct at91_pin_group *grp; 1079 int ret; 1080 static u32 grp_index; 1081 u32 i = 0; 1082 1083 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); 1084 1085 func = &info->functions[index]; 1086 1087 /* Initialise function */ 1088 func->name = np->name; 1089 func->ngroups = of_get_child_count(np); 1090 if (func->ngroups == 0) { 1091 dev_err(info->dev, "no groups defined\n"); 1092 return -EINVAL; 1093 } 1094 func->groups = devm_kzalloc(info->dev, 1095 func->ngroups * sizeof(char *), GFP_KERNEL); 1096 if (!func->groups) 1097 return -ENOMEM; 1098 1099 for_each_child_of_node(np, child) { 1100 func->groups[i] = child->name; 1101 grp = &info->groups[grp_index++]; 1102 ret = at91_pinctrl_parse_groups(child, grp, info, i++); 1103 if (ret) 1104 return ret; 1105 } 1106 1107 return 0; 1108 } 1109 1110 static struct of_device_id at91_pinctrl_of_match[] = { 1111 { .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops }, 1112 { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops }, 1113 { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops }, 1114 { /* sentinel */ } 1115 }; 1116 1117 static int at91_pinctrl_probe_dt(struct platform_device *pdev, 1118 struct at91_pinctrl *info) 1119 { 1120 int ret = 0; 1121 int i, j; 1122 uint32_t *tmp; 1123 struct device_node *np = pdev->dev.of_node; 1124 struct device_node *child; 1125 1126 if (!np) 1127 return -ENODEV; 1128 1129 info->dev = &pdev->dev; 1130 info->ops = (struct at91_pinctrl_mux_ops *) 1131 of_match_device(at91_pinctrl_of_match, &pdev->dev)->data; 1132 at91_pinctrl_child_count(info, np); 1133 1134 if (info->nbanks < 1) { 1135 dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n"); 1136 return -EINVAL; 1137 } 1138 1139 ret = at91_pinctrl_mux_mask(info, np); 1140 if (ret) 1141 return ret; 1142 1143 dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux); 1144 1145 dev_dbg(&pdev->dev, "mux-mask\n"); 1146 tmp = info->mux_mask; 1147 for (i = 0; i < info->nbanks; i++) { 1148 for (j = 0; j < info->nmux; j++, tmp++) { 1149 dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]); 1150 } 1151 } 1152 1153 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 1154 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 1155 info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * sizeof(struct at91_pmx_func), 1156 GFP_KERNEL); 1157 if (!info->functions) 1158 return -ENOMEM; 1159 1160 info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct at91_pin_group), 1161 GFP_KERNEL); 1162 if (!info->groups) 1163 return -ENOMEM; 1164 1165 dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks); 1166 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 1167 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 1168 1169 i = 0; 1170 1171 for_each_child_of_node(np, child) { 1172 if (of_device_is_compatible(child, gpio_compat)) 1173 continue; 1174 ret = at91_pinctrl_parse_functions(child, info, i++); 1175 if (ret) { 1176 dev_err(&pdev->dev, "failed to parse function\n"); 1177 return ret; 1178 } 1179 } 1180 1181 return 0; 1182 } 1183 1184 static int at91_pinctrl_probe(struct platform_device *pdev) 1185 { 1186 struct at91_pinctrl *info; 1187 struct pinctrl_pin_desc *pdesc; 1188 int ret, i, j, k; 1189 1190 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); 1191 if (!info) 1192 return -ENOMEM; 1193 1194 ret = at91_pinctrl_probe_dt(pdev, info); 1195 if (ret) 1196 return ret; 1197 1198 /* 1199 * We need all the GPIO drivers to probe FIRST, or we will not be able 1200 * to obtain references to the struct gpio_chip * for them, and we 1201 * need this to proceed. 1202 */ 1203 for (i = 0; i < info->nbanks; i++) { 1204 if (!gpio_chips[i]) { 1205 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i); 1206 devm_kfree(&pdev->dev, info); 1207 return -EPROBE_DEFER; 1208 } 1209 } 1210 1211 at91_pinctrl_desc.name = dev_name(&pdev->dev); 1212 at91_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK; 1213 at91_pinctrl_desc.pins = pdesc = 1214 devm_kzalloc(&pdev->dev, sizeof(*pdesc) * at91_pinctrl_desc.npins, GFP_KERNEL); 1215 1216 if (!at91_pinctrl_desc.pins) 1217 return -ENOMEM; 1218 1219 for (i = 0 , k = 0; i < info->nbanks; i++) { 1220 for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) { 1221 pdesc->number = k; 1222 pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j); 1223 pdesc++; 1224 } 1225 } 1226 1227 platform_set_drvdata(pdev, info); 1228 info->pctl = pinctrl_register(&at91_pinctrl_desc, &pdev->dev, info); 1229 1230 if (!info->pctl) { 1231 dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n"); 1232 ret = -EINVAL; 1233 goto err; 1234 } 1235 1236 /* We will handle a range of GPIO pins */ 1237 for (i = 0; i < info->nbanks; i++) 1238 pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range); 1239 1240 dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n"); 1241 1242 return 0; 1243 1244 err: 1245 return ret; 1246 } 1247 1248 static int at91_pinctrl_remove(struct platform_device *pdev) 1249 { 1250 struct at91_pinctrl *info = platform_get_drvdata(pdev); 1251 1252 pinctrl_unregister(info->pctl); 1253 1254 return 0; 1255 } 1256 1257 static int at91_gpio_request(struct gpio_chip *chip, unsigned offset) 1258 { 1259 /* 1260 * Map back to global GPIO space and request muxing, the direction 1261 * parameter does not matter for this controller. 1262 */ 1263 int gpio = chip->base + offset; 1264 int bank = chip->base / chip->ngpio; 1265 1266 dev_dbg(chip->dev, "%s:%d pio%c%d(%d)\n", __func__, __LINE__, 1267 'A' + bank, offset, gpio); 1268 1269 return pinctrl_request_gpio(gpio); 1270 } 1271 1272 static void at91_gpio_free(struct gpio_chip *chip, unsigned offset) 1273 { 1274 int gpio = chip->base + offset; 1275 1276 pinctrl_free_gpio(gpio); 1277 } 1278 1279 static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 1280 { 1281 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 1282 void __iomem *pio = at91_gpio->regbase; 1283 unsigned mask = 1 << offset; 1284 u32 osr; 1285 1286 osr = readl_relaxed(pio + PIO_OSR); 1287 return !(osr & mask); 1288 } 1289 1290 static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 1291 { 1292 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 1293 void __iomem *pio = at91_gpio->regbase; 1294 unsigned mask = 1 << offset; 1295 1296 writel_relaxed(mask, pio + PIO_ODR); 1297 return 0; 1298 } 1299 1300 static int at91_gpio_get(struct gpio_chip *chip, unsigned offset) 1301 { 1302 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 1303 void __iomem *pio = at91_gpio->regbase; 1304 unsigned mask = 1 << offset; 1305 u32 pdsr; 1306 1307 pdsr = readl_relaxed(pio + PIO_PDSR); 1308 return (pdsr & mask) != 0; 1309 } 1310 1311 static void at91_gpio_set(struct gpio_chip *chip, unsigned offset, 1312 int val) 1313 { 1314 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 1315 void __iomem *pio = at91_gpio->regbase; 1316 unsigned mask = 1 << offset; 1317 1318 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); 1319 } 1320 1321 static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 1322 int val) 1323 { 1324 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 1325 void __iomem *pio = at91_gpio->regbase; 1326 unsigned mask = 1 << offset; 1327 1328 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); 1329 writel_relaxed(mask, pio + PIO_OER); 1330 1331 return 0; 1332 } 1333 1334 #ifdef CONFIG_DEBUG_FS 1335 static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 1336 { 1337 enum at91_mux mode; 1338 int i; 1339 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 1340 void __iomem *pio = at91_gpio->regbase; 1341 1342 for (i = 0; i < chip->ngpio; i++) { 1343 unsigned mask = pin_to_mask(i); 1344 const char *gpio_label; 1345 1346 gpio_label = gpiochip_is_requested(chip, i); 1347 if (!gpio_label) 1348 continue; 1349 mode = at91_gpio->ops->get_periph(pio, mask); 1350 seq_printf(s, "[%s] GPIO%s%d: ", 1351 gpio_label, chip->label, i); 1352 if (mode == AT91_MUX_GPIO) { 1353 seq_printf(s, "[gpio] "); 1354 seq_printf(s, "%s ", 1355 readl_relaxed(pio + PIO_OSR) & mask ? 1356 "output" : "input"); 1357 seq_printf(s, "%s\n", 1358 readl_relaxed(pio + PIO_PDSR) & mask ? 1359 "set" : "clear"); 1360 } else { 1361 seq_printf(s, "[periph %c]\n", 1362 mode + 'A' - 1); 1363 } 1364 } 1365 } 1366 #else 1367 #define at91_gpio_dbg_show NULL 1368 #endif 1369 1370 /* Several AIC controller irqs are dispatched through this GPIO handler. 1371 * To use any AT91_PIN_* as an externally triggered IRQ, first call 1372 * at91_set_gpio_input() then maybe enable its glitch filter. 1373 * Then just request_irq() with the pin ID; it works like any ARM IRQ 1374 * handler. 1375 * First implementation always triggers on rising and falling edges 1376 * whereas the newer PIO3 can be additionally configured to trigger on 1377 * level, edge with any polarity. 1378 * 1379 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after 1380 * configuring them with at91_set_a_periph() or at91_set_b_periph(). 1381 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering. 1382 */ 1383 1384 static void gpio_irq_mask(struct irq_data *d) 1385 { 1386 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 1387 void __iomem *pio = at91_gpio->regbase; 1388 unsigned mask = 1 << d->hwirq; 1389 1390 if (pio) 1391 writel_relaxed(mask, pio + PIO_IDR); 1392 } 1393 1394 static void gpio_irq_unmask(struct irq_data *d) 1395 { 1396 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 1397 void __iomem *pio = at91_gpio->regbase; 1398 unsigned mask = 1 << d->hwirq; 1399 1400 if (pio) 1401 writel_relaxed(mask, pio + PIO_IER); 1402 } 1403 1404 static int gpio_irq_type(struct irq_data *d, unsigned type) 1405 { 1406 switch (type) { 1407 case IRQ_TYPE_NONE: 1408 case IRQ_TYPE_EDGE_BOTH: 1409 return 0; 1410 default: 1411 return -EINVAL; 1412 } 1413 } 1414 1415 /* Alternate irq type for PIO3 support */ 1416 static int alt_gpio_irq_type(struct irq_data *d, unsigned type) 1417 { 1418 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 1419 void __iomem *pio = at91_gpio->regbase; 1420 unsigned mask = 1 << d->hwirq; 1421 1422 switch (type) { 1423 case IRQ_TYPE_EDGE_RISING: 1424 __irq_set_handler_locked(d->irq, handle_simple_irq); 1425 writel_relaxed(mask, pio + PIO_ESR); 1426 writel_relaxed(mask, pio + PIO_REHLSR); 1427 break; 1428 case IRQ_TYPE_EDGE_FALLING: 1429 __irq_set_handler_locked(d->irq, handle_simple_irq); 1430 writel_relaxed(mask, pio + PIO_ESR); 1431 writel_relaxed(mask, pio + PIO_FELLSR); 1432 break; 1433 case IRQ_TYPE_LEVEL_LOW: 1434 __irq_set_handler_locked(d->irq, handle_level_irq); 1435 writel_relaxed(mask, pio + PIO_LSR); 1436 writel_relaxed(mask, pio + PIO_FELLSR); 1437 break; 1438 case IRQ_TYPE_LEVEL_HIGH: 1439 __irq_set_handler_locked(d->irq, handle_level_irq); 1440 writel_relaxed(mask, pio + PIO_LSR); 1441 writel_relaxed(mask, pio + PIO_REHLSR); 1442 break; 1443 case IRQ_TYPE_EDGE_BOTH: 1444 /* 1445 * disable additional interrupt modes: 1446 * fall back to default behavior 1447 */ 1448 __irq_set_handler_locked(d->irq, handle_simple_irq); 1449 writel_relaxed(mask, pio + PIO_AIMDR); 1450 return 0; 1451 case IRQ_TYPE_NONE: 1452 default: 1453 pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq)); 1454 return -EINVAL; 1455 } 1456 1457 /* enable additional interrupt modes */ 1458 writel_relaxed(mask, pio + PIO_AIMER); 1459 1460 return 0; 1461 } 1462 1463 static void gpio_irq_ack(struct irq_data *d) 1464 { 1465 /* the interrupt is already cleared before by reading ISR */ 1466 } 1467 1468 static unsigned int gpio_irq_startup(struct irq_data *d) 1469 { 1470 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 1471 unsigned pin = d->hwirq; 1472 int ret; 1473 1474 ret = gpiochip_lock_as_irq(&at91_gpio->chip, pin); 1475 if (ret) { 1476 dev_err(at91_gpio->chip.dev, "unable to lock pind %lu IRQ\n", 1477 d->hwirq); 1478 return ret; 1479 } 1480 gpio_irq_unmask(d); 1481 return 0; 1482 } 1483 1484 static void gpio_irq_shutdown(struct irq_data *d) 1485 { 1486 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 1487 unsigned pin = d->hwirq; 1488 1489 gpio_irq_mask(d); 1490 gpiochip_unlock_as_irq(&at91_gpio->chip, pin); 1491 } 1492 1493 #ifdef CONFIG_PM 1494 1495 static u32 wakeups[MAX_GPIO_BANKS]; 1496 static u32 backups[MAX_GPIO_BANKS]; 1497 1498 static int gpio_irq_set_wake(struct irq_data *d, unsigned state) 1499 { 1500 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 1501 unsigned bank = at91_gpio->pioc_idx; 1502 unsigned mask = 1 << d->hwirq; 1503 1504 if (unlikely(bank >= MAX_GPIO_BANKS)) 1505 return -EINVAL; 1506 1507 if (state) 1508 wakeups[bank] |= mask; 1509 else 1510 wakeups[bank] &= ~mask; 1511 1512 irq_set_irq_wake(at91_gpio->pioc_virq, state); 1513 1514 return 0; 1515 } 1516 1517 void at91_pinctrl_gpio_suspend(void) 1518 { 1519 int i; 1520 1521 for (i = 0; i < gpio_banks; i++) { 1522 void __iomem *pio; 1523 1524 if (!gpio_chips[i]) 1525 continue; 1526 1527 pio = gpio_chips[i]->regbase; 1528 1529 backups[i] = __raw_readl(pio + PIO_IMR); 1530 __raw_writel(backups[i], pio + PIO_IDR); 1531 __raw_writel(wakeups[i], pio + PIO_IER); 1532 1533 if (!wakeups[i]) 1534 clk_disable_unprepare(gpio_chips[i]->clock); 1535 else 1536 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 1537 'A'+i, wakeups[i]); 1538 } 1539 } 1540 1541 void at91_pinctrl_gpio_resume(void) 1542 { 1543 int i; 1544 1545 for (i = 0; i < gpio_banks; i++) { 1546 void __iomem *pio; 1547 1548 if (!gpio_chips[i]) 1549 continue; 1550 1551 pio = gpio_chips[i]->regbase; 1552 1553 if (!wakeups[i]) 1554 clk_prepare_enable(gpio_chips[i]->clock); 1555 1556 __raw_writel(wakeups[i], pio + PIO_IDR); 1557 __raw_writel(backups[i], pio + PIO_IER); 1558 } 1559 } 1560 1561 #else 1562 #define gpio_irq_set_wake NULL 1563 #endif /* CONFIG_PM */ 1564 1565 static struct irq_chip gpio_irqchip = { 1566 .name = "GPIO", 1567 .irq_ack = gpio_irq_ack, 1568 .irq_startup = gpio_irq_startup, 1569 .irq_shutdown = gpio_irq_shutdown, 1570 .irq_disable = gpio_irq_mask, 1571 .irq_mask = gpio_irq_mask, 1572 .irq_unmask = gpio_irq_unmask, 1573 /* .irq_set_type is set dynamically */ 1574 .irq_set_wake = gpio_irq_set_wake, 1575 }; 1576 1577 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) 1578 { 1579 struct irq_chip *chip = irq_get_chip(irq); 1580 struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc); 1581 struct at91_gpio_chip *at91_gpio = container_of(gpio_chip, 1582 struct at91_gpio_chip, chip); 1583 1584 void __iomem *pio = at91_gpio->regbase; 1585 unsigned long isr; 1586 int n; 1587 1588 chained_irq_enter(chip, desc); 1589 for (;;) { 1590 /* Reading ISR acks pending (edge triggered) GPIO interrupts. 1591 * When there are none pending, we're finished unless we need 1592 * to process multiple banks (like ID_PIOCDE on sam9263). 1593 */ 1594 isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR); 1595 if (!isr) { 1596 if (!at91_gpio->next) 1597 break; 1598 at91_gpio = at91_gpio->next; 1599 pio = at91_gpio->regbase; 1600 gpio_chip = &at91_gpio->chip; 1601 continue; 1602 } 1603 1604 for_each_set_bit(n, &isr, BITS_PER_LONG) { 1605 generic_handle_irq(irq_find_mapping( 1606 gpio_chip->irqdomain, n)); 1607 } 1608 } 1609 chained_irq_exit(chip, desc); 1610 /* now it may re-trigger */ 1611 } 1612 1613 static int at91_gpio_of_irq_setup(struct platform_device *pdev, 1614 struct at91_gpio_chip *at91_gpio) 1615 { 1616 struct at91_gpio_chip *prev = NULL; 1617 struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq); 1618 int ret; 1619 1620 at91_gpio->pioc_hwirq = irqd_to_hwirq(d); 1621 1622 /* Setup proper .irq_set_type function */ 1623 gpio_irqchip.irq_set_type = at91_gpio->ops->irq_type; 1624 1625 /* Disable irqs of this PIO controller */ 1626 writel_relaxed(~0, at91_gpio->regbase + PIO_IDR); 1627 1628 /* 1629 * Let the generic code handle this edge IRQ, the the chained 1630 * handler will perform the actual work of handling the parent 1631 * interrupt. 1632 */ 1633 ret = gpiochip_irqchip_add(&at91_gpio->chip, 1634 &gpio_irqchip, 1635 0, 1636 handle_edge_irq, 1637 IRQ_TYPE_EDGE_BOTH); 1638 if (ret) { 1639 dev_err(&pdev->dev, "at91_gpio.%d: Couldn't add irqchip to gpiochip.\n", 1640 at91_gpio->pioc_idx); 1641 return ret; 1642 } 1643 1644 /* Setup chained handler */ 1645 if (at91_gpio->pioc_idx) 1646 prev = gpio_chips[at91_gpio->pioc_idx - 1]; 1647 1648 /* The top level handler handles one bank of GPIOs, except 1649 * on some SoC it can handle up to three... 1650 * We only set up the handler for the first of the list. 1651 */ 1652 if (prev && prev->next == at91_gpio) 1653 return 0; 1654 1655 /* Then register the chain on the parent IRQ */ 1656 gpiochip_set_chained_irqchip(&at91_gpio->chip, 1657 &gpio_irqchip, 1658 at91_gpio->pioc_virq, 1659 gpio_irq_handler); 1660 1661 return 0; 1662 } 1663 1664 /* This structure is replicated for each GPIO block allocated at probe time */ 1665 static struct gpio_chip at91_gpio_template = { 1666 .request = at91_gpio_request, 1667 .free = at91_gpio_free, 1668 .get_direction = at91_gpio_get_direction, 1669 .direction_input = at91_gpio_direction_input, 1670 .get = at91_gpio_get, 1671 .direction_output = at91_gpio_direction_output, 1672 .set = at91_gpio_set, 1673 .dbg_show = at91_gpio_dbg_show, 1674 .can_sleep = false, 1675 .ngpio = MAX_NB_GPIO_PER_BANK, 1676 }; 1677 1678 static void at91_gpio_probe_fixup(void) 1679 { 1680 unsigned i; 1681 struct at91_gpio_chip *at91_gpio, *last = NULL; 1682 1683 for (i = 0; i < gpio_banks; i++) { 1684 at91_gpio = gpio_chips[i]; 1685 1686 /* 1687 * GPIO controller are grouped on some SoC: 1688 * PIOC, PIOD and PIOE can share the same IRQ line 1689 */ 1690 if (last && last->pioc_virq == at91_gpio->pioc_virq) 1691 last->next = at91_gpio; 1692 last = at91_gpio; 1693 } 1694 } 1695 1696 static struct of_device_id at91_gpio_of_match[] = { 1697 { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, }, 1698 { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops }, 1699 { /* sentinel */ } 1700 }; 1701 1702 static int at91_gpio_probe(struct platform_device *pdev) 1703 { 1704 struct device_node *np = pdev->dev.of_node; 1705 struct resource *res; 1706 struct at91_gpio_chip *at91_chip = NULL; 1707 struct gpio_chip *chip; 1708 struct pinctrl_gpio_range *range; 1709 int ret = 0; 1710 int irq, i; 1711 int alias_idx = of_alias_get_id(np, "gpio"); 1712 uint32_t ngpio; 1713 char **names; 1714 1715 BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips)); 1716 if (gpio_chips[alias_idx]) { 1717 ret = -EBUSY; 1718 goto err; 1719 } 1720 1721 irq = platform_get_irq(pdev, 0); 1722 if (irq < 0) { 1723 ret = irq; 1724 goto err; 1725 } 1726 1727 at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL); 1728 if (!at91_chip) { 1729 ret = -ENOMEM; 1730 goto err; 1731 } 1732 1733 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1734 at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res); 1735 if (IS_ERR(at91_chip->regbase)) { 1736 ret = PTR_ERR(at91_chip->regbase); 1737 goto err; 1738 } 1739 1740 at91_chip->ops = (struct at91_pinctrl_mux_ops *) 1741 of_match_device(at91_gpio_of_match, &pdev->dev)->data; 1742 at91_chip->pioc_virq = irq; 1743 at91_chip->pioc_idx = alias_idx; 1744 1745 at91_chip->clock = devm_clk_get(&pdev->dev, NULL); 1746 if (IS_ERR(at91_chip->clock)) { 1747 dev_err(&pdev->dev, "failed to get clock, ignoring.\n"); 1748 ret = PTR_ERR(at91_chip->clock); 1749 goto err; 1750 } 1751 1752 ret = clk_prepare(at91_chip->clock); 1753 if (ret) 1754 goto clk_prepare_err; 1755 1756 /* enable PIO controller's clock */ 1757 ret = clk_enable(at91_chip->clock); 1758 if (ret) { 1759 dev_err(&pdev->dev, "failed to enable clock, ignoring.\n"); 1760 goto clk_enable_err; 1761 } 1762 1763 at91_chip->chip = at91_gpio_template; 1764 1765 chip = &at91_chip->chip; 1766 chip->of_node = np; 1767 chip->label = dev_name(&pdev->dev); 1768 chip->dev = &pdev->dev; 1769 chip->owner = THIS_MODULE; 1770 chip->base = alias_idx * MAX_NB_GPIO_PER_BANK; 1771 1772 if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) { 1773 if (ngpio >= MAX_NB_GPIO_PER_BANK) 1774 pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n", 1775 alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK); 1776 else 1777 chip->ngpio = ngpio; 1778 } 1779 1780 names = devm_kzalloc(&pdev->dev, sizeof(char *) * chip->ngpio, 1781 GFP_KERNEL); 1782 1783 if (!names) { 1784 ret = -ENOMEM; 1785 goto clk_enable_err; 1786 } 1787 1788 for (i = 0; i < chip->ngpio; i++) 1789 names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i); 1790 1791 chip->names = (const char *const *)names; 1792 1793 range = &at91_chip->range; 1794 range->name = chip->label; 1795 range->id = alias_idx; 1796 range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK; 1797 1798 range->npins = chip->ngpio; 1799 range->gc = chip; 1800 1801 ret = gpiochip_add(chip); 1802 if (ret) 1803 goto gpiochip_add_err; 1804 1805 gpio_chips[alias_idx] = at91_chip; 1806 gpio_banks = max(gpio_banks, alias_idx + 1); 1807 1808 at91_gpio_probe_fixup(); 1809 1810 ret = at91_gpio_of_irq_setup(pdev, at91_chip); 1811 if (ret) 1812 goto irq_setup_err; 1813 1814 dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase); 1815 1816 return 0; 1817 1818 irq_setup_err: 1819 gpiochip_remove(chip); 1820 gpiochip_add_err: 1821 clk_disable(at91_chip->clock); 1822 clk_enable_err: 1823 clk_unprepare(at91_chip->clock); 1824 clk_prepare_err: 1825 err: 1826 dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx); 1827 1828 return ret; 1829 } 1830 1831 static struct platform_driver at91_gpio_driver = { 1832 .driver = { 1833 .name = "gpio-at91", 1834 .of_match_table = at91_gpio_of_match, 1835 }, 1836 .probe = at91_gpio_probe, 1837 }; 1838 1839 static struct platform_driver at91_pinctrl_driver = { 1840 .driver = { 1841 .name = "pinctrl-at91", 1842 .of_match_table = at91_pinctrl_of_match, 1843 }, 1844 .probe = at91_pinctrl_probe, 1845 .remove = at91_pinctrl_remove, 1846 }; 1847 1848 static int __init at91_pinctrl_init(void) 1849 { 1850 int ret; 1851 1852 ret = platform_driver_register(&at91_gpio_driver); 1853 if (ret) 1854 return ret; 1855 return platform_driver_register(&at91_pinctrl_driver); 1856 } 1857 arch_initcall(at91_pinctrl_init); 1858 1859 static void __exit at91_pinctrl_exit(void) 1860 { 1861 platform_driver_unregister(&at91_pinctrl_driver); 1862 } 1863 1864 module_exit(at91_pinctrl_exit); 1865 MODULE_AUTHOR("Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>"); 1866 MODULE_DESCRIPTION("Atmel AT91 pinctrl driver"); 1867 MODULE_LICENSE("GPL v2"); 1868