1 /*
2  * at91 pinctrl driver based on at91 pinmux core
3  *
4  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5  *
6  * Under GPLv2 only
7  */
8 
9 #include <linux/clk.h>
10 #include <linux/err.h>
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/of_device.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
17 #include <linux/slab.h>
18 #include <linux/interrupt.h>
19 #include <linux/io.h>
20 #include <linux/gpio.h>
21 #include <linux/pinctrl/machine.h>
22 #include <linux/pinctrl/pinconf.h>
23 #include <linux/pinctrl/pinctrl.h>
24 #include <linux/pinctrl/pinmux.h>
25 /* Since we request GPIOs from ourself */
26 #include <linux/pinctrl/consumer.h>
27 
28 #include <mach/hardware.h>
29 #include <mach/at91_pio.h>
30 
31 #include "core.h"
32 
33 #define MAX_GPIO_BANKS		5
34 #define MAX_NB_GPIO_PER_BANK	32
35 
36 struct at91_pinctrl_mux_ops;
37 
38 struct at91_gpio_chip {
39 	struct gpio_chip	chip;
40 	struct pinctrl_gpio_range range;
41 	struct at91_gpio_chip	*next;		/* Bank sharing same clock */
42 	int			pioc_hwirq;	/* PIO bank interrupt identifier on AIC */
43 	int			pioc_virq;	/* PIO bank Linux virtual interrupt */
44 	int			pioc_idx;	/* PIO bank index */
45 	void __iomem		*regbase;	/* PIO bank virtual address */
46 	struct clk		*clock;		/* associated clock */
47 	struct at91_pinctrl_mux_ops *ops;	/* ops */
48 };
49 
50 #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
51 
52 static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
53 
54 static int gpio_banks;
55 
56 #define PULL_UP		(1 << 0)
57 #define MULTI_DRIVE	(1 << 1)
58 #define DEGLITCH	(1 << 2)
59 #define PULL_DOWN	(1 << 3)
60 #define DIS_SCHMIT	(1 << 4)
61 #define DEBOUNCE	(1 << 16)
62 #define DEBOUNCE_VAL_SHIFT	17
63 #define DEBOUNCE_VAL	(0x3fff << DEBOUNCE_VAL_SHIFT)
64 
65 /**
66  * struct at91_pmx_func - describes AT91 pinmux functions
67  * @name: the name of this specific function
68  * @groups: corresponding pin groups
69  * @ngroups: the number of groups
70  */
71 struct at91_pmx_func {
72 	const char	*name;
73 	const char	**groups;
74 	unsigned	ngroups;
75 };
76 
77 enum at91_mux {
78 	AT91_MUX_GPIO = 0,
79 	AT91_MUX_PERIPH_A = 1,
80 	AT91_MUX_PERIPH_B = 2,
81 	AT91_MUX_PERIPH_C = 3,
82 	AT91_MUX_PERIPH_D = 4,
83 };
84 
85 /**
86  * struct at91_pmx_pin - describes an At91 pin mux
87  * @bank: the bank of the pin
88  * @pin: the pin number in the @bank
89  * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
90  * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
91  */
92 struct at91_pmx_pin {
93 	uint32_t	bank;
94 	uint32_t	pin;
95 	enum at91_mux	mux;
96 	unsigned long	conf;
97 };
98 
99 /**
100  * struct at91_pin_group - describes an At91 pin group
101  * @name: the name of this specific pin group
102  * @pins_conf: the mux mode for each pin in this group. The size of this
103  *	array is the same as pins.
104  * @pins: an array of discrete physical pins used in this group, taken
105  *	from the driver-local pin enumeration space
106  * @npins: the number of pins in this group array, i.e. the number of
107  *	elements in .pins so we can iterate over that array
108  */
109 struct at91_pin_group {
110 	const char		*name;
111 	struct at91_pmx_pin	*pins_conf;
112 	unsigned int		*pins;
113 	unsigned		npins;
114 };
115 
116 /**
117  * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
118  * on new IP with support for periph C and D the way to mux in
119  * periph A and B has changed
120  * So provide the right call back
121  * if not present means the IP does not support it
122  * @get_periph: return the periph mode configured
123  * @mux_A_periph: mux as periph A
124  * @mux_B_periph: mux as periph B
125  * @mux_C_periph: mux as periph C
126  * @mux_D_periph: mux as periph D
127  * @get_deglitch: get deglitch status
128  * @set_deglitch: enable/disable deglitch
129  * @get_debounce: get debounce status
130  * @set_debounce: enable/disable debounce
131  * @get_pulldown: get pulldown status
132  * @set_pulldown: enable/disable pulldown
133  * @get_schmitt_trig: get schmitt trigger status
134  * @disable_schmitt_trig: disable schmitt trigger
135  * @irq_type: return irq type
136  */
137 struct at91_pinctrl_mux_ops {
138 	enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
139 	void (*mux_A_periph)(void __iomem *pio, unsigned mask);
140 	void (*mux_B_periph)(void __iomem *pio, unsigned mask);
141 	void (*mux_C_periph)(void __iomem *pio, unsigned mask);
142 	void (*mux_D_periph)(void __iomem *pio, unsigned mask);
143 	bool (*get_deglitch)(void __iomem *pio, unsigned pin);
144 	void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on);
145 	bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
146 	void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div);
147 	bool (*get_pulldown)(void __iomem *pio, unsigned pin);
148 	void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
149 	bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
150 	void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
151 	/* irq */
152 	int (*irq_type)(struct irq_data *d, unsigned type);
153 };
154 
155 static int gpio_irq_type(struct irq_data *d, unsigned type);
156 static int alt_gpio_irq_type(struct irq_data *d, unsigned type);
157 
158 struct at91_pinctrl {
159 	struct device		*dev;
160 	struct pinctrl_dev	*pctl;
161 
162 	int			nbanks;
163 
164 	uint32_t		*mux_mask;
165 	int			nmux;
166 
167 	struct at91_pmx_func	*functions;
168 	int			nfunctions;
169 
170 	struct at91_pin_group	*groups;
171 	int			ngroups;
172 
173 	struct at91_pinctrl_mux_ops *ops;
174 };
175 
176 static const inline struct at91_pin_group *at91_pinctrl_find_group_by_name(
177 				const struct at91_pinctrl *info,
178 				const char *name)
179 {
180 	const struct at91_pin_group *grp = NULL;
181 	int i;
182 
183 	for (i = 0; i < info->ngroups; i++) {
184 		if (strcmp(info->groups[i].name, name))
185 			continue;
186 
187 		grp = &info->groups[i];
188 		dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]);
189 		break;
190 	}
191 
192 	return grp;
193 }
194 
195 static int at91_get_groups_count(struct pinctrl_dev *pctldev)
196 {
197 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
198 
199 	return info->ngroups;
200 }
201 
202 static const char *at91_get_group_name(struct pinctrl_dev *pctldev,
203 				       unsigned selector)
204 {
205 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
206 
207 	return info->groups[selector].name;
208 }
209 
210 static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
211 			       const unsigned **pins,
212 			       unsigned *npins)
213 {
214 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
215 
216 	if (selector >= info->ngroups)
217 		return -EINVAL;
218 
219 	*pins = info->groups[selector].pins;
220 	*npins = info->groups[selector].npins;
221 
222 	return 0;
223 }
224 
225 static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
226 		   unsigned offset)
227 {
228 	seq_printf(s, "%s", dev_name(pctldev->dev));
229 }
230 
231 static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
232 			struct device_node *np,
233 			struct pinctrl_map **map, unsigned *num_maps)
234 {
235 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
236 	const struct at91_pin_group *grp;
237 	struct pinctrl_map *new_map;
238 	struct device_node *parent;
239 	int map_num = 1;
240 	int i;
241 
242 	/*
243 	 * first find the group of this node and check if we need to create
244 	 * config maps for pins
245 	 */
246 	grp = at91_pinctrl_find_group_by_name(info, np->name);
247 	if (!grp) {
248 		dev_err(info->dev, "unable to find group for node %s\n",
249 			np->name);
250 		return -EINVAL;
251 	}
252 
253 	map_num += grp->npins;
254 	new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, GFP_KERNEL);
255 	if (!new_map)
256 		return -ENOMEM;
257 
258 	*map = new_map;
259 	*num_maps = map_num;
260 
261 	/* create mux map */
262 	parent = of_get_parent(np);
263 	if (!parent) {
264 		devm_kfree(pctldev->dev, new_map);
265 		return -EINVAL;
266 	}
267 	new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
268 	new_map[0].data.mux.function = parent->name;
269 	new_map[0].data.mux.group = np->name;
270 	of_node_put(parent);
271 
272 	/* create config map */
273 	new_map++;
274 	for (i = 0; i < grp->npins; i++) {
275 		new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
276 		new_map[i].data.configs.group_or_pin =
277 				pin_get_name(pctldev, grp->pins[i]);
278 		new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
279 		new_map[i].data.configs.num_configs = 1;
280 	}
281 
282 	dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
283 		(*map)->data.mux.function, (*map)->data.mux.group, map_num);
284 
285 	return 0;
286 }
287 
288 static void at91_dt_free_map(struct pinctrl_dev *pctldev,
289 				struct pinctrl_map *map, unsigned num_maps)
290 {
291 }
292 
293 static const struct pinctrl_ops at91_pctrl_ops = {
294 	.get_groups_count	= at91_get_groups_count,
295 	.get_group_name		= at91_get_group_name,
296 	.get_group_pins		= at91_get_group_pins,
297 	.pin_dbg_show		= at91_pin_dbg_show,
298 	.dt_node_to_map		= at91_dt_node_to_map,
299 	.dt_free_map		= at91_dt_free_map,
300 };
301 
302 static void __iomem *pin_to_controller(struct at91_pinctrl *info,
303 				 unsigned int bank)
304 {
305 	return gpio_chips[bank]->regbase;
306 }
307 
308 static inline int pin_to_bank(unsigned pin)
309 {
310 	return pin /= MAX_NB_GPIO_PER_BANK;
311 }
312 
313 static unsigned pin_to_mask(unsigned int pin)
314 {
315 	return 1 << pin;
316 }
317 
318 static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
319 {
320 	writel_relaxed(mask, pio + PIO_IDR);
321 }
322 
323 static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
324 {
325 	return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1);
326 }
327 
328 static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
329 {
330 	writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
331 }
332 
333 static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
334 {
335 	return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1;
336 }
337 
338 static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
339 {
340 	writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR));
341 }
342 
343 static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
344 {
345 	writel_relaxed(mask, pio + PIO_ASR);
346 }
347 
348 static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
349 {
350 	writel_relaxed(mask, pio + PIO_BSR);
351 }
352 
353 static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
354 {
355 
356 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask,
357 						pio + PIO_ABCDSR1);
358 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
359 						pio + PIO_ABCDSR2);
360 }
361 
362 static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
363 {
364 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask,
365 						pio + PIO_ABCDSR1);
366 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
367 						pio + PIO_ABCDSR2);
368 }
369 
370 static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
371 {
372 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
373 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
374 }
375 
376 static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
377 {
378 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
379 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
380 }
381 
382 static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask)
383 {
384 	unsigned select;
385 
386 	if (readl_relaxed(pio + PIO_PSR) & mask)
387 		return AT91_MUX_GPIO;
388 
389 	select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask);
390 	select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1);
391 
392 	return select + 1;
393 }
394 
395 static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)
396 {
397 	unsigned select;
398 
399 	if (readl_relaxed(pio + PIO_PSR) & mask)
400 		return AT91_MUX_GPIO;
401 
402 	select = readl_relaxed(pio + PIO_ABSR) & mask;
403 
404 	return select + 1;
405 }
406 
407 static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin)
408 {
409 	return (__raw_readl(pio + PIO_IFSR) >> pin) & 0x1;
410 }
411 
412 static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
413 {
414 	__raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
415 }
416 
417 static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin)
418 {
419 	if ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1)
420 		return !((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1);
421 
422 	return false;
423 }
424 
425 static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
426 {
427 	if (is_on)
428 		__raw_writel(mask, pio + PIO_IFSCDR);
429 	at91_mux_set_deglitch(pio, mask, is_on);
430 }
431 
432 static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
433 {
434 	*div = __raw_readl(pio + PIO_SCDR);
435 
436 	return ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1) &&
437 	       ((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1);
438 }
439 
440 static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
441 				bool is_on, u32 div)
442 {
443 	if (is_on) {
444 		__raw_writel(mask, pio + PIO_IFSCER);
445 		__raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
446 		__raw_writel(mask, pio + PIO_IFER);
447 	} else
448 		__raw_writel(mask, pio + PIO_IFSCDR);
449 }
450 
451 static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
452 {
453 	return !((__raw_readl(pio + PIO_PPDSR) >> pin) & 0x1);
454 }
455 
456 static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
457 {
458 	__raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
459 }
460 
461 static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
462 {
463 	__raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
464 }
465 
466 static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
467 {
468 	return (__raw_readl(pio + PIO_SCHMITT) >> pin) & 0x1;
469 }
470 
471 static struct at91_pinctrl_mux_ops at91rm9200_ops = {
472 	.get_periph	= at91_mux_get_periph,
473 	.mux_A_periph	= at91_mux_set_A_periph,
474 	.mux_B_periph	= at91_mux_set_B_periph,
475 	.get_deglitch	= at91_mux_get_deglitch,
476 	.set_deglitch	= at91_mux_set_deglitch,
477 	.irq_type	= gpio_irq_type,
478 };
479 
480 static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
481 	.get_periph	= at91_mux_pio3_get_periph,
482 	.mux_A_periph	= at91_mux_pio3_set_A_periph,
483 	.mux_B_periph	= at91_mux_pio3_set_B_periph,
484 	.mux_C_periph	= at91_mux_pio3_set_C_periph,
485 	.mux_D_periph	= at91_mux_pio3_set_D_periph,
486 	.get_deglitch	= at91_mux_pio3_get_deglitch,
487 	.set_deglitch	= at91_mux_pio3_set_deglitch,
488 	.get_debounce	= at91_mux_pio3_get_debounce,
489 	.set_debounce	= at91_mux_pio3_set_debounce,
490 	.get_pulldown	= at91_mux_pio3_get_pulldown,
491 	.set_pulldown	= at91_mux_pio3_set_pulldown,
492 	.get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
493 	.disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
494 	.irq_type	= alt_gpio_irq_type,
495 };
496 
497 static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
498 {
499 	if (pin->mux) {
500 		dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lu\n",
501 			pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
502 	} else {
503 		dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lu\n",
504 			pin->bank + 'A', pin->pin, pin->conf);
505 	}
506 }
507 
508 static int pin_check_config(struct at91_pinctrl *info, const char *name,
509 			    int index, const struct at91_pmx_pin *pin)
510 {
511 	int mux;
512 
513 	/* check if it's a valid config */
514 	if (pin->bank >= info->nbanks) {
515 		dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
516 			name, index, pin->bank, info->nbanks);
517 		return -EINVAL;
518 	}
519 
520 	if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
521 		dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
522 			name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
523 		return -EINVAL;
524 	}
525 
526 	if (!pin->mux)
527 		return 0;
528 
529 	mux = pin->mux - 1;
530 
531 	if (mux >= info->nmux) {
532 		dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
533 			name, index, mux, info->nmux);
534 		return -EINVAL;
535 	}
536 
537 	if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
538 		dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
539 			name, index, mux, pin->bank + 'A', pin->pin);
540 		return -EINVAL;
541 	}
542 
543 	return 0;
544 }
545 
546 static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
547 {
548 	writel_relaxed(mask, pio + PIO_PDR);
549 }
550 
551 static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)
552 {
553 	writel_relaxed(mask, pio + PIO_PER);
554 	writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
555 }
556 
557 static int at91_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
558 			   unsigned group)
559 {
560 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
561 	const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
562 	const struct at91_pmx_pin *pin;
563 	uint32_t npins = info->groups[group].npins;
564 	int i, ret;
565 	unsigned mask;
566 	void __iomem *pio;
567 
568 	dev_dbg(info->dev, "enable function %s group %s\n",
569 		info->functions[selector].name, info->groups[group].name);
570 
571 	/* first check that all the pins of the group are valid with a valid
572 	 * parameter */
573 	for (i = 0; i < npins; i++) {
574 		pin = &pins_conf[i];
575 		ret = pin_check_config(info, info->groups[group].name, i, pin);
576 		if (ret)
577 			return ret;
578 	}
579 
580 	for (i = 0; i < npins; i++) {
581 		pin = &pins_conf[i];
582 		at91_pin_dbg(info->dev, pin);
583 		pio = pin_to_controller(info, pin->bank);
584 		mask = pin_to_mask(pin->pin);
585 		at91_mux_disable_interrupt(pio, mask);
586 		switch (pin->mux) {
587 		case AT91_MUX_GPIO:
588 			at91_mux_gpio_enable(pio, mask, 1);
589 			break;
590 		case AT91_MUX_PERIPH_A:
591 			info->ops->mux_A_periph(pio, mask);
592 			break;
593 		case AT91_MUX_PERIPH_B:
594 			info->ops->mux_B_periph(pio, mask);
595 			break;
596 		case AT91_MUX_PERIPH_C:
597 			if (!info->ops->mux_C_periph)
598 				return -EINVAL;
599 			info->ops->mux_C_periph(pio, mask);
600 			break;
601 		case AT91_MUX_PERIPH_D:
602 			if (!info->ops->mux_D_periph)
603 				return -EINVAL;
604 			info->ops->mux_D_periph(pio, mask);
605 			break;
606 		}
607 		if (pin->mux)
608 			at91_mux_gpio_disable(pio, mask);
609 	}
610 
611 	return 0;
612 }
613 
614 static void at91_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
615 			   unsigned group)
616 {
617 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
618 	const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
619 	const struct at91_pmx_pin *pin;
620 	uint32_t npins = info->groups[group].npins;
621 	int i;
622 	unsigned mask;
623 	void __iomem *pio;
624 
625 	for (i = 0; i < npins; i++) {
626 		pin = &pins_conf[i];
627 		at91_pin_dbg(info->dev, pin);
628 		pio = pin_to_controller(info, pin->bank);
629 		mask = pin_to_mask(pin->pin);
630 		at91_mux_gpio_enable(pio, mask, 1);
631 	}
632 }
633 
634 static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
635 {
636 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
637 
638 	return info->nfunctions;
639 }
640 
641 static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev,
642 					  unsigned selector)
643 {
644 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
645 
646 	return info->functions[selector].name;
647 }
648 
649 static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
650 			       const char * const **groups,
651 			       unsigned * const num_groups)
652 {
653 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
654 
655 	*groups = info->functions[selector].groups;
656 	*num_groups = info->functions[selector].ngroups;
657 
658 	return 0;
659 }
660 
661 static int at91_gpio_request_enable(struct pinctrl_dev *pctldev,
662 				    struct pinctrl_gpio_range *range,
663 				    unsigned offset)
664 {
665 	struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
666 	struct at91_gpio_chip *at91_chip;
667 	struct gpio_chip *chip;
668 	unsigned mask;
669 
670 	if (!range) {
671 		dev_err(npct->dev, "invalid range\n");
672 		return -EINVAL;
673 	}
674 	if (!range->gc) {
675 		dev_err(npct->dev, "missing GPIO chip in range\n");
676 		return -EINVAL;
677 	}
678 	chip = range->gc;
679 	at91_chip = container_of(chip, struct at91_gpio_chip, chip);
680 
681 	dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
682 
683 	mask = 1 << (offset - chip->base);
684 
685 	dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n",
686 		offset, 'A' + range->id, offset - chip->base, mask);
687 
688 	writel_relaxed(mask, at91_chip->regbase + PIO_PER);
689 
690 	return 0;
691 }
692 
693 static void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
694 				   struct pinctrl_gpio_range *range,
695 				   unsigned offset)
696 {
697 	struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
698 
699 	dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
700 	/* Set the pin to some default state, GPIO is usually default */
701 }
702 
703 static const struct pinmux_ops at91_pmx_ops = {
704 	.get_functions_count	= at91_pmx_get_funcs_count,
705 	.get_function_name	= at91_pmx_get_func_name,
706 	.get_function_groups	= at91_pmx_get_groups,
707 	.enable			= at91_pmx_enable,
708 	.disable		= at91_pmx_disable,
709 	.gpio_request_enable	= at91_gpio_request_enable,
710 	.gpio_disable_free	= at91_gpio_disable_free,
711 };
712 
713 static int at91_pinconf_get(struct pinctrl_dev *pctldev,
714 			     unsigned pin_id, unsigned long *config)
715 {
716 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
717 	void __iomem *pio;
718 	unsigned pin;
719 	int div;
720 
721 	*config = 0;
722 	dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id);
723 	pio = pin_to_controller(info, pin_to_bank(pin_id));
724 	pin = pin_id % MAX_NB_GPIO_PER_BANK;
725 
726 	if (at91_mux_get_multidrive(pio, pin))
727 		*config |= MULTI_DRIVE;
728 
729 	if (at91_mux_get_pullup(pio, pin))
730 		*config |= PULL_UP;
731 
732 	if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin))
733 		*config |= DEGLITCH;
734 	if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div))
735 		*config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT);
736 	if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin))
737 		*config |= PULL_DOWN;
738 	if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin))
739 		*config |= DIS_SCHMIT;
740 
741 	return 0;
742 }
743 
744 static int at91_pinconf_set(struct pinctrl_dev *pctldev,
745 			     unsigned pin_id, unsigned long *configs,
746 			     unsigned num_configs)
747 {
748 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
749 	unsigned mask;
750 	void __iomem *pio;
751 	int i;
752 	unsigned long config;
753 
754 	for (i = 0; i < num_configs; i++) {
755 		config = configs[i];
756 
757 		dev_dbg(info->dev,
758 			"%s:%d, pin_id=%d, config=0x%lx",
759 			__func__, __LINE__, pin_id, config);
760 		pio = pin_to_controller(info, pin_to_bank(pin_id));
761 		mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK);
762 
763 		if (config & PULL_UP && config & PULL_DOWN)
764 			return -EINVAL;
765 
766 		at91_mux_set_pullup(pio, mask, config & PULL_UP);
767 		at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
768 		if (info->ops->set_deglitch)
769 			info->ops->set_deglitch(pio, mask, config & DEGLITCH);
770 		if (info->ops->set_debounce)
771 			info->ops->set_debounce(pio, mask, config & DEBOUNCE,
772 				(config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
773 		if (info->ops->set_pulldown)
774 			info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
775 		if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
776 			info->ops->disable_schmitt_trig(pio, mask);
777 
778 	} /* for each config */
779 
780 	return 0;
781 }
782 
783 #define DBG_SHOW_FLAG(flag) do {		\
784 	if (config & flag) {			\
785 		if (num_conf)			\
786 			seq_puts(s, "|");	\
787 		seq_puts(s, #flag);		\
788 		num_conf++;			\
789 	}					\
790 } while (0)
791 
792 static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
793 				   struct seq_file *s, unsigned pin_id)
794 {
795 	unsigned long config;
796 	int ret, val, num_conf = 0;
797 
798 	ret = at91_pinconf_get(pctldev, pin_id, &config);
799 
800 	DBG_SHOW_FLAG(MULTI_DRIVE);
801 	DBG_SHOW_FLAG(PULL_UP);
802 	DBG_SHOW_FLAG(PULL_DOWN);
803 	DBG_SHOW_FLAG(DIS_SCHMIT);
804 	DBG_SHOW_FLAG(DEGLITCH);
805 	DBG_SHOW_FLAG(DEBOUNCE);
806 	if (config & DEBOUNCE) {
807 		val = config >> DEBOUNCE_VAL_SHIFT;
808 		seq_printf(s, "(%d)", val);
809 	}
810 
811 	return;
812 }
813 
814 static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
815 					 struct seq_file *s, unsigned group)
816 {
817 }
818 
819 static const struct pinconf_ops at91_pinconf_ops = {
820 	.pin_config_get			= at91_pinconf_get,
821 	.pin_config_set			= at91_pinconf_set,
822 	.pin_config_dbg_show		= at91_pinconf_dbg_show,
823 	.pin_config_group_dbg_show	= at91_pinconf_group_dbg_show,
824 };
825 
826 static struct pinctrl_desc at91_pinctrl_desc = {
827 	.pctlops	= &at91_pctrl_ops,
828 	.pmxops		= &at91_pmx_ops,
829 	.confops	= &at91_pinconf_ops,
830 	.owner		= THIS_MODULE,
831 };
832 
833 static const char *gpio_compat = "atmel,at91rm9200-gpio";
834 
835 static void at91_pinctrl_child_count(struct at91_pinctrl *info,
836 				     struct device_node *np)
837 {
838 	struct device_node *child;
839 
840 	for_each_child_of_node(np, child) {
841 		if (of_device_is_compatible(child, gpio_compat)) {
842 			info->nbanks++;
843 		} else {
844 			info->nfunctions++;
845 			info->ngroups += of_get_child_count(child);
846 		}
847 	}
848 }
849 
850 static int at91_pinctrl_mux_mask(struct at91_pinctrl *info,
851 				 struct device_node *np)
852 {
853 	int ret = 0;
854 	int size;
855 	const __be32 *list;
856 
857 	list = of_get_property(np, "atmel,mux-mask", &size);
858 	if (!list) {
859 		dev_err(info->dev, "can not read the mux-mask of %d\n", size);
860 		return -EINVAL;
861 	}
862 
863 	size /= sizeof(*list);
864 	if (!size || size % info->nbanks) {
865 		dev_err(info->dev, "wrong mux mask array should be by %d\n", info->nbanks);
866 		return -EINVAL;
867 	}
868 	info->nmux = size / info->nbanks;
869 
870 	info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL);
871 	if (!info->mux_mask) {
872 		dev_err(info->dev, "could not alloc mux_mask\n");
873 		return -ENOMEM;
874 	}
875 
876 	ret = of_property_read_u32_array(np, "atmel,mux-mask",
877 					  info->mux_mask, size);
878 	if (ret)
879 		dev_err(info->dev, "can not read the mux-mask of %d\n", size);
880 	return ret;
881 }
882 
883 static int at91_pinctrl_parse_groups(struct device_node *np,
884 				     struct at91_pin_group *grp,
885 				     struct at91_pinctrl *info, u32 index)
886 {
887 	struct at91_pmx_pin *pin;
888 	int size;
889 	const __be32 *list;
890 	int i, j;
891 
892 	dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
893 
894 	/* Initialise group */
895 	grp->name = np->name;
896 
897 	/*
898 	 * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
899 	 * do sanity check and calculate pins number
900 	 */
901 	list = of_get_property(np, "atmel,pins", &size);
902 	/* we do not check return since it's safe node passed down */
903 	size /= sizeof(*list);
904 	if (!size || size % 4) {
905 		dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
906 		return -EINVAL;
907 	}
908 
909 	grp->npins = size / 4;
910 	pin = grp->pins_conf = devm_kzalloc(info->dev, grp->npins * sizeof(struct at91_pmx_pin),
911 				GFP_KERNEL);
912 	grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
913 				GFP_KERNEL);
914 	if (!grp->pins_conf || !grp->pins)
915 		return -ENOMEM;
916 
917 	for (i = 0, j = 0; i < size; i += 4, j++) {
918 		pin->bank = be32_to_cpu(*list++);
919 		pin->pin = be32_to_cpu(*list++);
920 		grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
921 		pin->mux = be32_to_cpu(*list++);
922 		pin->conf = be32_to_cpu(*list++);
923 
924 		at91_pin_dbg(info->dev, pin);
925 		pin++;
926 	}
927 
928 	return 0;
929 }
930 
931 static int at91_pinctrl_parse_functions(struct device_node *np,
932 					struct at91_pinctrl *info, u32 index)
933 {
934 	struct device_node *child;
935 	struct at91_pmx_func *func;
936 	struct at91_pin_group *grp;
937 	int ret;
938 	static u32 grp_index;
939 	u32 i = 0;
940 
941 	dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
942 
943 	func = &info->functions[index];
944 
945 	/* Initialise function */
946 	func->name = np->name;
947 	func->ngroups = of_get_child_count(np);
948 	if (func->ngroups <= 0) {
949 		dev_err(info->dev, "no groups defined\n");
950 		return -EINVAL;
951 	}
952 	func->groups = devm_kzalloc(info->dev,
953 			func->ngroups * sizeof(char *), GFP_KERNEL);
954 	if (!func->groups)
955 		return -ENOMEM;
956 
957 	for_each_child_of_node(np, child) {
958 		func->groups[i] = child->name;
959 		grp = &info->groups[grp_index++];
960 		ret = at91_pinctrl_parse_groups(child, grp, info, i++);
961 		if (ret)
962 			return ret;
963 	}
964 
965 	return 0;
966 }
967 
968 static struct of_device_id at91_pinctrl_of_match[] = {
969 	{ .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
970 	{ .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
971 	{ /* sentinel */ }
972 };
973 
974 static int at91_pinctrl_probe_dt(struct platform_device *pdev,
975 				 struct at91_pinctrl *info)
976 {
977 	int ret = 0;
978 	int i, j;
979 	uint32_t *tmp;
980 	struct device_node *np = pdev->dev.of_node;
981 	struct device_node *child;
982 
983 	if (!np)
984 		return -ENODEV;
985 
986 	info->dev = &pdev->dev;
987 	info->ops = (struct at91_pinctrl_mux_ops *)
988 		of_match_device(at91_pinctrl_of_match, &pdev->dev)->data;
989 	at91_pinctrl_child_count(info, np);
990 
991 	if (info->nbanks < 1) {
992 		dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n");
993 		return -EINVAL;
994 	}
995 
996 	ret = at91_pinctrl_mux_mask(info, np);
997 	if (ret)
998 		return ret;
999 
1000 	dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux);
1001 
1002 	dev_dbg(&pdev->dev, "mux-mask\n");
1003 	tmp = info->mux_mask;
1004 	for (i = 0; i < info->nbanks; i++) {
1005 		for (j = 0; j < info->nmux; j++, tmp++) {
1006 			dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
1007 		}
1008 	}
1009 
1010 	dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1011 	dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1012 	info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * sizeof(struct at91_pmx_func),
1013 					GFP_KERNEL);
1014 	if (!info->functions)
1015 		return -ENOMEM;
1016 
1017 	info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct at91_pin_group),
1018 					GFP_KERNEL);
1019 	if (!info->groups)
1020 		return -ENOMEM;
1021 
1022 	dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks);
1023 	dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1024 	dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1025 
1026 	i = 0;
1027 
1028 	for_each_child_of_node(np, child) {
1029 		if (of_device_is_compatible(child, gpio_compat))
1030 			continue;
1031 		ret = at91_pinctrl_parse_functions(child, info, i++);
1032 		if (ret) {
1033 			dev_err(&pdev->dev, "failed to parse function\n");
1034 			return ret;
1035 		}
1036 	}
1037 
1038 	return 0;
1039 }
1040 
1041 static int at91_pinctrl_probe(struct platform_device *pdev)
1042 {
1043 	struct at91_pinctrl *info;
1044 	struct pinctrl_pin_desc *pdesc;
1045 	int ret, i, j, k;
1046 
1047 	info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1048 	if (!info)
1049 		return -ENOMEM;
1050 
1051 	ret = at91_pinctrl_probe_dt(pdev, info);
1052 	if (ret)
1053 		return ret;
1054 
1055 	/*
1056 	 * We need all the GPIO drivers to probe FIRST, or we will not be able
1057 	 * to obtain references to the struct gpio_chip * for them, and we
1058 	 * need this to proceed.
1059 	 */
1060 	for (i = 0; i < info->nbanks; i++) {
1061 		if (!gpio_chips[i]) {
1062 			dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
1063 			devm_kfree(&pdev->dev, info);
1064 			return -EPROBE_DEFER;
1065 		}
1066 	}
1067 
1068 	at91_pinctrl_desc.name = dev_name(&pdev->dev);
1069 	at91_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK;
1070 	at91_pinctrl_desc.pins = pdesc =
1071 		devm_kzalloc(&pdev->dev, sizeof(*pdesc) * at91_pinctrl_desc.npins, GFP_KERNEL);
1072 
1073 	if (!at91_pinctrl_desc.pins)
1074 		return -ENOMEM;
1075 
1076 	for (i = 0 , k = 0; i < info->nbanks; i++) {
1077 		for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
1078 			pdesc->number = k;
1079 			pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j);
1080 			pdesc++;
1081 		}
1082 	}
1083 
1084 	platform_set_drvdata(pdev, info);
1085 	info->pctl = pinctrl_register(&at91_pinctrl_desc, &pdev->dev, info);
1086 
1087 	if (!info->pctl) {
1088 		dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n");
1089 		ret = -EINVAL;
1090 		goto err;
1091 	}
1092 
1093 	/* We will handle a range of GPIO pins */
1094 	for (i = 0; i < info->nbanks; i++)
1095 		pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
1096 
1097 	dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");
1098 
1099 	return 0;
1100 
1101 err:
1102 	return ret;
1103 }
1104 
1105 static int at91_pinctrl_remove(struct platform_device *pdev)
1106 {
1107 	struct at91_pinctrl *info = platform_get_drvdata(pdev);
1108 
1109 	pinctrl_unregister(info->pctl);
1110 
1111 	return 0;
1112 }
1113 
1114 static int at91_gpio_request(struct gpio_chip *chip, unsigned offset)
1115 {
1116 	/*
1117 	 * Map back to global GPIO space and request muxing, the direction
1118 	 * parameter does not matter for this controller.
1119 	 */
1120 	int gpio = chip->base + offset;
1121 	int bank = chip->base / chip->ngpio;
1122 
1123 	dev_dbg(chip->dev, "%s:%d pio%c%d(%d)\n", __func__, __LINE__,
1124 		 'A' + bank, offset, gpio);
1125 
1126 	return pinctrl_request_gpio(gpio);
1127 }
1128 
1129 static void at91_gpio_free(struct gpio_chip *chip, unsigned offset)
1130 {
1131 	int gpio = chip->base + offset;
1132 
1133 	pinctrl_free_gpio(gpio);
1134 }
1135 
1136 static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1137 {
1138 	struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1139 	void __iomem *pio = at91_gpio->regbase;
1140 	unsigned mask = 1 << offset;
1141 	u32 osr;
1142 
1143 	osr = readl_relaxed(pio + PIO_OSR);
1144 	return !(osr & mask);
1145 }
1146 
1147 static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1148 {
1149 	struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1150 	void __iomem *pio = at91_gpio->regbase;
1151 	unsigned mask = 1 << offset;
1152 
1153 	writel_relaxed(mask, pio + PIO_ODR);
1154 	return 0;
1155 }
1156 
1157 static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
1158 {
1159 	struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1160 	void __iomem *pio = at91_gpio->regbase;
1161 	unsigned mask = 1 << offset;
1162 	u32 pdsr;
1163 
1164 	pdsr = readl_relaxed(pio + PIO_PDSR);
1165 	return (pdsr & mask) != 0;
1166 }
1167 
1168 static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
1169 				int val)
1170 {
1171 	struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1172 	void __iomem *pio = at91_gpio->regbase;
1173 	unsigned mask = 1 << offset;
1174 
1175 	writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1176 }
1177 
1178 static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1179 				int val)
1180 {
1181 	struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1182 	void __iomem *pio = at91_gpio->regbase;
1183 	unsigned mask = 1 << offset;
1184 
1185 	writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1186 	writel_relaxed(mask, pio + PIO_OER);
1187 
1188 	return 0;
1189 }
1190 
1191 #ifdef CONFIG_DEBUG_FS
1192 static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1193 {
1194 	enum at91_mux mode;
1195 	int i;
1196 	struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1197 	void __iomem *pio = at91_gpio->regbase;
1198 
1199 	for (i = 0; i < chip->ngpio; i++) {
1200 		unsigned mask = pin_to_mask(i);
1201 		const char *gpio_label;
1202 		u32 pdsr;
1203 
1204 		gpio_label = gpiochip_is_requested(chip, i);
1205 		if (!gpio_label)
1206 			continue;
1207 		mode = at91_gpio->ops->get_periph(pio, mask);
1208 		seq_printf(s, "[%s] GPIO%s%d: ",
1209 			   gpio_label, chip->label, i);
1210 		if (mode == AT91_MUX_GPIO) {
1211 			pdsr = readl_relaxed(pio + PIO_PDSR);
1212 
1213 			seq_printf(s, "[gpio] %s\n",
1214 				   pdsr & mask ?
1215 				   "set" : "clear");
1216 		} else {
1217 			seq_printf(s, "[periph %c]\n",
1218 				   mode + 'A' - 1);
1219 		}
1220 	}
1221 }
1222 #else
1223 #define at91_gpio_dbg_show	NULL
1224 #endif
1225 
1226 /* Several AIC controller irqs are dispatched through this GPIO handler.
1227  * To use any AT91_PIN_* as an externally triggered IRQ, first call
1228  * at91_set_gpio_input() then maybe enable its glitch filter.
1229  * Then just request_irq() with the pin ID; it works like any ARM IRQ
1230  * handler.
1231  * First implementation always triggers on rising and falling edges
1232  * whereas the newer PIO3 can be additionally configured to trigger on
1233  * level, edge with any polarity.
1234  *
1235  * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
1236  * configuring them with at91_set_a_periph() or at91_set_b_periph().
1237  * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
1238  */
1239 
1240 static void gpio_irq_mask(struct irq_data *d)
1241 {
1242 	struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1243 	void __iomem	*pio = at91_gpio->regbase;
1244 	unsigned	mask = 1 << d->hwirq;
1245 
1246 	if (pio)
1247 		writel_relaxed(mask, pio + PIO_IDR);
1248 }
1249 
1250 static void gpio_irq_unmask(struct irq_data *d)
1251 {
1252 	struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1253 	void __iomem	*pio = at91_gpio->regbase;
1254 	unsigned	mask = 1 << d->hwirq;
1255 
1256 	if (pio)
1257 		writel_relaxed(mask, pio + PIO_IER);
1258 }
1259 
1260 static int gpio_irq_type(struct irq_data *d, unsigned type)
1261 {
1262 	switch (type) {
1263 	case IRQ_TYPE_NONE:
1264 	case IRQ_TYPE_EDGE_BOTH:
1265 		return 0;
1266 	default:
1267 		return -EINVAL;
1268 	}
1269 }
1270 
1271 /* Alternate irq type for PIO3 support */
1272 static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
1273 {
1274 	struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1275 	void __iomem	*pio = at91_gpio->regbase;
1276 	unsigned	mask = 1 << d->hwirq;
1277 
1278 	switch (type) {
1279 	case IRQ_TYPE_EDGE_RISING:
1280 		__irq_set_handler_locked(d->irq, handle_simple_irq);
1281 		writel_relaxed(mask, pio + PIO_ESR);
1282 		writel_relaxed(mask, pio + PIO_REHLSR);
1283 		break;
1284 	case IRQ_TYPE_EDGE_FALLING:
1285 		__irq_set_handler_locked(d->irq, handle_simple_irq);
1286 		writel_relaxed(mask, pio + PIO_ESR);
1287 		writel_relaxed(mask, pio + PIO_FELLSR);
1288 		break;
1289 	case IRQ_TYPE_LEVEL_LOW:
1290 		__irq_set_handler_locked(d->irq, handle_level_irq);
1291 		writel_relaxed(mask, pio + PIO_LSR);
1292 		writel_relaxed(mask, pio + PIO_FELLSR);
1293 		break;
1294 	case IRQ_TYPE_LEVEL_HIGH:
1295 		__irq_set_handler_locked(d->irq, handle_level_irq);
1296 		writel_relaxed(mask, pio + PIO_LSR);
1297 		writel_relaxed(mask, pio + PIO_REHLSR);
1298 		break;
1299 	case IRQ_TYPE_EDGE_BOTH:
1300 		/*
1301 		 * disable additional interrupt modes:
1302 		 * fall back to default behavior
1303 		 */
1304 		__irq_set_handler_locked(d->irq, handle_simple_irq);
1305 		writel_relaxed(mask, pio + PIO_AIMDR);
1306 		return 0;
1307 	case IRQ_TYPE_NONE:
1308 	default:
1309 		pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq));
1310 		return -EINVAL;
1311 	}
1312 
1313 	/* enable additional interrupt modes */
1314 	writel_relaxed(mask, pio + PIO_AIMER);
1315 
1316 	return 0;
1317 }
1318 
1319 static void gpio_irq_ack(struct irq_data *d)
1320 {
1321 	/* the interrupt is already cleared before by reading ISR */
1322 }
1323 
1324 static unsigned int gpio_irq_startup(struct irq_data *d)
1325 {
1326 	struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1327 	unsigned	pin = d->hwirq;
1328 	int ret;
1329 
1330 	ret = gpio_lock_as_irq(&at91_gpio->chip, pin);
1331 	if (ret) {
1332 		dev_err(at91_gpio->chip.dev, "unable to lock pind %lu IRQ\n",
1333 			d->hwirq);
1334 		return ret;
1335 	}
1336 	gpio_irq_unmask(d);
1337 	return 0;
1338 }
1339 
1340 static void gpio_irq_shutdown(struct irq_data *d)
1341 {
1342 	struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1343 	unsigned	pin = d->hwirq;
1344 
1345 	gpio_irq_mask(d);
1346 	gpio_unlock_as_irq(&at91_gpio->chip, pin);
1347 }
1348 
1349 #ifdef CONFIG_PM
1350 
1351 static u32 wakeups[MAX_GPIO_BANKS];
1352 static u32 backups[MAX_GPIO_BANKS];
1353 
1354 static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
1355 {
1356 	struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1357 	unsigned	bank = at91_gpio->pioc_idx;
1358 	unsigned mask = 1 << d->hwirq;
1359 
1360 	if (unlikely(bank >= MAX_GPIO_BANKS))
1361 		return -EINVAL;
1362 
1363 	if (state)
1364 		wakeups[bank] |= mask;
1365 	else
1366 		wakeups[bank] &= ~mask;
1367 
1368 	irq_set_irq_wake(at91_gpio->pioc_virq, state);
1369 
1370 	return 0;
1371 }
1372 
1373 void at91_pinctrl_gpio_suspend(void)
1374 {
1375 	int i;
1376 
1377 	for (i = 0; i < gpio_banks; i++) {
1378 		void __iomem  *pio;
1379 
1380 		if (!gpio_chips[i])
1381 			continue;
1382 
1383 		pio = gpio_chips[i]->regbase;
1384 
1385 		backups[i] = __raw_readl(pio + PIO_IMR);
1386 		__raw_writel(backups[i], pio + PIO_IDR);
1387 		__raw_writel(wakeups[i], pio + PIO_IER);
1388 
1389 		if (!wakeups[i])
1390 			clk_disable_unprepare(gpio_chips[i]->clock);
1391 		else
1392 			printk(KERN_DEBUG "GPIO-%c may wake for %08x\n",
1393 			       'A'+i, wakeups[i]);
1394 	}
1395 }
1396 
1397 void at91_pinctrl_gpio_resume(void)
1398 {
1399 	int i;
1400 
1401 	for (i = 0; i < gpio_banks; i++) {
1402 		void __iomem  *pio;
1403 
1404 		if (!gpio_chips[i])
1405 			continue;
1406 
1407 		pio = gpio_chips[i]->regbase;
1408 
1409 		if (!wakeups[i])
1410 			clk_prepare_enable(gpio_chips[i]->clock);
1411 
1412 		__raw_writel(wakeups[i], pio + PIO_IDR);
1413 		__raw_writel(backups[i], pio + PIO_IER);
1414 	}
1415 }
1416 
1417 #else
1418 #define gpio_irq_set_wake	NULL
1419 #endif /* CONFIG_PM */
1420 
1421 static struct irq_chip gpio_irqchip = {
1422 	.name		= "GPIO",
1423 	.irq_ack	= gpio_irq_ack,
1424 	.irq_startup	= gpio_irq_startup,
1425 	.irq_shutdown	= gpio_irq_shutdown,
1426 	.irq_disable	= gpio_irq_mask,
1427 	.irq_mask	= gpio_irq_mask,
1428 	.irq_unmask	= gpio_irq_unmask,
1429 	/* .irq_set_type is set dynamically */
1430 	.irq_set_wake	= gpio_irq_set_wake,
1431 };
1432 
1433 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
1434 {
1435 	struct irq_chip *chip = irq_get_chip(irq);
1436 	struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc);
1437 	struct at91_gpio_chip *at91_gpio = container_of(gpio_chip,
1438 					   struct at91_gpio_chip, chip);
1439 
1440 	void __iomem	*pio = at91_gpio->regbase;
1441 	unsigned long	isr;
1442 	int		n;
1443 
1444 	chained_irq_enter(chip, desc);
1445 	for (;;) {
1446 		/* Reading ISR acks pending (edge triggered) GPIO interrupts.
1447 		 * When there are none pending, we're finished unless we need
1448 		 * to process multiple banks (like ID_PIOCDE on sam9263).
1449 		 */
1450 		isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
1451 		if (!isr) {
1452 			if (!at91_gpio->next)
1453 				break;
1454 			at91_gpio = at91_gpio->next;
1455 			pio = at91_gpio->regbase;
1456 			gpio_chip = &at91_gpio->chip;
1457 			continue;
1458 		}
1459 
1460 		for_each_set_bit(n, &isr, BITS_PER_LONG) {
1461 			generic_handle_irq(irq_find_mapping(
1462 					   gpio_chip->irqdomain, n));
1463 		}
1464 	}
1465 	chained_irq_exit(chip, desc);
1466 	/* now it may re-trigger */
1467 }
1468 
1469 static int at91_gpio_of_irq_setup(struct device_node *node,
1470 				  struct at91_gpio_chip *at91_gpio)
1471 {
1472 	struct at91_gpio_chip   *prev = NULL;
1473 	struct irq_data		*d = irq_get_irq_data(at91_gpio->pioc_virq);
1474 	int ret;
1475 
1476 	at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
1477 
1478 	/* Setup proper .irq_set_type function */
1479 	gpio_irqchip.irq_set_type = at91_gpio->ops->irq_type;
1480 
1481 	/* Disable irqs of this PIO controller */
1482 	writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);
1483 
1484 	/*
1485 	 * Let the generic code handle this edge IRQ, the the chained
1486 	 * handler will perform the actual work of handling the parent
1487 	 * interrupt.
1488 	 */
1489 	ret = gpiochip_irqchip_add(&at91_gpio->chip,
1490 				   &gpio_irqchip,
1491 				   0,
1492 				   handle_edge_irq,
1493 				   IRQ_TYPE_EDGE_BOTH);
1494 	if (ret)
1495 		panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
1496 			at91_gpio->pioc_idx);
1497 
1498 	/* Setup chained handler */
1499 	if (at91_gpio->pioc_idx)
1500 		prev = gpio_chips[at91_gpio->pioc_idx - 1];
1501 
1502 	/* The top level handler handles one bank of GPIOs, except
1503 	 * on some SoC it can handle up to three...
1504 	 * We only set up the handler for the first of the list.
1505 	 */
1506 	if (prev && prev->next == at91_gpio)
1507 		return 0;
1508 
1509 	/* Then register the chain on the parent IRQ */
1510 	gpiochip_set_chained_irqchip(&at91_gpio->chip,
1511 				     &gpio_irqchip,
1512 				     at91_gpio->pioc_virq,
1513 				     gpio_irq_handler);
1514 
1515 	return 0;
1516 }
1517 
1518 /* This structure is replicated for each GPIO block allocated at probe time */
1519 static struct gpio_chip at91_gpio_template = {
1520 	.request		= at91_gpio_request,
1521 	.free			= at91_gpio_free,
1522 	.get_direction		= at91_gpio_get_direction,
1523 	.direction_input	= at91_gpio_direction_input,
1524 	.get			= at91_gpio_get,
1525 	.direction_output	= at91_gpio_direction_output,
1526 	.set			= at91_gpio_set,
1527 	.dbg_show		= at91_gpio_dbg_show,
1528 	.can_sleep		= false,
1529 	.ngpio			= MAX_NB_GPIO_PER_BANK,
1530 };
1531 
1532 static void at91_gpio_probe_fixup(void)
1533 {
1534 	unsigned i;
1535 	struct at91_gpio_chip *at91_gpio, *last = NULL;
1536 
1537 	for (i = 0; i < gpio_banks; i++) {
1538 		at91_gpio = gpio_chips[i];
1539 
1540 		/*
1541 		 * GPIO controller are grouped on some SoC:
1542 		 * PIOC, PIOD and PIOE can share the same IRQ line
1543 		 */
1544 		if (last && last->pioc_virq == at91_gpio->pioc_virq)
1545 			last->next = at91_gpio;
1546 		last = at91_gpio;
1547 	}
1548 }
1549 
1550 static struct of_device_id at91_gpio_of_match[] = {
1551 	{ .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
1552 	{ .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
1553 	{ /* sentinel */ }
1554 };
1555 
1556 static int at91_gpio_probe(struct platform_device *pdev)
1557 {
1558 	struct device_node *np = pdev->dev.of_node;
1559 	struct resource *res;
1560 	struct at91_gpio_chip *at91_chip = NULL;
1561 	struct gpio_chip *chip;
1562 	struct pinctrl_gpio_range *range;
1563 	int ret = 0;
1564 	int irq, i;
1565 	int alias_idx = of_alias_get_id(np, "gpio");
1566 	uint32_t ngpio;
1567 	char **names;
1568 
1569 	BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
1570 	if (gpio_chips[alias_idx]) {
1571 		ret = -EBUSY;
1572 		goto err;
1573 	}
1574 
1575 	irq = platform_get_irq(pdev, 0);
1576 	if (irq < 0) {
1577 		ret = irq;
1578 		goto err;
1579 	}
1580 
1581 	at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL);
1582 	if (!at91_chip) {
1583 		ret = -ENOMEM;
1584 		goto err;
1585 	}
1586 
1587 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1588 	at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res);
1589 	if (IS_ERR(at91_chip->regbase)) {
1590 		ret = PTR_ERR(at91_chip->regbase);
1591 		goto err;
1592 	}
1593 
1594 	at91_chip->ops = (struct at91_pinctrl_mux_ops *)
1595 		of_match_device(at91_gpio_of_match, &pdev->dev)->data;
1596 	at91_chip->pioc_virq = irq;
1597 	at91_chip->pioc_idx = alias_idx;
1598 
1599 	at91_chip->clock = clk_get(&pdev->dev, NULL);
1600 	if (IS_ERR(at91_chip->clock)) {
1601 		dev_err(&pdev->dev, "failed to get clock, ignoring.\n");
1602 		goto err;
1603 	}
1604 
1605 	if (clk_prepare(at91_chip->clock))
1606 		goto clk_prep_err;
1607 
1608 	/* enable PIO controller's clock */
1609 	if (clk_enable(at91_chip->clock)) {
1610 		dev_err(&pdev->dev, "failed to enable clock, ignoring.\n");
1611 		goto clk_err;
1612 	}
1613 
1614 	at91_chip->chip = at91_gpio_template;
1615 
1616 	chip = &at91_chip->chip;
1617 	chip->of_node = np;
1618 	chip->label = dev_name(&pdev->dev);
1619 	chip->dev = &pdev->dev;
1620 	chip->owner = THIS_MODULE;
1621 	chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
1622 
1623 	if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) {
1624 		if (ngpio >= MAX_NB_GPIO_PER_BANK)
1625 			pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
1626 			       alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
1627 		else
1628 			chip->ngpio = ngpio;
1629 	}
1630 
1631 	names = devm_kzalloc(&pdev->dev, sizeof(char *) * chip->ngpio,
1632 			     GFP_KERNEL);
1633 
1634 	if (!names) {
1635 		ret = -ENOMEM;
1636 		goto clk_err;
1637 	}
1638 
1639 	for (i = 0; i < chip->ngpio; i++)
1640 		names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i);
1641 
1642 	chip->names = (const char *const *)names;
1643 
1644 	range = &at91_chip->range;
1645 	range->name = chip->label;
1646 	range->id = alias_idx;
1647 	range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
1648 
1649 	range->npins = chip->ngpio;
1650 	range->gc = chip;
1651 
1652 	ret = gpiochip_add(chip);
1653 	if (ret)
1654 		goto clk_err;
1655 
1656 	gpio_chips[alias_idx] = at91_chip;
1657 	gpio_banks = max(gpio_banks, alias_idx + 1);
1658 
1659 	at91_gpio_probe_fixup();
1660 
1661 	at91_gpio_of_irq_setup(np, at91_chip);
1662 
1663 	dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
1664 
1665 	return 0;
1666 
1667 clk_err:
1668 	clk_unprepare(at91_chip->clock);
1669 clk_prep_err:
1670 	clk_put(at91_chip->clock);
1671 err:
1672 	dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
1673 
1674 	return ret;
1675 }
1676 
1677 static struct platform_driver at91_gpio_driver = {
1678 	.driver = {
1679 		.name = "gpio-at91",
1680 		.owner = THIS_MODULE,
1681 		.of_match_table = at91_gpio_of_match,
1682 	},
1683 	.probe = at91_gpio_probe,
1684 };
1685 
1686 static struct platform_driver at91_pinctrl_driver = {
1687 	.driver = {
1688 		.name = "pinctrl-at91",
1689 		.owner = THIS_MODULE,
1690 		.of_match_table = at91_pinctrl_of_match,
1691 	},
1692 	.probe = at91_pinctrl_probe,
1693 	.remove = at91_pinctrl_remove,
1694 };
1695 
1696 static int __init at91_pinctrl_init(void)
1697 {
1698 	int ret;
1699 
1700 	ret = platform_driver_register(&at91_gpio_driver);
1701 	if (ret)
1702 		return ret;
1703 	return platform_driver_register(&at91_pinctrl_driver);
1704 }
1705 arch_initcall(at91_pinctrl_init);
1706 
1707 static void __exit at91_pinctrl_exit(void)
1708 {
1709 	platform_driver_unregister(&at91_pinctrl_driver);
1710 }
1711 
1712 module_exit(at91_pinctrl_exit);
1713 MODULE_AUTHOR("Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>");
1714 MODULE_DESCRIPTION("Atmel AT91 pinctrl driver");
1715 MODULE_LICENSE("GPL v2");
1716