1 /* 2 * at91 pinctrl driver based on at91 pinmux core 3 * 4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 5 * 6 * Under GPLv2 only 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/err.h> 11 #include <linux/init.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_device.h> 15 #include <linux/of_address.h> 16 #include <linux/of_irq.h> 17 #include <linux/slab.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/irqdomain.h> 21 #include <linux/irqchip/chained_irq.h> 22 #include <linux/io.h> 23 #include <linux/gpio.h> 24 #include <linux/pinctrl/machine.h> 25 #include <linux/pinctrl/pinconf.h> 26 #include <linux/pinctrl/pinctrl.h> 27 #include <linux/pinctrl/pinmux.h> 28 /* Since we request GPIOs from ourself */ 29 #include <linux/pinctrl/consumer.h> 30 31 #include <mach/hardware.h> 32 #include <mach/at91_pio.h> 33 34 #include "core.h" 35 36 #define MAX_NB_GPIO_PER_BANK 32 37 38 struct at91_pinctrl_mux_ops; 39 40 struct at91_gpio_chip { 41 struct gpio_chip chip; 42 struct pinctrl_gpio_range range; 43 struct at91_gpio_chip *next; /* Bank sharing same clock */ 44 int pioc_hwirq; /* PIO bank interrupt identifier on AIC */ 45 int pioc_virq; /* PIO bank Linux virtual interrupt */ 46 int pioc_idx; /* PIO bank index */ 47 void __iomem *regbase; /* PIO bank virtual address */ 48 struct clk *clock; /* associated clock */ 49 struct irq_domain *domain; /* associated irq domain */ 50 struct at91_pinctrl_mux_ops *ops; /* ops */ 51 }; 52 53 #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip) 54 55 static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS]; 56 57 static int gpio_banks; 58 59 #define PULL_UP (1 << 0) 60 #define MULTI_DRIVE (1 << 1) 61 #define DEGLITCH (1 << 2) 62 #define PULL_DOWN (1 << 3) 63 #define DIS_SCHMIT (1 << 4) 64 #define DEBOUNCE (1 << 16) 65 #define DEBOUNCE_VAL_SHIFT 17 66 #define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT) 67 68 /** 69 * struct at91_pmx_func - describes AT91 pinmux functions 70 * @name: the name of this specific function 71 * @groups: corresponding pin groups 72 * @ngroups: the number of groups 73 */ 74 struct at91_pmx_func { 75 const char *name; 76 const char **groups; 77 unsigned ngroups; 78 }; 79 80 enum at91_mux { 81 AT91_MUX_GPIO = 0, 82 AT91_MUX_PERIPH_A = 1, 83 AT91_MUX_PERIPH_B = 2, 84 AT91_MUX_PERIPH_C = 3, 85 AT91_MUX_PERIPH_D = 4, 86 }; 87 88 /** 89 * struct at91_pmx_pin - describes an At91 pin mux 90 * @bank: the bank of the pin 91 * @pin: the pin number in the @bank 92 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function. 93 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc... 94 */ 95 struct at91_pmx_pin { 96 uint32_t bank; 97 uint32_t pin; 98 enum at91_mux mux; 99 unsigned long conf; 100 }; 101 102 /** 103 * struct at91_pin_group - describes an At91 pin group 104 * @name: the name of this specific pin group 105 * @pins_conf: the mux mode for each pin in this group. The size of this 106 * array is the same as pins. 107 * @pins: an array of discrete physical pins used in this group, taken 108 * from the driver-local pin enumeration space 109 * @npins: the number of pins in this group array, i.e. the number of 110 * elements in .pins so we can iterate over that array 111 */ 112 struct at91_pin_group { 113 const char *name; 114 struct at91_pmx_pin *pins_conf; 115 unsigned int *pins; 116 unsigned npins; 117 }; 118 119 /** 120 * struct at91_pinctrl_mux_ops - describes an At91 mux ops group 121 * on new IP with support for periph C and D the way to mux in 122 * periph A and B has changed 123 * So provide the right call back 124 * if not present means the IP does not support it 125 * @get_periph: return the periph mode configured 126 * @mux_A_periph: mux as periph A 127 * @mux_B_periph: mux as periph B 128 * @mux_C_periph: mux as periph C 129 * @mux_D_periph: mux as periph D 130 * @get_deglitch: get deglitch status 131 * @set_deglitch: enable/disable deglitch 132 * @get_debounce: get debounce status 133 * @set_debounce: enable/disable debounce 134 * @get_pulldown: get pulldown status 135 * @set_pulldown: enable/disable pulldown 136 * @get_schmitt_trig: get schmitt trigger status 137 * @disable_schmitt_trig: disable schmitt trigger 138 * @irq_type: return irq type 139 */ 140 struct at91_pinctrl_mux_ops { 141 enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask); 142 void (*mux_A_periph)(void __iomem *pio, unsigned mask); 143 void (*mux_B_periph)(void __iomem *pio, unsigned mask); 144 void (*mux_C_periph)(void __iomem *pio, unsigned mask); 145 void (*mux_D_periph)(void __iomem *pio, unsigned mask); 146 bool (*get_deglitch)(void __iomem *pio, unsigned pin); 147 void (*set_deglitch)(void __iomem *pio, unsigned mask, bool in_on); 148 bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div); 149 void (*set_debounce)(void __iomem *pio, unsigned mask, bool in_on, u32 div); 150 bool (*get_pulldown)(void __iomem *pio, unsigned pin); 151 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool in_on); 152 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin); 153 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask); 154 /* irq */ 155 int (*irq_type)(struct irq_data *d, unsigned type); 156 }; 157 158 static int gpio_irq_type(struct irq_data *d, unsigned type); 159 static int alt_gpio_irq_type(struct irq_data *d, unsigned type); 160 161 struct at91_pinctrl { 162 struct device *dev; 163 struct pinctrl_dev *pctl; 164 165 int nbanks; 166 167 uint32_t *mux_mask; 168 int nmux; 169 170 struct at91_pmx_func *functions; 171 int nfunctions; 172 173 struct at91_pin_group *groups; 174 int ngroups; 175 176 struct at91_pinctrl_mux_ops *ops; 177 }; 178 179 static const inline struct at91_pin_group *at91_pinctrl_find_group_by_name( 180 const struct at91_pinctrl *info, 181 const char *name) 182 { 183 const struct at91_pin_group *grp = NULL; 184 int i; 185 186 for (i = 0; i < info->ngroups; i++) { 187 if (strcmp(info->groups[i].name, name)) 188 continue; 189 190 grp = &info->groups[i]; 191 dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]); 192 break; 193 } 194 195 return grp; 196 } 197 198 static int at91_get_groups_count(struct pinctrl_dev *pctldev) 199 { 200 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 201 202 return info->ngroups; 203 } 204 205 static const char *at91_get_group_name(struct pinctrl_dev *pctldev, 206 unsigned selector) 207 { 208 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 209 210 return info->groups[selector].name; 211 } 212 213 static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, 214 const unsigned **pins, 215 unsigned *npins) 216 { 217 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 218 219 if (selector >= info->ngroups) 220 return -EINVAL; 221 222 *pins = info->groups[selector].pins; 223 *npins = info->groups[selector].npins; 224 225 return 0; 226 } 227 228 static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 229 unsigned offset) 230 { 231 seq_printf(s, "%s", dev_name(pctldev->dev)); 232 } 233 234 static int at91_dt_node_to_map(struct pinctrl_dev *pctldev, 235 struct device_node *np, 236 struct pinctrl_map **map, unsigned *num_maps) 237 { 238 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 239 const struct at91_pin_group *grp; 240 struct pinctrl_map *new_map; 241 struct device_node *parent; 242 int map_num = 1; 243 int i; 244 245 /* 246 * first find the group of this node and check if we need create 247 * config maps for pins 248 */ 249 grp = at91_pinctrl_find_group_by_name(info, np->name); 250 if (!grp) { 251 dev_err(info->dev, "unable to find group for node %s\n", 252 np->name); 253 return -EINVAL; 254 } 255 256 map_num += grp->npins; 257 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, GFP_KERNEL); 258 if (!new_map) 259 return -ENOMEM; 260 261 *map = new_map; 262 *num_maps = map_num; 263 264 /* create mux map */ 265 parent = of_get_parent(np); 266 if (!parent) { 267 devm_kfree(pctldev->dev, new_map); 268 return -EINVAL; 269 } 270 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 271 new_map[0].data.mux.function = parent->name; 272 new_map[0].data.mux.group = np->name; 273 of_node_put(parent); 274 275 /* create config map */ 276 new_map++; 277 for (i = 0; i < grp->npins; i++) { 278 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 279 new_map[i].data.configs.group_or_pin = 280 pin_get_name(pctldev, grp->pins[i]); 281 new_map[i].data.configs.configs = &grp->pins_conf[i].conf; 282 new_map[i].data.configs.num_configs = 1; 283 } 284 285 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 286 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 287 288 return 0; 289 } 290 291 static void at91_dt_free_map(struct pinctrl_dev *pctldev, 292 struct pinctrl_map *map, unsigned num_maps) 293 { 294 } 295 296 static const struct pinctrl_ops at91_pctrl_ops = { 297 .get_groups_count = at91_get_groups_count, 298 .get_group_name = at91_get_group_name, 299 .get_group_pins = at91_get_group_pins, 300 .pin_dbg_show = at91_pin_dbg_show, 301 .dt_node_to_map = at91_dt_node_to_map, 302 .dt_free_map = at91_dt_free_map, 303 }; 304 305 static void __iomem *pin_to_controller(struct at91_pinctrl *info, 306 unsigned int bank) 307 { 308 return gpio_chips[bank]->regbase; 309 } 310 311 static inline int pin_to_bank(unsigned pin) 312 { 313 return pin /= MAX_NB_GPIO_PER_BANK; 314 } 315 316 static unsigned pin_to_mask(unsigned int pin) 317 { 318 return 1 << pin; 319 } 320 321 static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask) 322 { 323 writel_relaxed(mask, pio + PIO_IDR); 324 } 325 326 static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin) 327 { 328 return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1); 329 } 330 331 static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on) 332 { 333 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR)); 334 } 335 336 static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin) 337 { 338 return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1; 339 } 340 341 static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on) 342 { 343 writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR)); 344 } 345 346 static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask) 347 { 348 writel_relaxed(mask, pio + PIO_ASR); 349 } 350 351 static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask) 352 { 353 writel_relaxed(mask, pio + PIO_BSR); 354 } 355 356 static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask) 357 { 358 359 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, 360 pio + PIO_ABCDSR1); 361 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, 362 pio + PIO_ABCDSR2); 363 } 364 365 static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask) 366 { 367 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, 368 pio + PIO_ABCDSR1); 369 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, 370 pio + PIO_ABCDSR2); 371 } 372 373 static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask) 374 { 375 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1); 376 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); 377 } 378 379 static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask) 380 { 381 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1); 382 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); 383 } 384 385 static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask) 386 { 387 unsigned select; 388 389 if (readl_relaxed(pio + PIO_PSR) & mask) 390 return AT91_MUX_GPIO; 391 392 select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask); 393 select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1); 394 395 return select + 1; 396 } 397 398 static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask) 399 { 400 unsigned select; 401 402 if (readl_relaxed(pio + PIO_PSR) & mask) 403 return AT91_MUX_GPIO; 404 405 select = readl_relaxed(pio + PIO_ABSR) & mask; 406 407 return select + 1; 408 } 409 410 static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin) 411 { 412 return (__raw_readl(pio + PIO_IFSR) >> pin) & 0x1; 413 } 414 415 static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) 416 { 417 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); 418 } 419 420 static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) 421 { 422 if (is_on) 423 __raw_writel(mask, pio + PIO_IFSCDR); 424 at91_mux_set_deglitch(pio, mask, is_on); 425 } 426 427 static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div) 428 { 429 *div = __raw_readl(pio + PIO_SCDR); 430 431 return (__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1; 432 } 433 434 static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask, 435 bool is_on, u32 div) 436 { 437 if (is_on) { 438 __raw_writel(mask, pio + PIO_IFSCER); 439 __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR); 440 __raw_writel(mask, pio + PIO_IFER); 441 } else { 442 __raw_writel(mask, pio + PIO_IFDR); 443 } 444 } 445 446 static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin) 447 { 448 return !((__raw_readl(pio + PIO_PPDSR) >> pin) & 0x1); 449 } 450 451 static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on) 452 { 453 __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR)); 454 } 455 456 static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask) 457 { 458 __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT); 459 } 460 461 static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin) 462 { 463 return (__raw_readl(pio + PIO_SCHMITT) >> pin) & 0x1; 464 } 465 466 static struct at91_pinctrl_mux_ops at91rm9200_ops = { 467 .get_periph = at91_mux_get_periph, 468 .mux_A_periph = at91_mux_set_A_periph, 469 .mux_B_periph = at91_mux_set_B_periph, 470 .get_deglitch = at91_mux_get_deglitch, 471 .set_deglitch = at91_mux_set_deglitch, 472 .irq_type = gpio_irq_type, 473 }; 474 475 static struct at91_pinctrl_mux_ops at91sam9x5_ops = { 476 .get_periph = at91_mux_pio3_get_periph, 477 .mux_A_periph = at91_mux_pio3_set_A_periph, 478 .mux_B_periph = at91_mux_pio3_set_B_periph, 479 .mux_C_periph = at91_mux_pio3_set_C_periph, 480 .mux_D_periph = at91_mux_pio3_set_D_periph, 481 .get_deglitch = at91_mux_get_deglitch, 482 .set_deglitch = at91_mux_pio3_set_deglitch, 483 .get_debounce = at91_mux_pio3_get_debounce, 484 .set_debounce = at91_mux_pio3_set_debounce, 485 .get_pulldown = at91_mux_pio3_get_pulldown, 486 .set_pulldown = at91_mux_pio3_set_pulldown, 487 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig, 488 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig, 489 .irq_type = alt_gpio_irq_type, 490 }; 491 492 static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin) 493 { 494 if (pin->mux) { 495 dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lu\n", 496 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf); 497 } else { 498 dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lu\n", 499 pin->bank + 'A', pin->pin, pin->conf); 500 } 501 } 502 503 static int pin_check_config(struct at91_pinctrl *info, const char *name, 504 int index, const struct at91_pmx_pin *pin) 505 { 506 int mux; 507 508 /* check if it's a valid config */ 509 if (pin->bank >= info->nbanks) { 510 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n", 511 name, index, pin->bank, info->nbanks); 512 return -EINVAL; 513 } 514 515 if (pin->pin >= MAX_NB_GPIO_PER_BANK) { 516 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n", 517 name, index, pin->pin, MAX_NB_GPIO_PER_BANK); 518 return -EINVAL; 519 } 520 521 if (!pin->mux) 522 return 0; 523 524 mux = pin->mux - 1; 525 526 if (mux >= info->nmux) { 527 dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n", 528 name, index, mux, info->nmux); 529 return -EINVAL; 530 } 531 532 if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) { 533 dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n", 534 name, index, mux, pin->bank + 'A', pin->pin); 535 return -EINVAL; 536 } 537 538 return 0; 539 } 540 541 static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask) 542 { 543 writel_relaxed(mask, pio + PIO_PDR); 544 } 545 546 static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input) 547 { 548 writel_relaxed(mask, pio + PIO_PER); 549 writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER)); 550 } 551 552 static int at91_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, 553 unsigned group) 554 { 555 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 556 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf; 557 const struct at91_pmx_pin *pin; 558 uint32_t npins = info->groups[group].npins; 559 int i, ret; 560 unsigned mask; 561 void __iomem *pio; 562 563 dev_dbg(info->dev, "enable function %s group %s\n", 564 info->functions[selector].name, info->groups[group].name); 565 566 /* first check that all the pins of the group are valid with a valid 567 * paramter */ 568 for (i = 0; i < npins; i++) { 569 pin = &pins_conf[i]; 570 ret = pin_check_config(info, info->groups[group].name, i, pin); 571 if (ret) 572 return ret; 573 } 574 575 for (i = 0; i < npins; i++) { 576 pin = &pins_conf[i]; 577 at91_pin_dbg(info->dev, pin); 578 pio = pin_to_controller(info, pin->bank); 579 mask = pin_to_mask(pin->pin); 580 at91_mux_disable_interrupt(pio, mask); 581 switch (pin->mux) { 582 case AT91_MUX_GPIO: 583 at91_mux_gpio_enable(pio, mask, 1); 584 break; 585 case AT91_MUX_PERIPH_A: 586 info->ops->mux_A_periph(pio, mask); 587 break; 588 case AT91_MUX_PERIPH_B: 589 info->ops->mux_B_periph(pio, mask); 590 break; 591 case AT91_MUX_PERIPH_C: 592 if (!info->ops->mux_C_periph) 593 return -EINVAL; 594 info->ops->mux_C_periph(pio, mask); 595 break; 596 case AT91_MUX_PERIPH_D: 597 if (!info->ops->mux_D_periph) 598 return -EINVAL; 599 info->ops->mux_D_periph(pio, mask); 600 break; 601 } 602 if (pin->mux) 603 at91_mux_gpio_disable(pio, mask); 604 } 605 606 return 0; 607 } 608 609 static void at91_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector, 610 unsigned group) 611 { 612 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 613 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf; 614 const struct at91_pmx_pin *pin; 615 uint32_t npins = info->groups[group].npins; 616 int i; 617 unsigned mask; 618 void __iomem *pio; 619 620 for (i = 0; i < npins; i++) { 621 pin = &pins_conf[i]; 622 at91_pin_dbg(info->dev, pin); 623 pio = pin_to_controller(info, pin->bank); 624 mask = pin_to_mask(pin->pin); 625 at91_mux_gpio_enable(pio, mask, 1); 626 } 627 } 628 629 static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 630 { 631 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 632 633 return info->nfunctions; 634 } 635 636 static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev, 637 unsigned selector) 638 { 639 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 640 641 return info->functions[selector].name; 642 } 643 644 static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, 645 const char * const **groups, 646 unsigned * const num_groups) 647 { 648 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 649 650 *groups = info->functions[selector].groups; 651 *num_groups = info->functions[selector].ngroups; 652 653 return 0; 654 } 655 656 static int at91_gpio_request_enable(struct pinctrl_dev *pctldev, 657 struct pinctrl_gpio_range *range, 658 unsigned offset) 659 { 660 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 661 struct at91_gpio_chip *at91_chip; 662 struct gpio_chip *chip; 663 unsigned mask; 664 665 if (!range) { 666 dev_err(npct->dev, "invalid range\n"); 667 return -EINVAL; 668 } 669 if (!range->gc) { 670 dev_err(npct->dev, "missing GPIO chip in range\n"); 671 return -EINVAL; 672 } 673 chip = range->gc; 674 at91_chip = container_of(chip, struct at91_gpio_chip, chip); 675 676 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); 677 678 mask = 1 << (offset - chip->base); 679 680 dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n", 681 offset, 'A' + range->id, offset - chip->base, mask); 682 683 writel_relaxed(mask, at91_chip->regbase + PIO_PER); 684 685 return 0; 686 } 687 688 static void at91_gpio_disable_free(struct pinctrl_dev *pctldev, 689 struct pinctrl_gpio_range *range, 690 unsigned offset) 691 { 692 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 693 694 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); 695 /* Set the pin to some default state, GPIO is usually default */ 696 } 697 698 static const struct pinmux_ops at91_pmx_ops = { 699 .get_functions_count = at91_pmx_get_funcs_count, 700 .get_function_name = at91_pmx_get_func_name, 701 .get_function_groups = at91_pmx_get_groups, 702 .enable = at91_pmx_enable, 703 .disable = at91_pmx_disable, 704 .gpio_request_enable = at91_gpio_request_enable, 705 .gpio_disable_free = at91_gpio_disable_free, 706 }; 707 708 static int at91_pinconf_get(struct pinctrl_dev *pctldev, 709 unsigned pin_id, unsigned long *config) 710 { 711 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 712 void __iomem *pio; 713 unsigned pin; 714 int div; 715 716 dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, *config); 717 pio = pin_to_controller(info, pin_to_bank(pin_id)); 718 pin = pin_id % MAX_NB_GPIO_PER_BANK; 719 720 if (at91_mux_get_multidrive(pio, pin)) 721 *config |= MULTI_DRIVE; 722 723 if (at91_mux_get_pullup(pio, pin)) 724 *config |= PULL_UP; 725 726 if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin)) 727 *config |= DEGLITCH; 728 if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div)) 729 *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT); 730 if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin)) 731 *config |= PULL_DOWN; 732 if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin)) 733 *config |= DIS_SCHMIT; 734 735 return 0; 736 } 737 738 static int at91_pinconf_set(struct pinctrl_dev *pctldev, 739 unsigned pin_id, unsigned long *configs, 740 unsigned num_configs) 741 { 742 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 743 unsigned mask; 744 void __iomem *pio; 745 int i; 746 unsigned long config; 747 748 for (i = 0; i < num_configs; i++) { 749 config = configs[i]; 750 751 dev_dbg(info->dev, 752 "%s:%d, pin_id=%d, config=0x%lx", 753 __func__, __LINE__, pin_id, config); 754 pio = pin_to_controller(info, pin_to_bank(pin_id)); 755 mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK); 756 757 if (config & PULL_UP && config & PULL_DOWN) 758 return -EINVAL; 759 760 at91_mux_set_pullup(pio, mask, config & PULL_UP); 761 at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE); 762 if (info->ops->set_deglitch) 763 info->ops->set_deglitch(pio, mask, config & DEGLITCH); 764 if (info->ops->set_debounce) 765 info->ops->set_debounce(pio, mask, config & DEBOUNCE, 766 (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT); 767 if (info->ops->set_pulldown) 768 info->ops->set_pulldown(pio, mask, config & PULL_DOWN); 769 if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT) 770 info->ops->disable_schmitt_trig(pio, mask); 771 772 } /* for each config */ 773 774 return 0; 775 } 776 777 static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev, 778 struct seq_file *s, unsigned pin_id) 779 { 780 781 } 782 783 static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 784 struct seq_file *s, unsigned group) 785 { 786 } 787 788 static const struct pinconf_ops at91_pinconf_ops = { 789 .pin_config_get = at91_pinconf_get, 790 .pin_config_set = at91_pinconf_set, 791 .pin_config_dbg_show = at91_pinconf_dbg_show, 792 .pin_config_group_dbg_show = at91_pinconf_group_dbg_show, 793 }; 794 795 static struct pinctrl_desc at91_pinctrl_desc = { 796 .pctlops = &at91_pctrl_ops, 797 .pmxops = &at91_pmx_ops, 798 .confops = &at91_pinconf_ops, 799 .owner = THIS_MODULE, 800 }; 801 802 static const char *gpio_compat = "atmel,at91rm9200-gpio"; 803 804 static void at91_pinctrl_child_count(struct at91_pinctrl *info, 805 struct device_node *np) 806 { 807 struct device_node *child; 808 809 for_each_child_of_node(np, child) { 810 if (of_device_is_compatible(child, gpio_compat)) { 811 info->nbanks++; 812 } else { 813 info->nfunctions++; 814 info->ngroups += of_get_child_count(child); 815 } 816 } 817 } 818 819 static int at91_pinctrl_mux_mask(struct at91_pinctrl *info, 820 struct device_node *np) 821 { 822 int ret = 0; 823 int size; 824 const __be32 *list; 825 826 list = of_get_property(np, "atmel,mux-mask", &size); 827 if (!list) { 828 dev_err(info->dev, "can not read the mux-mask of %d\n", size); 829 return -EINVAL; 830 } 831 832 size /= sizeof(*list); 833 if (!size || size % info->nbanks) { 834 dev_err(info->dev, "wrong mux mask array should be by %d\n", info->nbanks); 835 return -EINVAL; 836 } 837 info->nmux = size / info->nbanks; 838 839 info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL); 840 if (!info->mux_mask) { 841 dev_err(info->dev, "could not alloc mux_mask\n"); 842 return -ENOMEM; 843 } 844 845 ret = of_property_read_u32_array(np, "atmel,mux-mask", 846 info->mux_mask, size); 847 if (ret) 848 dev_err(info->dev, "can not read the mux-mask of %d\n", size); 849 return ret; 850 } 851 852 static int at91_pinctrl_parse_groups(struct device_node *np, 853 struct at91_pin_group *grp, 854 struct at91_pinctrl *info, u32 index) 855 { 856 struct at91_pmx_pin *pin; 857 int size; 858 const __be32 *list; 859 int i, j; 860 861 dev_dbg(info->dev, "group(%d): %s\n", index, np->name); 862 863 /* Initialise group */ 864 grp->name = np->name; 865 866 /* 867 * the binding format is atmel,pins = <bank pin mux CONFIG ...>, 868 * do sanity check and calculate pins number 869 */ 870 list = of_get_property(np, "atmel,pins", &size); 871 /* we do not check return since it's safe node passed down */ 872 size /= sizeof(*list); 873 if (!size || size % 4) { 874 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); 875 return -EINVAL; 876 } 877 878 grp->npins = size / 4; 879 pin = grp->pins_conf = devm_kzalloc(info->dev, grp->npins * sizeof(struct at91_pmx_pin), 880 GFP_KERNEL); 881 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), 882 GFP_KERNEL); 883 if (!grp->pins_conf || !grp->pins) 884 return -ENOMEM; 885 886 for (i = 0, j = 0; i < size; i += 4, j++) { 887 pin->bank = be32_to_cpu(*list++); 888 pin->pin = be32_to_cpu(*list++); 889 grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin; 890 pin->mux = be32_to_cpu(*list++); 891 pin->conf = be32_to_cpu(*list++); 892 893 at91_pin_dbg(info->dev, pin); 894 pin++; 895 } 896 897 return 0; 898 } 899 900 static int at91_pinctrl_parse_functions(struct device_node *np, 901 struct at91_pinctrl *info, u32 index) 902 { 903 struct device_node *child; 904 struct at91_pmx_func *func; 905 struct at91_pin_group *grp; 906 int ret; 907 static u32 grp_index; 908 u32 i = 0; 909 910 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); 911 912 func = &info->functions[index]; 913 914 /* Initialise function */ 915 func->name = np->name; 916 func->ngroups = of_get_child_count(np); 917 if (func->ngroups <= 0) { 918 dev_err(info->dev, "no groups defined\n"); 919 return -EINVAL; 920 } 921 func->groups = devm_kzalloc(info->dev, 922 func->ngroups * sizeof(char *), GFP_KERNEL); 923 if (!func->groups) 924 return -ENOMEM; 925 926 for_each_child_of_node(np, child) { 927 func->groups[i] = child->name; 928 grp = &info->groups[grp_index++]; 929 ret = at91_pinctrl_parse_groups(child, grp, info, i++); 930 if (ret) 931 return ret; 932 } 933 934 return 0; 935 } 936 937 static struct of_device_id at91_pinctrl_of_match[] = { 938 { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops }, 939 { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops }, 940 { /* sentinel */ } 941 }; 942 943 static int at91_pinctrl_probe_dt(struct platform_device *pdev, 944 struct at91_pinctrl *info) 945 { 946 int ret = 0; 947 int i, j; 948 uint32_t *tmp; 949 struct device_node *np = pdev->dev.of_node; 950 struct device_node *child; 951 952 if (!np) 953 return -ENODEV; 954 955 info->dev = &pdev->dev; 956 info->ops = (struct at91_pinctrl_mux_ops *) 957 of_match_device(at91_pinctrl_of_match, &pdev->dev)->data; 958 at91_pinctrl_child_count(info, np); 959 960 if (info->nbanks < 1) { 961 dev_err(&pdev->dev, "you need to specify atleast one gpio-controller\n"); 962 return -EINVAL; 963 } 964 965 ret = at91_pinctrl_mux_mask(info, np); 966 if (ret) 967 return ret; 968 969 dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux); 970 971 dev_dbg(&pdev->dev, "mux-mask\n"); 972 tmp = info->mux_mask; 973 for (i = 0; i < info->nbanks; i++) { 974 for (j = 0; j < info->nmux; j++, tmp++) { 975 dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]); 976 } 977 } 978 979 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 980 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 981 info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * sizeof(struct at91_pmx_func), 982 GFP_KERNEL); 983 if (!info->functions) 984 return -ENOMEM; 985 986 info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct at91_pin_group), 987 GFP_KERNEL); 988 if (!info->groups) 989 return -ENOMEM; 990 991 dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks); 992 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 993 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 994 995 i = 0; 996 997 for_each_child_of_node(np, child) { 998 if (of_device_is_compatible(child, gpio_compat)) 999 continue; 1000 ret = at91_pinctrl_parse_functions(child, info, i++); 1001 if (ret) { 1002 dev_err(&pdev->dev, "failed to parse function\n"); 1003 return ret; 1004 } 1005 } 1006 1007 return 0; 1008 } 1009 1010 static int at91_pinctrl_probe(struct platform_device *pdev) 1011 { 1012 struct at91_pinctrl *info; 1013 struct pinctrl_pin_desc *pdesc; 1014 int ret, i, j, k; 1015 1016 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); 1017 if (!info) 1018 return -ENOMEM; 1019 1020 ret = at91_pinctrl_probe_dt(pdev, info); 1021 if (ret) 1022 return ret; 1023 1024 /* 1025 * We need all the GPIO drivers to probe FIRST, or we will not be able 1026 * to obtain references to the struct gpio_chip * for them, and we 1027 * need this to proceed. 1028 */ 1029 for (i = 0; i < info->nbanks; i++) { 1030 if (!gpio_chips[i]) { 1031 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i); 1032 devm_kfree(&pdev->dev, info); 1033 return -EPROBE_DEFER; 1034 } 1035 } 1036 1037 at91_pinctrl_desc.name = dev_name(&pdev->dev); 1038 at91_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK; 1039 at91_pinctrl_desc.pins = pdesc = 1040 devm_kzalloc(&pdev->dev, sizeof(*pdesc) * at91_pinctrl_desc.npins, GFP_KERNEL); 1041 1042 if (!at91_pinctrl_desc.pins) 1043 return -ENOMEM; 1044 1045 for (i = 0 , k = 0; i < info->nbanks; i++) { 1046 for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) { 1047 pdesc->number = k; 1048 pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j); 1049 pdesc++; 1050 } 1051 } 1052 1053 platform_set_drvdata(pdev, info); 1054 info->pctl = pinctrl_register(&at91_pinctrl_desc, &pdev->dev, info); 1055 1056 if (!info->pctl) { 1057 dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n"); 1058 ret = -EINVAL; 1059 goto err; 1060 } 1061 1062 /* We will handle a range of GPIO pins */ 1063 for (i = 0; i < info->nbanks; i++) 1064 pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range); 1065 1066 dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n"); 1067 1068 return 0; 1069 1070 err: 1071 return ret; 1072 } 1073 1074 static int at91_pinctrl_remove(struct platform_device *pdev) 1075 { 1076 struct at91_pinctrl *info = platform_get_drvdata(pdev); 1077 1078 pinctrl_unregister(info->pctl); 1079 1080 return 0; 1081 } 1082 1083 static int at91_gpio_request(struct gpio_chip *chip, unsigned offset) 1084 { 1085 /* 1086 * Map back to global GPIO space and request muxing, the direction 1087 * parameter does not matter for this controller. 1088 */ 1089 int gpio = chip->base + offset; 1090 int bank = chip->base / chip->ngpio; 1091 1092 dev_dbg(chip->dev, "%s:%d pio%c%d(%d)\n", __func__, __LINE__, 1093 'A' + bank, offset, gpio); 1094 1095 return pinctrl_request_gpio(gpio); 1096 } 1097 1098 static void at91_gpio_free(struct gpio_chip *chip, unsigned offset) 1099 { 1100 int gpio = chip->base + offset; 1101 1102 pinctrl_free_gpio(gpio); 1103 } 1104 1105 static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 1106 { 1107 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 1108 void __iomem *pio = at91_gpio->regbase; 1109 unsigned mask = 1 << offset; 1110 1111 writel_relaxed(mask, pio + PIO_ODR); 1112 return 0; 1113 } 1114 1115 static int at91_gpio_get(struct gpio_chip *chip, unsigned offset) 1116 { 1117 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 1118 void __iomem *pio = at91_gpio->regbase; 1119 unsigned mask = 1 << offset; 1120 u32 pdsr; 1121 1122 pdsr = readl_relaxed(pio + PIO_PDSR); 1123 return (pdsr & mask) != 0; 1124 } 1125 1126 static void at91_gpio_set(struct gpio_chip *chip, unsigned offset, 1127 int val) 1128 { 1129 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 1130 void __iomem *pio = at91_gpio->regbase; 1131 unsigned mask = 1 << offset; 1132 1133 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); 1134 } 1135 1136 static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 1137 int val) 1138 { 1139 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 1140 void __iomem *pio = at91_gpio->regbase; 1141 unsigned mask = 1 << offset; 1142 1143 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); 1144 writel_relaxed(mask, pio + PIO_OER); 1145 1146 return 0; 1147 } 1148 1149 static int at91_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 1150 { 1151 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 1152 int virq; 1153 1154 if (offset < chip->ngpio) 1155 virq = irq_create_mapping(at91_gpio->domain, offset); 1156 else 1157 virq = -ENXIO; 1158 1159 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n", 1160 chip->label, offset + chip->base, virq); 1161 return virq; 1162 } 1163 1164 #ifdef CONFIG_DEBUG_FS 1165 static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 1166 { 1167 enum at91_mux mode; 1168 int i; 1169 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 1170 void __iomem *pio = at91_gpio->regbase; 1171 1172 for (i = 0; i < chip->ngpio; i++) { 1173 unsigned pin = chip->base + i; 1174 unsigned mask = pin_to_mask(pin); 1175 const char *gpio_label; 1176 u32 pdsr; 1177 1178 gpio_label = gpiochip_is_requested(chip, i); 1179 if (!gpio_label) 1180 continue; 1181 mode = at91_gpio->ops->get_periph(pio, mask); 1182 seq_printf(s, "[%s] GPIO%s%d: ", 1183 gpio_label, chip->label, i); 1184 if (mode == AT91_MUX_GPIO) { 1185 pdsr = readl_relaxed(pio + PIO_PDSR); 1186 1187 seq_printf(s, "[gpio] %s\n", 1188 pdsr & mask ? 1189 "set" : "clear"); 1190 } else { 1191 seq_printf(s, "[periph %c]\n", 1192 mode + 'A' - 1); 1193 } 1194 } 1195 } 1196 #else 1197 #define at91_gpio_dbg_show NULL 1198 #endif 1199 1200 /* Several AIC controller irqs are dispatched through this GPIO handler. 1201 * To use any AT91_PIN_* as an externally triggered IRQ, first call 1202 * at91_set_gpio_input() then maybe enable its glitch filter. 1203 * Then just request_irq() with the pin ID; it works like any ARM IRQ 1204 * handler. 1205 * First implementation always triggers on rising and falling edges 1206 * whereas the newer PIO3 can be additionally configured to trigger on 1207 * level, edge with any polarity. 1208 * 1209 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after 1210 * configuring them with at91_set_a_periph() or at91_set_b_periph(). 1211 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering. 1212 */ 1213 1214 static void gpio_irq_mask(struct irq_data *d) 1215 { 1216 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 1217 void __iomem *pio = at91_gpio->regbase; 1218 unsigned mask = 1 << d->hwirq; 1219 1220 if (pio) 1221 writel_relaxed(mask, pio + PIO_IDR); 1222 } 1223 1224 static void gpio_irq_unmask(struct irq_data *d) 1225 { 1226 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 1227 void __iomem *pio = at91_gpio->regbase; 1228 unsigned mask = 1 << d->hwirq; 1229 1230 if (pio) 1231 writel_relaxed(mask, pio + PIO_IER); 1232 } 1233 1234 static int gpio_irq_type(struct irq_data *d, unsigned type) 1235 { 1236 switch (type) { 1237 case IRQ_TYPE_NONE: 1238 case IRQ_TYPE_EDGE_BOTH: 1239 return 0; 1240 default: 1241 return -EINVAL; 1242 } 1243 } 1244 1245 /* Alternate irq type for PIO3 support */ 1246 static int alt_gpio_irq_type(struct irq_data *d, unsigned type) 1247 { 1248 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 1249 void __iomem *pio = at91_gpio->regbase; 1250 unsigned mask = 1 << d->hwirq; 1251 1252 switch (type) { 1253 case IRQ_TYPE_EDGE_RISING: 1254 irq_set_handler(d->irq, handle_simple_irq); 1255 writel_relaxed(mask, pio + PIO_ESR); 1256 writel_relaxed(mask, pio + PIO_REHLSR); 1257 break; 1258 case IRQ_TYPE_EDGE_FALLING: 1259 irq_set_handler(d->irq, handle_simple_irq); 1260 writel_relaxed(mask, pio + PIO_ESR); 1261 writel_relaxed(mask, pio + PIO_FELLSR); 1262 break; 1263 case IRQ_TYPE_LEVEL_LOW: 1264 irq_set_handler(d->irq, handle_level_irq); 1265 writel_relaxed(mask, pio + PIO_LSR); 1266 writel_relaxed(mask, pio + PIO_FELLSR); 1267 break; 1268 case IRQ_TYPE_LEVEL_HIGH: 1269 irq_set_handler(d->irq, handle_level_irq); 1270 writel_relaxed(mask, pio + PIO_LSR); 1271 writel_relaxed(mask, pio + PIO_REHLSR); 1272 break; 1273 case IRQ_TYPE_EDGE_BOTH: 1274 /* 1275 * disable additional interrupt modes: 1276 * fall back to default behavior 1277 */ 1278 irq_set_handler(d->irq, handle_simple_irq); 1279 writel_relaxed(mask, pio + PIO_AIMDR); 1280 return 0; 1281 case IRQ_TYPE_NONE: 1282 default: 1283 pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq)); 1284 return -EINVAL; 1285 } 1286 1287 /* enable additional interrupt modes */ 1288 writel_relaxed(mask, pio + PIO_AIMER); 1289 1290 return 0; 1291 } 1292 1293 #ifdef CONFIG_PM 1294 1295 static u32 wakeups[MAX_GPIO_BANKS]; 1296 static u32 backups[MAX_GPIO_BANKS]; 1297 1298 static int gpio_irq_set_wake(struct irq_data *d, unsigned state) 1299 { 1300 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 1301 unsigned bank = at91_gpio->pioc_idx; 1302 unsigned mask = 1 << d->hwirq; 1303 1304 if (unlikely(bank >= MAX_GPIO_BANKS)) 1305 return -EINVAL; 1306 1307 if (state) 1308 wakeups[bank] |= mask; 1309 else 1310 wakeups[bank] &= ~mask; 1311 1312 irq_set_irq_wake(at91_gpio->pioc_virq, state); 1313 1314 return 0; 1315 } 1316 1317 void at91_pinctrl_gpio_suspend(void) 1318 { 1319 int i; 1320 1321 for (i = 0; i < gpio_banks; i++) { 1322 void __iomem *pio; 1323 1324 if (!gpio_chips[i]) 1325 continue; 1326 1327 pio = gpio_chips[i]->regbase; 1328 1329 backups[i] = __raw_readl(pio + PIO_IMR); 1330 __raw_writel(backups[i], pio + PIO_IDR); 1331 __raw_writel(wakeups[i], pio + PIO_IER); 1332 1333 if (!wakeups[i]) { 1334 clk_unprepare(gpio_chips[i]->clock); 1335 clk_disable(gpio_chips[i]->clock); 1336 } else { 1337 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 1338 'A'+i, wakeups[i]); 1339 } 1340 } 1341 } 1342 1343 void at91_pinctrl_gpio_resume(void) 1344 { 1345 int i; 1346 1347 for (i = 0; i < gpio_banks; i++) { 1348 void __iomem *pio; 1349 1350 if (!gpio_chips[i]) 1351 continue; 1352 1353 pio = gpio_chips[i]->regbase; 1354 1355 if (!wakeups[i]) { 1356 if (clk_prepare(gpio_chips[i]->clock) == 0) 1357 clk_enable(gpio_chips[i]->clock); 1358 } 1359 1360 __raw_writel(wakeups[i], pio + PIO_IDR); 1361 __raw_writel(backups[i], pio + PIO_IER); 1362 } 1363 } 1364 1365 #else 1366 #define gpio_irq_set_wake NULL 1367 #endif /* CONFIG_PM */ 1368 1369 static struct irq_chip gpio_irqchip = { 1370 .name = "GPIO", 1371 .irq_disable = gpio_irq_mask, 1372 .irq_mask = gpio_irq_mask, 1373 .irq_unmask = gpio_irq_unmask, 1374 /* .irq_set_type is set dynamically */ 1375 .irq_set_wake = gpio_irq_set_wake, 1376 }; 1377 1378 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) 1379 { 1380 struct irq_chip *chip = irq_desc_get_chip(desc); 1381 struct irq_data *idata = irq_desc_get_irq_data(desc); 1382 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata); 1383 void __iomem *pio = at91_gpio->regbase; 1384 unsigned long isr; 1385 int n; 1386 1387 chained_irq_enter(chip, desc); 1388 for (;;) { 1389 /* Reading ISR acks pending (edge triggered) GPIO interrupts. 1390 * When there none are pending, we're finished unless we need 1391 * to process multiple banks (like ID_PIOCDE on sam9263). 1392 */ 1393 isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR); 1394 if (!isr) { 1395 if (!at91_gpio->next) 1396 break; 1397 at91_gpio = at91_gpio->next; 1398 pio = at91_gpio->regbase; 1399 continue; 1400 } 1401 1402 for_each_set_bit(n, &isr, BITS_PER_LONG) { 1403 generic_handle_irq(irq_find_mapping(at91_gpio->domain, n)); 1404 } 1405 } 1406 chained_irq_exit(chip, desc); 1407 /* now it may re-trigger */ 1408 } 1409 1410 /* 1411 * This lock class tells lockdep that GPIO irqs are in a different 1412 * category than their parents, so it won't report false recursion. 1413 */ 1414 static struct lock_class_key gpio_lock_class; 1415 1416 static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq, 1417 irq_hw_number_t hw) 1418 { 1419 struct at91_gpio_chip *at91_gpio = h->host_data; 1420 void __iomem *pio = at91_gpio->regbase; 1421 u32 mask = 1 << hw; 1422 1423 irq_set_lockdep_class(virq, &gpio_lock_class); 1424 1425 /* 1426 * Can use the "simple" and not "edge" handler since it's 1427 * shorter, and the AIC handles interrupts sanely. 1428 */ 1429 irq_set_chip(virq, &gpio_irqchip); 1430 if ((at91_gpio->ops == &at91sam9x5_ops) && 1431 (readl_relaxed(pio + PIO_AIMMR) & mask) && 1432 (readl_relaxed(pio + PIO_ELSR) & mask)) 1433 irq_set_handler(virq, handle_level_irq); 1434 else 1435 irq_set_handler(virq, handle_simple_irq); 1436 set_irq_flags(virq, IRQF_VALID); 1437 irq_set_chip_data(virq, at91_gpio); 1438 1439 return 0; 1440 } 1441 1442 static int at91_gpio_irq_domain_xlate(struct irq_domain *d, 1443 struct device_node *ctrlr, 1444 const u32 *intspec, unsigned int intsize, 1445 irq_hw_number_t *out_hwirq, 1446 unsigned int *out_type) 1447 { 1448 struct at91_gpio_chip *at91_gpio = d->host_data; 1449 int ret; 1450 int pin = at91_gpio->chip.base + intspec[0]; 1451 1452 if (WARN_ON(intsize < 2)) 1453 return -EINVAL; 1454 *out_hwirq = intspec[0]; 1455 *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK; 1456 1457 ret = gpio_request(pin, ctrlr->full_name); 1458 if (ret) 1459 return ret; 1460 1461 ret = gpio_direction_input(pin); 1462 if (ret) 1463 return ret; 1464 1465 return 0; 1466 } 1467 1468 static struct irq_domain_ops at91_gpio_ops = { 1469 .map = at91_gpio_irq_map, 1470 .xlate = at91_gpio_irq_domain_xlate, 1471 }; 1472 1473 static int at91_gpio_of_irq_setup(struct device_node *node, 1474 struct at91_gpio_chip *at91_gpio) 1475 { 1476 struct at91_gpio_chip *prev = NULL; 1477 struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq); 1478 1479 at91_gpio->pioc_hwirq = irqd_to_hwirq(d); 1480 1481 /* Setup proper .irq_set_type function */ 1482 gpio_irqchip.irq_set_type = at91_gpio->ops->irq_type; 1483 1484 /* Disable irqs of this PIO controller */ 1485 writel_relaxed(~0, at91_gpio->regbase + PIO_IDR); 1486 1487 /* Setup irq domain */ 1488 at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio, 1489 &at91_gpio_ops, at91_gpio); 1490 if (!at91_gpio->domain) 1491 panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n", 1492 at91_gpio->pioc_idx); 1493 1494 /* Setup chained handler */ 1495 if (at91_gpio->pioc_idx) 1496 prev = gpio_chips[at91_gpio->pioc_idx - 1]; 1497 1498 /* The toplevel handler handles one bank of GPIOs, except 1499 * on some SoC it can handles up to three... 1500 * We only set up the handler for the first of the list. 1501 */ 1502 if (prev && prev->next == at91_gpio) 1503 return 0; 1504 1505 irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio); 1506 irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler); 1507 1508 return 0; 1509 } 1510 1511 /* This structure is replicated for each GPIO block allocated at probe time */ 1512 static struct gpio_chip at91_gpio_template = { 1513 .request = at91_gpio_request, 1514 .free = at91_gpio_free, 1515 .direction_input = at91_gpio_direction_input, 1516 .get = at91_gpio_get, 1517 .direction_output = at91_gpio_direction_output, 1518 .set = at91_gpio_set, 1519 .to_irq = at91_gpio_to_irq, 1520 .dbg_show = at91_gpio_dbg_show, 1521 .can_sleep = 0, 1522 .ngpio = MAX_NB_GPIO_PER_BANK, 1523 }; 1524 1525 static void at91_gpio_probe_fixup(void) 1526 { 1527 unsigned i; 1528 struct at91_gpio_chip *at91_gpio, *last = NULL; 1529 1530 for (i = 0; i < gpio_banks; i++) { 1531 at91_gpio = gpio_chips[i]; 1532 1533 /* 1534 * GPIO controller are grouped on some SoC: 1535 * PIOC, PIOD and PIOE can share the same IRQ line 1536 */ 1537 if (last && last->pioc_virq == at91_gpio->pioc_virq) 1538 last->next = at91_gpio; 1539 last = at91_gpio; 1540 } 1541 } 1542 1543 static struct of_device_id at91_gpio_of_match[] = { 1544 { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, }, 1545 { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops }, 1546 { /* sentinel */ } 1547 }; 1548 1549 static int at91_gpio_probe(struct platform_device *pdev) 1550 { 1551 struct device_node *np = pdev->dev.of_node; 1552 struct resource *res; 1553 struct at91_gpio_chip *at91_chip = NULL; 1554 struct gpio_chip *chip; 1555 struct pinctrl_gpio_range *range; 1556 int ret = 0; 1557 int irq, i; 1558 int alias_idx = of_alias_get_id(np, "gpio"); 1559 uint32_t ngpio; 1560 char **names; 1561 1562 BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips)); 1563 if (gpio_chips[alias_idx]) { 1564 ret = -EBUSY; 1565 goto err; 1566 } 1567 1568 irq = platform_get_irq(pdev, 0); 1569 if (irq < 0) { 1570 ret = irq; 1571 goto err; 1572 } 1573 1574 at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL); 1575 if (!at91_chip) { 1576 ret = -ENOMEM; 1577 goto err; 1578 } 1579 1580 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1581 at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res); 1582 if (IS_ERR(at91_chip->regbase)) { 1583 ret = PTR_ERR(at91_chip->regbase); 1584 goto err; 1585 } 1586 1587 at91_chip->ops = (struct at91_pinctrl_mux_ops *) 1588 of_match_device(at91_gpio_of_match, &pdev->dev)->data; 1589 at91_chip->pioc_virq = irq; 1590 at91_chip->pioc_idx = alias_idx; 1591 1592 at91_chip->clock = clk_get(&pdev->dev, NULL); 1593 if (IS_ERR(at91_chip->clock)) { 1594 dev_err(&pdev->dev, "failed to get clock, ignoring.\n"); 1595 goto err; 1596 } 1597 1598 if (clk_prepare(at91_chip->clock)) 1599 goto clk_prep_err; 1600 1601 /* enable PIO controller's clock */ 1602 if (clk_enable(at91_chip->clock)) { 1603 dev_err(&pdev->dev, "failed to enable clock, ignoring.\n"); 1604 goto clk_err; 1605 } 1606 1607 at91_chip->chip = at91_gpio_template; 1608 1609 chip = &at91_chip->chip; 1610 chip->of_node = np; 1611 chip->label = dev_name(&pdev->dev); 1612 chip->dev = &pdev->dev; 1613 chip->owner = THIS_MODULE; 1614 chip->base = alias_idx * MAX_NB_GPIO_PER_BANK; 1615 1616 if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) { 1617 if (ngpio >= MAX_NB_GPIO_PER_BANK) 1618 pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n", 1619 alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK); 1620 else 1621 chip->ngpio = ngpio; 1622 } 1623 1624 names = devm_kzalloc(&pdev->dev, sizeof(char *) * chip->ngpio, 1625 GFP_KERNEL); 1626 1627 if (!names) { 1628 ret = -ENOMEM; 1629 goto clk_err; 1630 } 1631 1632 for (i = 0; i < chip->ngpio; i++) 1633 names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i); 1634 1635 chip->names = (const char *const *)names; 1636 1637 range = &at91_chip->range; 1638 range->name = chip->label; 1639 range->id = alias_idx; 1640 range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK; 1641 1642 range->npins = chip->ngpio; 1643 range->gc = chip; 1644 1645 ret = gpiochip_add(chip); 1646 if (ret) 1647 goto clk_err; 1648 1649 gpio_chips[alias_idx] = at91_chip; 1650 gpio_banks = max(gpio_banks, alias_idx + 1); 1651 1652 at91_gpio_probe_fixup(); 1653 1654 at91_gpio_of_irq_setup(np, at91_chip); 1655 1656 dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase); 1657 1658 return 0; 1659 1660 clk_err: 1661 clk_unprepare(at91_chip->clock); 1662 clk_prep_err: 1663 clk_put(at91_chip->clock); 1664 err: 1665 dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx); 1666 1667 return ret; 1668 } 1669 1670 static struct platform_driver at91_gpio_driver = { 1671 .driver = { 1672 .name = "gpio-at91", 1673 .owner = THIS_MODULE, 1674 .of_match_table = of_match_ptr(at91_gpio_of_match), 1675 }, 1676 .probe = at91_gpio_probe, 1677 }; 1678 1679 static struct platform_driver at91_pinctrl_driver = { 1680 .driver = { 1681 .name = "pinctrl-at91", 1682 .owner = THIS_MODULE, 1683 .of_match_table = of_match_ptr(at91_pinctrl_of_match), 1684 }, 1685 .probe = at91_pinctrl_probe, 1686 .remove = at91_pinctrl_remove, 1687 }; 1688 1689 static int __init at91_pinctrl_init(void) 1690 { 1691 int ret; 1692 1693 ret = platform_driver_register(&at91_gpio_driver); 1694 if (ret) 1695 return ret; 1696 return platform_driver_register(&at91_pinctrl_driver); 1697 } 1698 arch_initcall(at91_pinctrl_init); 1699 1700 static void __exit at91_pinctrl_exit(void) 1701 { 1702 platform_driver_unregister(&at91_pinctrl_driver); 1703 } 1704 1705 module_exit(at91_pinctrl_exit); 1706 MODULE_AUTHOR("Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>"); 1707 MODULE_DESCRIPTION("Atmel AT91 pinctrl driver"); 1708 MODULE_LICENSE("GPL v2"); 1709