1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * at91 pinctrl driver based on at91 pinmux core
4  *
5  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
6  */
7 
8 #include <linux/clk.h>
9 #include <linux/err.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/of_device.h>
17 #include <linux/of_irq.h>
18 #include <linux/pm.h>
19 #include <linux/seq_file.h>
20 #include <linux/slab.h>
21 
22 /* Since we request GPIOs from ourself */
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/pinctrl/machine.h>
25 #include <linux/pinctrl/pinconf.h>
26 #include <linux/pinctrl/pinctrl.h>
27 #include <linux/pinctrl/pinmux.h>
28 
29 #include "pinctrl-at91.h"
30 #include "core.h"
31 
32 #define MAX_GPIO_BANKS		5
33 #define MAX_NB_GPIO_PER_BANK	32
34 
35 struct at91_pinctrl_mux_ops;
36 
37 /**
38  * struct at91_gpio_chip: at91 gpio chip
39  * @chip: gpio chip
40  * @range: gpio range
41  * @next: bank sharing same clock
42  * @pioc_hwirq: PIO bank interrupt identifier on AIC
43  * @pioc_virq: PIO bank Linux virtual interrupt
44  * @pioc_idx: PIO bank index
45  * @regbase: PIO bank virtual address
46  * @clock: associated clock
47  * @ops: at91 pinctrl mux ops
48  * @wakeups: wakeup interrupts
49  * @backups: interrupts disabled in suspend
50  * @id: gpio chip identifier
51  */
52 struct at91_gpio_chip {
53 	struct gpio_chip	chip;
54 	struct pinctrl_gpio_range range;
55 	struct at91_gpio_chip	*next;
56 	int			pioc_hwirq;
57 	int			pioc_virq;
58 	int			pioc_idx;
59 	void __iomem		*regbase;
60 	struct clk		*clock;
61 	const struct at91_pinctrl_mux_ops *ops;
62 	u32			wakeups;
63 	u32			backups;
64 	u32			id;
65 };
66 
67 static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
68 
69 static int gpio_banks;
70 
71 #define PULL_UP		(1 << 0)
72 #define MULTI_DRIVE	(1 << 1)
73 #define DEGLITCH	(1 << 2)
74 #define PULL_DOWN	(1 << 3)
75 #define DIS_SCHMIT	(1 << 4)
76 #define DRIVE_STRENGTH_SHIFT	5
77 #define DRIVE_STRENGTH_MASK		0x3
78 #define DRIVE_STRENGTH   (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
79 #define OUTPUT		(1 << 7)
80 #define OUTPUT_VAL_SHIFT	8
81 #define OUTPUT_VAL	(0x1 << OUTPUT_VAL_SHIFT)
82 #define SLEWRATE_SHIFT	9
83 #define SLEWRATE_MASK	0x1
84 #define SLEWRATE	(SLEWRATE_MASK << SLEWRATE_SHIFT)
85 #define DEBOUNCE	(1 << 16)
86 #define DEBOUNCE_VAL_SHIFT	17
87 #define DEBOUNCE_VAL	(0x3fff << DEBOUNCE_VAL_SHIFT)
88 
89 /*
90  * These defines will translated the dt binding settings to our internal
91  * settings. They are not necessarily the same value as the register setting.
92  * The actual drive strength current of low, medium and high must be looked up
93  * from the corresponding device datasheet. This value is different for pins
94  * that are even in the same banks. It is also dependent on VCC.
95  * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
96  * strength when there is no dt config for it.
97  */
98 enum drive_strength_bit {
99 	DRIVE_STRENGTH_BIT_DEF,
100 	DRIVE_STRENGTH_BIT_LOW,
101 	DRIVE_STRENGTH_BIT_MED,
102 	DRIVE_STRENGTH_BIT_HI,
103 };
104 
105 #define DRIVE_STRENGTH_BIT_MSK(name)	(DRIVE_STRENGTH_BIT_##name << \
106 					 DRIVE_STRENGTH_SHIFT)
107 
108 enum slewrate_bit {
109 	SLEWRATE_BIT_ENA,
110 	SLEWRATE_BIT_DIS,
111 };
112 
113 #define SLEWRATE_BIT_MSK(name)		(SLEWRATE_BIT_##name << SLEWRATE_SHIFT)
114 
115 /**
116  * struct at91_pmx_func - describes AT91 pinmux functions
117  * @name: the name of this specific function
118  * @groups: corresponding pin groups
119  * @ngroups: the number of groups
120  */
121 struct at91_pmx_func {
122 	const char	*name;
123 	const char	**groups;
124 	unsigned	ngroups;
125 };
126 
127 enum at91_mux {
128 	AT91_MUX_GPIO = 0,
129 	AT91_MUX_PERIPH_A = 1,
130 	AT91_MUX_PERIPH_B = 2,
131 	AT91_MUX_PERIPH_C = 3,
132 	AT91_MUX_PERIPH_D = 4,
133 };
134 
135 /**
136  * struct at91_pmx_pin - describes an At91 pin mux
137  * @bank: the bank of the pin
138  * @pin: the pin number in the @bank
139  * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
140  * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
141  */
142 struct at91_pmx_pin {
143 	uint32_t	bank;
144 	uint32_t	pin;
145 	enum at91_mux	mux;
146 	unsigned long	conf;
147 };
148 
149 /**
150  * struct at91_pin_group - describes an At91 pin group
151  * @name: the name of this specific pin group
152  * @pins_conf: the mux mode for each pin in this group. The size of this
153  *	array is the same as pins.
154  * @pins: an array of discrete physical pins used in this group, taken
155  *	from the driver-local pin enumeration space
156  * @npins: the number of pins in this group array, i.e. the number of
157  *	elements in .pins so we can iterate over that array
158  */
159 struct at91_pin_group {
160 	const char		*name;
161 	struct at91_pmx_pin	*pins_conf;
162 	unsigned int		*pins;
163 	unsigned		npins;
164 };
165 
166 /**
167  * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
168  * on new IP with support for periph C and D the way to mux in
169  * periph A and B has changed
170  * So provide the right call back
171  * if not present means the IP does not support it
172  * @get_periph: return the periph mode configured
173  * @mux_A_periph: mux as periph A
174  * @mux_B_periph: mux as periph B
175  * @mux_C_periph: mux as periph C
176  * @mux_D_periph: mux as periph D
177  * @get_deglitch: get deglitch status
178  * @set_deglitch: enable/disable deglitch
179  * @get_debounce: get debounce status
180  * @set_debounce: enable/disable debounce
181  * @get_pulldown: get pulldown status
182  * @set_pulldown: enable/disable pulldown
183  * @get_schmitt_trig: get schmitt trigger status
184  * @disable_schmitt_trig: disable schmitt trigger
185  * @get_drivestrength: get driver strength
186  * @set_drivestrength: set driver strength
187  * @get_slewrate: get slew rate
188  * @set_slewrate: set slew rate
189  * @irq_type: return irq type
190  */
191 struct at91_pinctrl_mux_ops {
192 	enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
193 	void (*mux_A_periph)(void __iomem *pio, unsigned mask);
194 	void (*mux_B_periph)(void __iomem *pio, unsigned mask);
195 	void (*mux_C_periph)(void __iomem *pio, unsigned mask);
196 	void (*mux_D_periph)(void __iomem *pio, unsigned mask);
197 	bool (*get_deglitch)(void __iomem *pio, unsigned pin);
198 	void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on);
199 	bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
200 	void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div);
201 	bool (*get_pulldown)(void __iomem *pio, unsigned pin);
202 	void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
203 	bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
204 	void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
205 	unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
206 	void (*set_drivestrength)(void __iomem *pio, unsigned pin,
207 					u32 strength);
208 	unsigned (*get_slewrate)(void __iomem *pio, unsigned pin);
209 	void (*set_slewrate)(void __iomem *pio, unsigned pin, u32 slewrate);
210 	/* irq */
211 	int (*irq_type)(struct irq_data *d, unsigned type);
212 };
213 
214 static int gpio_irq_type(struct irq_data *d, unsigned type);
215 static int alt_gpio_irq_type(struct irq_data *d, unsigned type);
216 
217 struct at91_pinctrl {
218 	struct device		*dev;
219 	struct pinctrl_dev	*pctl;
220 
221 	int			nactive_banks;
222 
223 	uint32_t		*mux_mask;
224 	int			nmux;
225 
226 	struct at91_pmx_func	*functions;
227 	int			nfunctions;
228 
229 	struct at91_pin_group	*groups;
230 	int			ngroups;
231 
232 	const struct at91_pinctrl_mux_ops *ops;
233 };
234 
235 static inline const struct at91_pin_group *at91_pinctrl_find_group_by_name(
236 				const struct at91_pinctrl *info,
237 				const char *name)
238 {
239 	const struct at91_pin_group *grp = NULL;
240 	int i;
241 
242 	for (i = 0; i < info->ngroups; i++) {
243 		if (strcmp(info->groups[i].name, name))
244 			continue;
245 
246 		grp = &info->groups[i];
247 		dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]);
248 		break;
249 	}
250 
251 	return grp;
252 }
253 
254 static int at91_get_groups_count(struct pinctrl_dev *pctldev)
255 {
256 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
257 
258 	return info->ngroups;
259 }
260 
261 static const char *at91_get_group_name(struct pinctrl_dev *pctldev,
262 				       unsigned selector)
263 {
264 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
265 
266 	return info->groups[selector].name;
267 }
268 
269 static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
270 			       const unsigned **pins,
271 			       unsigned *npins)
272 {
273 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
274 
275 	if (selector >= info->ngroups)
276 		return -EINVAL;
277 
278 	*pins = info->groups[selector].pins;
279 	*npins = info->groups[selector].npins;
280 
281 	return 0;
282 }
283 
284 static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
285 		   unsigned offset)
286 {
287 	seq_printf(s, "%s", dev_name(pctldev->dev));
288 }
289 
290 static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
291 			struct device_node *np,
292 			struct pinctrl_map **map, unsigned *num_maps)
293 {
294 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
295 	const struct at91_pin_group *grp;
296 	struct pinctrl_map *new_map;
297 	struct device_node *parent;
298 	int map_num = 1;
299 	int i;
300 
301 	/*
302 	 * first find the group of this node and check if we need to create
303 	 * config maps for pins
304 	 */
305 	grp = at91_pinctrl_find_group_by_name(info, np->name);
306 	if (!grp) {
307 		dev_err(info->dev, "unable to find group for node %pOFn\n",
308 			np);
309 		return -EINVAL;
310 	}
311 
312 	map_num += grp->npins;
313 	new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map),
314 			       GFP_KERNEL);
315 	if (!new_map)
316 		return -ENOMEM;
317 
318 	*map = new_map;
319 	*num_maps = map_num;
320 
321 	/* create mux map */
322 	parent = of_get_parent(np);
323 	if (!parent) {
324 		devm_kfree(pctldev->dev, new_map);
325 		return -EINVAL;
326 	}
327 	new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
328 	new_map[0].data.mux.function = parent->name;
329 	new_map[0].data.mux.group = np->name;
330 	of_node_put(parent);
331 
332 	/* create config map */
333 	new_map++;
334 	for (i = 0; i < grp->npins; i++) {
335 		new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
336 		new_map[i].data.configs.group_or_pin =
337 				pin_get_name(pctldev, grp->pins[i]);
338 		new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
339 		new_map[i].data.configs.num_configs = 1;
340 	}
341 
342 	dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
343 		(*map)->data.mux.function, (*map)->data.mux.group, map_num);
344 
345 	return 0;
346 }
347 
348 static void at91_dt_free_map(struct pinctrl_dev *pctldev,
349 				struct pinctrl_map *map, unsigned num_maps)
350 {
351 }
352 
353 static const struct pinctrl_ops at91_pctrl_ops = {
354 	.get_groups_count	= at91_get_groups_count,
355 	.get_group_name		= at91_get_group_name,
356 	.get_group_pins		= at91_get_group_pins,
357 	.pin_dbg_show		= at91_pin_dbg_show,
358 	.dt_node_to_map		= at91_dt_node_to_map,
359 	.dt_free_map		= at91_dt_free_map,
360 };
361 
362 static void __iomem *pin_to_controller(struct at91_pinctrl *info,
363 				 unsigned int bank)
364 {
365 	if (!gpio_chips[bank])
366 		return NULL;
367 
368 	return gpio_chips[bank]->regbase;
369 }
370 
371 static inline int pin_to_bank(unsigned pin)
372 {
373 	return pin /= MAX_NB_GPIO_PER_BANK;
374 }
375 
376 static unsigned pin_to_mask(unsigned int pin)
377 {
378 	return 1 << pin;
379 }
380 
381 static unsigned two_bit_pin_value_shift_amount(unsigned int pin)
382 {
383 	/* return the shift value for a pin for "two bit" per pin registers,
384 	 * i.e. drive strength */
385 	return 2*((pin >= MAX_NB_GPIO_PER_BANK/2)
386 			? pin - MAX_NB_GPIO_PER_BANK/2 : pin);
387 }
388 
389 static unsigned sama5d3_get_drive_register(unsigned int pin)
390 {
391 	/* drive strength is split between two registers
392 	 * with two bits per pin */
393 	return (pin >= MAX_NB_GPIO_PER_BANK/2)
394 			? SAMA5D3_PIO_DRIVER2 : SAMA5D3_PIO_DRIVER1;
395 }
396 
397 static unsigned at91sam9x5_get_drive_register(unsigned int pin)
398 {
399 	/* drive strength is split between two registers
400 	 * with two bits per pin */
401 	return (pin >= MAX_NB_GPIO_PER_BANK/2)
402 			? AT91SAM9X5_PIO_DRIVER2 : AT91SAM9X5_PIO_DRIVER1;
403 }
404 
405 static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
406 {
407 	writel_relaxed(mask, pio + PIO_IDR);
408 }
409 
410 static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
411 {
412 	return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1);
413 }
414 
415 static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
416 {
417 	if (on)
418 		writel_relaxed(mask, pio + PIO_PPDDR);
419 
420 	writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
421 }
422 
423 static bool at91_mux_get_output(void __iomem *pio, unsigned int pin, bool *val)
424 {
425 	*val = (readl_relaxed(pio + PIO_ODSR) >> pin) & 0x1;
426 	return (readl_relaxed(pio + PIO_OSR) >> pin) & 0x1;
427 }
428 
429 static void at91_mux_set_output(void __iomem *pio, unsigned int mask,
430 				bool is_on, bool val)
431 {
432 	writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
433 	writel_relaxed(mask, pio + (is_on ? PIO_OER : PIO_ODR));
434 }
435 
436 static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
437 {
438 	return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1;
439 }
440 
441 static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
442 {
443 	writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR));
444 }
445 
446 static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
447 {
448 	writel_relaxed(mask, pio + PIO_ASR);
449 }
450 
451 static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
452 {
453 	writel_relaxed(mask, pio + PIO_BSR);
454 }
455 
456 static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
457 {
458 
459 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask,
460 						pio + PIO_ABCDSR1);
461 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
462 						pio + PIO_ABCDSR2);
463 }
464 
465 static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
466 {
467 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask,
468 						pio + PIO_ABCDSR1);
469 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
470 						pio + PIO_ABCDSR2);
471 }
472 
473 static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
474 {
475 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
476 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
477 }
478 
479 static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
480 {
481 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
482 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
483 }
484 
485 static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask)
486 {
487 	unsigned select;
488 
489 	if (readl_relaxed(pio + PIO_PSR) & mask)
490 		return AT91_MUX_GPIO;
491 
492 	select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask);
493 	select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1);
494 
495 	return select + 1;
496 }
497 
498 static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)
499 {
500 	unsigned select;
501 
502 	if (readl_relaxed(pio + PIO_PSR) & mask)
503 		return AT91_MUX_GPIO;
504 
505 	select = readl_relaxed(pio + PIO_ABSR) & mask;
506 
507 	return select + 1;
508 }
509 
510 static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin)
511 {
512 	return (readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1;
513 }
514 
515 static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
516 {
517 	writel_relaxed(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
518 }
519 
520 static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin)
521 {
522 	if ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1)
523 		return !((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
524 
525 	return false;
526 }
527 
528 static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
529 {
530 	if (is_on)
531 		writel_relaxed(mask, pio + PIO_IFSCDR);
532 	at91_mux_set_deglitch(pio, mask, is_on);
533 }
534 
535 static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
536 {
537 	*div = readl_relaxed(pio + PIO_SCDR);
538 
539 	return ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) &&
540 	       ((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
541 }
542 
543 static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
544 				bool is_on, u32 div)
545 {
546 	if (is_on) {
547 		writel_relaxed(mask, pio + PIO_IFSCER);
548 		writel_relaxed(div & PIO_SCDR_DIV, pio + PIO_SCDR);
549 		writel_relaxed(mask, pio + PIO_IFER);
550 	} else
551 		writel_relaxed(mask, pio + PIO_IFSCDR);
552 }
553 
554 static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
555 {
556 	return !((readl_relaxed(pio + PIO_PPDSR) >> pin) & 0x1);
557 }
558 
559 static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
560 {
561 	if (is_on)
562 		writel_relaxed(mask, pio + PIO_PUDR);
563 
564 	writel_relaxed(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
565 }
566 
567 static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
568 {
569 	writel_relaxed(readl_relaxed(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
570 }
571 
572 static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
573 {
574 	return (readl_relaxed(pio + PIO_SCHMITT) >> pin) & 0x1;
575 }
576 
577 static inline u32 read_drive_strength(void __iomem *reg, unsigned pin)
578 {
579 	unsigned tmp = readl_relaxed(reg);
580 
581 	tmp = tmp >> two_bit_pin_value_shift_amount(pin);
582 
583 	return tmp & DRIVE_STRENGTH_MASK;
584 }
585 
586 static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
587 							unsigned pin)
588 {
589 	unsigned tmp = read_drive_strength(pio +
590 					sama5d3_get_drive_register(pin), pin);
591 
592 	/* SAMA5 strength is 1:1 with our defines,
593 	 * except 0 is equivalent to low per datasheet */
594 	if (!tmp)
595 		tmp = DRIVE_STRENGTH_BIT_MSK(LOW);
596 
597 	return tmp;
598 }
599 
600 static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
601 							unsigned pin)
602 {
603 	unsigned tmp = read_drive_strength(pio +
604 				at91sam9x5_get_drive_register(pin), pin);
605 
606 	/* strength is inverse in SAM9x5s hardware with the pinctrl defines
607 	 * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
608 	tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp;
609 
610 	return tmp;
611 }
612 
613 static unsigned at91_mux_sam9x60_get_drivestrength(void __iomem *pio,
614 						   unsigned pin)
615 {
616 	unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
617 
618 	if (tmp & BIT(pin))
619 		return DRIVE_STRENGTH_BIT_HI;
620 
621 	return DRIVE_STRENGTH_BIT_LOW;
622 }
623 
624 static unsigned at91_mux_sam9x60_get_slewrate(void __iomem *pio, unsigned pin)
625 {
626 	unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
627 
628 	if ((tmp & BIT(pin)))
629 		return SLEWRATE_BIT_ENA;
630 
631 	return SLEWRATE_BIT_DIS;
632 }
633 
634 static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
635 {
636 	unsigned tmp = readl_relaxed(reg);
637 	unsigned shift = two_bit_pin_value_shift_amount(pin);
638 
639 	tmp &= ~(DRIVE_STRENGTH_MASK  <<  shift);
640 	tmp |= strength << shift;
641 
642 	writel_relaxed(tmp, reg);
643 }
644 
645 static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin,
646 						u32 setting)
647 {
648 	/* do nothing if setting is zero */
649 	if (!setting)
650 		return;
651 
652 	/* strength is 1 to 1 with setting for SAMA5 */
653 	set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting);
654 }
655 
656 static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
657 						u32 setting)
658 {
659 	/* do nothing if setting is zero */
660 	if (!setting)
661 		return;
662 
663 	/* strength is inverse on SAM9x5s with our defines
664 	 * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
665 	setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
666 
667 	set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
668 				setting);
669 }
670 
671 static void at91_mux_sam9x60_set_drivestrength(void __iomem *pio, unsigned pin,
672 					       u32 setting)
673 {
674 	unsigned int tmp;
675 
676 	if (setting <= DRIVE_STRENGTH_BIT_DEF ||
677 	    setting == DRIVE_STRENGTH_BIT_MED ||
678 	    setting > DRIVE_STRENGTH_BIT_HI)
679 		return;
680 
681 	tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
682 
683 	/* Strength is 0: low, 1: hi */
684 	if (setting == DRIVE_STRENGTH_BIT_LOW)
685 		tmp &= ~BIT(pin);
686 	else
687 		tmp |= BIT(pin);
688 
689 	writel_relaxed(tmp, pio + SAM9X60_PIO_DRIVER1);
690 }
691 
692 static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin,
693 					  u32 setting)
694 {
695 	unsigned int tmp;
696 
697 	if (setting < SLEWRATE_BIT_ENA || setting > SLEWRATE_BIT_DIS)
698 		return;
699 
700 	tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
701 
702 	if (setting == SLEWRATE_BIT_DIS)
703 		tmp &= ~BIT(pin);
704 	else
705 		tmp |= BIT(pin);
706 
707 	writel_relaxed(tmp, pio + SAM9X60_PIO_SLEWR);
708 }
709 
710 static const struct at91_pinctrl_mux_ops at91rm9200_ops = {
711 	.get_periph	= at91_mux_get_periph,
712 	.mux_A_periph	= at91_mux_set_A_periph,
713 	.mux_B_periph	= at91_mux_set_B_periph,
714 	.get_deglitch	= at91_mux_get_deglitch,
715 	.set_deglitch	= at91_mux_set_deglitch,
716 	.irq_type	= gpio_irq_type,
717 };
718 
719 static const struct at91_pinctrl_mux_ops at91sam9x5_ops = {
720 	.get_periph	= at91_mux_pio3_get_periph,
721 	.mux_A_periph	= at91_mux_pio3_set_A_periph,
722 	.mux_B_periph	= at91_mux_pio3_set_B_periph,
723 	.mux_C_periph	= at91_mux_pio3_set_C_periph,
724 	.mux_D_periph	= at91_mux_pio3_set_D_periph,
725 	.get_deglitch	= at91_mux_pio3_get_deglitch,
726 	.set_deglitch	= at91_mux_pio3_set_deglitch,
727 	.get_debounce	= at91_mux_pio3_get_debounce,
728 	.set_debounce	= at91_mux_pio3_set_debounce,
729 	.get_pulldown	= at91_mux_pio3_get_pulldown,
730 	.set_pulldown	= at91_mux_pio3_set_pulldown,
731 	.get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
732 	.disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
733 	.get_drivestrength = at91_mux_sam9x5_get_drivestrength,
734 	.set_drivestrength = at91_mux_sam9x5_set_drivestrength,
735 	.irq_type	= alt_gpio_irq_type,
736 };
737 
738 static const struct at91_pinctrl_mux_ops sam9x60_ops = {
739 	.get_periph	= at91_mux_pio3_get_periph,
740 	.mux_A_periph	= at91_mux_pio3_set_A_periph,
741 	.mux_B_periph	= at91_mux_pio3_set_B_periph,
742 	.mux_C_periph	= at91_mux_pio3_set_C_periph,
743 	.mux_D_periph	= at91_mux_pio3_set_D_periph,
744 	.get_deglitch	= at91_mux_pio3_get_deglitch,
745 	.set_deglitch	= at91_mux_pio3_set_deglitch,
746 	.get_debounce	= at91_mux_pio3_get_debounce,
747 	.set_debounce	= at91_mux_pio3_set_debounce,
748 	.get_pulldown	= at91_mux_pio3_get_pulldown,
749 	.set_pulldown	= at91_mux_pio3_set_pulldown,
750 	.get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
751 	.disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
752 	.get_drivestrength = at91_mux_sam9x60_get_drivestrength,
753 	.set_drivestrength = at91_mux_sam9x60_set_drivestrength,
754 	.get_slewrate   = at91_mux_sam9x60_get_slewrate,
755 	.set_slewrate   = at91_mux_sam9x60_set_slewrate,
756 	.irq_type	= alt_gpio_irq_type,
757 };
758 
759 static const struct at91_pinctrl_mux_ops sama5d3_ops = {
760 	.get_periph	= at91_mux_pio3_get_periph,
761 	.mux_A_periph	= at91_mux_pio3_set_A_periph,
762 	.mux_B_periph	= at91_mux_pio3_set_B_periph,
763 	.mux_C_periph	= at91_mux_pio3_set_C_periph,
764 	.mux_D_periph	= at91_mux_pio3_set_D_periph,
765 	.get_deglitch	= at91_mux_pio3_get_deglitch,
766 	.set_deglitch	= at91_mux_pio3_set_deglitch,
767 	.get_debounce	= at91_mux_pio3_get_debounce,
768 	.set_debounce	= at91_mux_pio3_set_debounce,
769 	.get_pulldown	= at91_mux_pio3_get_pulldown,
770 	.set_pulldown	= at91_mux_pio3_set_pulldown,
771 	.get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
772 	.disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
773 	.get_drivestrength = at91_mux_sama5d3_get_drivestrength,
774 	.set_drivestrength = at91_mux_sama5d3_set_drivestrength,
775 	.irq_type	= alt_gpio_irq_type,
776 };
777 
778 static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
779 {
780 	if (pin->mux) {
781 		dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lx\n",
782 			pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
783 	} else {
784 		dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lx\n",
785 			pin->bank + 'A', pin->pin, pin->conf);
786 	}
787 }
788 
789 static int pin_check_config(struct at91_pinctrl *info, const char *name,
790 			    int index, const struct at91_pmx_pin *pin)
791 {
792 	int mux;
793 
794 	/* check if it's a valid config */
795 	if (pin->bank >= gpio_banks) {
796 		dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
797 			name, index, pin->bank, gpio_banks);
798 		return -EINVAL;
799 	}
800 
801 	if (!gpio_chips[pin->bank]) {
802 		dev_err(info->dev, "%s: pin conf %d bank_id %d not enabled\n",
803 			name, index, pin->bank);
804 		return -ENXIO;
805 	}
806 
807 	if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
808 		dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
809 			name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
810 		return -EINVAL;
811 	}
812 
813 	if (!pin->mux)
814 		return 0;
815 
816 	mux = pin->mux - 1;
817 
818 	if (mux >= info->nmux) {
819 		dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
820 			name, index, mux, info->nmux);
821 		return -EINVAL;
822 	}
823 
824 	if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
825 		dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
826 			name, index, mux, pin->bank + 'A', pin->pin);
827 		return -EINVAL;
828 	}
829 
830 	return 0;
831 }
832 
833 static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
834 {
835 	writel_relaxed(mask, pio + PIO_PDR);
836 }
837 
838 static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)
839 {
840 	writel_relaxed(mask, pio + PIO_PER);
841 	writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
842 }
843 
844 static int at91_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
845 			unsigned group)
846 {
847 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
848 	const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
849 	const struct at91_pmx_pin *pin;
850 	uint32_t npins = info->groups[group].npins;
851 	int i, ret;
852 	unsigned mask;
853 	void __iomem *pio;
854 
855 	dev_dbg(info->dev, "enable function %s group %s\n",
856 		info->functions[selector].name, info->groups[group].name);
857 
858 	/* first check that all the pins of the group are valid with a valid
859 	 * parameter */
860 	for (i = 0; i < npins; i++) {
861 		pin = &pins_conf[i];
862 		ret = pin_check_config(info, info->groups[group].name, i, pin);
863 		if (ret)
864 			return ret;
865 	}
866 
867 	for (i = 0; i < npins; i++) {
868 		pin = &pins_conf[i];
869 		at91_pin_dbg(info->dev, pin);
870 		pio = pin_to_controller(info, pin->bank);
871 
872 		if (!pio)
873 			continue;
874 
875 		mask = pin_to_mask(pin->pin);
876 		at91_mux_disable_interrupt(pio, mask);
877 		switch (pin->mux) {
878 		case AT91_MUX_GPIO:
879 			at91_mux_gpio_enable(pio, mask, 1);
880 			break;
881 		case AT91_MUX_PERIPH_A:
882 			info->ops->mux_A_periph(pio, mask);
883 			break;
884 		case AT91_MUX_PERIPH_B:
885 			info->ops->mux_B_periph(pio, mask);
886 			break;
887 		case AT91_MUX_PERIPH_C:
888 			if (!info->ops->mux_C_periph)
889 				return -EINVAL;
890 			info->ops->mux_C_periph(pio, mask);
891 			break;
892 		case AT91_MUX_PERIPH_D:
893 			if (!info->ops->mux_D_periph)
894 				return -EINVAL;
895 			info->ops->mux_D_periph(pio, mask);
896 			break;
897 		}
898 		if (pin->mux)
899 			at91_mux_gpio_disable(pio, mask);
900 	}
901 
902 	return 0;
903 }
904 
905 static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
906 {
907 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
908 
909 	return info->nfunctions;
910 }
911 
912 static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev,
913 					  unsigned selector)
914 {
915 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
916 
917 	return info->functions[selector].name;
918 }
919 
920 static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
921 			       const char * const **groups,
922 			       unsigned * const num_groups)
923 {
924 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
925 
926 	*groups = info->functions[selector].groups;
927 	*num_groups = info->functions[selector].ngroups;
928 
929 	return 0;
930 }
931 
932 static int at91_gpio_request_enable(struct pinctrl_dev *pctldev,
933 				    struct pinctrl_gpio_range *range,
934 				    unsigned offset)
935 {
936 	struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
937 	struct at91_gpio_chip *at91_chip;
938 	struct gpio_chip *chip;
939 	unsigned mask;
940 
941 	if (!range) {
942 		dev_err(npct->dev, "invalid range\n");
943 		return -EINVAL;
944 	}
945 	if (!range->gc) {
946 		dev_err(npct->dev, "missing GPIO chip in range\n");
947 		return -EINVAL;
948 	}
949 	chip = range->gc;
950 	at91_chip = gpiochip_get_data(chip);
951 
952 	dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
953 
954 	mask = 1 << (offset - chip->base);
955 
956 	dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n",
957 		offset, 'A' + range->id, offset - chip->base, mask);
958 
959 	writel_relaxed(mask, at91_chip->regbase + PIO_PER);
960 
961 	return 0;
962 }
963 
964 static void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
965 				   struct pinctrl_gpio_range *range,
966 				   unsigned offset)
967 {
968 	struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
969 
970 	dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
971 	/* Set the pin to some default state, GPIO is usually default */
972 }
973 
974 static const struct pinmux_ops at91_pmx_ops = {
975 	.get_functions_count	= at91_pmx_get_funcs_count,
976 	.get_function_name	= at91_pmx_get_func_name,
977 	.get_function_groups	= at91_pmx_get_groups,
978 	.set_mux		= at91_pmx_set,
979 	.gpio_request_enable	= at91_gpio_request_enable,
980 	.gpio_disable_free	= at91_gpio_disable_free,
981 };
982 
983 static int at91_pinconf_get(struct pinctrl_dev *pctldev,
984 			     unsigned pin_id, unsigned long *config)
985 {
986 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
987 	void __iomem *pio;
988 	unsigned pin;
989 	int div;
990 	bool out;
991 
992 	*config = 0;
993 	dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id);
994 	pio = pin_to_controller(info, pin_to_bank(pin_id));
995 
996 	if (!pio)
997 		return -EINVAL;
998 
999 	pin = pin_id % MAX_NB_GPIO_PER_BANK;
1000 
1001 	if (at91_mux_get_multidrive(pio, pin))
1002 		*config |= MULTI_DRIVE;
1003 
1004 	if (at91_mux_get_pullup(pio, pin))
1005 		*config |= PULL_UP;
1006 
1007 	if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin))
1008 		*config |= DEGLITCH;
1009 	if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div))
1010 		*config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT);
1011 	if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin))
1012 		*config |= PULL_DOWN;
1013 	if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin))
1014 		*config |= DIS_SCHMIT;
1015 	if (info->ops->get_drivestrength)
1016 		*config |= (info->ops->get_drivestrength(pio, pin)
1017 				<< DRIVE_STRENGTH_SHIFT);
1018 	if (info->ops->get_slewrate)
1019 		*config |= (info->ops->get_slewrate(pio, pin) << SLEWRATE_SHIFT);
1020 	if (at91_mux_get_output(pio, pin, &out))
1021 		*config |= OUTPUT | (out << OUTPUT_VAL_SHIFT);
1022 
1023 	return 0;
1024 }
1025 
1026 static int at91_pinconf_set(struct pinctrl_dev *pctldev,
1027 			     unsigned pin_id, unsigned long *configs,
1028 			     unsigned num_configs)
1029 {
1030 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1031 	unsigned mask;
1032 	void __iomem *pio;
1033 	int i;
1034 	unsigned long config;
1035 	unsigned pin;
1036 
1037 	for (i = 0; i < num_configs; i++) {
1038 		config = configs[i];
1039 
1040 		dev_dbg(info->dev,
1041 			"%s:%d, pin_id=%d, config=0x%lx",
1042 			__func__, __LINE__, pin_id, config);
1043 		pio = pin_to_controller(info, pin_to_bank(pin_id));
1044 
1045 		if (!pio)
1046 			return -EINVAL;
1047 
1048 		pin = pin_id % MAX_NB_GPIO_PER_BANK;
1049 		mask = pin_to_mask(pin);
1050 
1051 		if (config & PULL_UP && config & PULL_DOWN)
1052 			return -EINVAL;
1053 
1054 		at91_mux_set_output(pio, mask, config & OUTPUT,
1055 				    (config & OUTPUT_VAL) >> OUTPUT_VAL_SHIFT);
1056 		at91_mux_set_pullup(pio, mask, config & PULL_UP);
1057 		at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
1058 		if (info->ops->set_deglitch)
1059 			info->ops->set_deglitch(pio, mask, config & DEGLITCH);
1060 		if (info->ops->set_debounce)
1061 			info->ops->set_debounce(pio, mask, config & DEBOUNCE,
1062 				(config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
1063 		if (info->ops->set_pulldown)
1064 			info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
1065 		if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
1066 			info->ops->disable_schmitt_trig(pio, mask);
1067 		if (info->ops->set_drivestrength)
1068 			info->ops->set_drivestrength(pio, pin,
1069 				(config & DRIVE_STRENGTH)
1070 					>> DRIVE_STRENGTH_SHIFT);
1071 		if (info->ops->set_slewrate)
1072 			info->ops->set_slewrate(pio, pin,
1073 				(config & SLEWRATE) >> SLEWRATE_SHIFT);
1074 
1075 	} /* for each config */
1076 
1077 	return 0;
1078 }
1079 
1080 #define DBG_SHOW_FLAG(flag) do {		\
1081 	if (config & flag) {			\
1082 		if (num_conf)			\
1083 			seq_puts(s, "|");	\
1084 		seq_puts(s, #flag);		\
1085 		num_conf++;			\
1086 	}					\
1087 } while (0)
1088 
1089 #define DBG_SHOW_FLAG_MASKED(mask, flag, name) do { \
1090 	if ((config & mask) == flag) {		\
1091 		if (num_conf)			\
1092 			seq_puts(s, "|");	\
1093 		seq_puts(s, #name);		\
1094 		num_conf++;			\
1095 	}					\
1096 } while (0)
1097 
1098 static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
1099 				   struct seq_file *s, unsigned pin_id)
1100 {
1101 	unsigned long config;
1102 	int val, num_conf = 0;
1103 
1104 	at91_pinconf_get(pctldev, pin_id, &config);
1105 
1106 	DBG_SHOW_FLAG(MULTI_DRIVE);
1107 	DBG_SHOW_FLAG(PULL_UP);
1108 	DBG_SHOW_FLAG(PULL_DOWN);
1109 	DBG_SHOW_FLAG(DIS_SCHMIT);
1110 	DBG_SHOW_FLAG(DEGLITCH);
1111 	DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW),
1112 			     DRIVE_STRENGTH_LOW);
1113 	DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED),
1114 			     DRIVE_STRENGTH_MED);
1115 	DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI),
1116 			     DRIVE_STRENGTH_HI);
1117 	DBG_SHOW_FLAG(SLEWRATE);
1118 	DBG_SHOW_FLAG(DEBOUNCE);
1119 	if (config & DEBOUNCE) {
1120 		val = config >> DEBOUNCE_VAL_SHIFT;
1121 		seq_printf(s, "(%d)", val);
1122 	}
1123 
1124 	return;
1125 }
1126 
1127 static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
1128 					 struct seq_file *s, unsigned group)
1129 {
1130 }
1131 
1132 static const struct pinconf_ops at91_pinconf_ops = {
1133 	.pin_config_get			= at91_pinconf_get,
1134 	.pin_config_set			= at91_pinconf_set,
1135 	.pin_config_dbg_show		= at91_pinconf_dbg_show,
1136 	.pin_config_group_dbg_show	= at91_pinconf_group_dbg_show,
1137 };
1138 
1139 static struct pinctrl_desc at91_pinctrl_desc = {
1140 	.pctlops	= &at91_pctrl_ops,
1141 	.pmxops		= &at91_pmx_ops,
1142 	.confops	= &at91_pinconf_ops,
1143 	.owner		= THIS_MODULE,
1144 };
1145 
1146 static const char *gpio_compat = "atmel,at91rm9200-gpio";
1147 
1148 static void at91_pinctrl_child_count(struct at91_pinctrl *info,
1149 				     struct device_node *np)
1150 {
1151 	struct device_node *child;
1152 
1153 	for_each_child_of_node(np, child) {
1154 		if (of_device_is_compatible(child, gpio_compat)) {
1155 			if (of_device_is_available(child))
1156 				info->nactive_banks++;
1157 		} else {
1158 			info->nfunctions++;
1159 			info->ngroups += of_get_child_count(child);
1160 		}
1161 	}
1162 }
1163 
1164 static int at91_pinctrl_mux_mask(struct at91_pinctrl *info,
1165 				 struct device_node *np)
1166 {
1167 	int ret = 0;
1168 	int size;
1169 	const __be32 *list;
1170 
1171 	list = of_get_property(np, "atmel,mux-mask", &size);
1172 	if (!list) {
1173 		dev_err(info->dev, "can not read the mux-mask of %d\n", size);
1174 		return -EINVAL;
1175 	}
1176 
1177 	size /= sizeof(*list);
1178 	if (!size || size % gpio_banks) {
1179 		dev_err(info->dev, "wrong mux mask array should be by %d\n", gpio_banks);
1180 		return -EINVAL;
1181 	}
1182 	info->nmux = size / gpio_banks;
1183 
1184 	info->mux_mask = devm_kcalloc(info->dev, size, sizeof(u32),
1185 				      GFP_KERNEL);
1186 	if (!info->mux_mask)
1187 		return -ENOMEM;
1188 
1189 	ret = of_property_read_u32_array(np, "atmel,mux-mask",
1190 					  info->mux_mask, size);
1191 	if (ret)
1192 		dev_err(info->dev, "can not read the mux-mask of %d\n", size);
1193 	return ret;
1194 }
1195 
1196 static int at91_pinctrl_parse_groups(struct device_node *np,
1197 				     struct at91_pin_group *grp,
1198 				     struct at91_pinctrl *info, u32 index)
1199 {
1200 	struct at91_pmx_pin *pin;
1201 	int size;
1202 	const __be32 *list;
1203 	int i, j;
1204 
1205 	dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
1206 
1207 	/* Initialise group */
1208 	grp->name = np->name;
1209 
1210 	/*
1211 	 * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
1212 	 * do sanity check and calculate pins number
1213 	 */
1214 	list = of_get_property(np, "atmel,pins", &size);
1215 	/* we do not check return since it's safe node passed down */
1216 	size /= sizeof(*list);
1217 	if (!size || size % 4) {
1218 		dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1219 		return -EINVAL;
1220 	}
1221 
1222 	grp->npins = size / 4;
1223 	pin = grp->pins_conf = devm_kcalloc(info->dev,
1224 					    grp->npins,
1225 					    sizeof(struct at91_pmx_pin),
1226 					    GFP_KERNEL);
1227 	grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
1228 				 GFP_KERNEL);
1229 	if (!grp->pins_conf || !grp->pins)
1230 		return -ENOMEM;
1231 
1232 	for (i = 0, j = 0; i < size; i += 4, j++) {
1233 		pin->bank = be32_to_cpu(*list++);
1234 		pin->pin = be32_to_cpu(*list++);
1235 		grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
1236 		pin->mux = be32_to_cpu(*list++);
1237 		pin->conf = be32_to_cpu(*list++);
1238 
1239 		at91_pin_dbg(info->dev, pin);
1240 		pin++;
1241 	}
1242 
1243 	return 0;
1244 }
1245 
1246 static int at91_pinctrl_parse_functions(struct device_node *np,
1247 					struct at91_pinctrl *info, u32 index)
1248 {
1249 	struct device_node *child;
1250 	struct at91_pmx_func *func;
1251 	struct at91_pin_group *grp;
1252 	int ret;
1253 	static u32 grp_index;
1254 	u32 i = 0;
1255 
1256 	dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
1257 
1258 	func = &info->functions[index];
1259 
1260 	/* Initialise function */
1261 	func->name = np->name;
1262 	func->ngroups = of_get_child_count(np);
1263 	if (func->ngroups == 0) {
1264 		dev_err(info->dev, "no groups defined\n");
1265 		return -EINVAL;
1266 	}
1267 	func->groups = devm_kcalloc(info->dev,
1268 			func->ngroups, sizeof(char *), GFP_KERNEL);
1269 	if (!func->groups)
1270 		return -ENOMEM;
1271 
1272 	for_each_child_of_node(np, child) {
1273 		func->groups[i] = child->name;
1274 		grp = &info->groups[grp_index++];
1275 		ret = at91_pinctrl_parse_groups(child, grp, info, i++);
1276 		if (ret) {
1277 			of_node_put(child);
1278 			return ret;
1279 		}
1280 	}
1281 
1282 	return 0;
1283 }
1284 
1285 static const struct of_device_id at91_pinctrl_of_match[] = {
1286 	{ .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops },
1287 	{ .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
1288 	{ .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
1289 	{ .compatible = "microchip,sam9x60-pinctrl", .data = &sam9x60_ops },
1290 	{ /* sentinel */ }
1291 };
1292 
1293 static int at91_pinctrl_probe_dt(struct platform_device *pdev,
1294 				 struct at91_pinctrl *info)
1295 {
1296 	int ret = 0;
1297 	int i, j, ngpio_chips_enabled = 0;
1298 	uint32_t *tmp;
1299 	struct device_node *np = pdev->dev.of_node;
1300 	struct device_node *child;
1301 
1302 	if (!np)
1303 		return -ENODEV;
1304 
1305 	info->dev = &pdev->dev;
1306 	info->ops = (const struct at91_pinctrl_mux_ops *)
1307 		of_match_device(at91_pinctrl_of_match, &pdev->dev)->data;
1308 	at91_pinctrl_child_count(info, np);
1309 
1310 	/*
1311 	 * We need all the GPIO drivers to probe FIRST, or we will not be able
1312 	 * to obtain references to the struct gpio_chip * for them, and we
1313 	 * need this to proceed.
1314 	 */
1315 	for (i = 0; i < MAX_GPIO_BANKS; i++)
1316 		if (gpio_chips[i])
1317 			ngpio_chips_enabled++;
1318 
1319 	if (ngpio_chips_enabled < info->nactive_banks)
1320 		return -EPROBE_DEFER;
1321 
1322 	ret = at91_pinctrl_mux_mask(info, np);
1323 	if (ret)
1324 		return ret;
1325 
1326 	dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux);
1327 
1328 	dev_dbg(&pdev->dev, "mux-mask\n");
1329 	tmp = info->mux_mask;
1330 	for (i = 0; i < gpio_banks; i++) {
1331 		for (j = 0; j < info->nmux; j++, tmp++) {
1332 			dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
1333 		}
1334 	}
1335 
1336 	dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1337 	dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1338 	info->functions = devm_kcalloc(&pdev->dev,
1339 					info->nfunctions,
1340 					sizeof(struct at91_pmx_func),
1341 					GFP_KERNEL);
1342 	if (!info->functions)
1343 		return -ENOMEM;
1344 
1345 	info->groups = devm_kcalloc(&pdev->dev,
1346 					info->ngroups,
1347 					sizeof(struct at91_pin_group),
1348 					GFP_KERNEL);
1349 	if (!info->groups)
1350 		return -ENOMEM;
1351 
1352 	dev_dbg(&pdev->dev, "nbanks = %d\n", gpio_banks);
1353 	dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1354 	dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1355 
1356 	i = 0;
1357 
1358 	for_each_child_of_node(np, child) {
1359 		if (of_device_is_compatible(child, gpio_compat))
1360 			continue;
1361 		ret = at91_pinctrl_parse_functions(child, info, i++);
1362 		if (ret) {
1363 			dev_err(&pdev->dev, "failed to parse function\n");
1364 			of_node_put(child);
1365 			return ret;
1366 		}
1367 	}
1368 
1369 	return 0;
1370 }
1371 
1372 static int at91_pinctrl_probe(struct platform_device *pdev)
1373 {
1374 	struct at91_pinctrl *info;
1375 	struct pinctrl_pin_desc *pdesc;
1376 	int ret, i, j, k;
1377 
1378 	info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1379 	if (!info)
1380 		return -ENOMEM;
1381 
1382 	ret = at91_pinctrl_probe_dt(pdev, info);
1383 	if (ret)
1384 		return ret;
1385 
1386 	at91_pinctrl_desc.name = dev_name(&pdev->dev);
1387 	at91_pinctrl_desc.npins = gpio_banks * MAX_NB_GPIO_PER_BANK;
1388 	at91_pinctrl_desc.pins = pdesc =
1389 		devm_kcalloc(&pdev->dev,
1390 			     at91_pinctrl_desc.npins, sizeof(*pdesc),
1391 			     GFP_KERNEL);
1392 
1393 	if (!at91_pinctrl_desc.pins)
1394 		return -ENOMEM;
1395 
1396 	for (i = 0, k = 0; i < gpio_banks; i++) {
1397 		for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
1398 			pdesc->number = k;
1399 			pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j);
1400 			pdesc++;
1401 		}
1402 	}
1403 
1404 	platform_set_drvdata(pdev, info);
1405 	info->pctl = devm_pinctrl_register(&pdev->dev, &at91_pinctrl_desc,
1406 					   info);
1407 
1408 	if (IS_ERR(info->pctl)) {
1409 		dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n");
1410 		return PTR_ERR(info->pctl);
1411 	}
1412 
1413 	/* We will handle a range of GPIO pins */
1414 	for (i = 0; i < gpio_banks; i++)
1415 		if (gpio_chips[i])
1416 			pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
1417 
1418 	dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");
1419 
1420 	return 0;
1421 }
1422 
1423 static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1424 {
1425 	struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1426 	void __iomem *pio = at91_gpio->regbase;
1427 	unsigned mask = 1 << offset;
1428 	u32 osr;
1429 
1430 	osr = readl_relaxed(pio + PIO_OSR);
1431 	if (osr & mask)
1432 		return GPIO_LINE_DIRECTION_OUT;
1433 
1434 	return GPIO_LINE_DIRECTION_IN;
1435 }
1436 
1437 static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1438 {
1439 	struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1440 	void __iomem *pio = at91_gpio->regbase;
1441 	unsigned mask = 1 << offset;
1442 
1443 	writel_relaxed(mask, pio + PIO_ODR);
1444 	return 0;
1445 }
1446 
1447 static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
1448 {
1449 	struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1450 	void __iomem *pio = at91_gpio->regbase;
1451 	unsigned mask = 1 << offset;
1452 	u32 pdsr;
1453 
1454 	pdsr = readl_relaxed(pio + PIO_PDSR);
1455 	return (pdsr & mask) != 0;
1456 }
1457 
1458 static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
1459 				int val)
1460 {
1461 	struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1462 	void __iomem *pio = at91_gpio->regbase;
1463 	unsigned mask = 1 << offset;
1464 
1465 	writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1466 }
1467 
1468 static void at91_gpio_set_multiple(struct gpio_chip *chip,
1469 				      unsigned long *mask, unsigned long *bits)
1470 {
1471 	struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1472 	void __iomem *pio = at91_gpio->regbase;
1473 
1474 #define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1))
1475 	/* Mask additionally to ngpio as not all GPIO controllers have 32 pins */
1476 	uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio);
1477 	uint32_t clear_mask = (*mask & ~(*bits)) & BITS_MASK(chip->ngpio);
1478 
1479 	writel_relaxed(set_mask, pio + PIO_SODR);
1480 	writel_relaxed(clear_mask, pio + PIO_CODR);
1481 }
1482 
1483 static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1484 				int val)
1485 {
1486 	struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1487 	void __iomem *pio = at91_gpio->regbase;
1488 	unsigned mask = 1 << offset;
1489 
1490 	writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1491 	writel_relaxed(mask, pio + PIO_OER);
1492 
1493 	return 0;
1494 }
1495 
1496 #ifdef CONFIG_DEBUG_FS
1497 static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1498 {
1499 	enum at91_mux mode;
1500 	int i;
1501 	struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1502 	void __iomem *pio = at91_gpio->regbase;
1503 	const char *gpio_label;
1504 
1505 	for_each_requested_gpio(chip, i, gpio_label) {
1506 		unsigned mask = pin_to_mask(i);
1507 
1508 		mode = at91_gpio->ops->get_periph(pio, mask);
1509 		seq_printf(s, "[%s] GPIO%s%d: ",
1510 			   gpio_label, chip->label, i);
1511 		if (mode == AT91_MUX_GPIO) {
1512 			seq_printf(s, "[gpio] ");
1513 			seq_printf(s, "%s ",
1514 				      readl_relaxed(pio + PIO_OSR) & mask ?
1515 				      "output" : "input");
1516 			seq_printf(s, "%s\n",
1517 				      readl_relaxed(pio + PIO_PDSR) & mask ?
1518 				      "set" : "clear");
1519 		} else {
1520 			seq_printf(s, "[periph %c]\n",
1521 				   mode + 'A' - 1);
1522 		}
1523 	}
1524 }
1525 #else
1526 #define at91_gpio_dbg_show	NULL
1527 #endif
1528 
1529 /* Several AIC controller irqs are dispatched through this GPIO handler.
1530  * To use any AT91_PIN_* as an externally triggered IRQ, first call
1531  * at91_set_gpio_input() then maybe enable its glitch filter.
1532  * Then just request_irq() with the pin ID; it works like any ARM IRQ
1533  * handler.
1534  * First implementation always triggers on rising and falling edges
1535  * whereas the newer PIO3 can be additionally configured to trigger on
1536  * level, edge with any polarity.
1537  *
1538  * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
1539  * configuring them with at91_set_a_periph() or at91_set_b_periph().
1540  * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
1541  */
1542 
1543 static void gpio_irq_mask(struct irq_data *d)
1544 {
1545 	struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1546 	void __iomem	*pio = at91_gpio->regbase;
1547 	unsigned	mask = 1 << d->hwirq;
1548 
1549 	if (pio)
1550 		writel_relaxed(mask, pio + PIO_IDR);
1551 }
1552 
1553 static void gpio_irq_unmask(struct irq_data *d)
1554 {
1555 	struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1556 	void __iomem	*pio = at91_gpio->regbase;
1557 	unsigned	mask = 1 << d->hwirq;
1558 
1559 	if (pio)
1560 		writel_relaxed(mask, pio + PIO_IER);
1561 }
1562 
1563 static int gpio_irq_type(struct irq_data *d, unsigned type)
1564 {
1565 	switch (type) {
1566 	case IRQ_TYPE_NONE:
1567 	case IRQ_TYPE_EDGE_BOTH:
1568 		return 0;
1569 	default:
1570 		return -EINVAL;
1571 	}
1572 }
1573 
1574 /* Alternate irq type for PIO3 support */
1575 static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
1576 {
1577 	struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1578 	void __iomem	*pio = at91_gpio->regbase;
1579 	unsigned	mask = 1 << d->hwirq;
1580 
1581 	switch (type) {
1582 	case IRQ_TYPE_EDGE_RISING:
1583 		irq_set_handler_locked(d, handle_simple_irq);
1584 		writel_relaxed(mask, pio + PIO_ESR);
1585 		writel_relaxed(mask, pio + PIO_REHLSR);
1586 		break;
1587 	case IRQ_TYPE_EDGE_FALLING:
1588 		irq_set_handler_locked(d, handle_simple_irq);
1589 		writel_relaxed(mask, pio + PIO_ESR);
1590 		writel_relaxed(mask, pio + PIO_FELLSR);
1591 		break;
1592 	case IRQ_TYPE_LEVEL_LOW:
1593 		irq_set_handler_locked(d, handle_level_irq);
1594 		writel_relaxed(mask, pio + PIO_LSR);
1595 		writel_relaxed(mask, pio + PIO_FELLSR);
1596 		break;
1597 	case IRQ_TYPE_LEVEL_HIGH:
1598 		irq_set_handler_locked(d, handle_level_irq);
1599 		writel_relaxed(mask, pio + PIO_LSR);
1600 		writel_relaxed(mask, pio + PIO_REHLSR);
1601 		break;
1602 	case IRQ_TYPE_EDGE_BOTH:
1603 		/*
1604 		 * disable additional interrupt modes:
1605 		 * fall back to default behavior
1606 		 */
1607 		irq_set_handler_locked(d, handle_simple_irq);
1608 		writel_relaxed(mask, pio + PIO_AIMDR);
1609 		return 0;
1610 	case IRQ_TYPE_NONE:
1611 	default:
1612 		pr_warn("AT91: No type for GPIO irq offset %d\n", d->irq);
1613 		return -EINVAL;
1614 	}
1615 
1616 	/* enable additional interrupt modes */
1617 	writel_relaxed(mask, pio + PIO_AIMER);
1618 
1619 	return 0;
1620 }
1621 
1622 static void gpio_irq_ack(struct irq_data *d)
1623 {
1624 	/* the interrupt is already cleared before by reading ISR */
1625 }
1626 
1627 static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
1628 {
1629 	struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1630 	unsigned mask = 1 << d->hwirq;
1631 
1632 	if (state)
1633 		at91_gpio->wakeups |= mask;
1634 	else
1635 		at91_gpio->wakeups &= ~mask;
1636 
1637 	irq_set_irq_wake(at91_gpio->pioc_virq, state);
1638 
1639 	return 0;
1640 }
1641 
1642 static int __maybe_unused at91_gpio_suspend(struct device *dev)
1643 {
1644 	struct at91_gpio_chip *at91_chip = dev_get_drvdata(dev);
1645 	void __iomem *pio = at91_chip->regbase;
1646 
1647 	at91_chip->backups = readl_relaxed(pio + PIO_IMR);
1648 	writel_relaxed(at91_chip->backups, pio + PIO_IDR);
1649 	writel_relaxed(at91_chip->wakeups, pio + PIO_IER);
1650 
1651 	if (!at91_chip->wakeups)
1652 		clk_disable_unprepare(at91_chip->clock);
1653 	else
1654 		dev_dbg(dev, "GPIO-%c may wake for %08x\n",
1655 			'A' + at91_chip->id, at91_chip->wakeups);
1656 
1657 	return 0;
1658 }
1659 
1660 static int __maybe_unused at91_gpio_resume(struct device *dev)
1661 {
1662 	struct at91_gpio_chip *at91_chip = dev_get_drvdata(dev);
1663 	void __iomem *pio = at91_chip->regbase;
1664 
1665 	if (!at91_chip->wakeups)
1666 		clk_prepare_enable(at91_chip->clock);
1667 
1668 	writel_relaxed(at91_chip->wakeups, pio + PIO_IDR);
1669 	writel_relaxed(at91_chip->backups, pio + PIO_IER);
1670 
1671 	return 0;
1672 }
1673 
1674 static void gpio_irq_handler(struct irq_desc *desc)
1675 {
1676 	struct irq_chip *chip = irq_desc_get_chip(desc);
1677 	struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc);
1678 	struct at91_gpio_chip *at91_gpio = gpiochip_get_data(gpio_chip);
1679 	void __iomem	*pio = at91_gpio->regbase;
1680 	unsigned long	isr;
1681 	int		n;
1682 
1683 	chained_irq_enter(chip, desc);
1684 	for (;;) {
1685 		/* Reading ISR acks pending (edge triggered) GPIO interrupts.
1686 		 * When there are none pending, we're finished unless we need
1687 		 * to process multiple banks (like ID_PIOCDE on sam9263).
1688 		 */
1689 		isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
1690 		if (!isr) {
1691 			if (!at91_gpio->next)
1692 				break;
1693 			at91_gpio = at91_gpio->next;
1694 			pio = at91_gpio->regbase;
1695 			gpio_chip = &at91_gpio->chip;
1696 			continue;
1697 		}
1698 
1699 		for_each_set_bit(n, &isr, BITS_PER_LONG)
1700 			generic_handle_domain_irq(gpio_chip->irq.domain, n);
1701 	}
1702 	chained_irq_exit(chip, desc);
1703 	/* now it may re-trigger */
1704 }
1705 
1706 static int at91_gpio_of_irq_setup(struct platform_device *pdev,
1707 				  struct at91_gpio_chip *at91_gpio)
1708 {
1709 	struct gpio_chip	*gpiochip_prev = NULL;
1710 	struct at91_gpio_chip   *prev = NULL;
1711 	struct irq_data		*d = irq_get_irq_data(at91_gpio->pioc_virq);
1712 	struct irq_chip		*gpio_irqchip;
1713 	struct gpio_irq_chip	*girq;
1714 	int i;
1715 
1716 	gpio_irqchip = devm_kzalloc(&pdev->dev, sizeof(*gpio_irqchip),
1717 				    GFP_KERNEL);
1718 	if (!gpio_irqchip)
1719 		return -ENOMEM;
1720 
1721 	at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
1722 
1723 	gpio_irqchip->name = "GPIO";
1724 	gpio_irqchip->irq_ack = gpio_irq_ack;
1725 	gpio_irqchip->irq_disable = gpio_irq_mask;
1726 	gpio_irqchip->irq_mask = gpio_irq_mask;
1727 	gpio_irqchip->irq_unmask = gpio_irq_unmask;
1728 	gpio_irqchip->irq_set_wake = pm_ptr(gpio_irq_set_wake);
1729 	gpio_irqchip->irq_set_type = at91_gpio->ops->irq_type;
1730 
1731 	/* Disable irqs of this PIO controller */
1732 	writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);
1733 
1734 	/*
1735 	 * Let the generic code handle this edge IRQ, the chained
1736 	 * handler will perform the actual work of handling the parent
1737 	 * interrupt.
1738 	 */
1739 	girq = &at91_gpio->chip.irq;
1740 	girq->chip = gpio_irqchip;
1741 	girq->default_type = IRQ_TYPE_NONE;
1742 	girq->handler = handle_edge_irq;
1743 
1744 	/*
1745 	 * The top level handler handles one bank of GPIOs, except
1746 	 * on some SoC it can handle up to three...
1747 	 * We only set up the handler for the first of the list.
1748 	 */
1749 	gpiochip_prev = irq_get_handler_data(at91_gpio->pioc_virq);
1750 	if (!gpiochip_prev) {
1751 		girq->parent_handler = gpio_irq_handler;
1752 		girq->num_parents = 1;
1753 		girq->parents = devm_kcalloc(&pdev->dev, 1,
1754 					     sizeof(*girq->parents),
1755 					     GFP_KERNEL);
1756 		if (!girq->parents)
1757 			return -ENOMEM;
1758 		girq->parents[0] = at91_gpio->pioc_virq;
1759 		return 0;
1760 	}
1761 
1762 	prev = gpiochip_get_data(gpiochip_prev);
1763 	/* we can only have 2 banks before */
1764 	for (i = 0; i < 2; i++) {
1765 		if (prev->next) {
1766 			prev = prev->next;
1767 		} else {
1768 			prev->next = at91_gpio;
1769 			return 0;
1770 		}
1771 	}
1772 
1773 	return -EINVAL;
1774 }
1775 
1776 /* This structure is replicated for each GPIO block allocated at probe time */
1777 static const struct gpio_chip at91_gpio_template = {
1778 	.request		= gpiochip_generic_request,
1779 	.free			= gpiochip_generic_free,
1780 	.get_direction		= at91_gpio_get_direction,
1781 	.direction_input	= at91_gpio_direction_input,
1782 	.get			= at91_gpio_get,
1783 	.direction_output	= at91_gpio_direction_output,
1784 	.set			= at91_gpio_set,
1785 	.set_multiple		= at91_gpio_set_multiple,
1786 	.dbg_show		= at91_gpio_dbg_show,
1787 	.can_sleep		= false,
1788 	.ngpio			= MAX_NB_GPIO_PER_BANK,
1789 };
1790 
1791 static const struct of_device_id at91_gpio_of_match[] = {
1792 	{ .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
1793 	{ .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
1794 	{ .compatible = "microchip,sam9x60-gpio", .data = &sam9x60_ops },
1795 	{ /* sentinel */ }
1796 };
1797 
1798 static int at91_gpio_probe(struct platform_device *pdev)
1799 {
1800 	struct device_node *np = pdev->dev.of_node;
1801 	struct at91_gpio_chip *at91_chip = NULL;
1802 	struct gpio_chip *chip;
1803 	struct pinctrl_gpio_range *range;
1804 	int ret = 0;
1805 	int irq, i;
1806 	int alias_idx = of_alias_get_id(np, "gpio");
1807 	uint32_t ngpio;
1808 	char **names;
1809 
1810 	BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
1811 	if (gpio_chips[alias_idx]) {
1812 		ret = -EBUSY;
1813 		goto err;
1814 	}
1815 
1816 	irq = platform_get_irq(pdev, 0);
1817 	if (irq < 0) {
1818 		ret = irq;
1819 		goto err;
1820 	}
1821 
1822 	at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL);
1823 	if (!at91_chip) {
1824 		ret = -ENOMEM;
1825 		goto err;
1826 	}
1827 
1828 	at91_chip->regbase = devm_platform_ioremap_resource(pdev, 0);
1829 	if (IS_ERR(at91_chip->regbase)) {
1830 		ret = PTR_ERR(at91_chip->regbase);
1831 		goto err;
1832 	}
1833 
1834 	at91_chip->ops = (const struct at91_pinctrl_mux_ops *)
1835 		of_match_device(at91_gpio_of_match, &pdev->dev)->data;
1836 	at91_chip->pioc_virq = irq;
1837 	at91_chip->pioc_idx = alias_idx;
1838 
1839 	at91_chip->clock = devm_clk_get(&pdev->dev, NULL);
1840 	if (IS_ERR(at91_chip->clock)) {
1841 		dev_err(&pdev->dev, "failed to get clock, ignoring.\n");
1842 		ret = PTR_ERR(at91_chip->clock);
1843 		goto err;
1844 	}
1845 
1846 	ret = clk_prepare_enable(at91_chip->clock);
1847 	if (ret) {
1848 		dev_err(&pdev->dev, "failed to prepare and enable clock, ignoring.\n");
1849 		goto clk_enable_err;
1850 	}
1851 
1852 	at91_chip->chip = at91_gpio_template;
1853 	at91_chip->id = alias_idx;
1854 
1855 	chip = &at91_chip->chip;
1856 	chip->label = dev_name(&pdev->dev);
1857 	chip->parent = &pdev->dev;
1858 	chip->owner = THIS_MODULE;
1859 	chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
1860 
1861 	if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) {
1862 		if (ngpio >= MAX_NB_GPIO_PER_BANK)
1863 			pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
1864 			       alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
1865 		else
1866 			chip->ngpio = ngpio;
1867 	}
1868 
1869 	names = devm_kcalloc(&pdev->dev, chip->ngpio, sizeof(char *),
1870 			     GFP_KERNEL);
1871 
1872 	if (!names) {
1873 		ret = -ENOMEM;
1874 		goto clk_enable_err;
1875 	}
1876 
1877 	for (i = 0; i < chip->ngpio; i++)
1878 		names[i] = devm_kasprintf(&pdev->dev, GFP_KERNEL, "pio%c%d", alias_idx + 'A', i);
1879 
1880 	chip->names = (const char *const *)names;
1881 
1882 	range = &at91_chip->range;
1883 	range->name = chip->label;
1884 	range->id = alias_idx;
1885 	range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
1886 
1887 	range->npins = chip->ngpio;
1888 	range->gc = chip;
1889 
1890 	ret = at91_gpio_of_irq_setup(pdev, at91_chip);
1891 	if (ret)
1892 		goto gpiochip_add_err;
1893 
1894 	ret = gpiochip_add_data(chip, at91_chip);
1895 	if (ret)
1896 		goto gpiochip_add_err;
1897 
1898 	gpio_chips[alias_idx] = at91_chip;
1899 	platform_set_drvdata(pdev, at91_chip);
1900 	gpio_banks = max(gpio_banks, alias_idx + 1);
1901 
1902 	dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
1903 
1904 	return 0;
1905 
1906 gpiochip_add_err:
1907 clk_enable_err:
1908 	clk_disable_unprepare(at91_chip->clock);
1909 err:
1910 	dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
1911 
1912 	return ret;
1913 }
1914 
1915 static const struct dev_pm_ops at91_gpio_pm_ops = {
1916 	NOIRQ_SYSTEM_SLEEP_PM_OPS(at91_gpio_suspend, at91_gpio_resume)
1917 };
1918 
1919 static struct platform_driver at91_gpio_driver = {
1920 	.driver = {
1921 		.name = "gpio-at91",
1922 		.of_match_table = at91_gpio_of_match,
1923 		.pm = pm_ptr(&at91_gpio_pm_ops),
1924 	},
1925 	.probe = at91_gpio_probe,
1926 };
1927 
1928 static struct platform_driver at91_pinctrl_driver = {
1929 	.driver = {
1930 		.name = "pinctrl-at91",
1931 		.of_match_table = at91_pinctrl_of_match,
1932 	},
1933 	.probe = at91_pinctrl_probe,
1934 };
1935 
1936 static struct platform_driver * const drivers[] = {
1937 	&at91_gpio_driver,
1938 	&at91_pinctrl_driver,
1939 };
1940 
1941 static int __init at91_pinctrl_init(void)
1942 {
1943 	return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
1944 }
1945 arch_initcall(at91_pinctrl_init);
1946