1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * at91 pinctrl driver based on at91 pinmux core
4  *
5  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
6  */
7 
8 #include <linux/clk.h>
9 #include <linux/err.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/of_device.h>
17 #include <linux/of_irq.h>
18 #include <linux/pm.h>
19 #include <linux/seq_file.h>
20 #include <linux/slab.h>
21 #include <linux/string_helpers.h>
22 
23 /* Since we request GPIOs from ourself */
24 #include <linux/pinctrl/consumer.h>
25 #include <linux/pinctrl/machine.h>
26 #include <linux/pinctrl/pinconf.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinmux.h>
29 
30 #include "pinctrl-at91.h"
31 #include "core.h"
32 
33 #define MAX_GPIO_BANKS		5
34 #define MAX_NB_GPIO_PER_BANK	32
35 
36 struct at91_pinctrl_mux_ops;
37 
38 /**
39  * struct at91_gpio_chip: at91 gpio chip
40  * @chip: gpio chip
41  * @range: gpio range
42  * @next: bank sharing same clock
43  * @pioc_hwirq: PIO bank interrupt identifier on AIC
44  * @pioc_virq: PIO bank Linux virtual interrupt
45  * @regbase: PIO bank virtual address
46  * @clock: associated clock
47  * @ops: at91 pinctrl mux ops
48  * @wakeups: wakeup interrupts
49  * @backups: interrupts disabled in suspend
50  * @id: gpio chip identifier
51  */
52 struct at91_gpio_chip {
53 	struct gpio_chip	chip;
54 	struct pinctrl_gpio_range range;
55 	struct at91_gpio_chip	*next;
56 	int			pioc_hwirq;
57 	int			pioc_virq;
58 	void __iomem		*regbase;
59 	struct clk		*clock;
60 	const struct at91_pinctrl_mux_ops *ops;
61 	u32			wakeups;
62 	u32			backups;
63 	u32			id;
64 };
65 
66 static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
67 
68 static int gpio_banks;
69 
70 #define PULL_UP		(1 << 0)
71 #define MULTI_DRIVE	(1 << 1)
72 #define DEGLITCH	(1 << 2)
73 #define PULL_DOWN	(1 << 3)
74 #define DIS_SCHMIT	(1 << 4)
75 #define DRIVE_STRENGTH_SHIFT	5
76 #define DRIVE_STRENGTH_MASK		0x3
77 #define DRIVE_STRENGTH   (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
78 #define OUTPUT		(1 << 7)
79 #define OUTPUT_VAL_SHIFT	8
80 #define OUTPUT_VAL	(0x1 << OUTPUT_VAL_SHIFT)
81 #define SLEWRATE_SHIFT	9
82 #define SLEWRATE_MASK	0x1
83 #define SLEWRATE	(SLEWRATE_MASK << SLEWRATE_SHIFT)
84 #define DEBOUNCE	(1 << 16)
85 #define DEBOUNCE_VAL_SHIFT	17
86 #define DEBOUNCE_VAL	(0x3fff << DEBOUNCE_VAL_SHIFT)
87 
88 /*
89  * These defines will translated the dt binding settings to our internal
90  * settings. They are not necessarily the same value as the register setting.
91  * The actual drive strength current of low, medium and high must be looked up
92  * from the corresponding device datasheet. This value is different for pins
93  * that are even in the same banks. It is also dependent on VCC.
94  * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
95  * strength when there is no dt config for it.
96  */
97 enum drive_strength_bit {
98 	DRIVE_STRENGTH_BIT_DEF,
99 	DRIVE_STRENGTH_BIT_LOW,
100 	DRIVE_STRENGTH_BIT_MED,
101 	DRIVE_STRENGTH_BIT_HI,
102 };
103 
104 #define DRIVE_STRENGTH_BIT_MSK(name)	(DRIVE_STRENGTH_BIT_##name << \
105 					 DRIVE_STRENGTH_SHIFT)
106 
107 enum slewrate_bit {
108 	SLEWRATE_BIT_ENA,
109 	SLEWRATE_BIT_DIS,
110 };
111 
112 #define SLEWRATE_BIT_MSK(name)		(SLEWRATE_BIT_##name << SLEWRATE_SHIFT)
113 
114 /**
115  * struct at91_pmx_func - describes AT91 pinmux functions
116  * @name: the name of this specific function
117  * @groups: corresponding pin groups
118  * @ngroups: the number of groups
119  */
120 struct at91_pmx_func {
121 	const char	*name;
122 	const char	**groups;
123 	unsigned	ngroups;
124 };
125 
126 enum at91_mux {
127 	AT91_MUX_GPIO = 0,
128 	AT91_MUX_PERIPH_A = 1,
129 	AT91_MUX_PERIPH_B = 2,
130 	AT91_MUX_PERIPH_C = 3,
131 	AT91_MUX_PERIPH_D = 4,
132 };
133 
134 /**
135  * struct at91_pmx_pin - describes an At91 pin mux
136  * @bank: the bank of the pin
137  * @pin: the pin number in the @bank
138  * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
139  * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
140  */
141 struct at91_pmx_pin {
142 	uint32_t	bank;
143 	uint32_t	pin;
144 	enum at91_mux	mux;
145 	unsigned long	conf;
146 };
147 
148 /**
149  * struct at91_pin_group - describes an At91 pin group
150  * @name: the name of this specific pin group
151  * @pins_conf: the mux mode for each pin in this group. The size of this
152  *	array is the same as pins.
153  * @pins: an array of discrete physical pins used in this group, taken
154  *	from the driver-local pin enumeration space
155  * @npins: the number of pins in this group array, i.e. the number of
156  *	elements in .pins so we can iterate over that array
157  */
158 struct at91_pin_group {
159 	const char		*name;
160 	struct at91_pmx_pin	*pins_conf;
161 	unsigned int		*pins;
162 	unsigned		npins;
163 };
164 
165 /**
166  * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
167  * on new IP with support for periph C and D the way to mux in
168  * periph A and B has changed
169  * So provide the right call back
170  * if not present means the IP does not support it
171  * @get_periph: return the periph mode configured
172  * @mux_A_periph: mux as periph A
173  * @mux_B_periph: mux as periph B
174  * @mux_C_periph: mux as periph C
175  * @mux_D_periph: mux as periph D
176  * @get_deglitch: get deglitch status
177  * @set_deglitch: enable/disable deglitch
178  * @get_debounce: get debounce status
179  * @set_debounce: enable/disable debounce
180  * @get_pulldown: get pulldown status
181  * @set_pulldown: enable/disable pulldown
182  * @get_schmitt_trig: get schmitt trigger status
183  * @disable_schmitt_trig: disable schmitt trigger
184  * @get_drivestrength: get driver strength
185  * @set_drivestrength: set driver strength
186  * @get_slewrate: get slew rate
187  * @set_slewrate: set slew rate
188  * @irq_type: return irq type
189  */
190 struct at91_pinctrl_mux_ops {
191 	enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
192 	void (*mux_A_periph)(void __iomem *pio, unsigned mask);
193 	void (*mux_B_periph)(void __iomem *pio, unsigned mask);
194 	void (*mux_C_periph)(void __iomem *pio, unsigned mask);
195 	void (*mux_D_periph)(void __iomem *pio, unsigned mask);
196 	bool (*get_deglitch)(void __iomem *pio, unsigned pin);
197 	void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on);
198 	bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
199 	void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div);
200 	bool (*get_pulldown)(void __iomem *pio, unsigned pin);
201 	void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
202 	bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
203 	void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
204 	unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
205 	void (*set_drivestrength)(void __iomem *pio, unsigned pin,
206 					u32 strength);
207 	unsigned (*get_slewrate)(void __iomem *pio, unsigned pin);
208 	void (*set_slewrate)(void __iomem *pio, unsigned pin, u32 slewrate);
209 	/* irq */
210 	int (*irq_type)(struct irq_data *d, unsigned type);
211 };
212 
213 static int gpio_irq_type(struct irq_data *d, unsigned type);
214 static int alt_gpio_irq_type(struct irq_data *d, unsigned type);
215 
216 struct at91_pinctrl {
217 	struct device		*dev;
218 	struct pinctrl_dev	*pctl;
219 
220 	int			nactive_banks;
221 
222 	uint32_t		*mux_mask;
223 	int			nmux;
224 
225 	struct at91_pmx_func	*functions;
226 	int			nfunctions;
227 
228 	struct at91_pin_group	*groups;
229 	int			ngroups;
230 
231 	const struct at91_pinctrl_mux_ops *ops;
232 };
233 
234 static inline const struct at91_pin_group *at91_pinctrl_find_group_by_name(
235 				const struct at91_pinctrl *info,
236 				const char *name)
237 {
238 	const struct at91_pin_group *grp = NULL;
239 	int i;
240 
241 	for (i = 0; i < info->ngroups; i++) {
242 		if (strcmp(info->groups[i].name, name))
243 			continue;
244 
245 		grp = &info->groups[i];
246 		dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]);
247 		break;
248 	}
249 
250 	return grp;
251 }
252 
253 static int at91_get_groups_count(struct pinctrl_dev *pctldev)
254 {
255 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
256 
257 	return info->ngroups;
258 }
259 
260 static const char *at91_get_group_name(struct pinctrl_dev *pctldev,
261 				       unsigned selector)
262 {
263 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
264 
265 	return info->groups[selector].name;
266 }
267 
268 static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
269 			       const unsigned **pins,
270 			       unsigned *npins)
271 {
272 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
273 
274 	if (selector >= info->ngroups)
275 		return -EINVAL;
276 
277 	*pins = info->groups[selector].pins;
278 	*npins = info->groups[selector].npins;
279 
280 	return 0;
281 }
282 
283 static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
284 		   unsigned offset)
285 {
286 	seq_printf(s, "%s", dev_name(pctldev->dev));
287 }
288 
289 static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
290 			struct device_node *np,
291 			struct pinctrl_map **map, unsigned *num_maps)
292 {
293 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
294 	const struct at91_pin_group *grp;
295 	struct pinctrl_map *new_map;
296 	struct device_node *parent;
297 	int map_num = 1;
298 	int i;
299 
300 	/*
301 	 * first find the group of this node and check if we need to create
302 	 * config maps for pins
303 	 */
304 	grp = at91_pinctrl_find_group_by_name(info, np->name);
305 	if (!grp) {
306 		dev_err(info->dev, "unable to find group for node %pOFn\n",
307 			np);
308 		return -EINVAL;
309 	}
310 
311 	map_num += grp->npins;
312 	new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map),
313 			       GFP_KERNEL);
314 	if (!new_map)
315 		return -ENOMEM;
316 
317 	*map = new_map;
318 	*num_maps = map_num;
319 
320 	/* create mux map */
321 	parent = of_get_parent(np);
322 	if (!parent) {
323 		devm_kfree(pctldev->dev, new_map);
324 		return -EINVAL;
325 	}
326 	new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
327 	new_map[0].data.mux.function = parent->name;
328 	new_map[0].data.mux.group = np->name;
329 	of_node_put(parent);
330 
331 	/* create config map */
332 	new_map++;
333 	for (i = 0; i < grp->npins; i++) {
334 		new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
335 		new_map[i].data.configs.group_or_pin =
336 				pin_get_name(pctldev, grp->pins[i]);
337 		new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
338 		new_map[i].data.configs.num_configs = 1;
339 	}
340 
341 	dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
342 		(*map)->data.mux.function, (*map)->data.mux.group, map_num);
343 
344 	return 0;
345 }
346 
347 static void at91_dt_free_map(struct pinctrl_dev *pctldev,
348 				struct pinctrl_map *map, unsigned num_maps)
349 {
350 }
351 
352 static const struct pinctrl_ops at91_pctrl_ops = {
353 	.get_groups_count	= at91_get_groups_count,
354 	.get_group_name		= at91_get_group_name,
355 	.get_group_pins		= at91_get_group_pins,
356 	.pin_dbg_show		= at91_pin_dbg_show,
357 	.dt_node_to_map		= at91_dt_node_to_map,
358 	.dt_free_map		= at91_dt_free_map,
359 };
360 
361 static void __iomem *pin_to_controller(struct at91_pinctrl *info,
362 				 unsigned int bank)
363 {
364 	if (!gpio_chips[bank])
365 		return NULL;
366 
367 	return gpio_chips[bank]->regbase;
368 }
369 
370 static inline int pin_to_bank(unsigned pin)
371 {
372 	return pin /= MAX_NB_GPIO_PER_BANK;
373 }
374 
375 static unsigned pin_to_mask(unsigned int pin)
376 {
377 	return 1 << pin;
378 }
379 
380 static unsigned two_bit_pin_value_shift_amount(unsigned int pin)
381 {
382 	/* return the shift value for a pin for "two bit" per pin registers,
383 	 * i.e. drive strength */
384 	return 2*((pin >= MAX_NB_GPIO_PER_BANK/2)
385 			? pin - MAX_NB_GPIO_PER_BANK/2 : pin);
386 }
387 
388 static unsigned sama5d3_get_drive_register(unsigned int pin)
389 {
390 	/* drive strength is split between two registers
391 	 * with two bits per pin */
392 	return (pin >= MAX_NB_GPIO_PER_BANK/2)
393 			? SAMA5D3_PIO_DRIVER2 : SAMA5D3_PIO_DRIVER1;
394 }
395 
396 static unsigned at91sam9x5_get_drive_register(unsigned int pin)
397 {
398 	/* drive strength is split between two registers
399 	 * with two bits per pin */
400 	return (pin >= MAX_NB_GPIO_PER_BANK/2)
401 			? AT91SAM9X5_PIO_DRIVER2 : AT91SAM9X5_PIO_DRIVER1;
402 }
403 
404 static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
405 {
406 	writel_relaxed(mask, pio + PIO_IDR);
407 }
408 
409 static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
410 {
411 	return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1);
412 }
413 
414 static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
415 {
416 	if (on)
417 		writel_relaxed(mask, pio + PIO_PPDDR);
418 
419 	writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
420 }
421 
422 static bool at91_mux_get_output(void __iomem *pio, unsigned int pin, bool *val)
423 {
424 	*val = (readl_relaxed(pio + PIO_ODSR) >> pin) & 0x1;
425 	return (readl_relaxed(pio + PIO_OSR) >> pin) & 0x1;
426 }
427 
428 static void at91_mux_set_output(void __iomem *pio, unsigned int mask,
429 				bool is_on, bool val)
430 {
431 	writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
432 	writel_relaxed(mask, pio + (is_on ? PIO_OER : PIO_ODR));
433 }
434 
435 static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
436 {
437 	return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1;
438 }
439 
440 static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
441 {
442 	writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR));
443 }
444 
445 static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
446 {
447 	writel_relaxed(mask, pio + PIO_ASR);
448 }
449 
450 static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
451 {
452 	writel_relaxed(mask, pio + PIO_BSR);
453 }
454 
455 static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
456 {
457 
458 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask,
459 						pio + PIO_ABCDSR1);
460 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
461 						pio + PIO_ABCDSR2);
462 }
463 
464 static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
465 {
466 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask,
467 						pio + PIO_ABCDSR1);
468 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
469 						pio + PIO_ABCDSR2);
470 }
471 
472 static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
473 {
474 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
475 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
476 }
477 
478 static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
479 {
480 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
481 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
482 }
483 
484 static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask)
485 {
486 	unsigned select;
487 
488 	if (readl_relaxed(pio + PIO_PSR) & mask)
489 		return AT91_MUX_GPIO;
490 
491 	select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask);
492 	select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1);
493 
494 	return select + 1;
495 }
496 
497 static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)
498 {
499 	unsigned select;
500 
501 	if (readl_relaxed(pio + PIO_PSR) & mask)
502 		return AT91_MUX_GPIO;
503 
504 	select = readl_relaxed(pio + PIO_ABSR) & mask;
505 
506 	return select + 1;
507 }
508 
509 static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin)
510 {
511 	return (readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1;
512 }
513 
514 static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
515 {
516 	writel_relaxed(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
517 }
518 
519 static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin)
520 {
521 	if ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1)
522 		return !((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
523 
524 	return false;
525 }
526 
527 static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
528 {
529 	if (is_on)
530 		writel_relaxed(mask, pio + PIO_IFSCDR);
531 	at91_mux_set_deglitch(pio, mask, is_on);
532 }
533 
534 static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
535 {
536 	*div = readl_relaxed(pio + PIO_SCDR);
537 
538 	return ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) &&
539 	       ((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
540 }
541 
542 static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
543 				bool is_on, u32 div)
544 {
545 	if (is_on) {
546 		writel_relaxed(mask, pio + PIO_IFSCER);
547 		writel_relaxed(div & PIO_SCDR_DIV, pio + PIO_SCDR);
548 		writel_relaxed(mask, pio + PIO_IFER);
549 	} else
550 		writel_relaxed(mask, pio + PIO_IFSCDR);
551 }
552 
553 static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
554 {
555 	return !((readl_relaxed(pio + PIO_PPDSR) >> pin) & 0x1);
556 }
557 
558 static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
559 {
560 	if (is_on)
561 		writel_relaxed(mask, pio + PIO_PUDR);
562 
563 	writel_relaxed(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
564 }
565 
566 static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
567 {
568 	writel_relaxed(readl_relaxed(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
569 }
570 
571 static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
572 {
573 	return (readl_relaxed(pio + PIO_SCHMITT) >> pin) & 0x1;
574 }
575 
576 static inline u32 read_drive_strength(void __iomem *reg, unsigned pin)
577 {
578 	unsigned tmp = readl_relaxed(reg);
579 
580 	tmp = tmp >> two_bit_pin_value_shift_amount(pin);
581 
582 	return tmp & DRIVE_STRENGTH_MASK;
583 }
584 
585 static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
586 							unsigned pin)
587 {
588 	unsigned tmp = read_drive_strength(pio +
589 					sama5d3_get_drive_register(pin), pin);
590 
591 	/* SAMA5 strength is 1:1 with our defines,
592 	 * except 0 is equivalent to low per datasheet */
593 	if (!tmp)
594 		tmp = DRIVE_STRENGTH_BIT_MSK(LOW);
595 
596 	return tmp;
597 }
598 
599 static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
600 							unsigned pin)
601 {
602 	unsigned tmp = read_drive_strength(pio +
603 				at91sam9x5_get_drive_register(pin), pin);
604 
605 	/* strength is inverse in SAM9x5s hardware with the pinctrl defines
606 	 * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
607 	tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp;
608 
609 	return tmp;
610 }
611 
612 static unsigned at91_mux_sam9x60_get_drivestrength(void __iomem *pio,
613 						   unsigned pin)
614 {
615 	unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
616 
617 	if (tmp & BIT(pin))
618 		return DRIVE_STRENGTH_BIT_HI;
619 
620 	return DRIVE_STRENGTH_BIT_LOW;
621 }
622 
623 static unsigned at91_mux_sam9x60_get_slewrate(void __iomem *pio, unsigned pin)
624 {
625 	unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
626 
627 	if ((tmp & BIT(pin)))
628 		return SLEWRATE_BIT_ENA;
629 
630 	return SLEWRATE_BIT_DIS;
631 }
632 
633 static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
634 {
635 	unsigned tmp = readl_relaxed(reg);
636 	unsigned shift = two_bit_pin_value_shift_amount(pin);
637 
638 	tmp &= ~(DRIVE_STRENGTH_MASK  <<  shift);
639 	tmp |= strength << shift;
640 
641 	writel_relaxed(tmp, reg);
642 }
643 
644 static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin,
645 						u32 setting)
646 {
647 	/* do nothing if setting is zero */
648 	if (!setting)
649 		return;
650 
651 	/* strength is 1 to 1 with setting for SAMA5 */
652 	set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting);
653 }
654 
655 static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
656 						u32 setting)
657 {
658 	/* do nothing if setting is zero */
659 	if (!setting)
660 		return;
661 
662 	/* strength is inverse on SAM9x5s with our defines
663 	 * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
664 	setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
665 
666 	set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
667 				setting);
668 }
669 
670 static void at91_mux_sam9x60_set_drivestrength(void __iomem *pio, unsigned pin,
671 					       u32 setting)
672 {
673 	unsigned int tmp;
674 
675 	if (setting <= DRIVE_STRENGTH_BIT_DEF ||
676 	    setting == DRIVE_STRENGTH_BIT_MED ||
677 	    setting > DRIVE_STRENGTH_BIT_HI)
678 		return;
679 
680 	tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
681 
682 	/* Strength is 0: low, 1: hi */
683 	if (setting == DRIVE_STRENGTH_BIT_LOW)
684 		tmp &= ~BIT(pin);
685 	else
686 		tmp |= BIT(pin);
687 
688 	writel_relaxed(tmp, pio + SAM9X60_PIO_DRIVER1);
689 }
690 
691 static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin,
692 					  u32 setting)
693 {
694 	unsigned int tmp;
695 
696 	if (setting < SLEWRATE_BIT_ENA || setting > SLEWRATE_BIT_DIS)
697 		return;
698 
699 	tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
700 
701 	if (setting == SLEWRATE_BIT_DIS)
702 		tmp &= ~BIT(pin);
703 	else
704 		tmp |= BIT(pin);
705 
706 	writel_relaxed(tmp, pio + SAM9X60_PIO_SLEWR);
707 }
708 
709 static const struct at91_pinctrl_mux_ops at91rm9200_ops = {
710 	.get_periph	= at91_mux_get_periph,
711 	.mux_A_periph	= at91_mux_set_A_periph,
712 	.mux_B_periph	= at91_mux_set_B_periph,
713 	.get_deglitch	= at91_mux_get_deglitch,
714 	.set_deglitch	= at91_mux_set_deglitch,
715 	.irq_type	= gpio_irq_type,
716 };
717 
718 static const struct at91_pinctrl_mux_ops at91sam9x5_ops = {
719 	.get_periph	= at91_mux_pio3_get_periph,
720 	.mux_A_periph	= at91_mux_pio3_set_A_periph,
721 	.mux_B_periph	= at91_mux_pio3_set_B_periph,
722 	.mux_C_periph	= at91_mux_pio3_set_C_periph,
723 	.mux_D_periph	= at91_mux_pio3_set_D_periph,
724 	.get_deglitch	= at91_mux_pio3_get_deglitch,
725 	.set_deglitch	= at91_mux_pio3_set_deglitch,
726 	.get_debounce	= at91_mux_pio3_get_debounce,
727 	.set_debounce	= at91_mux_pio3_set_debounce,
728 	.get_pulldown	= at91_mux_pio3_get_pulldown,
729 	.set_pulldown	= at91_mux_pio3_set_pulldown,
730 	.get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
731 	.disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
732 	.get_drivestrength = at91_mux_sam9x5_get_drivestrength,
733 	.set_drivestrength = at91_mux_sam9x5_set_drivestrength,
734 	.irq_type	= alt_gpio_irq_type,
735 };
736 
737 static const struct at91_pinctrl_mux_ops sam9x60_ops = {
738 	.get_periph	= at91_mux_pio3_get_periph,
739 	.mux_A_periph	= at91_mux_pio3_set_A_periph,
740 	.mux_B_periph	= at91_mux_pio3_set_B_periph,
741 	.mux_C_periph	= at91_mux_pio3_set_C_periph,
742 	.mux_D_periph	= at91_mux_pio3_set_D_periph,
743 	.get_deglitch	= at91_mux_pio3_get_deglitch,
744 	.set_deglitch	= at91_mux_pio3_set_deglitch,
745 	.get_debounce	= at91_mux_pio3_get_debounce,
746 	.set_debounce	= at91_mux_pio3_set_debounce,
747 	.get_pulldown	= at91_mux_pio3_get_pulldown,
748 	.set_pulldown	= at91_mux_pio3_set_pulldown,
749 	.get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
750 	.disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
751 	.get_drivestrength = at91_mux_sam9x60_get_drivestrength,
752 	.set_drivestrength = at91_mux_sam9x60_set_drivestrength,
753 	.get_slewrate   = at91_mux_sam9x60_get_slewrate,
754 	.set_slewrate   = at91_mux_sam9x60_set_slewrate,
755 	.irq_type	= alt_gpio_irq_type,
756 };
757 
758 static const struct at91_pinctrl_mux_ops sama5d3_ops = {
759 	.get_periph	= at91_mux_pio3_get_periph,
760 	.mux_A_periph	= at91_mux_pio3_set_A_periph,
761 	.mux_B_periph	= at91_mux_pio3_set_B_periph,
762 	.mux_C_periph	= at91_mux_pio3_set_C_periph,
763 	.mux_D_periph	= at91_mux_pio3_set_D_periph,
764 	.get_deglitch	= at91_mux_pio3_get_deglitch,
765 	.set_deglitch	= at91_mux_pio3_set_deglitch,
766 	.get_debounce	= at91_mux_pio3_get_debounce,
767 	.set_debounce	= at91_mux_pio3_set_debounce,
768 	.get_pulldown	= at91_mux_pio3_get_pulldown,
769 	.set_pulldown	= at91_mux_pio3_set_pulldown,
770 	.get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
771 	.disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
772 	.get_drivestrength = at91_mux_sama5d3_get_drivestrength,
773 	.set_drivestrength = at91_mux_sama5d3_set_drivestrength,
774 	.irq_type	= alt_gpio_irq_type,
775 };
776 
777 static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
778 {
779 	if (pin->mux) {
780 		dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lx\n",
781 			pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
782 	} else {
783 		dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lx\n",
784 			pin->bank + 'A', pin->pin, pin->conf);
785 	}
786 }
787 
788 static int pin_check_config(struct at91_pinctrl *info, const char *name,
789 			    int index, const struct at91_pmx_pin *pin)
790 {
791 	int mux;
792 
793 	/* check if it's a valid config */
794 	if (pin->bank >= gpio_banks) {
795 		dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
796 			name, index, pin->bank, gpio_banks);
797 		return -EINVAL;
798 	}
799 
800 	if (!gpio_chips[pin->bank]) {
801 		dev_err(info->dev, "%s: pin conf %d bank_id %d not enabled\n",
802 			name, index, pin->bank);
803 		return -ENXIO;
804 	}
805 
806 	if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
807 		dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
808 			name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
809 		return -EINVAL;
810 	}
811 
812 	if (!pin->mux)
813 		return 0;
814 
815 	mux = pin->mux - 1;
816 
817 	if (mux >= info->nmux) {
818 		dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
819 			name, index, mux, info->nmux);
820 		return -EINVAL;
821 	}
822 
823 	if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
824 		dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
825 			name, index, mux, pin->bank + 'A', pin->pin);
826 		return -EINVAL;
827 	}
828 
829 	return 0;
830 }
831 
832 static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
833 {
834 	writel_relaxed(mask, pio + PIO_PDR);
835 }
836 
837 static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)
838 {
839 	writel_relaxed(mask, pio + PIO_PER);
840 	writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
841 }
842 
843 static int at91_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
844 			unsigned group)
845 {
846 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
847 	const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
848 	const struct at91_pmx_pin *pin;
849 	uint32_t npins = info->groups[group].npins;
850 	int i, ret;
851 	unsigned mask;
852 	void __iomem *pio;
853 
854 	dev_dbg(info->dev, "enable function %s group %s\n",
855 		info->functions[selector].name, info->groups[group].name);
856 
857 	/* first check that all the pins of the group are valid with a valid
858 	 * parameter */
859 	for (i = 0; i < npins; i++) {
860 		pin = &pins_conf[i];
861 		ret = pin_check_config(info, info->groups[group].name, i, pin);
862 		if (ret)
863 			return ret;
864 	}
865 
866 	for (i = 0; i < npins; i++) {
867 		pin = &pins_conf[i];
868 		at91_pin_dbg(info->dev, pin);
869 		pio = pin_to_controller(info, pin->bank);
870 
871 		if (!pio)
872 			continue;
873 
874 		mask = pin_to_mask(pin->pin);
875 		at91_mux_disable_interrupt(pio, mask);
876 		switch (pin->mux) {
877 		case AT91_MUX_GPIO:
878 			at91_mux_gpio_enable(pio, mask, 1);
879 			break;
880 		case AT91_MUX_PERIPH_A:
881 			info->ops->mux_A_periph(pio, mask);
882 			break;
883 		case AT91_MUX_PERIPH_B:
884 			info->ops->mux_B_periph(pio, mask);
885 			break;
886 		case AT91_MUX_PERIPH_C:
887 			if (!info->ops->mux_C_periph)
888 				return -EINVAL;
889 			info->ops->mux_C_periph(pio, mask);
890 			break;
891 		case AT91_MUX_PERIPH_D:
892 			if (!info->ops->mux_D_periph)
893 				return -EINVAL;
894 			info->ops->mux_D_periph(pio, mask);
895 			break;
896 		}
897 		if (pin->mux)
898 			at91_mux_gpio_disable(pio, mask);
899 	}
900 
901 	return 0;
902 }
903 
904 static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
905 {
906 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
907 
908 	return info->nfunctions;
909 }
910 
911 static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev,
912 					  unsigned selector)
913 {
914 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
915 
916 	return info->functions[selector].name;
917 }
918 
919 static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
920 			       const char * const **groups,
921 			       unsigned * const num_groups)
922 {
923 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
924 
925 	*groups = info->functions[selector].groups;
926 	*num_groups = info->functions[selector].ngroups;
927 
928 	return 0;
929 }
930 
931 static int at91_gpio_request_enable(struct pinctrl_dev *pctldev,
932 				    struct pinctrl_gpio_range *range,
933 				    unsigned offset)
934 {
935 	struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
936 	struct at91_gpio_chip *at91_chip;
937 	struct gpio_chip *chip;
938 	unsigned mask;
939 
940 	if (!range) {
941 		dev_err(npct->dev, "invalid range\n");
942 		return -EINVAL;
943 	}
944 	if (!range->gc) {
945 		dev_err(npct->dev, "missing GPIO chip in range\n");
946 		return -EINVAL;
947 	}
948 	chip = range->gc;
949 	at91_chip = gpiochip_get_data(chip);
950 
951 	dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
952 
953 	mask = 1 << (offset - chip->base);
954 
955 	dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n",
956 		offset, 'A' + range->id, offset - chip->base, mask);
957 
958 	writel_relaxed(mask, at91_chip->regbase + PIO_PER);
959 
960 	return 0;
961 }
962 
963 static void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
964 				   struct pinctrl_gpio_range *range,
965 				   unsigned offset)
966 {
967 	struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
968 
969 	dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
970 	/* Set the pin to some default state, GPIO is usually default */
971 }
972 
973 static const struct pinmux_ops at91_pmx_ops = {
974 	.get_functions_count	= at91_pmx_get_funcs_count,
975 	.get_function_name	= at91_pmx_get_func_name,
976 	.get_function_groups	= at91_pmx_get_groups,
977 	.set_mux		= at91_pmx_set,
978 	.gpio_request_enable	= at91_gpio_request_enable,
979 	.gpio_disable_free	= at91_gpio_disable_free,
980 };
981 
982 static int at91_pinconf_get(struct pinctrl_dev *pctldev,
983 			     unsigned pin_id, unsigned long *config)
984 {
985 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
986 	void __iomem *pio;
987 	unsigned pin;
988 	int div;
989 	bool out;
990 
991 	*config = 0;
992 	dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id);
993 	pio = pin_to_controller(info, pin_to_bank(pin_id));
994 
995 	if (!pio)
996 		return -EINVAL;
997 
998 	pin = pin_id % MAX_NB_GPIO_PER_BANK;
999 
1000 	if (at91_mux_get_multidrive(pio, pin))
1001 		*config |= MULTI_DRIVE;
1002 
1003 	if (at91_mux_get_pullup(pio, pin))
1004 		*config |= PULL_UP;
1005 
1006 	if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin))
1007 		*config |= DEGLITCH;
1008 	if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div))
1009 		*config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT);
1010 	if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin))
1011 		*config |= PULL_DOWN;
1012 	if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin))
1013 		*config |= DIS_SCHMIT;
1014 	if (info->ops->get_drivestrength)
1015 		*config |= (info->ops->get_drivestrength(pio, pin)
1016 				<< DRIVE_STRENGTH_SHIFT);
1017 	if (info->ops->get_slewrate)
1018 		*config |= (info->ops->get_slewrate(pio, pin) << SLEWRATE_SHIFT);
1019 	if (at91_mux_get_output(pio, pin, &out))
1020 		*config |= OUTPUT | (out << OUTPUT_VAL_SHIFT);
1021 
1022 	return 0;
1023 }
1024 
1025 static int at91_pinconf_set(struct pinctrl_dev *pctldev,
1026 			     unsigned pin_id, unsigned long *configs,
1027 			     unsigned num_configs)
1028 {
1029 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1030 	unsigned mask;
1031 	void __iomem *pio;
1032 	int i;
1033 	unsigned long config;
1034 	unsigned pin;
1035 
1036 	for (i = 0; i < num_configs; i++) {
1037 		config = configs[i];
1038 
1039 		dev_dbg(info->dev,
1040 			"%s:%d, pin_id=%d, config=0x%lx",
1041 			__func__, __LINE__, pin_id, config);
1042 		pio = pin_to_controller(info, pin_to_bank(pin_id));
1043 
1044 		if (!pio)
1045 			return -EINVAL;
1046 
1047 		pin = pin_id % MAX_NB_GPIO_PER_BANK;
1048 		mask = pin_to_mask(pin);
1049 
1050 		if (config & PULL_UP && config & PULL_DOWN)
1051 			return -EINVAL;
1052 
1053 		at91_mux_set_output(pio, mask, config & OUTPUT,
1054 				    (config & OUTPUT_VAL) >> OUTPUT_VAL_SHIFT);
1055 		at91_mux_set_pullup(pio, mask, config & PULL_UP);
1056 		at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
1057 		if (info->ops->set_deglitch)
1058 			info->ops->set_deglitch(pio, mask, config & DEGLITCH);
1059 		if (info->ops->set_debounce)
1060 			info->ops->set_debounce(pio, mask, config & DEBOUNCE,
1061 				(config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
1062 		if (info->ops->set_pulldown)
1063 			info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
1064 		if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
1065 			info->ops->disable_schmitt_trig(pio, mask);
1066 		if (info->ops->set_drivestrength)
1067 			info->ops->set_drivestrength(pio, pin,
1068 				(config & DRIVE_STRENGTH)
1069 					>> DRIVE_STRENGTH_SHIFT);
1070 		if (info->ops->set_slewrate)
1071 			info->ops->set_slewrate(pio, pin,
1072 				(config & SLEWRATE) >> SLEWRATE_SHIFT);
1073 
1074 	} /* for each config */
1075 
1076 	return 0;
1077 }
1078 
1079 #define DBG_SHOW_FLAG(flag) do {		\
1080 	if (config & flag) {			\
1081 		if (num_conf)			\
1082 			seq_puts(s, "|");	\
1083 		seq_puts(s, #flag);		\
1084 		num_conf++;			\
1085 	}					\
1086 } while (0)
1087 
1088 #define DBG_SHOW_FLAG_MASKED(mask, flag, name) do { \
1089 	if ((config & mask) == flag) {		\
1090 		if (num_conf)			\
1091 			seq_puts(s, "|");	\
1092 		seq_puts(s, #name);		\
1093 		num_conf++;			\
1094 	}					\
1095 } while (0)
1096 
1097 static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
1098 				   struct seq_file *s, unsigned pin_id)
1099 {
1100 	unsigned long config;
1101 	int val, num_conf = 0;
1102 
1103 	at91_pinconf_get(pctldev, pin_id, &config);
1104 
1105 	DBG_SHOW_FLAG(MULTI_DRIVE);
1106 	DBG_SHOW_FLAG(PULL_UP);
1107 	DBG_SHOW_FLAG(PULL_DOWN);
1108 	DBG_SHOW_FLAG(DIS_SCHMIT);
1109 	DBG_SHOW_FLAG(DEGLITCH);
1110 	DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW),
1111 			     DRIVE_STRENGTH_LOW);
1112 	DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED),
1113 			     DRIVE_STRENGTH_MED);
1114 	DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI),
1115 			     DRIVE_STRENGTH_HI);
1116 	DBG_SHOW_FLAG(SLEWRATE);
1117 	DBG_SHOW_FLAG(DEBOUNCE);
1118 	if (config & DEBOUNCE) {
1119 		val = config >> DEBOUNCE_VAL_SHIFT;
1120 		seq_printf(s, "(%d)", val);
1121 	}
1122 
1123 	return;
1124 }
1125 
1126 static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
1127 					 struct seq_file *s, unsigned group)
1128 {
1129 }
1130 
1131 static const struct pinconf_ops at91_pinconf_ops = {
1132 	.pin_config_get			= at91_pinconf_get,
1133 	.pin_config_set			= at91_pinconf_set,
1134 	.pin_config_dbg_show		= at91_pinconf_dbg_show,
1135 	.pin_config_group_dbg_show	= at91_pinconf_group_dbg_show,
1136 };
1137 
1138 static struct pinctrl_desc at91_pinctrl_desc = {
1139 	.pctlops	= &at91_pctrl_ops,
1140 	.pmxops		= &at91_pmx_ops,
1141 	.confops	= &at91_pinconf_ops,
1142 	.owner		= THIS_MODULE,
1143 };
1144 
1145 static const char *gpio_compat = "atmel,at91rm9200-gpio";
1146 
1147 static void at91_pinctrl_child_count(struct at91_pinctrl *info,
1148 				     struct device_node *np)
1149 {
1150 	struct device_node *child;
1151 
1152 	for_each_child_of_node(np, child) {
1153 		if (of_device_is_compatible(child, gpio_compat)) {
1154 			if (of_device_is_available(child))
1155 				info->nactive_banks++;
1156 		} else {
1157 			info->nfunctions++;
1158 			info->ngroups += of_get_child_count(child);
1159 		}
1160 	}
1161 }
1162 
1163 static int at91_pinctrl_mux_mask(struct at91_pinctrl *info,
1164 				 struct device_node *np)
1165 {
1166 	int ret = 0;
1167 	int size;
1168 	const __be32 *list;
1169 
1170 	list = of_get_property(np, "atmel,mux-mask", &size);
1171 	if (!list) {
1172 		dev_err(info->dev, "can not read the mux-mask of %d\n", size);
1173 		return -EINVAL;
1174 	}
1175 
1176 	size /= sizeof(*list);
1177 	if (!size || size % gpio_banks) {
1178 		dev_err(info->dev, "wrong mux mask array should be by %d\n", gpio_banks);
1179 		return -EINVAL;
1180 	}
1181 	info->nmux = size / gpio_banks;
1182 
1183 	info->mux_mask = devm_kcalloc(info->dev, size, sizeof(u32),
1184 				      GFP_KERNEL);
1185 	if (!info->mux_mask)
1186 		return -ENOMEM;
1187 
1188 	ret = of_property_read_u32_array(np, "atmel,mux-mask",
1189 					  info->mux_mask, size);
1190 	if (ret)
1191 		dev_err(info->dev, "can not read the mux-mask of %d\n", size);
1192 	return ret;
1193 }
1194 
1195 static int at91_pinctrl_parse_groups(struct device_node *np,
1196 				     struct at91_pin_group *grp,
1197 				     struct at91_pinctrl *info, u32 index)
1198 {
1199 	struct at91_pmx_pin *pin;
1200 	int size;
1201 	const __be32 *list;
1202 	int i, j;
1203 
1204 	dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
1205 
1206 	/* Initialise group */
1207 	grp->name = np->name;
1208 
1209 	/*
1210 	 * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
1211 	 * do sanity check and calculate pins number
1212 	 */
1213 	list = of_get_property(np, "atmel,pins", &size);
1214 	/* we do not check return since it's safe node passed down */
1215 	size /= sizeof(*list);
1216 	if (!size || size % 4) {
1217 		dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1218 		return -EINVAL;
1219 	}
1220 
1221 	grp->npins = size / 4;
1222 	pin = grp->pins_conf = devm_kcalloc(info->dev,
1223 					    grp->npins,
1224 					    sizeof(struct at91_pmx_pin),
1225 					    GFP_KERNEL);
1226 	grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
1227 				 GFP_KERNEL);
1228 	if (!grp->pins_conf || !grp->pins)
1229 		return -ENOMEM;
1230 
1231 	for (i = 0, j = 0; i < size; i += 4, j++) {
1232 		pin->bank = be32_to_cpu(*list++);
1233 		pin->pin = be32_to_cpu(*list++);
1234 		grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
1235 		pin->mux = be32_to_cpu(*list++);
1236 		pin->conf = be32_to_cpu(*list++);
1237 
1238 		at91_pin_dbg(info->dev, pin);
1239 		pin++;
1240 	}
1241 
1242 	return 0;
1243 }
1244 
1245 static int at91_pinctrl_parse_functions(struct device_node *np,
1246 					struct at91_pinctrl *info, u32 index)
1247 {
1248 	struct device_node *child;
1249 	struct at91_pmx_func *func;
1250 	struct at91_pin_group *grp;
1251 	int ret;
1252 	static u32 grp_index;
1253 	u32 i = 0;
1254 
1255 	dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
1256 
1257 	func = &info->functions[index];
1258 
1259 	/* Initialise function */
1260 	func->name = np->name;
1261 	func->ngroups = of_get_child_count(np);
1262 	if (func->ngroups == 0) {
1263 		dev_err(info->dev, "no groups defined\n");
1264 		return -EINVAL;
1265 	}
1266 	func->groups = devm_kcalloc(info->dev,
1267 			func->ngroups, sizeof(char *), GFP_KERNEL);
1268 	if (!func->groups)
1269 		return -ENOMEM;
1270 
1271 	for_each_child_of_node(np, child) {
1272 		func->groups[i] = child->name;
1273 		grp = &info->groups[grp_index++];
1274 		ret = at91_pinctrl_parse_groups(child, grp, info, i++);
1275 		if (ret) {
1276 			of_node_put(child);
1277 			return ret;
1278 		}
1279 	}
1280 
1281 	return 0;
1282 }
1283 
1284 static const struct of_device_id at91_pinctrl_of_match[] = {
1285 	{ .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops },
1286 	{ .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
1287 	{ .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
1288 	{ .compatible = "microchip,sam9x60-pinctrl", .data = &sam9x60_ops },
1289 	{ /* sentinel */ }
1290 };
1291 
1292 static int at91_pinctrl_probe_dt(struct platform_device *pdev,
1293 				 struct at91_pinctrl *info)
1294 {
1295 	struct device *dev = &pdev->dev;
1296 	int ret = 0;
1297 	int i, j, ngpio_chips_enabled = 0;
1298 	uint32_t *tmp;
1299 	struct device_node *np = dev->of_node;
1300 	struct device_node *child;
1301 
1302 	if (!np)
1303 		return -ENODEV;
1304 
1305 	info->dev = dev;
1306 	info->ops = of_device_get_match_data(dev);
1307 	at91_pinctrl_child_count(info, np);
1308 
1309 	/*
1310 	 * We need all the GPIO drivers to probe FIRST, or we will not be able
1311 	 * to obtain references to the struct gpio_chip * for them, and we
1312 	 * need this to proceed.
1313 	 */
1314 	for (i = 0; i < MAX_GPIO_BANKS; i++)
1315 		if (gpio_chips[i])
1316 			ngpio_chips_enabled++;
1317 
1318 	if (ngpio_chips_enabled < info->nactive_banks)
1319 		return -EPROBE_DEFER;
1320 
1321 	ret = at91_pinctrl_mux_mask(info, np);
1322 	if (ret)
1323 		return ret;
1324 
1325 	dev_dbg(dev, "nmux = %d\n", info->nmux);
1326 
1327 	dev_dbg(dev, "mux-mask\n");
1328 	tmp = info->mux_mask;
1329 	for (i = 0; i < gpio_banks; i++) {
1330 		for (j = 0; j < info->nmux; j++, tmp++) {
1331 			dev_dbg(dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
1332 		}
1333 	}
1334 
1335 	dev_dbg(dev, "nfunctions = %d\n", info->nfunctions);
1336 	dev_dbg(dev, "ngroups = %d\n", info->ngroups);
1337 	info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions),
1338 				       GFP_KERNEL);
1339 	if (!info->functions)
1340 		return -ENOMEM;
1341 
1342 	info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups),
1343 				    GFP_KERNEL);
1344 	if (!info->groups)
1345 		return -ENOMEM;
1346 
1347 	dev_dbg(dev, "nbanks = %d\n", gpio_banks);
1348 	dev_dbg(dev, "nfunctions = %d\n", info->nfunctions);
1349 	dev_dbg(dev, "ngroups = %d\n", info->ngroups);
1350 
1351 	i = 0;
1352 
1353 	for_each_child_of_node(np, child) {
1354 		if (of_device_is_compatible(child, gpio_compat))
1355 			continue;
1356 		ret = at91_pinctrl_parse_functions(child, info, i++);
1357 		if (ret) {
1358 			of_node_put(child);
1359 			return dev_err_probe(dev, ret, "failed to parse function\n");
1360 		}
1361 	}
1362 
1363 	return 0;
1364 }
1365 
1366 static int at91_pinctrl_probe(struct platform_device *pdev)
1367 {
1368 	struct device *dev = &pdev->dev;
1369 	struct at91_pinctrl *info;
1370 	struct pinctrl_pin_desc *pdesc;
1371 	int ret, i, j, k;
1372 
1373 	info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
1374 	if (!info)
1375 		return -ENOMEM;
1376 
1377 	ret = at91_pinctrl_probe_dt(pdev, info);
1378 	if (ret)
1379 		return ret;
1380 
1381 	at91_pinctrl_desc.name = dev_name(dev);
1382 	at91_pinctrl_desc.npins = gpio_banks * MAX_NB_GPIO_PER_BANK;
1383 	at91_pinctrl_desc.pins = pdesc =
1384 		devm_kcalloc(dev, at91_pinctrl_desc.npins, sizeof(*pdesc), GFP_KERNEL);
1385 	if (!at91_pinctrl_desc.pins)
1386 		return -ENOMEM;
1387 
1388 	for (i = 0, k = 0; i < gpio_banks; i++) {
1389 		char **names;
1390 
1391 		names = devm_kasprintf_strarray(dev, "pio", MAX_NB_GPIO_PER_BANK);
1392 		if (IS_ERR(names))
1393 			return PTR_ERR(names);
1394 
1395 		for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
1396 			char *name = names[j];
1397 
1398 			strreplace(name, '-', i + 'A');
1399 
1400 			pdesc->number = k;
1401 			pdesc->name = name;
1402 			pdesc++;
1403 		}
1404 	}
1405 
1406 	platform_set_drvdata(pdev, info);
1407 	info->pctl = devm_pinctrl_register(dev, &at91_pinctrl_desc, info);
1408 	if (IS_ERR(info->pctl))
1409 		return dev_err_probe(dev, PTR_ERR(info->pctl), "could not register AT91 pinctrl driver\n");
1410 
1411 	/* We will handle a range of GPIO pins */
1412 	for (i = 0; i < gpio_banks; i++)
1413 		if (gpio_chips[i])
1414 			pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
1415 
1416 	dev_info(dev, "initialized AT91 pinctrl driver\n");
1417 
1418 	return 0;
1419 }
1420 
1421 static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1422 {
1423 	struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1424 	void __iomem *pio = at91_gpio->regbase;
1425 	unsigned mask = 1 << offset;
1426 	u32 osr;
1427 
1428 	osr = readl_relaxed(pio + PIO_OSR);
1429 	if (osr & mask)
1430 		return GPIO_LINE_DIRECTION_OUT;
1431 
1432 	return GPIO_LINE_DIRECTION_IN;
1433 }
1434 
1435 static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1436 {
1437 	struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1438 	void __iomem *pio = at91_gpio->regbase;
1439 	unsigned mask = 1 << offset;
1440 
1441 	writel_relaxed(mask, pio + PIO_ODR);
1442 	return 0;
1443 }
1444 
1445 static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
1446 {
1447 	struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1448 	void __iomem *pio = at91_gpio->regbase;
1449 	unsigned mask = 1 << offset;
1450 	u32 pdsr;
1451 
1452 	pdsr = readl_relaxed(pio + PIO_PDSR);
1453 	return (pdsr & mask) != 0;
1454 }
1455 
1456 static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
1457 				int val)
1458 {
1459 	struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1460 	void __iomem *pio = at91_gpio->regbase;
1461 	unsigned mask = 1 << offset;
1462 
1463 	writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1464 }
1465 
1466 static void at91_gpio_set_multiple(struct gpio_chip *chip,
1467 				      unsigned long *mask, unsigned long *bits)
1468 {
1469 	struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1470 	void __iomem *pio = at91_gpio->regbase;
1471 
1472 #define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1))
1473 	/* Mask additionally to ngpio as not all GPIO controllers have 32 pins */
1474 	uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio);
1475 	uint32_t clear_mask = (*mask & ~(*bits)) & BITS_MASK(chip->ngpio);
1476 
1477 	writel_relaxed(set_mask, pio + PIO_SODR);
1478 	writel_relaxed(clear_mask, pio + PIO_CODR);
1479 }
1480 
1481 static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1482 				int val)
1483 {
1484 	struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1485 	void __iomem *pio = at91_gpio->regbase;
1486 	unsigned mask = 1 << offset;
1487 
1488 	writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1489 	writel_relaxed(mask, pio + PIO_OER);
1490 
1491 	return 0;
1492 }
1493 
1494 #ifdef CONFIG_DEBUG_FS
1495 static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1496 {
1497 	enum at91_mux mode;
1498 	int i;
1499 	struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1500 	void __iomem *pio = at91_gpio->regbase;
1501 	const char *gpio_label;
1502 
1503 	for_each_requested_gpio(chip, i, gpio_label) {
1504 		unsigned mask = pin_to_mask(i);
1505 
1506 		mode = at91_gpio->ops->get_periph(pio, mask);
1507 		seq_printf(s, "[%s] GPIO%s%d: ",
1508 			   gpio_label, chip->label, i);
1509 		if (mode == AT91_MUX_GPIO) {
1510 			seq_printf(s, "[gpio] ");
1511 			seq_printf(s, "%s ",
1512 				      readl_relaxed(pio + PIO_OSR) & mask ?
1513 				      "output" : "input");
1514 			seq_printf(s, "%s\n",
1515 				      readl_relaxed(pio + PIO_PDSR) & mask ?
1516 				      "set" : "clear");
1517 		} else {
1518 			seq_printf(s, "[periph %c]\n",
1519 				   mode + 'A' - 1);
1520 		}
1521 	}
1522 }
1523 #else
1524 #define at91_gpio_dbg_show	NULL
1525 #endif
1526 
1527 static int gpio_irq_request_resources(struct irq_data *d)
1528 {
1529 	struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1530 
1531 	return gpiochip_lock_as_irq(&at91_gpio->chip, irqd_to_hwirq(d));
1532 }
1533 
1534 static void gpio_irq_release_resources(struct irq_data *d)
1535 {
1536 	struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1537 
1538 	gpiochip_unlock_as_irq(&at91_gpio->chip, irqd_to_hwirq(d));
1539 }
1540 
1541 /* Several AIC controller irqs are dispatched through this GPIO handler.
1542  * To use any AT91_PIN_* as an externally triggered IRQ, first call
1543  * at91_set_gpio_input() then maybe enable its glitch filter.
1544  * Then just request_irq() with the pin ID; it works like any ARM IRQ
1545  * handler.
1546  * First implementation always triggers on rising and falling edges
1547  * whereas the newer PIO3 can be additionally configured to trigger on
1548  * level, edge with any polarity.
1549  *
1550  * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
1551  * configuring them with at91_set_a_periph() or at91_set_b_periph().
1552  * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
1553  */
1554 
1555 static void gpio_irq_mask(struct irq_data *d)
1556 {
1557 	struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1558 	void __iomem	*pio = at91_gpio->regbase;
1559 	unsigned	mask = 1 << d->hwirq;
1560 	unsigned        gpio = irqd_to_hwirq(d);
1561 
1562 	gpiochip_disable_irq(&at91_gpio->chip, gpio);
1563 
1564 	if (pio)
1565 		writel_relaxed(mask, pio + PIO_IDR);
1566 }
1567 
1568 static void gpio_irq_unmask(struct irq_data *d)
1569 {
1570 	struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1571 	void __iomem	*pio = at91_gpio->regbase;
1572 	unsigned	mask = 1 << d->hwirq;
1573 	unsigned        gpio = irqd_to_hwirq(d);
1574 
1575 	gpiochip_enable_irq(&at91_gpio->chip, gpio);
1576 
1577 	if (pio)
1578 		writel_relaxed(mask, pio + PIO_IER);
1579 }
1580 
1581 static int gpio_irq_type(struct irq_data *d, unsigned type)
1582 {
1583 	switch (type) {
1584 	case IRQ_TYPE_NONE:
1585 	case IRQ_TYPE_EDGE_BOTH:
1586 		return 0;
1587 	default:
1588 		return -EINVAL;
1589 	}
1590 }
1591 
1592 /* Alternate irq type for PIO3 support */
1593 static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
1594 {
1595 	struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1596 	void __iomem	*pio = at91_gpio->regbase;
1597 	unsigned	mask = 1 << d->hwirq;
1598 
1599 	switch (type) {
1600 	case IRQ_TYPE_EDGE_RISING:
1601 		irq_set_handler_locked(d, handle_simple_irq);
1602 		writel_relaxed(mask, pio + PIO_ESR);
1603 		writel_relaxed(mask, pio + PIO_REHLSR);
1604 		break;
1605 	case IRQ_TYPE_EDGE_FALLING:
1606 		irq_set_handler_locked(d, handle_simple_irq);
1607 		writel_relaxed(mask, pio + PIO_ESR);
1608 		writel_relaxed(mask, pio + PIO_FELLSR);
1609 		break;
1610 	case IRQ_TYPE_LEVEL_LOW:
1611 		irq_set_handler_locked(d, handle_level_irq);
1612 		writel_relaxed(mask, pio + PIO_LSR);
1613 		writel_relaxed(mask, pio + PIO_FELLSR);
1614 		break;
1615 	case IRQ_TYPE_LEVEL_HIGH:
1616 		irq_set_handler_locked(d, handle_level_irq);
1617 		writel_relaxed(mask, pio + PIO_LSR);
1618 		writel_relaxed(mask, pio + PIO_REHLSR);
1619 		break;
1620 	case IRQ_TYPE_EDGE_BOTH:
1621 		/*
1622 		 * disable additional interrupt modes:
1623 		 * fall back to default behavior
1624 		 */
1625 		irq_set_handler_locked(d, handle_simple_irq);
1626 		writel_relaxed(mask, pio + PIO_AIMDR);
1627 		return 0;
1628 	case IRQ_TYPE_NONE:
1629 	default:
1630 		pr_warn("AT91: No type for GPIO irq offset %d\n", d->irq);
1631 		return -EINVAL;
1632 	}
1633 
1634 	/* enable additional interrupt modes */
1635 	writel_relaxed(mask, pio + PIO_AIMER);
1636 
1637 	return 0;
1638 }
1639 
1640 static void gpio_irq_ack(struct irq_data *d)
1641 {
1642 	/* the interrupt is already cleared before by reading ISR */
1643 }
1644 
1645 static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
1646 {
1647 	struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1648 	unsigned mask = 1 << d->hwirq;
1649 
1650 	if (state)
1651 		at91_gpio->wakeups |= mask;
1652 	else
1653 		at91_gpio->wakeups &= ~mask;
1654 
1655 	irq_set_irq_wake(at91_gpio->pioc_virq, state);
1656 
1657 	return 0;
1658 }
1659 
1660 static int __maybe_unused at91_gpio_suspend(struct device *dev)
1661 {
1662 	struct at91_gpio_chip *at91_chip = dev_get_drvdata(dev);
1663 	void __iomem *pio = at91_chip->regbase;
1664 
1665 	at91_chip->backups = readl_relaxed(pio + PIO_IMR);
1666 	writel_relaxed(at91_chip->backups, pio + PIO_IDR);
1667 	writel_relaxed(at91_chip->wakeups, pio + PIO_IER);
1668 
1669 	if (!at91_chip->wakeups)
1670 		clk_disable_unprepare(at91_chip->clock);
1671 	else
1672 		dev_dbg(dev, "GPIO-%c may wake for %08x\n",
1673 			'A' + at91_chip->id, at91_chip->wakeups);
1674 
1675 	return 0;
1676 }
1677 
1678 static int __maybe_unused at91_gpio_resume(struct device *dev)
1679 {
1680 	struct at91_gpio_chip *at91_chip = dev_get_drvdata(dev);
1681 	void __iomem *pio = at91_chip->regbase;
1682 
1683 	if (!at91_chip->wakeups)
1684 		clk_prepare_enable(at91_chip->clock);
1685 
1686 	writel_relaxed(at91_chip->wakeups, pio + PIO_IDR);
1687 	writel_relaxed(at91_chip->backups, pio + PIO_IER);
1688 
1689 	return 0;
1690 }
1691 
1692 static void gpio_irq_handler(struct irq_desc *desc)
1693 {
1694 	struct irq_chip *chip = irq_desc_get_chip(desc);
1695 	struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc);
1696 	struct at91_gpio_chip *at91_gpio = gpiochip_get_data(gpio_chip);
1697 	void __iomem	*pio = at91_gpio->regbase;
1698 	unsigned long	isr;
1699 	int		n;
1700 
1701 	chained_irq_enter(chip, desc);
1702 	for (;;) {
1703 		/* Reading ISR acks pending (edge triggered) GPIO interrupts.
1704 		 * When there are none pending, we're finished unless we need
1705 		 * to process multiple banks (like ID_PIOCDE on sam9263).
1706 		 */
1707 		isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
1708 		if (!isr) {
1709 			if (!at91_gpio->next)
1710 				break;
1711 			at91_gpio = at91_gpio->next;
1712 			pio = at91_gpio->regbase;
1713 			gpio_chip = &at91_gpio->chip;
1714 			continue;
1715 		}
1716 
1717 		for_each_set_bit(n, &isr, BITS_PER_LONG)
1718 			generic_handle_domain_irq(gpio_chip->irq.domain, n);
1719 	}
1720 	chained_irq_exit(chip, desc);
1721 	/* now it may re-trigger */
1722 }
1723 
1724 static int at91_gpio_of_irq_setup(struct platform_device *pdev,
1725 				  struct at91_gpio_chip *at91_gpio)
1726 {
1727 	struct device		*dev = &pdev->dev;
1728 	struct gpio_chip	*gpiochip_prev = NULL;
1729 	struct at91_gpio_chip   *prev = NULL;
1730 	struct irq_data		*d = irq_get_irq_data(at91_gpio->pioc_virq);
1731 	struct irq_chip		*gpio_irqchip;
1732 	struct gpio_irq_chip	*girq;
1733 	int i;
1734 
1735 	gpio_irqchip = devm_kzalloc(dev, sizeof(*gpio_irqchip), GFP_KERNEL);
1736 	if (!gpio_irqchip)
1737 		return -ENOMEM;
1738 
1739 	at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
1740 
1741 	gpio_irqchip->name = "GPIO";
1742 	gpio_irqchip->irq_request_resources = gpio_irq_request_resources;
1743 	gpio_irqchip->irq_release_resources = gpio_irq_release_resources;
1744 	gpio_irqchip->irq_ack = gpio_irq_ack;
1745 	gpio_irqchip->irq_disable = gpio_irq_mask;
1746 	gpio_irqchip->irq_mask = gpio_irq_mask;
1747 	gpio_irqchip->irq_unmask = gpio_irq_unmask;
1748 	gpio_irqchip->irq_set_wake = pm_ptr(gpio_irq_set_wake);
1749 	gpio_irqchip->irq_set_type = at91_gpio->ops->irq_type;
1750 	gpio_irqchip->flags = IRQCHIP_IMMUTABLE;
1751 
1752 	/* Disable irqs of this PIO controller */
1753 	writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);
1754 
1755 	/*
1756 	 * Let the generic code handle this edge IRQ, the chained
1757 	 * handler will perform the actual work of handling the parent
1758 	 * interrupt.
1759 	 */
1760 	girq = &at91_gpio->chip.irq;
1761 	gpio_irq_chip_set_chip(girq, gpio_irqchip);
1762 	girq->default_type = IRQ_TYPE_NONE;
1763 	girq->handler = handle_edge_irq;
1764 
1765 	/*
1766 	 * The top level handler handles one bank of GPIOs, except
1767 	 * on some SoC it can handle up to three...
1768 	 * We only set up the handler for the first of the list.
1769 	 */
1770 	gpiochip_prev = irq_get_handler_data(at91_gpio->pioc_virq);
1771 	if (!gpiochip_prev) {
1772 		girq->parent_handler = gpio_irq_handler;
1773 		girq->num_parents = 1;
1774 		girq->parents = devm_kcalloc(dev, girq->num_parents,
1775 					     sizeof(*girq->parents),
1776 					     GFP_KERNEL);
1777 		if (!girq->parents)
1778 			return -ENOMEM;
1779 		girq->parents[0] = at91_gpio->pioc_virq;
1780 		return 0;
1781 	}
1782 
1783 	prev = gpiochip_get_data(gpiochip_prev);
1784 	/* we can only have 2 banks before */
1785 	for (i = 0; i < 2; i++) {
1786 		if (prev->next) {
1787 			prev = prev->next;
1788 		} else {
1789 			prev->next = at91_gpio;
1790 			return 0;
1791 		}
1792 	}
1793 
1794 	return -EINVAL;
1795 }
1796 
1797 /* This structure is replicated for each GPIO block allocated at probe time */
1798 static const struct gpio_chip at91_gpio_template = {
1799 	.request		= gpiochip_generic_request,
1800 	.free			= gpiochip_generic_free,
1801 	.get_direction		= at91_gpio_get_direction,
1802 	.direction_input	= at91_gpio_direction_input,
1803 	.get			= at91_gpio_get,
1804 	.direction_output	= at91_gpio_direction_output,
1805 	.set			= at91_gpio_set,
1806 	.set_multiple		= at91_gpio_set_multiple,
1807 	.dbg_show		= at91_gpio_dbg_show,
1808 	.can_sleep		= false,
1809 	.ngpio			= MAX_NB_GPIO_PER_BANK,
1810 };
1811 
1812 static const struct of_device_id at91_gpio_of_match[] = {
1813 	{ .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
1814 	{ .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
1815 	{ .compatible = "microchip,sam9x60-gpio", .data = &sam9x60_ops },
1816 	{ /* sentinel */ }
1817 };
1818 
1819 static int at91_gpio_probe(struct platform_device *pdev)
1820 {
1821 	struct device *dev = &pdev->dev;
1822 	struct device_node *np = dev->of_node;
1823 	struct at91_gpio_chip *at91_chip = NULL;
1824 	struct gpio_chip *chip;
1825 	struct pinctrl_gpio_range *range;
1826 	int ret = 0;
1827 	int irq, i;
1828 	int alias_idx = of_alias_get_id(np, "gpio");
1829 	uint32_t ngpio;
1830 	char **names;
1831 
1832 	BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
1833 	if (gpio_chips[alias_idx])
1834 		return dev_err_probe(dev, -EBUSY, "%d slot is occupied.\n", alias_idx);
1835 
1836 	irq = platform_get_irq(pdev, 0);
1837 	if (irq < 0)
1838 		return irq;
1839 
1840 	at91_chip = devm_kzalloc(dev, sizeof(*at91_chip), GFP_KERNEL);
1841 	if (!at91_chip)
1842 		return -ENOMEM;
1843 
1844 	at91_chip->regbase = devm_platform_ioremap_resource(pdev, 0);
1845 	if (IS_ERR(at91_chip->regbase))
1846 		return PTR_ERR(at91_chip->regbase);
1847 
1848 	at91_chip->ops = of_device_get_match_data(dev);
1849 	at91_chip->pioc_virq = irq;
1850 
1851 	at91_chip->clock = devm_clk_get_enabled(dev, NULL);
1852 	if (IS_ERR(at91_chip->clock))
1853 		return dev_err_probe(dev, PTR_ERR(at91_chip->clock), "failed to get clock, ignoring.\n");
1854 
1855 	at91_chip->chip = at91_gpio_template;
1856 	at91_chip->id = alias_idx;
1857 
1858 	chip = &at91_chip->chip;
1859 	chip->label = dev_name(dev);
1860 	chip->parent = dev;
1861 	chip->owner = THIS_MODULE;
1862 	chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
1863 
1864 	if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) {
1865 		if (ngpio >= MAX_NB_GPIO_PER_BANK)
1866 			dev_err(dev, "at91_gpio.%d, gpio-nb >= %d failback to %d\n",
1867 				alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
1868 		else
1869 			chip->ngpio = ngpio;
1870 	}
1871 
1872 	names = devm_kasprintf_strarray(dev, "pio", chip->ngpio);
1873 	if (IS_ERR(names))
1874 		return PTR_ERR(names);
1875 
1876 	for (i = 0; i < chip->ngpio; i++)
1877 		strreplace(names[i], '-', alias_idx + 'A');
1878 
1879 	chip->names = (const char *const *)names;
1880 
1881 	range = &at91_chip->range;
1882 	range->name = chip->label;
1883 	range->id = alias_idx;
1884 	range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
1885 
1886 	range->npins = chip->ngpio;
1887 	range->gc = chip;
1888 
1889 	ret = at91_gpio_of_irq_setup(pdev, at91_chip);
1890 	if (ret)
1891 		return ret;
1892 
1893 	ret = gpiochip_add_data(chip, at91_chip);
1894 	if (ret)
1895 		return ret;
1896 
1897 	gpio_chips[alias_idx] = at91_chip;
1898 	platform_set_drvdata(pdev, at91_chip);
1899 	gpio_banks = max(gpio_banks, alias_idx + 1);
1900 
1901 	dev_info(dev, "at address %p\n", at91_chip->regbase);
1902 
1903 	return 0;
1904 }
1905 
1906 static const struct dev_pm_ops at91_gpio_pm_ops = {
1907 	NOIRQ_SYSTEM_SLEEP_PM_OPS(at91_gpio_suspend, at91_gpio_resume)
1908 };
1909 
1910 static struct platform_driver at91_gpio_driver = {
1911 	.driver = {
1912 		.name = "gpio-at91",
1913 		.of_match_table = at91_gpio_of_match,
1914 		.pm = pm_ptr(&at91_gpio_pm_ops),
1915 	},
1916 	.probe = at91_gpio_probe,
1917 };
1918 
1919 static struct platform_driver at91_pinctrl_driver = {
1920 	.driver = {
1921 		.name = "pinctrl-at91",
1922 		.of_match_table = at91_pinctrl_of_match,
1923 	},
1924 	.probe = at91_pinctrl_probe,
1925 };
1926 
1927 static struct platform_driver * const drivers[] = {
1928 	&at91_gpio_driver,
1929 	&at91_pinctrl_driver,
1930 };
1931 
1932 static int __init at91_pinctrl_init(void)
1933 {
1934 	return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
1935 }
1936 arch_initcall(at91_pinctrl_init);
1937