16732ae5cSJean-Christophe PLAGNIOL-VILLARD /* 26732ae5cSJean-Christophe PLAGNIOL-VILLARD * at91 pinctrl driver based on at91 pinmux core 36732ae5cSJean-Christophe PLAGNIOL-VILLARD * 46732ae5cSJean-Christophe PLAGNIOL-VILLARD * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 56732ae5cSJean-Christophe PLAGNIOL-VILLARD * 66732ae5cSJean-Christophe PLAGNIOL-VILLARD * Under GPLv2 only 76732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 86732ae5cSJean-Christophe PLAGNIOL-VILLARD 96732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/clk.h> 106732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/err.h> 116732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/init.h> 126732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/module.h> 136732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/of.h> 146732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/of_device.h> 156732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/of_address.h> 166732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/of_irq.h> 176732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/slab.h> 186732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/interrupt.h> 196732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/io.h> 206732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/gpio.h> 216732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/pinctrl/machine.h> 226732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/pinctrl/pinconf.h> 236732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/pinctrl/pinctrl.h> 246732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/pinctrl/pinmux.h> 256732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Since we request GPIOs from ourself */ 266732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/pinctrl/consumer.h> 276732ae5cSJean-Christophe PLAGNIOL-VILLARD 28c654b6bfSAlexandre Belloni #include "pinctrl-at91.h" 296732ae5cSJean-Christophe PLAGNIOL-VILLARD #include "core.h" 306732ae5cSJean-Christophe PLAGNIOL-VILLARD 3194daf85eSLinus Walleij #define MAX_GPIO_BANKS 5 326732ae5cSJean-Christophe PLAGNIOL-VILLARD #define MAX_NB_GPIO_PER_BANK 32 336732ae5cSJean-Christophe PLAGNIOL-VILLARD 346732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl_mux_ops; 356732ae5cSJean-Christophe PLAGNIOL-VILLARD 366732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip { 376732ae5cSJean-Christophe PLAGNIOL-VILLARD struct gpio_chip chip; 386732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_gpio_range range; 396732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *next; /* Bank sharing same clock */ 406732ae5cSJean-Christophe PLAGNIOL-VILLARD int pioc_hwirq; /* PIO bank interrupt identifier on AIC */ 416732ae5cSJean-Christophe PLAGNIOL-VILLARD int pioc_virq; /* PIO bank Linux virtual interrupt */ 426732ae5cSJean-Christophe PLAGNIOL-VILLARD int pioc_idx; /* PIO bank index */ 436732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *regbase; /* PIO bank virtual address */ 446732ae5cSJean-Christophe PLAGNIOL-VILLARD struct clk *clock; /* associated clock */ 456732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl_mux_ops *ops; /* ops */ 466732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 476732ae5cSJean-Christophe PLAGNIOL-VILLARD 486732ae5cSJean-Christophe PLAGNIOL-VILLARD #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip) 496732ae5cSJean-Christophe PLAGNIOL-VILLARD 506732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS]; 516732ae5cSJean-Christophe PLAGNIOL-VILLARD 526732ae5cSJean-Christophe PLAGNIOL-VILLARD static int gpio_banks; 536732ae5cSJean-Christophe PLAGNIOL-VILLARD 54525fae21SJean-Christophe PLAGNIOL-VILLARD #define PULL_UP (1 << 0) 556732ae5cSJean-Christophe PLAGNIOL-VILLARD #define MULTI_DRIVE (1 << 1) 567ebd7a3aSJean-Christophe PLAGNIOL-VILLARD #define DEGLITCH (1 << 2) 577ebd7a3aSJean-Christophe PLAGNIOL-VILLARD #define PULL_DOWN (1 << 3) 587ebd7a3aSJean-Christophe PLAGNIOL-VILLARD #define DIS_SCHMIT (1 << 4) 594334ac2dSMarek Roszko #define DRIVE_STRENGTH_SHIFT 5 604334ac2dSMarek Roszko #define DRIVE_STRENGTH_MASK 0x3 614334ac2dSMarek Roszko #define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT) 627ebd7a3aSJean-Christophe PLAGNIOL-VILLARD #define DEBOUNCE (1 << 16) 637ebd7a3aSJean-Christophe PLAGNIOL-VILLARD #define DEBOUNCE_VAL_SHIFT 17 647ebd7a3aSJean-Christophe PLAGNIOL-VILLARD #define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT) 656732ae5cSJean-Christophe PLAGNIOL-VILLARD 666732ae5cSJean-Christophe PLAGNIOL-VILLARD /** 674334ac2dSMarek Roszko * These defines will translated the dt binding settings to our internal 684334ac2dSMarek Roszko * settings. They are not necessarily the same value as the register setting. 694334ac2dSMarek Roszko * The actual drive strength current of low, medium and high must be looked up 704334ac2dSMarek Roszko * from the corresponding device datasheet. This value is different for pins 714334ac2dSMarek Roszko * that are even in the same banks. It is also dependent on VCC. 724334ac2dSMarek Roszko * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive 734334ac2dSMarek Roszko * strength when there is no dt config for it. 744334ac2dSMarek Roszko */ 754334ac2dSMarek Roszko #define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT) 764334ac2dSMarek Roszko #define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT) 774334ac2dSMarek Roszko #define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT) 784334ac2dSMarek Roszko #define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT) 794334ac2dSMarek Roszko 804334ac2dSMarek Roszko /** 816732ae5cSJean-Christophe PLAGNIOL-VILLARD * struct at91_pmx_func - describes AT91 pinmux functions 826732ae5cSJean-Christophe PLAGNIOL-VILLARD * @name: the name of this specific function 836732ae5cSJean-Christophe PLAGNIOL-VILLARD * @groups: corresponding pin groups 846732ae5cSJean-Christophe PLAGNIOL-VILLARD * @ngroups: the number of groups 856732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 866732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pmx_func { 876732ae5cSJean-Christophe PLAGNIOL-VILLARD const char *name; 886732ae5cSJean-Christophe PLAGNIOL-VILLARD const char **groups; 896732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned ngroups; 906732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 916732ae5cSJean-Christophe PLAGNIOL-VILLARD 926732ae5cSJean-Christophe PLAGNIOL-VILLARD enum at91_mux { 936732ae5cSJean-Christophe PLAGNIOL-VILLARD AT91_MUX_GPIO = 0, 946732ae5cSJean-Christophe PLAGNIOL-VILLARD AT91_MUX_PERIPH_A = 1, 956732ae5cSJean-Christophe PLAGNIOL-VILLARD AT91_MUX_PERIPH_B = 2, 966732ae5cSJean-Christophe PLAGNIOL-VILLARD AT91_MUX_PERIPH_C = 3, 976732ae5cSJean-Christophe PLAGNIOL-VILLARD AT91_MUX_PERIPH_D = 4, 986732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 996732ae5cSJean-Christophe PLAGNIOL-VILLARD 1006732ae5cSJean-Christophe PLAGNIOL-VILLARD /** 1016732ae5cSJean-Christophe PLAGNIOL-VILLARD * struct at91_pmx_pin - describes an At91 pin mux 1026732ae5cSJean-Christophe PLAGNIOL-VILLARD * @bank: the bank of the pin 1036732ae5cSJean-Christophe PLAGNIOL-VILLARD * @pin: the pin number in the @bank 1046732ae5cSJean-Christophe PLAGNIOL-VILLARD * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function. 1056732ae5cSJean-Christophe PLAGNIOL-VILLARD * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc... 1066732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 1076732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pmx_pin { 1086732ae5cSJean-Christophe PLAGNIOL-VILLARD uint32_t bank; 1096732ae5cSJean-Christophe PLAGNIOL-VILLARD uint32_t pin; 1106732ae5cSJean-Christophe PLAGNIOL-VILLARD enum at91_mux mux; 1116732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned long conf; 1126732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 1136732ae5cSJean-Christophe PLAGNIOL-VILLARD 1146732ae5cSJean-Christophe PLAGNIOL-VILLARD /** 1156732ae5cSJean-Christophe PLAGNIOL-VILLARD * struct at91_pin_group - describes an At91 pin group 1166732ae5cSJean-Christophe PLAGNIOL-VILLARD * @name: the name of this specific pin group 1176732ae5cSJean-Christophe PLAGNIOL-VILLARD * @pins_conf: the mux mode for each pin in this group. The size of this 1186732ae5cSJean-Christophe PLAGNIOL-VILLARD * array is the same as pins. 1196732ae5cSJean-Christophe PLAGNIOL-VILLARD * @pins: an array of discrete physical pins used in this group, taken 1206732ae5cSJean-Christophe PLAGNIOL-VILLARD * from the driver-local pin enumeration space 1216732ae5cSJean-Christophe PLAGNIOL-VILLARD * @npins: the number of pins in this group array, i.e. the number of 1226732ae5cSJean-Christophe PLAGNIOL-VILLARD * elements in .pins so we can iterate over that array 1236732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 1246732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pin_group { 1256732ae5cSJean-Christophe PLAGNIOL-VILLARD const char *name; 1266732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pmx_pin *pins_conf; 1276732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned int *pins; 1286732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned npins; 1296732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 1306732ae5cSJean-Christophe PLAGNIOL-VILLARD 1316732ae5cSJean-Christophe PLAGNIOL-VILLARD /** 132c2eb9e7fSAlexandre Belloni * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group 1336732ae5cSJean-Christophe PLAGNIOL-VILLARD * on new IP with support for periph C and D the way to mux in 1346732ae5cSJean-Christophe PLAGNIOL-VILLARD * periph A and B has changed 1356732ae5cSJean-Christophe PLAGNIOL-VILLARD * So provide the right call back 1366732ae5cSJean-Christophe PLAGNIOL-VILLARD * if not present means the IP does not support it 1376732ae5cSJean-Christophe PLAGNIOL-VILLARD * @get_periph: return the periph mode configured 1386732ae5cSJean-Christophe PLAGNIOL-VILLARD * @mux_A_periph: mux as periph A 1396732ae5cSJean-Christophe PLAGNIOL-VILLARD * @mux_B_periph: mux as periph B 1406732ae5cSJean-Christophe PLAGNIOL-VILLARD * @mux_C_periph: mux as periph C 1416732ae5cSJean-Christophe PLAGNIOL-VILLARD * @mux_D_periph: mux as periph D 1427ebd7a3aSJean-Christophe PLAGNIOL-VILLARD * @get_deglitch: get deglitch status 1437ebd7a3aSJean-Christophe PLAGNIOL-VILLARD * @set_deglitch: enable/disable deglitch 1447ebd7a3aSJean-Christophe PLAGNIOL-VILLARD * @get_debounce: get debounce status 1457ebd7a3aSJean-Christophe PLAGNIOL-VILLARD * @set_debounce: enable/disable debounce 1467ebd7a3aSJean-Christophe PLAGNIOL-VILLARD * @get_pulldown: get pulldown status 1477ebd7a3aSJean-Christophe PLAGNIOL-VILLARD * @set_pulldown: enable/disable pulldown 1487ebd7a3aSJean-Christophe PLAGNIOL-VILLARD * @get_schmitt_trig: get schmitt trigger status 1497ebd7a3aSJean-Christophe PLAGNIOL-VILLARD * @disable_schmitt_trig: disable schmitt trigger 1506732ae5cSJean-Christophe PLAGNIOL-VILLARD * @irq_type: return irq type 1516732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 1526732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl_mux_ops { 1536732ae5cSJean-Christophe PLAGNIOL-VILLARD enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask); 1546732ae5cSJean-Christophe PLAGNIOL-VILLARD void (*mux_A_periph)(void __iomem *pio, unsigned mask); 1556732ae5cSJean-Christophe PLAGNIOL-VILLARD void (*mux_B_periph)(void __iomem *pio, unsigned mask); 1566732ae5cSJean-Christophe PLAGNIOL-VILLARD void (*mux_C_periph)(void __iomem *pio, unsigned mask); 1576732ae5cSJean-Christophe PLAGNIOL-VILLARD void (*mux_D_periph)(void __iomem *pio, unsigned mask); 1587ebd7a3aSJean-Christophe PLAGNIOL-VILLARD bool (*get_deglitch)(void __iomem *pio, unsigned pin); 15977966ad7SBoris BREZILLON void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on); 1607ebd7a3aSJean-Christophe PLAGNIOL-VILLARD bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div); 16177966ad7SBoris BREZILLON void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div); 1627ebd7a3aSJean-Christophe PLAGNIOL-VILLARD bool (*get_pulldown)(void __iomem *pio, unsigned pin); 16377966ad7SBoris BREZILLON void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on); 1647ebd7a3aSJean-Christophe PLAGNIOL-VILLARD bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin); 1657ebd7a3aSJean-Christophe PLAGNIOL-VILLARD void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask); 1664334ac2dSMarek Roszko unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin); 1674334ac2dSMarek Roszko void (*set_drivestrength)(void __iomem *pio, unsigned pin, 1684334ac2dSMarek Roszko u32 strength); 1696732ae5cSJean-Christophe PLAGNIOL-VILLARD /* irq */ 1706732ae5cSJean-Christophe PLAGNIOL-VILLARD int (*irq_type)(struct irq_data *d, unsigned type); 1716732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 1726732ae5cSJean-Christophe PLAGNIOL-VILLARD 1736732ae5cSJean-Christophe PLAGNIOL-VILLARD static int gpio_irq_type(struct irq_data *d, unsigned type); 1746732ae5cSJean-Christophe PLAGNIOL-VILLARD static int alt_gpio_irq_type(struct irq_data *d, unsigned type); 1756732ae5cSJean-Christophe PLAGNIOL-VILLARD 1766732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl { 1776732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device *dev; 1786732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_dev *pctl; 1796732ae5cSJean-Christophe PLAGNIOL-VILLARD 180a0b957f3SJean-Christophe PLAGNIOL-VILLARD int nactive_banks; 1816732ae5cSJean-Christophe PLAGNIOL-VILLARD 1826732ae5cSJean-Christophe PLAGNIOL-VILLARD uint32_t *mux_mask; 1836732ae5cSJean-Christophe PLAGNIOL-VILLARD int nmux; 1846732ae5cSJean-Christophe PLAGNIOL-VILLARD 1856732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pmx_func *functions; 1866732ae5cSJean-Christophe PLAGNIOL-VILLARD int nfunctions; 1876732ae5cSJean-Christophe PLAGNIOL-VILLARD 1886732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pin_group *groups; 1896732ae5cSJean-Christophe PLAGNIOL-VILLARD int ngroups; 1906732ae5cSJean-Christophe PLAGNIOL-VILLARD 1916732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl_mux_ops *ops; 1926732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 1936732ae5cSJean-Christophe PLAGNIOL-VILLARD 1946732ae5cSJean-Christophe PLAGNIOL-VILLARD static const inline struct at91_pin_group *at91_pinctrl_find_group_by_name( 1956732ae5cSJean-Christophe PLAGNIOL-VILLARD const struct at91_pinctrl *info, 1966732ae5cSJean-Christophe PLAGNIOL-VILLARD const char *name) 1976732ae5cSJean-Christophe PLAGNIOL-VILLARD { 1986732ae5cSJean-Christophe PLAGNIOL-VILLARD const struct at91_pin_group *grp = NULL; 1996732ae5cSJean-Christophe PLAGNIOL-VILLARD int i; 2006732ae5cSJean-Christophe PLAGNIOL-VILLARD 2016732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < info->ngroups; i++) { 2026732ae5cSJean-Christophe PLAGNIOL-VILLARD if (strcmp(info->groups[i].name, name)) 2036732ae5cSJean-Christophe PLAGNIOL-VILLARD continue; 2046732ae5cSJean-Christophe PLAGNIOL-VILLARD 2056732ae5cSJean-Christophe PLAGNIOL-VILLARD grp = &info->groups[i]; 2066732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]); 2076732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 2086732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2096732ae5cSJean-Christophe PLAGNIOL-VILLARD 2106732ae5cSJean-Christophe PLAGNIOL-VILLARD return grp; 2116732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2126732ae5cSJean-Christophe PLAGNIOL-VILLARD 2136732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_get_groups_count(struct pinctrl_dev *pctldev) 2146732ae5cSJean-Christophe PLAGNIOL-VILLARD { 2156732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2166732ae5cSJean-Christophe PLAGNIOL-VILLARD 2176732ae5cSJean-Christophe PLAGNIOL-VILLARD return info->ngroups; 2186732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2196732ae5cSJean-Christophe PLAGNIOL-VILLARD 2206732ae5cSJean-Christophe PLAGNIOL-VILLARD static const char *at91_get_group_name(struct pinctrl_dev *pctldev, 2216732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned selector) 2226732ae5cSJean-Christophe PLAGNIOL-VILLARD { 2236732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2246732ae5cSJean-Christophe PLAGNIOL-VILLARD 2256732ae5cSJean-Christophe PLAGNIOL-VILLARD return info->groups[selector].name; 2266732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2276732ae5cSJean-Christophe PLAGNIOL-VILLARD 2286732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, 2296732ae5cSJean-Christophe PLAGNIOL-VILLARD const unsigned **pins, 2306732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned *npins) 2316732ae5cSJean-Christophe PLAGNIOL-VILLARD { 2326732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2336732ae5cSJean-Christophe PLAGNIOL-VILLARD 2346732ae5cSJean-Christophe PLAGNIOL-VILLARD if (selector >= info->ngroups) 2356732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 2366732ae5cSJean-Christophe PLAGNIOL-VILLARD 2376732ae5cSJean-Christophe PLAGNIOL-VILLARD *pins = info->groups[selector].pins; 2386732ae5cSJean-Christophe PLAGNIOL-VILLARD *npins = info->groups[selector].npins; 2396732ae5cSJean-Christophe PLAGNIOL-VILLARD 2406732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 2416732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2426732ae5cSJean-Christophe PLAGNIOL-VILLARD 2436732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 2446732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned offset) 2456732ae5cSJean-Christophe PLAGNIOL-VILLARD { 2466732ae5cSJean-Christophe PLAGNIOL-VILLARD seq_printf(s, "%s", dev_name(pctldev->dev)); 2476732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2486732ae5cSJean-Christophe PLAGNIOL-VILLARD 2496732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_dt_node_to_map(struct pinctrl_dev *pctldev, 2506732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *np, 2516732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_map **map, unsigned *num_maps) 2526732ae5cSJean-Christophe PLAGNIOL-VILLARD { 2536732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2546732ae5cSJean-Christophe PLAGNIOL-VILLARD const struct at91_pin_group *grp; 2556732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_map *new_map; 2566732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *parent; 2576732ae5cSJean-Christophe PLAGNIOL-VILLARD int map_num = 1; 2586732ae5cSJean-Christophe PLAGNIOL-VILLARD int i; 2596732ae5cSJean-Christophe PLAGNIOL-VILLARD 2606732ae5cSJean-Christophe PLAGNIOL-VILLARD /* 26161e310a1SAlexandre Belloni * first find the group of this node and check if we need to create 2626732ae5cSJean-Christophe PLAGNIOL-VILLARD * config maps for pins 2636732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 2646732ae5cSJean-Christophe PLAGNIOL-VILLARD grp = at91_pinctrl_find_group_by_name(info, np->name); 2656732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!grp) { 2666732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "unable to find group for node %s\n", 2676732ae5cSJean-Christophe PLAGNIOL-VILLARD np->name); 2686732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 2696732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2706732ae5cSJean-Christophe PLAGNIOL-VILLARD 2716732ae5cSJean-Christophe PLAGNIOL-VILLARD map_num += grp->npins; 2726732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, GFP_KERNEL); 2736732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!new_map) 2746732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENOMEM; 2756732ae5cSJean-Christophe PLAGNIOL-VILLARD 2766732ae5cSJean-Christophe PLAGNIOL-VILLARD *map = new_map; 2776732ae5cSJean-Christophe PLAGNIOL-VILLARD *num_maps = map_num; 2786732ae5cSJean-Christophe PLAGNIOL-VILLARD 2796732ae5cSJean-Christophe PLAGNIOL-VILLARD /* create mux map */ 2806732ae5cSJean-Christophe PLAGNIOL-VILLARD parent = of_get_parent(np); 2816732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!parent) { 282c62b2b34SJulia Lawall devm_kfree(pctldev->dev, new_map); 2836732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 2846732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2856732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 2866732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map[0].data.mux.function = parent->name; 2876732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map[0].data.mux.group = np->name; 2886732ae5cSJean-Christophe PLAGNIOL-VILLARD of_node_put(parent); 2896732ae5cSJean-Christophe PLAGNIOL-VILLARD 2906732ae5cSJean-Christophe PLAGNIOL-VILLARD /* create config map */ 2916732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map++; 2926732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < grp->npins; i++) { 2936732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 2946732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map[i].data.configs.group_or_pin = 2956732ae5cSJean-Christophe PLAGNIOL-VILLARD pin_get_name(pctldev, grp->pins[i]); 2966732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map[i].data.configs.configs = &grp->pins_conf[i].conf; 2976732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map[i].data.configs.num_configs = 1; 2986732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2996732ae5cSJean-Christophe PLAGNIOL-VILLARD 3006732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 3016732ae5cSJean-Christophe PLAGNIOL-VILLARD (*map)->data.mux.function, (*map)->data.mux.group, map_num); 3026732ae5cSJean-Christophe PLAGNIOL-VILLARD 3036732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 3046732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3056732ae5cSJean-Christophe PLAGNIOL-VILLARD 3066732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_dt_free_map(struct pinctrl_dev *pctldev, 3076732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_map *map, unsigned num_maps) 3086732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3096732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3106732ae5cSJean-Christophe PLAGNIOL-VILLARD 311022ab148SLaurent Pinchart static const struct pinctrl_ops at91_pctrl_ops = { 3126732ae5cSJean-Christophe PLAGNIOL-VILLARD .get_groups_count = at91_get_groups_count, 3136732ae5cSJean-Christophe PLAGNIOL-VILLARD .get_group_name = at91_get_group_name, 3146732ae5cSJean-Christophe PLAGNIOL-VILLARD .get_group_pins = at91_get_group_pins, 3156732ae5cSJean-Christophe PLAGNIOL-VILLARD .pin_dbg_show = at91_pin_dbg_show, 3166732ae5cSJean-Christophe PLAGNIOL-VILLARD .dt_node_to_map = at91_dt_node_to_map, 3176732ae5cSJean-Christophe PLAGNIOL-VILLARD .dt_free_map = at91_dt_free_map, 3186732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 3196732ae5cSJean-Christophe PLAGNIOL-VILLARD 3206732ae5cSJean-Christophe PLAGNIOL-VILLARD static void __iomem *pin_to_controller(struct at91_pinctrl *info, 3216732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned int bank) 3226732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3231ab36387SDavid Dueck if (!gpio_chips[bank]) 3241ab36387SDavid Dueck return NULL; 3251ab36387SDavid Dueck 3266732ae5cSJean-Christophe PLAGNIOL-VILLARD return gpio_chips[bank]->regbase; 3276732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3286732ae5cSJean-Christophe PLAGNIOL-VILLARD 3296732ae5cSJean-Christophe PLAGNIOL-VILLARD static inline int pin_to_bank(unsigned pin) 3306732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3316732ae5cSJean-Christophe PLAGNIOL-VILLARD return pin /= MAX_NB_GPIO_PER_BANK; 3326732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3336732ae5cSJean-Christophe PLAGNIOL-VILLARD 3346732ae5cSJean-Christophe PLAGNIOL-VILLARD static unsigned pin_to_mask(unsigned int pin) 3356732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3366732ae5cSJean-Christophe PLAGNIOL-VILLARD return 1 << pin; 3376732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3386732ae5cSJean-Christophe PLAGNIOL-VILLARD 3394334ac2dSMarek Roszko static unsigned two_bit_pin_value_shift_amount(unsigned int pin) 3404334ac2dSMarek Roszko { 3414334ac2dSMarek Roszko /* return the shift value for a pin for "two bit" per pin registers, 3424334ac2dSMarek Roszko * i.e. drive strength */ 3434334ac2dSMarek Roszko return 2*((pin >= MAX_NB_GPIO_PER_BANK/2) 3444334ac2dSMarek Roszko ? pin - MAX_NB_GPIO_PER_BANK/2 : pin); 3454334ac2dSMarek Roszko } 3464334ac2dSMarek Roszko 3474334ac2dSMarek Roszko static unsigned sama5d3_get_drive_register(unsigned int pin) 3484334ac2dSMarek Roszko { 3494334ac2dSMarek Roszko /* drive strength is split between two registers 3504334ac2dSMarek Roszko * with two bits per pin */ 3514334ac2dSMarek Roszko return (pin >= MAX_NB_GPIO_PER_BANK/2) 3524334ac2dSMarek Roszko ? SAMA5D3_PIO_DRIVER2 : SAMA5D3_PIO_DRIVER1; 3534334ac2dSMarek Roszko } 3544334ac2dSMarek Roszko 3554334ac2dSMarek Roszko static unsigned at91sam9x5_get_drive_register(unsigned int pin) 3564334ac2dSMarek Roszko { 3574334ac2dSMarek Roszko /* drive strength is split between two registers 3584334ac2dSMarek Roszko * with two bits per pin */ 3594334ac2dSMarek Roszko return (pin >= MAX_NB_GPIO_PER_BANK/2) 3604334ac2dSMarek Roszko ? AT91SAM9X5_PIO_DRIVER2 : AT91SAM9X5_PIO_DRIVER1; 3614334ac2dSMarek Roszko } 3624334ac2dSMarek Roszko 3636732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask) 3646732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3656732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_IDR); 3666732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3676732ae5cSJean-Christophe PLAGNIOL-VILLARD 3686732ae5cSJean-Christophe PLAGNIOL-VILLARD static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin) 3696732ae5cSJean-Christophe PLAGNIOL-VILLARD { 37005d3534aSBoris BREZILLON return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1); 3716732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3726732ae5cSJean-Christophe PLAGNIOL-VILLARD 3736732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on) 3746732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3753d784273SWenyou Yang if (on) 3763d784273SWenyou Yang writel_relaxed(mask, pio + PIO_PPDDR); 3773d784273SWenyou Yang 3786732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR)); 3796732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3806732ae5cSJean-Christophe PLAGNIOL-VILLARD 3816732ae5cSJean-Christophe PLAGNIOL-VILLARD static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin) 3826732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3836732ae5cSJean-Christophe PLAGNIOL-VILLARD return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1; 3846732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3856732ae5cSJean-Christophe PLAGNIOL-VILLARD 3866732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on) 3876732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3886732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR)); 3896732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3906732ae5cSJean-Christophe PLAGNIOL-VILLARD 3916732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask) 3926732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3936732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_ASR); 3946732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3956732ae5cSJean-Christophe PLAGNIOL-VILLARD 3966732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask) 3976732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3986732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_BSR); 3996732ae5cSJean-Christophe PLAGNIOL-VILLARD } 4006732ae5cSJean-Christophe PLAGNIOL-VILLARD 4016732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask) 4026732ae5cSJean-Christophe PLAGNIOL-VILLARD { 4036732ae5cSJean-Christophe PLAGNIOL-VILLARD 4046732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, 4056732ae5cSJean-Christophe PLAGNIOL-VILLARD pio + PIO_ABCDSR1); 4066732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, 4076732ae5cSJean-Christophe PLAGNIOL-VILLARD pio + PIO_ABCDSR2); 4086732ae5cSJean-Christophe PLAGNIOL-VILLARD } 4096732ae5cSJean-Christophe PLAGNIOL-VILLARD 4106732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask) 4116732ae5cSJean-Christophe PLAGNIOL-VILLARD { 4126732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, 4136732ae5cSJean-Christophe PLAGNIOL-VILLARD pio + PIO_ABCDSR1); 4146732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, 4156732ae5cSJean-Christophe PLAGNIOL-VILLARD pio + PIO_ABCDSR2); 4166732ae5cSJean-Christophe PLAGNIOL-VILLARD } 4176732ae5cSJean-Christophe PLAGNIOL-VILLARD 4186732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask) 4196732ae5cSJean-Christophe PLAGNIOL-VILLARD { 4206732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1); 4216732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); 4226732ae5cSJean-Christophe PLAGNIOL-VILLARD } 4236732ae5cSJean-Christophe PLAGNIOL-VILLARD 4246732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask) 4256732ae5cSJean-Christophe PLAGNIOL-VILLARD { 4266732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1); 4276732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); 4286732ae5cSJean-Christophe PLAGNIOL-VILLARD } 4296732ae5cSJean-Christophe PLAGNIOL-VILLARD 4306732ae5cSJean-Christophe PLAGNIOL-VILLARD static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask) 4316732ae5cSJean-Christophe PLAGNIOL-VILLARD { 4326732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned select; 4336732ae5cSJean-Christophe PLAGNIOL-VILLARD 4346732ae5cSJean-Christophe PLAGNIOL-VILLARD if (readl_relaxed(pio + PIO_PSR) & mask) 4356732ae5cSJean-Christophe PLAGNIOL-VILLARD return AT91_MUX_GPIO; 4366732ae5cSJean-Christophe PLAGNIOL-VILLARD 4376732ae5cSJean-Christophe PLAGNIOL-VILLARD select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask); 4386732ae5cSJean-Christophe PLAGNIOL-VILLARD select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1); 4396732ae5cSJean-Christophe PLAGNIOL-VILLARD 4406732ae5cSJean-Christophe PLAGNIOL-VILLARD return select + 1; 4416732ae5cSJean-Christophe PLAGNIOL-VILLARD } 4426732ae5cSJean-Christophe PLAGNIOL-VILLARD 4436732ae5cSJean-Christophe PLAGNIOL-VILLARD static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask) 4446732ae5cSJean-Christophe PLAGNIOL-VILLARD { 4456732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned select; 4466732ae5cSJean-Christophe PLAGNIOL-VILLARD 4476732ae5cSJean-Christophe PLAGNIOL-VILLARD if (readl_relaxed(pio + PIO_PSR) & mask) 4486732ae5cSJean-Christophe PLAGNIOL-VILLARD return AT91_MUX_GPIO; 4496732ae5cSJean-Christophe PLAGNIOL-VILLARD 4506732ae5cSJean-Christophe PLAGNIOL-VILLARD select = readl_relaxed(pio + PIO_ABSR) & mask; 4516732ae5cSJean-Christophe PLAGNIOL-VILLARD 4526732ae5cSJean-Christophe PLAGNIOL-VILLARD return select + 1; 4536732ae5cSJean-Christophe PLAGNIOL-VILLARD } 4546732ae5cSJean-Christophe PLAGNIOL-VILLARD 4557ebd7a3aSJean-Christophe PLAGNIOL-VILLARD static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin) 4567ebd7a3aSJean-Christophe PLAGNIOL-VILLARD { 457d480239bSBen Dooks return (readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1; 4587ebd7a3aSJean-Christophe PLAGNIOL-VILLARD } 4597ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 4607ebd7a3aSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) 4617ebd7a3aSJean-Christophe PLAGNIOL-VILLARD { 462d480239bSBen Dooks writel_relaxed(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); 4637ebd7a3aSJean-Christophe PLAGNIOL-VILLARD } 4647ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 465c8dba02eSBoris BREZILLON static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin) 466c8dba02eSBoris BREZILLON { 467d480239bSBen Dooks if ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) 468d480239bSBen Dooks return !((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1); 469c8dba02eSBoris BREZILLON 470c8dba02eSBoris BREZILLON return false; 471c8dba02eSBoris BREZILLON } 472c8dba02eSBoris BREZILLON 4737ebd7a3aSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) 4747ebd7a3aSJean-Christophe PLAGNIOL-VILLARD { 4757ebd7a3aSJean-Christophe PLAGNIOL-VILLARD if (is_on) 476d480239bSBen Dooks writel_relaxed(mask, pio + PIO_IFSCDR); 4777ebd7a3aSJean-Christophe PLAGNIOL-VILLARD at91_mux_set_deglitch(pio, mask, is_on); 4787ebd7a3aSJean-Christophe PLAGNIOL-VILLARD } 4797ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 4807ebd7a3aSJean-Christophe PLAGNIOL-VILLARD static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div) 4817ebd7a3aSJean-Christophe PLAGNIOL-VILLARD { 482d480239bSBen Dooks *div = readl_relaxed(pio + PIO_SCDR); 4837ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 484d480239bSBen Dooks return ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) && 485d480239bSBen Dooks ((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1); 4867ebd7a3aSJean-Christophe PLAGNIOL-VILLARD } 4877ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 4887ebd7a3aSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask, 4897ebd7a3aSJean-Christophe PLAGNIOL-VILLARD bool is_on, u32 div) 4907ebd7a3aSJean-Christophe PLAGNIOL-VILLARD { 4917ebd7a3aSJean-Christophe PLAGNIOL-VILLARD if (is_on) { 492d480239bSBen Dooks writel_relaxed(mask, pio + PIO_IFSCER); 493d480239bSBen Dooks writel_relaxed(div & PIO_SCDR_DIV, pio + PIO_SCDR); 494d480239bSBen Dooks writel_relaxed(mask, pio + PIO_IFER); 495c8dba02eSBoris BREZILLON } else 496d480239bSBen Dooks writel_relaxed(mask, pio + PIO_IFSCDR); 4977ebd7a3aSJean-Christophe PLAGNIOL-VILLARD } 4987ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 4997ebd7a3aSJean-Christophe PLAGNIOL-VILLARD static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin) 5007ebd7a3aSJean-Christophe PLAGNIOL-VILLARD { 501d480239bSBen Dooks return !((readl_relaxed(pio + PIO_PPDSR) >> pin) & 0x1); 5027ebd7a3aSJean-Christophe PLAGNIOL-VILLARD } 5037ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 5047ebd7a3aSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on) 5057ebd7a3aSJean-Christophe PLAGNIOL-VILLARD { 5063d784273SWenyou Yang if (is_on) 507d480239bSBen Dooks writel_relaxed(mask, pio + PIO_PUDR); 5083d784273SWenyou Yang 509d480239bSBen Dooks writel_relaxed(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR)); 5107ebd7a3aSJean-Christophe PLAGNIOL-VILLARD } 5117ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 5127ebd7a3aSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask) 5137ebd7a3aSJean-Christophe PLAGNIOL-VILLARD { 514d480239bSBen Dooks writel_relaxed(readl_relaxed(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT); 5157ebd7a3aSJean-Christophe PLAGNIOL-VILLARD } 5167ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 5177ebd7a3aSJean-Christophe PLAGNIOL-VILLARD static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin) 5187ebd7a3aSJean-Christophe PLAGNIOL-VILLARD { 519d480239bSBen Dooks return (readl_relaxed(pio + PIO_SCHMITT) >> pin) & 0x1; 5207ebd7a3aSJean-Christophe PLAGNIOL-VILLARD } 5217ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 5224334ac2dSMarek Roszko static inline u32 read_drive_strength(void __iomem *reg, unsigned pin) 5234334ac2dSMarek Roszko { 524d480239bSBen Dooks unsigned tmp = readl_relaxed(reg); 5254334ac2dSMarek Roszko 5264334ac2dSMarek Roszko tmp = tmp >> two_bit_pin_value_shift_amount(pin); 5274334ac2dSMarek Roszko 5284334ac2dSMarek Roszko return tmp & DRIVE_STRENGTH_MASK; 5294334ac2dSMarek Roszko } 5304334ac2dSMarek Roszko 5314334ac2dSMarek Roszko static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio, 5324334ac2dSMarek Roszko unsigned pin) 5334334ac2dSMarek Roszko { 5344334ac2dSMarek Roszko unsigned tmp = read_drive_strength(pio + 5354334ac2dSMarek Roszko sama5d3_get_drive_register(pin), pin); 5364334ac2dSMarek Roszko 5374334ac2dSMarek Roszko /* SAMA5 strength is 1:1 with our defines, 5384334ac2dSMarek Roszko * except 0 is equivalent to low per datasheet */ 5394334ac2dSMarek Roszko if (!tmp) 5404334ac2dSMarek Roszko tmp = DRIVE_STRENGTH_LOW; 5414334ac2dSMarek Roszko 5424334ac2dSMarek Roszko return tmp; 5434334ac2dSMarek Roszko } 5444334ac2dSMarek Roszko 5454334ac2dSMarek Roszko static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio, 5464334ac2dSMarek Roszko unsigned pin) 5474334ac2dSMarek Roszko { 5484334ac2dSMarek Roszko unsigned tmp = read_drive_strength(pio + 5494334ac2dSMarek Roszko at91sam9x5_get_drive_register(pin), pin); 5504334ac2dSMarek Roszko 5514334ac2dSMarek Roszko /* strength is inverse in SAM9x5s hardware with the pinctrl defines 5524334ac2dSMarek Roszko * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */ 5534334ac2dSMarek Roszko tmp = DRIVE_STRENGTH_HI - tmp; 5544334ac2dSMarek Roszko 5554334ac2dSMarek Roszko return tmp; 5564334ac2dSMarek Roszko } 5574334ac2dSMarek Roszko 5584334ac2dSMarek Roszko static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength) 5594334ac2dSMarek Roszko { 560d480239bSBen Dooks unsigned tmp = readl_relaxed(reg); 5614334ac2dSMarek Roszko unsigned shift = two_bit_pin_value_shift_amount(pin); 5624334ac2dSMarek Roszko 5634334ac2dSMarek Roszko tmp &= ~(DRIVE_STRENGTH_MASK << shift); 5644334ac2dSMarek Roszko tmp |= strength << shift; 5654334ac2dSMarek Roszko 566d480239bSBen Dooks writel_relaxed(tmp, reg); 5674334ac2dSMarek Roszko } 5684334ac2dSMarek Roszko 5694334ac2dSMarek Roszko static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin, 5704334ac2dSMarek Roszko u32 setting) 5714334ac2dSMarek Roszko { 5724334ac2dSMarek Roszko /* do nothing if setting is zero */ 5734334ac2dSMarek Roszko if (!setting) 5744334ac2dSMarek Roszko return; 5754334ac2dSMarek Roszko 5764334ac2dSMarek Roszko /* strength is 1 to 1 with setting for SAMA5 */ 5774334ac2dSMarek Roszko set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting); 5784334ac2dSMarek Roszko } 5794334ac2dSMarek Roszko 5804334ac2dSMarek Roszko static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin, 5814334ac2dSMarek Roszko u32 setting) 5824334ac2dSMarek Roszko { 5834334ac2dSMarek Roszko /* do nothing if setting is zero */ 5844334ac2dSMarek Roszko if (!setting) 5854334ac2dSMarek Roszko return; 5864334ac2dSMarek Roszko 5874334ac2dSMarek Roszko /* strength is inverse on SAM9x5s with our defines 5884334ac2dSMarek Roszko * 0 = hi, 1 = med, 2 = low, 3 = rsvd */ 5894334ac2dSMarek Roszko setting = DRIVE_STRENGTH_HI - setting; 5904334ac2dSMarek Roszko 5914334ac2dSMarek Roszko set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin, 5924334ac2dSMarek Roszko setting); 5934334ac2dSMarek Roszko } 5944334ac2dSMarek Roszko 5956732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct at91_pinctrl_mux_ops at91rm9200_ops = { 5966732ae5cSJean-Christophe PLAGNIOL-VILLARD .get_periph = at91_mux_get_periph, 5976732ae5cSJean-Christophe PLAGNIOL-VILLARD .mux_A_periph = at91_mux_set_A_periph, 5986732ae5cSJean-Christophe PLAGNIOL-VILLARD .mux_B_periph = at91_mux_set_B_periph, 5997ebd7a3aSJean-Christophe PLAGNIOL-VILLARD .get_deglitch = at91_mux_get_deglitch, 6007ebd7a3aSJean-Christophe PLAGNIOL-VILLARD .set_deglitch = at91_mux_set_deglitch, 6016732ae5cSJean-Christophe PLAGNIOL-VILLARD .irq_type = gpio_irq_type, 6026732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 6036732ae5cSJean-Christophe PLAGNIOL-VILLARD 6046732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct at91_pinctrl_mux_ops at91sam9x5_ops = { 6056732ae5cSJean-Christophe PLAGNIOL-VILLARD .get_periph = at91_mux_pio3_get_periph, 6066732ae5cSJean-Christophe PLAGNIOL-VILLARD .mux_A_periph = at91_mux_pio3_set_A_periph, 6076732ae5cSJean-Christophe PLAGNIOL-VILLARD .mux_B_periph = at91_mux_pio3_set_B_periph, 6086732ae5cSJean-Christophe PLAGNIOL-VILLARD .mux_C_periph = at91_mux_pio3_set_C_periph, 6096732ae5cSJean-Christophe PLAGNIOL-VILLARD .mux_D_periph = at91_mux_pio3_set_D_periph, 610c8dba02eSBoris BREZILLON .get_deglitch = at91_mux_pio3_get_deglitch, 6117ebd7a3aSJean-Christophe PLAGNIOL-VILLARD .set_deglitch = at91_mux_pio3_set_deglitch, 6127ebd7a3aSJean-Christophe PLAGNIOL-VILLARD .get_debounce = at91_mux_pio3_get_debounce, 6137ebd7a3aSJean-Christophe PLAGNIOL-VILLARD .set_debounce = at91_mux_pio3_set_debounce, 6147ebd7a3aSJean-Christophe PLAGNIOL-VILLARD .get_pulldown = at91_mux_pio3_get_pulldown, 6157ebd7a3aSJean-Christophe PLAGNIOL-VILLARD .set_pulldown = at91_mux_pio3_set_pulldown, 6167ebd7a3aSJean-Christophe PLAGNIOL-VILLARD .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig, 6177ebd7a3aSJean-Christophe PLAGNIOL-VILLARD .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig, 6184334ac2dSMarek Roszko .get_drivestrength = at91_mux_sam9x5_get_drivestrength, 6194334ac2dSMarek Roszko .set_drivestrength = at91_mux_sam9x5_set_drivestrength, 6204334ac2dSMarek Roszko .irq_type = alt_gpio_irq_type, 6214334ac2dSMarek Roszko }; 6224334ac2dSMarek Roszko 6234334ac2dSMarek Roszko static struct at91_pinctrl_mux_ops sama5d3_ops = { 6244334ac2dSMarek Roszko .get_periph = at91_mux_pio3_get_periph, 6254334ac2dSMarek Roszko .mux_A_periph = at91_mux_pio3_set_A_periph, 6264334ac2dSMarek Roszko .mux_B_periph = at91_mux_pio3_set_B_periph, 6274334ac2dSMarek Roszko .mux_C_periph = at91_mux_pio3_set_C_periph, 6284334ac2dSMarek Roszko .mux_D_periph = at91_mux_pio3_set_D_periph, 6294334ac2dSMarek Roszko .get_deglitch = at91_mux_pio3_get_deglitch, 6304334ac2dSMarek Roszko .set_deglitch = at91_mux_pio3_set_deglitch, 6314334ac2dSMarek Roszko .get_debounce = at91_mux_pio3_get_debounce, 6324334ac2dSMarek Roszko .set_debounce = at91_mux_pio3_set_debounce, 6334334ac2dSMarek Roszko .get_pulldown = at91_mux_pio3_get_pulldown, 6344334ac2dSMarek Roszko .set_pulldown = at91_mux_pio3_set_pulldown, 6354334ac2dSMarek Roszko .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig, 6364334ac2dSMarek Roszko .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig, 6374334ac2dSMarek Roszko .get_drivestrength = at91_mux_sama5d3_get_drivestrength, 6384334ac2dSMarek Roszko .set_drivestrength = at91_mux_sama5d3_set_drivestrength, 6396732ae5cSJean-Christophe PLAGNIOL-VILLARD .irq_type = alt_gpio_irq_type, 6406732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 6416732ae5cSJean-Christophe PLAGNIOL-VILLARD 6426732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin) 6436732ae5cSJean-Christophe PLAGNIOL-VILLARD { 6446732ae5cSJean-Christophe PLAGNIOL-VILLARD if (pin->mux) { 6454b6fe45aSHans Wennborg dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lx\n", 6466732ae5cSJean-Christophe PLAGNIOL-VILLARD pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf); 6476732ae5cSJean-Christophe PLAGNIOL-VILLARD } else { 6484b6fe45aSHans Wennborg dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lx\n", 6496732ae5cSJean-Christophe PLAGNIOL-VILLARD pin->bank + 'A', pin->pin, pin->conf); 6506732ae5cSJean-Christophe PLAGNIOL-VILLARD } 6516732ae5cSJean-Christophe PLAGNIOL-VILLARD } 6526732ae5cSJean-Christophe PLAGNIOL-VILLARD 6536732ae5cSJean-Christophe PLAGNIOL-VILLARD static int pin_check_config(struct at91_pinctrl *info, const char *name, 6546732ae5cSJean-Christophe PLAGNIOL-VILLARD int index, const struct at91_pmx_pin *pin) 6556732ae5cSJean-Christophe PLAGNIOL-VILLARD { 6566732ae5cSJean-Christophe PLAGNIOL-VILLARD int mux; 6576732ae5cSJean-Christophe PLAGNIOL-VILLARD 6586732ae5cSJean-Christophe PLAGNIOL-VILLARD /* check if it's a valid config */ 659a0b957f3SJean-Christophe PLAGNIOL-VILLARD if (pin->bank >= gpio_banks) { 6606732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n", 661a0b957f3SJean-Christophe PLAGNIOL-VILLARD name, index, pin->bank, gpio_banks); 6626732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 6636732ae5cSJean-Christophe PLAGNIOL-VILLARD } 6646732ae5cSJean-Christophe PLAGNIOL-VILLARD 665a0b957f3SJean-Christophe PLAGNIOL-VILLARD if (!gpio_chips[pin->bank]) { 666a0b957f3SJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "%s: pin conf %d bank_id %d not enabled\n", 667a0b957f3SJean-Christophe PLAGNIOL-VILLARD name, index, pin->bank); 668a0b957f3SJean-Christophe PLAGNIOL-VILLARD return -ENXIO; 669a0b957f3SJean-Christophe PLAGNIOL-VILLARD } 670a0b957f3SJean-Christophe PLAGNIOL-VILLARD 6716732ae5cSJean-Christophe PLAGNIOL-VILLARD if (pin->pin >= MAX_NB_GPIO_PER_BANK) { 6726732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n", 6736732ae5cSJean-Christophe PLAGNIOL-VILLARD name, index, pin->pin, MAX_NB_GPIO_PER_BANK); 6746732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 6756732ae5cSJean-Christophe PLAGNIOL-VILLARD } 6766732ae5cSJean-Christophe PLAGNIOL-VILLARD 6776732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!pin->mux) 6786732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 6796732ae5cSJean-Christophe PLAGNIOL-VILLARD 6806732ae5cSJean-Christophe PLAGNIOL-VILLARD mux = pin->mux - 1; 6816732ae5cSJean-Christophe PLAGNIOL-VILLARD 6826732ae5cSJean-Christophe PLAGNIOL-VILLARD if (mux >= info->nmux) { 6836732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n", 6846732ae5cSJean-Christophe PLAGNIOL-VILLARD name, index, mux, info->nmux); 6856732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 6866732ae5cSJean-Christophe PLAGNIOL-VILLARD } 6876732ae5cSJean-Christophe PLAGNIOL-VILLARD 6886732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) { 6896732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n", 6906732ae5cSJean-Christophe PLAGNIOL-VILLARD name, index, mux, pin->bank + 'A', pin->pin); 6916732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 6926732ae5cSJean-Christophe PLAGNIOL-VILLARD } 6936732ae5cSJean-Christophe PLAGNIOL-VILLARD 6946732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 6956732ae5cSJean-Christophe PLAGNIOL-VILLARD } 6966732ae5cSJean-Christophe PLAGNIOL-VILLARD 6976732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask) 6986732ae5cSJean-Christophe PLAGNIOL-VILLARD { 6996732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_PDR); 7006732ae5cSJean-Christophe PLAGNIOL-VILLARD } 7016732ae5cSJean-Christophe PLAGNIOL-VILLARD 7026732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input) 7036732ae5cSJean-Christophe PLAGNIOL-VILLARD { 7046732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_PER); 7056732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER)); 7066732ae5cSJean-Christophe PLAGNIOL-VILLARD } 7076732ae5cSJean-Christophe PLAGNIOL-VILLARD 70803e9f0caSLinus Walleij static int at91_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 7096732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned group) 7106732ae5cSJean-Christophe PLAGNIOL-VILLARD { 7116732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 7126732ae5cSJean-Christophe PLAGNIOL-VILLARD const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf; 7136732ae5cSJean-Christophe PLAGNIOL-VILLARD const struct at91_pmx_pin *pin; 7146732ae5cSJean-Christophe PLAGNIOL-VILLARD uint32_t npins = info->groups[group].npins; 7156732ae5cSJean-Christophe PLAGNIOL-VILLARD int i, ret; 7166732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask; 7176732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio; 7186732ae5cSJean-Christophe PLAGNIOL-VILLARD 7196732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(info->dev, "enable function %s group %s\n", 7206732ae5cSJean-Christophe PLAGNIOL-VILLARD info->functions[selector].name, info->groups[group].name); 7216732ae5cSJean-Christophe PLAGNIOL-VILLARD 7226732ae5cSJean-Christophe PLAGNIOL-VILLARD /* first check that all the pins of the group are valid with a valid 72361e310a1SAlexandre Belloni * parameter */ 7246732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < npins; i++) { 7256732ae5cSJean-Christophe PLAGNIOL-VILLARD pin = &pins_conf[i]; 7266732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = pin_check_config(info, info->groups[group].name, i, pin); 7276732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ret) 7286732ae5cSJean-Christophe PLAGNIOL-VILLARD return ret; 7296732ae5cSJean-Christophe PLAGNIOL-VILLARD } 7306732ae5cSJean-Christophe PLAGNIOL-VILLARD 7316732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < npins; i++) { 7326732ae5cSJean-Christophe PLAGNIOL-VILLARD pin = &pins_conf[i]; 7336732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_pin_dbg(info->dev, pin); 7346732ae5cSJean-Christophe PLAGNIOL-VILLARD pio = pin_to_controller(info, pin->bank); 7351ab36387SDavid Dueck 7361ab36387SDavid Dueck if (!pio) 7371ab36387SDavid Dueck continue; 7381ab36387SDavid Dueck 7396732ae5cSJean-Christophe PLAGNIOL-VILLARD mask = pin_to_mask(pin->pin); 7406732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_mux_disable_interrupt(pio, mask); 7416732ae5cSJean-Christophe PLAGNIOL-VILLARD switch (pin->mux) { 7426732ae5cSJean-Christophe PLAGNIOL-VILLARD case AT91_MUX_GPIO: 7436732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_mux_gpio_enable(pio, mask, 1); 7446732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 7456732ae5cSJean-Christophe PLAGNIOL-VILLARD case AT91_MUX_PERIPH_A: 7466732ae5cSJean-Christophe PLAGNIOL-VILLARD info->ops->mux_A_periph(pio, mask); 7476732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 7486732ae5cSJean-Christophe PLAGNIOL-VILLARD case AT91_MUX_PERIPH_B: 7496732ae5cSJean-Christophe PLAGNIOL-VILLARD info->ops->mux_B_periph(pio, mask); 7506732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 7516732ae5cSJean-Christophe PLAGNIOL-VILLARD case AT91_MUX_PERIPH_C: 7526732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!info->ops->mux_C_periph) 7536732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 7546732ae5cSJean-Christophe PLAGNIOL-VILLARD info->ops->mux_C_periph(pio, mask); 7556732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 7566732ae5cSJean-Christophe PLAGNIOL-VILLARD case AT91_MUX_PERIPH_D: 7576732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!info->ops->mux_D_periph) 7586732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 7596732ae5cSJean-Christophe PLAGNIOL-VILLARD info->ops->mux_D_periph(pio, mask); 7606732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 7616732ae5cSJean-Christophe PLAGNIOL-VILLARD } 7626732ae5cSJean-Christophe PLAGNIOL-VILLARD if (pin->mux) 7636732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_mux_gpio_disable(pio, mask); 7646732ae5cSJean-Christophe PLAGNIOL-VILLARD } 7656732ae5cSJean-Christophe PLAGNIOL-VILLARD 7666732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 7676732ae5cSJean-Christophe PLAGNIOL-VILLARD } 7686732ae5cSJean-Christophe PLAGNIOL-VILLARD 7696732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 7706732ae5cSJean-Christophe PLAGNIOL-VILLARD { 7716732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 7726732ae5cSJean-Christophe PLAGNIOL-VILLARD 7736732ae5cSJean-Christophe PLAGNIOL-VILLARD return info->nfunctions; 7746732ae5cSJean-Christophe PLAGNIOL-VILLARD } 7756732ae5cSJean-Christophe PLAGNIOL-VILLARD 7766732ae5cSJean-Christophe PLAGNIOL-VILLARD static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev, 7776732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned selector) 7786732ae5cSJean-Christophe PLAGNIOL-VILLARD { 7796732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 7806732ae5cSJean-Christophe PLAGNIOL-VILLARD 7816732ae5cSJean-Christophe PLAGNIOL-VILLARD return info->functions[selector].name; 7826732ae5cSJean-Christophe PLAGNIOL-VILLARD } 7836732ae5cSJean-Christophe PLAGNIOL-VILLARD 7846732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, 7856732ae5cSJean-Christophe PLAGNIOL-VILLARD const char * const **groups, 7866732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned * const num_groups) 7876732ae5cSJean-Christophe PLAGNIOL-VILLARD { 7886732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 7896732ae5cSJean-Christophe PLAGNIOL-VILLARD 7906732ae5cSJean-Christophe PLAGNIOL-VILLARD *groups = info->functions[selector].groups; 7916732ae5cSJean-Christophe PLAGNIOL-VILLARD *num_groups = info->functions[selector].ngroups; 7926732ae5cSJean-Christophe PLAGNIOL-VILLARD 7936732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 7946732ae5cSJean-Christophe PLAGNIOL-VILLARD } 7956732ae5cSJean-Christophe PLAGNIOL-VILLARD 796f6f94f66SAxel Lin static int at91_gpio_request_enable(struct pinctrl_dev *pctldev, 7976732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_gpio_range *range, 7986732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned offset) 7996732ae5cSJean-Christophe PLAGNIOL-VILLARD { 8006732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 8016732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_chip; 8026732ae5cSJean-Christophe PLAGNIOL-VILLARD struct gpio_chip *chip; 8036732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask; 8046732ae5cSJean-Christophe PLAGNIOL-VILLARD 8056732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!range) { 8066732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(npct->dev, "invalid range\n"); 8076732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 8086732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8096732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!range->gc) { 8106732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(npct->dev, "missing GPIO chip in range\n"); 8116732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 8126732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8136732ae5cSJean-Christophe PLAGNIOL-VILLARD chip = range->gc; 8146732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_chip = container_of(chip, struct at91_gpio_chip, chip); 8156732ae5cSJean-Christophe PLAGNIOL-VILLARD 8166732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); 8176732ae5cSJean-Christophe PLAGNIOL-VILLARD 8186732ae5cSJean-Christophe PLAGNIOL-VILLARD mask = 1 << (offset - chip->base); 8196732ae5cSJean-Christophe PLAGNIOL-VILLARD 8206732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n", 8216732ae5cSJean-Christophe PLAGNIOL-VILLARD offset, 'A' + range->id, offset - chip->base, mask); 8226732ae5cSJean-Christophe PLAGNIOL-VILLARD 8236732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, at91_chip->regbase + PIO_PER); 8246732ae5cSJean-Christophe PLAGNIOL-VILLARD 8256732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 8266732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8276732ae5cSJean-Christophe PLAGNIOL-VILLARD 828f6f94f66SAxel Lin static void at91_gpio_disable_free(struct pinctrl_dev *pctldev, 8296732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_gpio_range *range, 8306732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned offset) 8316732ae5cSJean-Christophe PLAGNIOL-VILLARD { 8326732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 8336732ae5cSJean-Christophe PLAGNIOL-VILLARD 8346732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); 8356732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Set the pin to some default state, GPIO is usually default */ 8366732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8376732ae5cSJean-Christophe PLAGNIOL-VILLARD 838022ab148SLaurent Pinchart static const struct pinmux_ops at91_pmx_ops = { 8396732ae5cSJean-Christophe PLAGNIOL-VILLARD .get_functions_count = at91_pmx_get_funcs_count, 8406732ae5cSJean-Christophe PLAGNIOL-VILLARD .get_function_name = at91_pmx_get_func_name, 8416732ae5cSJean-Christophe PLAGNIOL-VILLARD .get_function_groups = at91_pmx_get_groups, 84203e9f0caSLinus Walleij .set_mux = at91_pmx_set, 8436732ae5cSJean-Christophe PLAGNIOL-VILLARD .gpio_request_enable = at91_gpio_request_enable, 8446732ae5cSJean-Christophe PLAGNIOL-VILLARD .gpio_disable_free = at91_gpio_disable_free, 8456732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 8466732ae5cSJean-Christophe PLAGNIOL-VILLARD 8476732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_pinconf_get(struct pinctrl_dev *pctldev, 8486732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned pin_id, unsigned long *config) 8496732ae5cSJean-Christophe PLAGNIOL-VILLARD { 8506732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 8516732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio; 8526732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned pin; 8537ebd7a3aSJean-Christophe PLAGNIOL-VILLARD int div; 8546732ae5cSJean-Christophe PLAGNIOL-VILLARD 8551292e693SAlexandre Belloni *config = 0; 8561292e693SAlexandre Belloni dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id); 8576732ae5cSJean-Christophe PLAGNIOL-VILLARD pio = pin_to_controller(info, pin_to_bank(pin_id)); 8581ab36387SDavid Dueck 8591ab36387SDavid Dueck if (!pio) 8601ab36387SDavid Dueck return -EINVAL; 8611ab36387SDavid Dueck 8626732ae5cSJean-Christophe PLAGNIOL-VILLARD pin = pin_id % MAX_NB_GPIO_PER_BANK; 8636732ae5cSJean-Christophe PLAGNIOL-VILLARD 8646732ae5cSJean-Christophe PLAGNIOL-VILLARD if (at91_mux_get_multidrive(pio, pin)) 8656732ae5cSJean-Christophe PLAGNIOL-VILLARD *config |= MULTI_DRIVE; 8666732ae5cSJean-Christophe PLAGNIOL-VILLARD 8676732ae5cSJean-Christophe PLAGNIOL-VILLARD if (at91_mux_get_pullup(pio, pin)) 8686732ae5cSJean-Christophe PLAGNIOL-VILLARD *config |= PULL_UP; 8696732ae5cSJean-Christophe PLAGNIOL-VILLARD 8707ebd7a3aSJean-Christophe PLAGNIOL-VILLARD if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin)) 8717ebd7a3aSJean-Christophe PLAGNIOL-VILLARD *config |= DEGLITCH; 8727ebd7a3aSJean-Christophe PLAGNIOL-VILLARD if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div)) 8737ebd7a3aSJean-Christophe PLAGNIOL-VILLARD *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT); 8747ebd7a3aSJean-Christophe PLAGNIOL-VILLARD if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin)) 8757ebd7a3aSJean-Christophe PLAGNIOL-VILLARD *config |= PULL_DOWN; 8767ebd7a3aSJean-Christophe PLAGNIOL-VILLARD if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin)) 8777ebd7a3aSJean-Christophe PLAGNIOL-VILLARD *config |= DIS_SCHMIT; 8784334ac2dSMarek Roszko if (info->ops->get_drivestrength) 8794334ac2dSMarek Roszko *config |= (info->ops->get_drivestrength(pio, pin) 8804334ac2dSMarek Roszko << DRIVE_STRENGTH_SHIFT); 8817ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 8826732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 8836732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8846732ae5cSJean-Christophe PLAGNIOL-VILLARD 8856732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_pinconf_set(struct pinctrl_dev *pctldev, 88603b054e9SSherman Yin unsigned pin_id, unsigned long *configs, 88703b054e9SSherman Yin unsigned num_configs) 8886732ae5cSJean-Christophe PLAGNIOL-VILLARD { 8896732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 8906732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask; 8916732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio; 89203b054e9SSherman Yin int i; 89303b054e9SSherman Yin unsigned long config; 8944334ac2dSMarek Roszko unsigned pin; 8956732ae5cSJean-Christophe PLAGNIOL-VILLARD 89603b054e9SSherman Yin for (i = 0; i < num_configs; i++) { 89703b054e9SSherman Yin config = configs[i]; 89803b054e9SSherman Yin 89903b054e9SSherman Yin dev_dbg(info->dev, 90003b054e9SSherman Yin "%s:%d, pin_id=%d, config=0x%lx", 90103b054e9SSherman Yin __func__, __LINE__, pin_id, config); 9026732ae5cSJean-Christophe PLAGNIOL-VILLARD pio = pin_to_controller(info, pin_to_bank(pin_id)); 9031ab36387SDavid Dueck 9041ab36387SDavid Dueck if (!pio) 9051ab36387SDavid Dueck return -EINVAL; 9061ab36387SDavid Dueck 9074334ac2dSMarek Roszko pin = pin_id % MAX_NB_GPIO_PER_BANK; 9084334ac2dSMarek Roszko mask = pin_to_mask(pin); 9096732ae5cSJean-Christophe PLAGNIOL-VILLARD 9107ebd7a3aSJean-Christophe PLAGNIOL-VILLARD if (config & PULL_UP && config & PULL_DOWN) 9117ebd7a3aSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 9127ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 9136732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_mux_set_pullup(pio, mask, config & PULL_UP); 9146732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE); 9157ebd7a3aSJean-Christophe PLAGNIOL-VILLARD if (info->ops->set_deglitch) 9167ebd7a3aSJean-Christophe PLAGNIOL-VILLARD info->ops->set_deglitch(pio, mask, config & DEGLITCH); 9177ebd7a3aSJean-Christophe PLAGNIOL-VILLARD if (info->ops->set_debounce) 9187ebd7a3aSJean-Christophe PLAGNIOL-VILLARD info->ops->set_debounce(pio, mask, config & DEBOUNCE, 9197ebd7a3aSJean-Christophe PLAGNIOL-VILLARD (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT); 9207ebd7a3aSJean-Christophe PLAGNIOL-VILLARD if (info->ops->set_pulldown) 9217ebd7a3aSJean-Christophe PLAGNIOL-VILLARD info->ops->set_pulldown(pio, mask, config & PULL_DOWN); 9227ebd7a3aSJean-Christophe PLAGNIOL-VILLARD if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT) 9237ebd7a3aSJean-Christophe PLAGNIOL-VILLARD info->ops->disable_schmitt_trig(pio, mask); 9244334ac2dSMarek Roszko if (info->ops->set_drivestrength) 9254334ac2dSMarek Roszko info->ops->set_drivestrength(pio, pin, 9264334ac2dSMarek Roszko (config & DRIVE_STRENGTH) 9274334ac2dSMarek Roszko >> DRIVE_STRENGTH_SHIFT); 9287ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 92903b054e9SSherman Yin } /* for each config */ 93003b054e9SSherman Yin 9316732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 9326732ae5cSJean-Christophe PLAGNIOL-VILLARD } 9336732ae5cSJean-Christophe PLAGNIOL-VILLARD 9344d9b8a8eSAlexandre Belloni #define DBG_SHOW_FLAG(flag) do { \ 9354d9b8a8eSAlexandre Belloni if (config & flag) { \ 9364d9b8a8eSAlexandre Belloni if (num_conf) \ 9374d9b8a8eSAlexandre Belloni seq_puts(s, "|"); \ 9384d9b8a8eSAlexandre Belloni seq_puts(s, #flag); \ 9394d9b8a8eSAlexandre Belloni num_conf++; \ 9404d9b8a8eSAlexandre Belloni } \ 9414d9b8a8eSAlexandre Belloni } while (0) 9424d9b8a8eSAlexandre Belloni 9434334ac2dSMarek Roszko #define DBG_SHOW_FLAG_MASKED(mask,flag) do { \ 9444334ac2dSMarek Roszko if ((config & mask) == flag) { \ 9454334ac2dSMarek Roszko if (num_conf) \ 9464334ac2dSMarek Roszko seq_puts(s, "|"); \ 9474334ac2dSMarek Roszko seq_puts(s, #flag); \ 9484334ac2dSMarek Roszko num_conf++; \ 9494334ac2dSMarek Roszko } \ 9504334ac2dSMarek Roszko } while (0) 9514334ac2dSMarek Roszko 9526732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev, 9536732ae5cSJean-Christophe PLAGNIOL-VILLARD struct seq_file *s, unsigned pin_id) 9546732ae5cSJean-Christophe PLAGNIOL-VILLARD { 9554d9b8a8eSAlexandre Belloni unsigned long config; 956445d2026SRickard Strandqvist int val, num_conf = 0; 9576732ae5cSJean-Christophe PLAGNIOL-VILLARD 958445d2026SRickard Strandqvist at91_pinconf_get(pctldev, pin_id, &config); 9594d9b8a8eSAlexandre Belloni 9604d9b8a8eSAlexandre Belloni DBG_SHOW_FLAG(MULTI_DRIVE); 9614d9b8a8eSAlexandre Belloni DBG_SHOW_FLAG(PULL_UP); 9624d9b8a8eSAlexandre Belloni DBG_SHOW_FLAG(PULL_DOWN); 9634d9b8a8eSAlexandre Belloni DBG_SHOW_FLAG(DIS_SCHMIT); 9644d9b8a8eSAlexandre Belloni DBG_SHOW_FLAG(DEGLITCH); 9654334ac2dSMarek Roszko DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW); 9664334ac2dSMarek Roszko DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED); 9674334ac2dSMarek Roszko DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI); 9684d9b8a8eSAlexandre Belloni DBG_SHOW_FLAG(DEBOUNCE); 9694d9b8a8eSAlexandre Belloni if (config & DEBOUNCE) { 9704d9b8a8eSAlexandre Belloni val = config >> DEBOUNCE_VAL_SHIFT; 9714d9b8a8eSAlexandre Belloni seq_printf(s, "(%d)", val); 9724d9b8a8eSAlexandre Belloni } 9734d9b8a8eSAlexandre Belloni 9744d9b8a8eSAlexandre Belloni return; 9756732ae5cSJean-Christophe PLAGNIOL-VILLARD } 9766732ae5cSJean-Christophe PLAGNIOL-VILLARD 9776732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 9786732ae5cSJean-Christophe PLAGNIOL-VILLARD struct seq_file *s, unsigned group) 9796732ae5cSJean-Christophe PLAGNIOL-VILLARD { 9806732ae5cSJean-Christophe PLAGNIOL-VILLARD } 9816732ae5cSJean-Christophe PLAGNIOL-VILLARD 982022ab148SLaurent Pinchart static const struct pinconf_ops at91_pinconf_ops = { 9836732ae5cSJean-Christophe PLAGNIOL-VILLARD .pin_config_get = at91_pinconf_get, 9846732ae5cSJean-Christophe PLAGNIOL-VILLARD .pin_config_set = at91_pinconf_set, 9856732ae5cSJean-Christophe PLAGNIOL-VILLARD .pin_config_dbg_show = at91_pinconf_dbg_show, 9866732ae5cSJean-Christophe PLAGNIOL-VILLARD .pin_config_group_dbg_show = at91_pinconf_group_dbg_show, 9876732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 9886732ae5cSJean-Christophe PLAGNIOL-VILLARD 9896732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct pinctrl_desc at91_pinctrl_desc = { 9906732ae5cSJean-Christophe PLAGNIOL-VILLARD .pctlops = &at91_pctrl_ops, 9916732ae5cSJean-Christophe PLAGNIOL-VILLARD .pmxops = &at91_pmx_ops, 9926732ae5cSJean-Christophe PLAGNIOL-VILLARD .confops = &at91_pinconf_ops, 9936732ae5cSJean-Christophe PLAGNIOL-VILLARD .owner = THIS_MODULE, 9946732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 9956732ae5cSJean-Christophe PLAGNIOL-VILLARD 9966732ae5cSJean-Christophe PLAGNIOL-VILLARD static const char *gpio_compat = "atmel,at91rm9200-gpio"; 9976732ae5cSJean-Christophe PLAGNIOL-VILLARD 998150632b0SGreg Kroah-Hartman static void at91_pinctrl_child_count(struct at91_pinctrl *info, 9996732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *np) 10006732ae5cSJean-Christophe PLAGNIOL-VILLARD { 10016732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *child; 10026732ae5cSJean-Christophe PLAGNIOL-VILLARD 10036732ae5cSJean-Christophe PLAGNIOL-VILLARD for_each_child_of_node(np, child) { 10046732ae5cSJean-Christophe PLAGNIOL-VILLARD if (of_device_is_compatible(child, gpio_compat)) { 1005a0b957f3SJean-Christophe PLAGNIOL-VILLARD if (of_device_is_available(child)) 1006a0b957f3SJean-Christophe PLAGNIOL-VILLARD info->nactive_banks++; 10076732ae5cSJean-Christophe PLAGNIOL-VILLARD } else { 10086732ae5cSJean-Christophe PLAGNIOL-VILLARD info->nfunctions++; 10096732ae5cSJean-Christophe PLAGNIOL-VILLARD info->ngroups += of_get_child_count(child); 10106732ae5cSJean-Christophe PLAGNIOL-VILLARD } 10116732ae5cSJean-Christophe PLAGNIOL-VILLARD } 10126732ae5cSJean-Christophe PLAGNIOL-VILLARD } 10136732ae5cSJean-Christophe PLAGNIOL-VILLARD 1014150632b0SGreg Kroah-Hartman static int at91_pinctrl_mux_mask(struct at91_pinctrl *info, 10156732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *np) 10166732ae5cSJean-Christophe PLAGNIOL-VILLARD { 10176732ae5cSJean-Christophe PLAGNIOL-VILLARD int ret = 0; 10186732ae5cSJean-Christophe PLAGNIOL-VILLARD int size; 10191164d73aSSachin Kamat const __be32 *list; 10206732ae5cSJean-Christophe PLAGNIOL-VILLARD 10216732ae5cSJean-Christophe PLAGNIOL-VILLARD list = of_get_property(np, "atmel,mux-mask", &size); 10226732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!list) { 10236732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "can not read the mux-mask of %d\n", size); 10246732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 10256732ae5cSJean-Christophe PLAGNIOL-VILLARD } 10266732ae5cSJean-Christophe PLAGNIOL-VILLARD 10276732ae5cSJean-Christophe PLAGNIOL-VILLARD size /= sizeof(*list); 1028a0b957f3SJean-Christophe PLAGNIOL-VILLARD if (!size || size % gpio_banks) { 1029a0b957f3SJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "wrong mux mask array should be by %d\n", gpio_banks); 10306732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 10316732ae5cSJean-Christophe PLAGNIOL-VILLARD } 1032a0b957f3SJean-Christophe PLAGNIOL-VILLARD info->nmux = size / gpio_banks; 10336732ae5cSJean-Christophe PLAGNIOL-VILLARD 10346732ae5cSJean-Christophe PLAGNIOL-VILLARD info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL); 10356732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!info->mux_mask) { 10366732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "could not alloc mux_mask\n"); 10376732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENOMEM; 10386732ae5cSJean-Christophe PLAGNIOL-VILLARD } 10396732ae5cSJean-Christophe PLAGNIOL-VILLARD 10406732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = of_property_read_u32_array(np, "atmel,mux-mask", 10416732ae5cSJean-Christophe PLAGNIOL-VILLARD info->mux_mask, size); 10426732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ret) 10436732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "can not read the mux-mask of %d\n", size); 10446732ae5cSJean-Christophe PLAGNIOL-VILLARD return ret; 10456732ae5cSJean-Christophe PLAGNIOL-VILLARD } 10466732ae5cSJean-Christophe PLAGNIOL-VILLARD 1047150632b0SGreg Kroah-Hartman static int at91_pinctrl_parse_groups(struct device_node *np, 10486732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pin_group *grp, 1049150632b0SGreg Kroah-Hartman struct at91_pinctrl *info, u32 index) 10506732ae5cSJean-Christophe PLAGNIOL-VILLARD { 10516732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pmx_pin *pin; 10526732ae5cSJean-Christophe PLAGNIOL-VILLARD int size; 10531164d73aSSachin Kamat const __be32 *list; 10546732ae5cSJean-Christophe PLAGNIOL-VILLARD int i, j; 10556732ae5cSJean-Christophe PLAGNIOL-VILLARD 10566732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(info->dev, "group(%d): %s\n", index, np->name); 10576732ae5cSJean-Christophe PLAGNIOL-VILLARD 10586732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Initialise group */ 10596732ae5cSJean-Christophe PLAGNIOL-VILLARD grp->name = np->name; 10606732ae5cSJean-Christophe PLAGNIOL-VILLARD 10616732ae5cSJean-Christophe PLAGNIOL-VILLARD /* 10626732ae5cSJean-Christophe PLAGNIOL-VILLARD * the binding format is atmel,pins = <bank pin mux CONFIG ...>, 10636732ae5cSJean-Christophe PLAGNIOL-VILLARD * do sanity check and calculate pins number 10646732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 10656732ae5cSJean-Christophe PLAGNIOL-VILLARD list = of_get_property(np, "atmel,pins", &size); 10666732ae5cSJean-Christophe PLAGNIOL-VILLARD /* we do not check return since it's safe node passed down */ 10676732ae5cSJean-Christophe PLAGNIOL-VILLARD size /= sizeof(*list); 10686732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!size || size % 4) { 10696732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); 10706732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 10716732ae5cSJean-Christophe PLAGNIOL-VILLARD } 10726732ae5cSJean-Christophe PLAGNIOL-VILLARD 10736732ae5cSJean-Christophe PLAGNIOL-VILLARD grp->npins = size / 4; 10746732ae5cSJean-Christophe PLAGNIOL-VILLARD pin = grp->pins_conf = devm_kzalloc(info->dev, grp->npins * sizeof(struct at91_pmx_pin), 10756732ae5cSJean-Christophe PLAGNIOL-VILLARD GFP_KERNEL); 10766732ae5cSJean-Christophe PLAGNIOL-VILLARD grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), 10776732ae5cSJean-Christophe PLAGNIOL-VILLARD GFP_KERNEL); 10786732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!grp->pins_conf || !grp->pins) 10796732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENOMEM; 10806732ae5cSJean-Christophe PLAGNIOL-VILLARD 10816732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0, j = 0; i < size; i += 4, j++) { 10826732ae5cSJean-Christophe PLAGNIOL-VILLARD pin->bank = be32_to_cpu(*list++); 10836732ae5cSJean-Christophe PLAGNIOL-VILLARD pin->pin = be32_to_cpu(*list++); 10846732ae5cSJean-Christophe PLAGNIOL-VILLARD grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin; 10856732ae5cSJean-Christophe PLAGNIOL-VILLARD pin->mux = be32_to_cpu(*list++); 10866732ae5cSJean-Christophe PLAGNIOL-VILLARD pin->conf = be32_to_cpu(*list++); 10876732ae5cSJean-Christophe PLAGNIOL-VILLARD 10886732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_pin_dbg(info->dev, pin); 10896732ae5cSJean-Christophe PLAGNIOL-VILLARD pin++; 10906732ae5cSJean-Christophe PLAGNIOL-VILLARD } 10916732ae5cSJean-Christophe PLAGNIOL-VILLARD 10926732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 10936732ae5cSJean-Christophe PLAGNIOL-VILLARD } 10946732ae5cSJean-Christophe PLAGNIOL-VILLARD 1095150632b0SGreg Kroah-Hartman static int at91_pinctrl_parse_functions(struct device_node *np, 10966732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info, u32 index) 10976732ae5cSJean-Christophe PLAGNIOL-VILLARD { 10986732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *child; 10996732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pmx_func *func; 11006732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pin_group *grp; 11016732ae5cSJean-Christophe PLAGNIOL-VILLARD int ret; 11026732ae5cSJean-Christophe PLAGNIOL-VILLARD static u32 grp_index; 11036732ae5cSJean-Christophe PLAGNIOL-VILLARD u32 i = 0; 11046732ae5cSJean-Christophe PLAGNIOL-VILLARD 11056732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); 11066732ae5cSJean-Christophe PLAGNIOL-VILLARD 11076732ae5cSJean-Christophe PLAGNIOL-VILLARD func = &info->functions[index]; 11086732ae5cSJean-Christophe PLAGNIOL-VILLARD 11096732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Initialise function */ 11106732ae5cSJean-Christophe PLAGNIOL-VILLARD func->name = np->name; 11116732ae5cSJean-Christophe PLAGNIOL-VILLARD func->ngroups = of_get_child_count(np); 1112ca7162adSRickard Strandqvist if (func->ngroups == 0) { 11136732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "no groups defined\n"); 11146732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 11156732ae5cSJean-Christophe PLAGNIOL-VILLARD } 11166732ae5cSJean-Christophe PLAGNIOL-VILLARD func->groups = devm_kzalloc(info->dev, 11176732ae5cSJean-Christophe PLAGNIOL-VILLARD func->ngroups * sizeof(char *), GFP_KERNEL); 11186732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!func->groups) 11196732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENOMEM; 11206732ae5cSJean-Christophe PLAGNIOL-VILLARD 11216732ae5cSJean-Christophe PLAGNIOL-VILLARD for_each_child_of_node(np, child) { 11226732ae5cSJean-Christophe PLAGNIOL-VILLARD func->groups[i] = child->name; 11236732ae5cSJean-Christophe PLAGNIOL-VILLARD grp = &info->groups[grp_index++]; 11246732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = at91_pinctrl_parse_groups(child, grp, info, i++); 11256732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ret) 11266732ae5cSJean-Christophe PLAGNIOL-VILLARD return ret; 11276732ae5cSJean-Christophe PLAGNIOL-VILLARD } 11286732ae5cSJean-Christophe PLAGNIOL-VILLARD 11296732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 11306732ae5cSJean-Christophe PLAGNIOL-VILLARD } 11316732ae5cSJean-Christophe PLAGNIOL-VILLARD 1132baa9946eSFabian Frederick static const struct of_device_id at91_pinctrl_of_match[] = { 11334334ac2dSMarek Roszko { .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops }, 11346732ae5cSJean-Christophe PLAGNIOL-VILLARD { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops }, 11356732ae5cSJean-Christophe PLAGNIOL-VILLARD { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops }, 11366732ae5cSJean-Christophe PLAGNIOL-VILLARD { /* sentinel */ } 11376732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 11386732ae5cSJean-Christophe PLAGNIOL-VILLARD 1139150632b0SGreg Kroah-Hartman static int at91_pinctrl_probe_dt(struct platform_device *pdev, 11406732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info) 11416732ae5cSJean-Christophe PLAGNIOL-VILLARD { 11426732ae5cSJean-Christophe PLAGNIOL-VILLARD int ret = 0; 11436732ae5cSJean-Christophe PLAGNIOL-VILLARD int i, j; 11446732ae5cSJean-Christophe PLAGNIOL-VILLARD uint32_t *tmp; 11456732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *np = pdev->dev.of_node; 11466732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *child; 11476732ae5cSJean-Christophe PLAGNIOL-VILLARD 11486732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!np) 11496732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENODEV; 11506732ae5cSJean-Christophe PLAGNIOL-VILLARD 11516732ae5cSJean-Christophe PLAGNIOL-VILLARD info->dev = &pdev->dev; 1152dffa9123SJean-Christophe PLAGNIOL-VILLARD info->ops = (struct at91_pinctrl_mux_ops *) 11536732ae5cSJean-Christophe PLAGNIOL-VILLARD of_match_device(at91_pinctrl_of_match, &pdev->dev)->data; 11546732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_pinctrl_child_count(info, np); 11556732ae5cSJean-Christophe PLAGNIOL-VILLARD 1156a0b957f3SJean-Christophe PLAGNIOL-VILLARD if (gpio_banks < 1) { 11576732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n"); 11586732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 11596732ae5cSJean-Christophe PLAGNIOL-VILLARD } 11606732ae5cSJean-Christophe PLAGNIOL-VILLARD 11616732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = at91_pinctrl_mux_mask(info, np); 11626732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ret) 11636732ae5cSJean-Christophe PLAGNIOL-VILLARD return ret; 11646732ae5cSJean-Christophe PLAGNIOL-VILLARD 11656732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux); 11666732ae5cSJean-Christophe PLAGNIOL-VILLARD 11676732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(&pdev->dev, "mux-mask\n"); 11686732ae5cSJean-Christophe PLAGNIOL-VILLARD tmp = info->mux_mask; 1169a0b957f3SJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < gpio_banks; i++) { 11706732ae5cSJean-Christophe PLAGNIOL-VILLARD for (j = 0; j < info->nmux; j++, tmp++) { 11716732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]); 11726732ae5cSJean-Christophe PLAGNIOL-VILLARD } 11736732ae5cSJean-Christophe PLAGNIOL-VILLARD } 11746732ae5cSJean-Christophe PLAGNIOL-VILLARD 11756732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 11766732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 11776732ae5cSJean-Christophe PLAGNIOL-VILLARD info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * sizeof(struct at91_pmx_func), 11786732ae5cSJean-Christophe PLAGNIOL-VILLARD GFP_KERNEL); 11796732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!info->functions) 11806732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENOMEM; 11816732ae5cSJean-Christophe PLAGNIOL-VILLARD 11826732ae5cSJean-Christophe PLAGNIOL-VILLARD info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct at91_pin_group), 11836732ae5cSJean-Christophe PLAGNIOL-VILLARD GFP_KERNEL); 11846732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!info->groups) 11856732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENOMEM; 11866732ae5cSJean-Christophe PLAGNIOL-VILLARD 1187a0b957f3SJean-Christophe PLAGNIOL-VILLARD dev_dbg(&pdev->dev, "nbanks = %d\n", gpio_banks); 11886732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 11896732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 11906732ae5cSJean-Christophe PLAGNIOL-VILLARD 11916732ae5cSJean-Christophe PLAGNIOL-VILLARD i = 0; 11926732ae5cSJean-Christophe PLAGNIOL-VILLARD 11936732ae5cSJean-Christophe PLAGNIOL-VILLARD for_each_child_of_node(np, child) { 11946732ae5cSJean-Christophe PLAGNIOL-VILLARD if (of_device_is_compatible(child, gpio_compat)) 11956732ae5cSJean-Christophe PLAGNIOL-VILLARD continue; 11966732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = at91_pinctrl_parse_functions(child, info, i++); 11976732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ret) { 11986732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(&pdev->dev, "failed to parse function\n"); 11996732ae5cSJean-Christophe PLAGNIOL-VILLARD return ret; 12006732ae5cSJean-Christophe PLAGNIOL-VILLARD } 12016732ae5cSJean-Christophe PLAGNIOL-VILLARD } 12026732ae5cSJean-Christophe PLAGNIOL-VILLARD 12036732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 12046732ae5cSJean-Christophe PLAGNIOL-VILLARD } 12056732ae5cSJean-Christophe PLAGNIOL-VILLARD 1206150632b0SGreg Kroah-Hartman static int at91_pinctrl_probe(struct platform_device *pdev) 12076732ae5cSJean-Christophe PLAGNIOL-VILLARD { 12086732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info; 12096732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_pin_desc *pdesc; 1210a0b957f3SJean-Christophe PLAGNIOL-VILLARD int ret, i, j, k, ngpio_chips_enabled = 0; 12116732ae5cSJean-Christophe PLAGNIOL-VILLARD 12126732ae5cSJean-Christophe PLAGNIOL-VILLARD info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); 12136732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!info) 12146732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENOMEM; 12156732ae5cSJean-Christophe PLAGNIOL-VILLARD 12166732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = at91_pinctrl_probe_dt(pdev, info); 12176732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ret) 12186732ae5cSJean-Christophe PLAGNIOL-VILLARD return ret; 12196732ae5cSJean-Christophe PLAGNIOL-VILLARD 12206732ae5cSJean-Christophe PLAGNIOL-VILLARD /* 12216732ae5cSJean-Christophe PLAGNIOL-VILLARD * We need all the GPIO drivers to probe FIRST, or we will not be able 12226732ae5cSJean-Christophe PLAGNIOL-VILLARD * to obtain references to the struct gpio_chip * for them, and we 12236732ae5cSJean-Christophe PLAGNIOL-VILLARD * need this to proceed. 12246732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 1225a0b957f3SJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < gpio_banks; i++) 1226a0b957f3SJean-Christophe PLAGNIOL-VILLARD if (gpio_chips[i]) 1227a0b957f3SJean-Christophe PLAGNIOL-VILLARD ngpio_chips_enabled++; 1228a0b957f3SJean-Christophe PLAGNIOL-VILLARD 1229a0b957f3SJean-Christophe PLAGNIOL-VILLARD if (ngpio_chips_enabled < info->nactive_banks) { 1230a0b957f3SJean-Christophe PLAGNIOL-VILLARD dev_warn(&pdev->dev, 1231a0b957f3SJean-Christophe PLAGNIOL-VILLARD "All GPIO chips are not registered yet (%d/%d)\n", 1232a0b957f3SJean-Christophe PLAGNIOL-VILLARD ngpio_chips_enabled, info->nactive_banks); 12336732ae5cSJean-Christophe PLAGNIOL-VILLARD devm_kfree(&pdev->dev, info); 12346732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EPROBE_DEFER; 12356732ae5cSJean-Christophe PLAGNIOL-VILLARD } 12366732ae5cSJean-Christophe PLAGNIOL-VILLARD 12376732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_pinctrl_desc.name = dev_name(&pdev->dev); 1238a0b957f3SJean-Christophe PLAGNIOL-VILLARD at91_pinctrl_desc.npins = gpio_banks * MAX_NB_GPIO_PER_BANK; 12396732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_pinctrl_desc.pins = pdesc = 12406732ae5cSJean-Christophe PLAGNIOL-VILLARD devm_kzalloc(&pdev->dev, sizeof(*pdesc) * at91_pinctrl_desc.npins, GFP_KERNEL); 12416732ae5cSJean-Christophe PLAGNIOL-VILLARD 12426732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!at91_pinctrl_desc.pins) 12436732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENOMEM; 12446732ae5cSJean-Christophe PLAGNIOL-VILLARD 1245a0b957f3SJean-Christophe PLAGNIOL-VILLARD for (i = 0, k = 0; i < gpio_banks; i++) { 12466732ae5cSJean-Christophe PLAGNIOL-VILLARD for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) { 12476732ae5cSJean-Christophe PLAGNIOL-VILLARD pdesc->number = k; 12486732ae5cSJean-Christophe PLAGNIOL-VILLARD pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j); 12496732ae5cSJean-Christophe PLAGNIOL-VILLARD pdesc++; 12506732ae5cSJean-Christophe PLAGNIOL-VILLARD } 12516732ae5cSJean-Christophe PLAGNIOL-VILLARD } 12526732ae5cSJean-Christophe PLAGNIOL-VILLARD 12536732ae5cSJean-Christophe PLAGNIOL-VILLARD platform_set_drvdata(pdev, info); 12546732ae5cSJean-Christophe PLAGNIOL-VILLARD info->pctl = pinctrl_register(&at91_pinctrl_desc, &pdev->dev, info); 12556732ae5cSJean-Christophe PLAGNIOL-VILLARD 1256323de9efSMasahiro Yamada if (IS_ERR(info->pctl)) { 12576732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n"); 1258323de9efSMasahiro Yamada return PTR_ERR(info->pctl); 12596732ae5cSJean-Christophe PLAGNIOL-VILLARD } 12606732ae5cSJean-Christophe PLAGNIOL-VILLARD 12616732ae5cSJean-Christophe PLAGNIOL-VILLARD /* We will handle a range of GPIO pins */ 1262a0b957f3SJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < gpio_banks; i++) 1263a0b957f3SJean-Christophe PLAGNIOL-VILLARD if (gpio_chips[i]) 12646732ae5cSJean-Christophe PLAGNIOL-VILLARD pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range); 12656732ae5cSJean-Christophe PLAGNIOL-VILLARD 12666732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n"); 12676732ae5cSJean-Christophe PLAGNIOL-VILLARD 12686732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 12696732ae5cSJean-Christophe PLAGNIOL-VILLARD } 12706732ae5cSJean-Christophe PLAGNIOL-VILLARD 1271150632b0SGreg Kroah-Hartman static int at91_pinctrl_remove(struct platform_device *pdev) 12726732ae5cSJean-Christophe PLAGNIOL-VILLARD { 12736732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = platform_get_drvdata(pdev); 12746732ae5cSJean-Christophe PLAGNIOL-VILLARD 12756732ae5cSJean-Christophe PLAGNIOL-VILLARD pinctrl_unregister(info->pctl); 12766732ae5cSJean-Christophe PLAGNIOL-VILLARD 12776732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 12786732ae5cSJean-Christophe PLAGNIOL-VILLARD } 12796732ae5cSJean-Christophe PLAGNIOL-VILLARD 12806732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_gpio_request(struct gpio_chip *chip, unsigned offset) 12816732ae5cSJean-Christophe PLAGNIOL-VILLARD { 12826732ae5cSJean-Christophe PLAGNIOL-VILLARD /* 12836732ae5cSJean-Christophe PLAGNIOL-VILLARD * Map back to global GPIO space and request muxing, the direction 12846732ae5cSJean-Christophe PLAGNIOL-VILLARD * parameter does not matter for this controller. 12856732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 12866732ae5cSJean-Christophe PLAGNIOL-VILLARD int gpio = chip->base + offset; 12876732ae5cSJean-Christophe PLAGNIOL-VILLARD int bank = chip->base / chip->ngpio; 12886732ae5cSJean-Christophe PLAGNIOL-VILLARD 12896732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(chip->dev, "%s:%d pio%c%d(%d)\n", __func__, __LINE__, 12906732ae5cSJean-Christophe PLAGNIOL-VILLARD 'A' + bank, offset, gpio); 12916732ae5cSJean-Christophe PLAGNIOL-VILLARD 12926732ae5cSJean-Christophe PLAGNIOL-VILLARD return pinctrl_request_gpio(gpio); 12936732ae5cSJean-Christophe PLAGNIOL-VILLARD } 12946732ae5cSJean-Christophe PLAGNIOL-VILLARD 12956732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_gpio_free(struct gpio_chip *chip, unsigned offset) 12966732ae5cSJean-Christophe PLAGNIOL-VILLARD { 12976732ae5cSJean-Christophe PLAGNIOL-VILLARD int gpio = chip->base + offset; 12986732ae5cSJean-Christophe PLAGNIOL-VILLARD 12996732ae5cSJean-Christophe PLAGNIOL-VILLARD pinctrl_free_gpio(gpio); 13006732ae5cSJean-Christophe PLAGNIOL-VILLARD } 13016732ae5cSJean-Christophe PLAGNIOL-VILLARD 13028af584b8SRichard Genoud static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 13038af584b8SRichard Genoud { 13048af584b8SRichard Genoud struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 13058af584b8SRichard Genoud void __iomem *pio = at91_gpio->regbase; 13068af584b8SRichard Genoud unsigned mask = 1 << offset; 13078af584b8SRichard Genoud u32 osr; 13088af584b8SRichard Genoud 13098af584b8SRichard Genoud osr = readl_relaxed(pio + PIO_OSR); 13108af584b8SRichard Genoud return !(osr & mask); 13118af584b8SRichard Genoud } 13128af584b8SRichard Genoud 13136732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 13146732ae5cSJean-Christophe PLAGNIOL-VILLARD { 13156732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 13166732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 13176732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask = 1 << offset; 13186732ae5cSJean-Christophe PLAGNIOL-VILLARD 13196732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_ODR); 13206732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 13216732ae5cSJean-Christophe PLAGNIOL-VILLARD } 13226732ae5cSJean-Christophe PLAGNIOL-VILLARD 13236732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_gpio_get(struct gpio_chip *chip, unsigned offset) 13246732ae5cSJean-Christophe PLAGNIOL-VILLARD { 13256732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 13266732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 13276732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask = 1 << offset; 13286732ae5cSJean-Christophe PLAGNIOL-VILLARD u32 pdsr; 13296732ae5cSJean-Christophe PLAGNIOL-VILLARD 13306732ae5cSJean-Christophe PLAGNIOL-VILLARD pdsr = readl_relaxed(pio + PIO_PDSR); 13316732ae5cSJean-Christophe PLAGNIOL-VILLARD return (pdsr & mask) != 0; 13326732ae5cSJean-Christophe PLAGNIOL-VILLARD } 13336732ae5cSJean-Christophe PLAGNIOL-VILLARD 13346732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_gpio_set(struct gpio_chip *chip, unsigned offset, 13356732ae5cSJean-Christophe PLAGNIOL-VILLARD int val) 13366732ae5cSJean-Christophe PLAGNIOL-VILLARD { 13376732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 13386732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 13396732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask = 1 << offset; 13406732ae5cSJean-Christophe PLAGNIOL-VILLARD 13416732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); 13426732ae5cSJean-Christophe PLAGNIOL-VILLARD } 13436732ae5cSJean-Christophe PLAGNIOL-VILLARD 13441893b2cfSAlexander Stein static void at91_gpio_set_multiple(struct gpio_chip *chip, 13451893b2cfSAlexander Stein unsigned long *mask, unsigned long *bits) 13461893b2cfSAlexander Stein { 13471893b2cfSAlexander Stein struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 13481893b2cfSAlexander Stein void __iomem *pio = at91_gpio->regbase; 13491893b2cfSAlexander Stein 13501893b2cfSAlexander Stein #define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1)) 13511893b2cfSAlexander Stein /* Mask additionally to ngpio as not all GPIO controllers have 32 pins */ 13521893b2cfSAlexander Stein uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio); 13531893b2cfSAlexander Stein uint32_t clear_mask = (*mask & ~(*bits)) & BITS_MASK(chip->ngpio); 13541893b2cfSAlexander Stein 13551893b2cfSAlexander Stein writel_relaxed(set_mask, pio + PIO_SODR); 13561893b2cfSAlexander Stein writel_relaxed(clear_mask, pio + PIO_CODR); 13571893b2cfSAlexander Stein } 13581893b2cfSAlexander Stein 13596732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 13606732ae5cSJean-Christophe PLAGNIOL-VILLARD int val) 13616732ae5cSJean-Christophe PLAGNIOL-VILLARD { 13626732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 13636732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 13646732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask = 1 << offset; 13656732ae5cSJean-Christophe PLAGNIOL-VILLARD 13666732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); 13676732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_OER); 13686732ae5cSJean-Christophe PLAGNIOL-VILLARD 13696732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 13706732ae5cSJean-Christophe PLAGNIOL-VILLARD } 13716732ae5cSJean-Christophe PLAGNIOL-VILLARD 13726732ae5cSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_DEBUG_FS 13736732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 13746732ae5cSJean-Christophe PLAGNIOL-VILLARD { 13756732ae5cSJean-Christophe PLAGNIOL-VILLARD enum at91_mux mode; 13766732ae5cSJean-Christophe PLAGNIOL-VILLARD int i; 13776732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 13786732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 13796732ae5cSJean-Christophe PLAGNIOL-VILLARD 13806732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < chip->ngpio; i++) { 138147f22716SAlexander Stein unsigned mask = pin_to_mask(i); 13826732ae5cSJean-Christophe PLAGNIOL-VILLARD const char *gpio_label; 13836732ae5cSJean-Christophe PLAGNIOL-VILLARD 13846732ae5cSJean-Christophe PLAGNIOL-VILLARD gpio_label = gpiochip_is_requested(chip, i); 13856732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!gpio_label) 13866732ae5cSJean-Christophe PLAGNIOL-VILLARD continue; 13876732ae5cSJean-Christophe PLAGNIOL-VILLARD mode = at91_gpio->ops->get_periph(pio, mask); 13886732ae5cSJean-Christophe PLAGNIOL-VILLARD seq_printf(s, "[%s] GPIO%s%d: ", 13896732ae5cSJean-Christophe PLAGNIOL-VILLARD gpio_label, chip->label, i); 13906732ae5cSJean-Christophe PLAGNIOL-VILLARD if (mode == AT91_MUX_GPIO) { 1391853b6bf0SMatthieu Crapet seq_printf(s, "[gpio] "); 1392853b6bf0SMatthieu Crapet seq_printf(s, "%s ", 1393853b6bf0SMatthieu Crapet readl_relaxed(pio + PIO_OSR) & mask ? 1394853b6bf0SMatthieu Crapet "output" : "input"); 1395853b6bf0SMatthieu Crapet seq_printf(s, "%s\n", 1396853b6bf0SMatthieu Crapet readl_relaxed(pio + PIO_PDSR) & mask ? 13976732ae5cSJean-Christophe PLAGNIOL-VILLARD "set" : "clear"); 13986732ae5cSJean-Christophe PLAGNIOL-VILLARD } else { 13996732ae5cSJean-Christophe PLAGNIOL-VILLARD seq_printf(s, "[periph %c]\n", 14006732ae5cSJean-Christophe PLAGNIOL-VILLARD mode + 'A' - 1); 14016732ae5cSJean-Christophe PLAGNIOL-VILLARD } 14026732ae5cSJean-Christophe PLAGNIOL-VILLARD } 14036732ae5cSJean-Christophe PLAGNIOL-VILLARD } 14046732ae5cSJean-Christophe PLAGNIOL-VILLARD #else 14056732ae5cSJean-Christophe PLAGNIOL-VILLARD #define at91_gpio_dbg_show NULL 14066732ae5cSJean-Christophe PLAGNIOL-VILLARD #endif 14076732ae5cSJean-Christophe PLAGNIOL-VILLARD 14086732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Several AIC controller irqs are dispatched through this GPIO handler. 14096732ae5cSJean-Christophe PLAGNIOL-VILLARD * To use any AT91_PIN_* as an externally triggered IRQ, first call 14106732ae5cSJean-Christophe PLAGNIOL-VILLARD * at91_set_gpio_input() then maybe enable its glitch filter. 14116732ae5cSJean-Christophe PLAGNIOL-VILLARD * Then just request_irq() with the pin ID; it works like any ARM IRQ 14126732ae5cSJean-Christophe PLAGNIOL-VILLARD * handler. 14136732ae5cSJean-Christophe PLAGNIOL-VILLARD * First implementation always triggers on rising and falling edges 14146732ae5cSJean-Christophe PLAGNIOL-VILLARD * whereas the newer PIO3 can be additionally configured to trigger on 14156732ae5cSJean-Christophe PLAGNIOL-VILLARD * level, edge with any polarity. 14166732ae5cSJean-Christophe PLAGNIOL-VILLARD * 14176732ae5cSJean-Christophe PLAGNIOL-VILLARD * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after 14186732ae5cSJean-Christophe PLAGNIOL-VILLARD * configuring them with at91_set_a_periph() or at91_set_b_periph(). 14196732ae5cSJean-Christophe PLAGNIOL-VILLARD * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering. 14206732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 14216732ae5cSJean-Christophe PLAGNIOL-VILLARD 14226732ae5cSJean-Christophe PLAGNIOL-VILLARD static void gpio_irq_mask(struct irq_data *d) 14236732ae5cSJean-Christophe PLAGNIOL-VILLARD { 14246732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 14256732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 14266732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask = 1 << d->hwirq; 14276732ae5cSJean-Christophe PLAGNIOL-VILLARD 14286732ae5cSJean-Christophe PLAGNIOL-VILLARD if (pio) 14296732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_IDR); 14306732ae5cSJean-Christophe PLAGNIOL-VILLARD } 14316732ae5cSJean-Christophe PLAGNIOL-VILLARD 14326732ae5cSJean-Christophe PLAGNIOL-VILLARD static void gpio_irq_unmask(struct irq_data *d) 14336732ae5cSJean-Christophe PLAGNIOL-VILLARD { 14346732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 14356732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 14366732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask = 1 << d->hwirq; 14376732ae5cSJean-Christophe PLAGNIOL-VILLARD 14386732ae5cSJean-Christophe PLAGNIOL-VILLARD if (pio) 14396732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_IER); 14406732ae5cSJean-Christophe PLAGNIOL-VILLARD } 14416732ae5cSJean-Christophe PLAGNIOL-VILLARD 14426732ae5cSJean-Christophe PLAGNIOL-VILLARD static int gpio_irq_type(struct irq_data *d, unsigned type) 14436732ae5cSJean-Christophe PLAGNIOL-VILLARD { 14446732ae5cSJean-Christophe PLAGNIOL-VILLARD switch (type) { 14456732ae5cSJean-Christophe PLAGNIOL-VILLARD case IRQ_TYPE_NONE: 14466732ae5cSJean-Christophe PLAGNIOL-VILLARD case IRQ_TYPE_EDGE_BOTH: 14476732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 14486732ae5cSJean-Christophe PLAGNIOL-VILLARD default: 14496732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 14506732ae5cSJean-Christophe PLAGNIOL-VILLARD } 14516732ae5cSJean-Christophe PLAGNIOL-VILLARD } 14526732ae5cSJean-Christophe PLAGNIOL-VILLARD 14536732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Alternate irq type for PIO3 support */ 14546732ae5cSJean-Christophe PLAGNIOL-VILLARD static int alt_gpio_irq_type(struct irq_data *d, unsigned type) 14556732ae5cSJean-Christophe PLAGNIOL-VILLARD { 14566732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 14576732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 14586732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask = 1 << d->hwirq; 14596732ae5cSJean-Christophe PLAGNIOL-VILLARD 14606732ae5cSJean-Christophe PLAGNIOL-VILLARD switch (type) { 14616732ae5cSJean-Christophe PLAGNIOL-VILLARD case IRQ_TYPE_EDGE_RISING: 1462c639845bSThomas Gleixner irq_set_handler_locked(d, handle_simple_irq); 14636732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_ESR); 14646732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_REHLSR); 14656732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 14666732ae5cSJean-Christophe PLAGNIOL-VILLARD case IRQ_TYPE_EDGE_FALLING: 1467c639845bSThomas Gleixner irq_set_handler_locked(d, handle_simple_irq); 14686732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_ESR); 14696732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_FELLSR); 14706732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 14716732ae5cSJean-Christophe PLAGNIOL-VILLARD case IRQ_TYPE_LEVEL_LOW: 1472c639845bSThomas Gleixner irq_set_handler_locked(d, handle_level_irq); 14736732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_LSR); 14746732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_FELLSR); 14756732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 14766732ae5cSJean-Christophe PLAGNIOL-VILLARD case IRQ_TYPE_LEVEL_HIGH: 1477c639845bSThomas Gleixner irq_set_handler_locked(d, handle_level_irq); 14786732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_LSR); 14796732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_REHLSR); 14806732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 14816732ae5cSJean-Christophe PLAGNIOL-VILLARD case IRQ_TYPE_EDGE_BOTH: 14826732ae5cSJean-Christophe PLAGNIOL-VILLARD /* 14836732ae5cSJean-Christophe PLAGNIOL-VILLARD * disable additional interrupt modes: 14846732ae5cSJean-Christophe PLAGNIOL-VILLARD * fall back to default behavior 14856732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 1486c639845bSThomas Gleixner irq_set_handler_locked(d, handle_simple_irq); 14876732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_AIMDR); 14886732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 14896732ae5cSJean-Christophe PLAGNIOL-VILLARD case IRQ_TYPE_NONE: 14906732ae5cSJean-Christophe PLAGNIOL-VILLARD default: 14916732ae5cSJean-Christophe PLAGNIOL-VILLARD pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq)); 14926732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 14936732ae5cSJean-Christophe PLAGNIOL-VILLARD } 14946732ae5cSJean-Christophe PLAGNIOL-VILLARD 14956732ae5cSJean-Christophe PLAGNIOL-VILLARD /* enable additional interrupt modes */ 14966732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_AIMER); 14976732ae5cSJean-Christophe PLAGNIOL-VILLARD 14986732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 14996732ae5cSJean-Christophe PLAGNIOL-VILLARD } 15006732ae5cSJean-Christophe PLAGNIOL-VILLARD 150180cc3732SAlexander Stein static void gpio_irq_ack(struct irq_data *d) 150280cc3732SAlexander Stein { 150380cc3732SAlexander Stein /* the interrupt is already cleared before by reading ISR */ 150480cc3732SAlexander Stein } 150580cc3732SAlexander Stein 15066732ae5cSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_PM 1507647f8d94SLudovic Desroches 1508647f8d94SLudovic Desroches static u32 wakeups[MAX_GPIO_BANKS]; 1509647f8d94SLudovic Desroches static u32 backups[MAX_GPIO_BANKS]; 1510647f8d94SLudovic Desroches 15116732ae5cSJean-Christophe PLAGNIOL-VILLARD static int gpio_irq_set_wake(struct irq_data *d, unsigned state) 15126732ae5cSJean-Christophe PLAGNIOL-VILLARD { 15136732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 15146732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned bank = at91_gpio->pioc_idx; 1515647f8d94SLudovic Desroches unsigned mask = 1 << d->hwirq; 15166732ae5cSJean-Christophe PLAGNIOL-VILLARD 15176732ae5cSJean-Christophe PLAGNIOL-VILLARD if (unlikely(bank >= MAX_GPIO_BANKS)) 15186732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 15196732ae5cSJean-Christophe PLAGNIOL-VILLARD 1520647f8d94SLudovic Desroches if (state) 1521647f8d94SLudovic Desroches wakeups[bank] |= mask; 1522647f8d94SLudovic Desroches else 1523647f8d94SLudovic Desroches wakeups[bank] &= ~mask; 1524647f8d94SLudovic Desroches 15256732ae5cSJean-Christophe PLAGNIOL-VILLARD irq_set_irq_wake(at91_gpio->pioc_virq, state); 15266732ae5cSJean-Christophe PLAGNIOL-VILLARD 15276732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 15286732ae5cSJean-Christophe PLAGNIOL-VILLARD } 1529647f8d94SLudovic Desroches 1530647f8d94SLudovic Desroches void at91_pinctrl_gpio_suspend(void) 1531647f8d94SLudovic Desroches { 1532647f8d94SLudovic Desroches int i; 1533647f8d94SLudovic Desroches 1534647f8d94SLudovic Desroches for (i = 0; i < gpio_banks; i++) { 1535647f8d94SLudovic Desroches void __iomem *pio; 1536647f8d94SLudovic Desroches 1537647f8d94SLudovic Desroches if (!gpio_chips[i]) 1538647f8d94SLudovic Desroches continue; 1539647f8d94SLudovic Desroches 1540647f8d94SLudovic Desroches pio = gpio_chips[i]->regbase; 1541647f8d94SLudovic Desroches 1542d480239bSBen Dooks backups[i] = readl_relaxed(pio + PIO_IMR); 1543d480239bSBen Dooks writel_relaxed(backups[i], pio + PIO_IDR); 1544d480239bSBen Dooks writel_relaxed(wakeups[i], pio + PIO_IER); 1545647f8d94SLudovic Desroches 1546795f9953SBoris BREZILLON if (!wakeups[i]) 1547795f9953SBoris BREZILLON clk_disable_unprepare(gpio_chips[i]->clock); 1548795f9953SBoris BREZILLON else 1549647f8d94SLudovic Desroches printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 1550647f8d94SLudovic Desroches 'A'+i, wakeups[i]); 1551647f8d94SLudovic Desroches } 1552647f8d94SLudovic Desroches } 1553647f8d94SLudovic Desroches 1554647f8d94SLudovic Desroches void at91_pinctrl_gpio_resume(void) 1555647f8d94SLudovic Desroches { 1556647f8d94SLudovic Desroches int i; 1557647f8d94SLudovic Desroches 1558647f8d94SLudovic Desroches for (i = 0; i < gpio_banks; i++) { 1559647f8d94SLudovic Desroches void __iomem *pio; 1560647f8d94SLudovic Desroches 1561647f8d94SLudovic Desroches if (!gpio_chips[i]) 1562647f8d94SLudovic Desroches continue; 1563647f8d94SLudovic Desroches 1564647f8d94SLudovic Desroches pio = gpio_chips[i]->regbase; 1565647f8d94SLudovic Desroches 156637ef1d92SBoris BREZILLON if (!wakeups[i]) 156737ef1d92SBoris BREZILLON clk_prepare_enable(gpio_chips[i]->clock); 1568647f8d94SLudovic Desroches 1569d480239bSBen Dooks writel_relaxed(wakeups[i], pio + PIO_IDR); 1570d480239bSBen Dooks writel_relaxed(backups[i], pio + PIO_IER); 1571647f8d94SLudovic Desroches } 1572647f8d94SLudovic Desroches } 1573647f8d94SLudovic Desroches 15746732ae5cSJean-Christophe PLAGNIOL-VILLARD #else 15756732ae5cSJean-Christophe PLAGNIOL-VILLARD #define gpio_irq_set_wake NULL 1576647f8d94SLudovic Desroches #endif /* CONFIG_PM */ 15776732ae5cSJean-Christophe PLAGNIOL-VILLARD 15786732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct irq_chip gpio_irqchip = { 15796732ae5cSJean-Christophe PLAGNIOL-VILLARD .name = "GPIO", 158080cc3732SAlexander Stein .irq_ack = gpio_irq_ack, 15816732ae5cSJean-Christophe PLAGNIOL-VILLARD .irq_disable = gpio_irq_mask, 15826732ae5cSJean-Christophe PLAGNIOL-VILLARD .irq_mask = gpio_irq_mask, 15836732ae5cSJean-Christophe PLAGNIOL-VILLARD .irq_unmask = gpio_irq_unmask, 15846732ae5cSJean-Christophe PLAGNIOL-VILLARD /* .irq_set_type is set dynamically */ 15856732ae5cSJean-Christophe PLAGNIOL-VILLARD .irq_set_wake = gpio_irq_set_wake, 15866732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 15876732ae5cSJean-Christophe PLAGNIOL-VILLARD 1588bd0b9ac4SThomas Gleixner static void gpio_irq_handler(struct irq_desc *desc) 15896732ae5cSJean-Christophe PLAGNIOL-VILLARD { 15905663bb27SJiang Liu struct irq_chip *chip = irq_desc_get_chip(desc); 159180cc3732SAlexander Stein struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc); 159280cc3732SAlexander Stein struct at91_gpio_chip *at91_gpio = container_of(gpio_chip, 159380cc3732SAlexander Stein struct at91_gpio_chip, chip); 159480cc3732SAlexander Stein 15956732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 15966732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned long isr; 15976732ae5cSJean-Christophe PLAGNIOL-VILLARD int n; 15986732ae5cSJean-Christophe PLAGNIOL-VILLARD 15996732ae5cSJean-Christophe PLAGNIOL-VILLARD chained_irq_enter(chip, desc); 16006732ae5cSJean-Christophe PLAGNIOL-VILLARD for (;;) { 16016732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Reading ISR acks pending (edge triggered) GPIO interrupts. 1602c2eb9e7fSAlexandre Belloni * When there are none pending, we're finished unless we need 16036732ae5cSJean-Christophe PLAGNIOL-VILLARD * to process multiple banks (like ID_PIOCDE on sam9263). 16046732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 16056732ae5cSJean-Christophe PLAGNIOL-VILLARD isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR); 16066732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!isr) { 16076732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!at91_gpio->next) 16086732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 16096732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_gpio = at91_gpio->next; 16106732ae5cSJean-Christophe PLAGNIOL-VILLARD pio = at91_gpio->regbase; 1611cccb0c3eSAlexander Stein gpio_chip = &at91_gpio->chip; 16126732ae5cSJean-Christophe PLAGNIOL-VILLARD continue; 16136732ae5cSJean-Christophe PLAGNIOL-VILLARD } 16146732ae5cSJean-Christophe PLAGNIOL-VILLARD 161505daa16aSWei Yongjun for_each_set_bit(n, &isr, BITS_PER_LONG) { 161680cc3732SAlexander Stein generic_handle_irq(irq_find_mapping( 161780cc3732SAlexander Stein gpio_chip->irqdomain, n)); 16186732ae5cSJean-Christophe PLAGNIOL-VILLARD } 16196732ae5cSJean-Christophe PLAGNIOL-VILLARD } 16206732ae5cSJean-Christophe PLAGNIOL-VILLARD chained_irq_exit(chip, desc); 16216732ae5cSJean-Christophe PLAGNIOL-VILLARD /* now it may re-trigger */ 16226732ae5cSJean-Christophe PLAGNIOL-VILLARD } 16236732ae5cSJean-Christophe PLAGNIOL-VILLARD 1624834e1678SPramod Gurav static int at91_gpio_of_irq_setup(struct platform_device *pdev, 16256732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio) 16266732ae5cSJean-Christophe PLAGNIOL-VILLARD { 1627a0b957f3SJean-Christophe PLAGNIOL-VILLARD struct gpio_chip *gpiochip_prev = NULL; 1628cccb0c3eSAlexander Stein struct at91_gpio_chip *prev = NULL; 16296732ae5cSJean-Christophe PLAGNIOL-VILLARD struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq); 1630a0b957f3SJean-Christophe PLAGNIOL-VILLARD int ret, i; 16316732ae5cSJean-Christophe PLAGNIOL-VILLARD 16326732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_gpio->pioc_hwirq = irqd_to_hwirq(d); 16336732ae5cSJean-Christophe PLAGNIOL-VILLARD 16346732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Setup proper .irq_set_type function */ 16356732ae5cSJean-Christophe PLAGNIOL-VILLARD gpio_irqchip.irq_set_type = at91_gpio->ops->irq_type; 16366732ae5cSJean-Christophe PLAGNIOL-VILLARD 16376732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Disable irqs of this PIO controller */ 16386732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(~0, at91_gpio->regbase + PIO_IDR); 16396732ae5cSJean-Christophe PLAGNIOL-VILLARD 164080cc3732SAlexander Stein /* 164180cc3732SAlexander Stein * Let the generic code handle this edge IRQ, the the chained 164280cc3732SAlexander Stein * handler will perform the actual work of handling the parent 164380cc3732SAlexander Stein * interrupt. 164480cc3732SAlexander Stein */ 164580cc3732SAlexander Stein ret = gpiochip_irqchip_add(&at91_gpio->chip, 164680cc3732SAlexander Stein &gpio_irqchip, 164780cc3732SAlexander Stein 0, 164880cc3732SAlexander Stein handle_edge_irq, 164980cc3732SAlexander Stein IRQ_TYPE_EDGE_BOTH); 1650834e1678SPramod Gurav if (ret) { 1651834e1678SPramod Gurav dev_err(&pdev->dev, "at91_gpio.%d: Couldn't add irqchip to gpiochip.\n", 16526732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_gpio->pioc_idx); 1653834e1678SPramod Gurav return ret; 1654834e1678SPramod Gurav } 16556732ae5cSJean-Christophe PLAGNIOL-VILLARD 1656cccb0c3eSAlexander Stein /* The top level handler handles one bank of GPIOs, except 1657cccb0c3eSAlexander Stein * on some SoC it can handle up to three... 1658cccb0c3eSAlexander Stein * We only set up the handler for the first of the list. 1659cccb0c3eSAlexander Stein */ 1660a0b957f3SJean-Christophe PLAGNIOL-VILLARD gpiochip_prev = irq_get_handler_data(at91_gpio->pioc_virq); 1661a0b957f3SJean-Christophe PLAGNIOL-VILLARD if (!gpiochip_prev) { 166280cc3732SAlexander Stein /* Then register the chain on the parent IRQ */ 166380cc3732SAlexander Stein gpiochip_set_chained_irqchip(&at91_gpio->chip, 166480cc3732SAlexander Stein &gpio_irqchip, 166580cc3732SAlexander Stein at91_gpio->pioc_virq, 166680cc3732SAlexander Stein gpio_irq_handler); 16676732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 16686732ae5cSJean-Christophe PLAGNIOL-VILLARD } 16696732ae5cSJean-Christophe PLAGNIOL-VILLARD 1670a0b957f3SJean-Christophe PLAGNIOL-VILLARD prev = container_of(gpiochip_prev, struct at91_gpio_chip, chip); 1671a0b957f3SJean-Christophe PLAGNIOL-VILLARD 1672a0b957f3SJean-Christophe PLAGNIOL-VILLARD /* we can only have 2 banks before */ 1673a0b957f3SJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < 2; i++) { 1674a0b957f3SJean-Christophe PLAGNIOL-VILLARD if (prev->next) { 1675a0b957f3SJean-Christophe PLAGNIOL-VILLARD prev = prev->next; 1676a0b957f3SJean-Christophe PLAGNIOL-VILLARD } else { 1677a0b957f3SJean-Christophe PLAGNIOL-VILLARD prev->next = at91_gpio; 1678a0b957f3SJean-Christophe PLAGNIOL-VILLARD return 0; 1679a0b957f3SJean-Christophe PLAGNIOL-VILLARD } 1680a0b957f3SJean-Christophe PLAGNIOL-VILLARD } 1681a0b957f3SJean-Christophe PLAGNIOL-VILLARD 1682a0b957f3SJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 1683a0b957f3SJean-Christophe PLAGNIOL-VILLARD } 1684a0b957f3SJean-Christophe PLAGNIOL-VILLARD 16856732ae5cSJean-Christophe PLAGNIOL-VILLARD /* This structure is replicated for each GPIO block allocated at probe time */ 16866732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct gpio_chip at91_gpio_template = { 16876732ae5cSJean-Christophe PLAGNIOL-VILLARD .request = at91_gpio_request, 16886732ae5cSJean-Christophe PLAGNIOL-VILLARD .free = at91_gpio_free, 16898af584b8SRichard Genoud .get_direction = at91_gpio_get_direction, 16906732ae5cSJean-Christophe PLAGNIOL-VILLARD .direction_input = at91_gpio_direction_input, 16916732ae5cSJean-Christophe PLAGNIOL-VILLARD .get = at91_gpio_get, 16926732ae5cSJean-Christophe PLAGNIOL-VILLARD .direction_output = at91_gpio_direction_output, 16936732ae5cSJean-Christophe PLAGNIOL-VILLARD .set = at91_gpio_set, 16941893b2cfSAlexander Stein .set_multiple = at91_gpio_set_multiple, 16956732ae5cSJean-Christophe PLAGNIOL-VILLARD .dbg_show = at91_gpio_dbg_show, 16969fb1f39eSLinus Walleij .can_sleep = false, 16976732ae5cSJean-Christophe PLAGNIOL-VILLARD .ngpio = MAX_NB_GPIO_PER_BANK, 16986732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 16996732ae5cSJean-Christophe PLAGNIOL-VILLARD 1700baa9946eSFabian Frederick static const struct of_device_id at91_gpio_of_match[] = { 17016732ae5cSJean-Christophe PLAGNIOL-VILLARD { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, }, 17026732ae5cSJean-Christophe PLAGNIOL-VILLARD { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops }, 17036732ae5cSJean-Christophe PLAGNIOL-VILLARD { /* sentinel */ } 17046732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 17056732ae5cSJean-Christophe PLAGNIOL-VILLARD 1706150632b0SGreg Kroah-Hartman static int at91_gpio_probe(struct platform_device *pdev) 17076732ae5cSJean-Christophe PLAGNIOL-VILLARD { 17086732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *np = pdev->dev.of_node; 17096732ae5cSJean-Christophe PLAGNIOL-VILLARD struct resource *res; 17106732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_chip = NULL; 17116732ae5cSJean-Christophe PLAGNIOL-VILLARD struct gpio_chip *chip; 17126732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_gpio_range *range; 17136732ae5cSJean-Christophe PLAGNIOL-VILLARD int ret = 0; 171432b01a36SJean-Christophe PLAGNIOL-VILLARD int irq, i; 17156732ae5cSJean-Christophe PLAGNIOL-VILLARD int alias_idx = of_alias_get_id(np, "gpio"); 17166732ae5cSJean-Christophe PLAGNIOL-VILLARD uint32_t ngpio; 171732b01a36SJean-Christophe PLAGNIOL-VILLARD char **names; 17186732ae5cSJean-Christophe PLAGNIOL-VILLARD 17196732ae5cSJean-Christophe PLAGNIOL-VILLARD BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips)); 17206732ae5cSJean-Christophe PLAGNIOL-VILLARD if (gpio_chips[alias_idx]) { 17216732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = -EBUSY; 17226732ae5cSJean-Christophe PLAGNIOL-VILLARD goto err; 17236732ae5cSJean-Christophe PLAGNIOL-VILLARD } 17246732ae5cSJean-Christophe PLAGNIOL-VILLARD 17256732ae5cSJean-Christophe PLAGNIOL-VILLARD irq = platform_get_irq(pdev, 0); 17266732ae5cSJean-Christophe PLAGNIOL-VILLARD if (irq < 0) { 17276732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = irq; 17286732ae5cSJean-Christophe PLAGNIOL-VILLARD goto err; 17296732ae5cSJean-Christophe PLAGNIOL-VILLARD } 17306732ae5cSJean-Christophe PLAGNIOL-VILLARD 17316732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL); 17326732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!at91_chip) { 17336732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = -ENOMEM; 17346732ae5cSJean-Christophe PLAGNIOL-VILLARD goto err; 17356732ae5cSJean-Christophe PLAGNIOL-VILLARD } 17366732ae5cSJean-Christophe PLAGNIOL-VILLARD 1737f50b9e12SWolfram Sang res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 17389e0c1fb2SThierry Reding at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res); 17399e0c1fb2SThierry Reding if (IS_ERR(at91_chip->regbase)) { 17409e0c1fb2SThierry Reding ret = PTR_ERR(at91_chip->regbase); 17416732ae5cSJean-Christophe PLAGNIOL-VILLARD goto err; 17426732ae5cSJean-Christophe PLAGNIOL-VILLARD } 17436732ae5cSJean-Christophe PLAGNIOL-VILLARD 1744dffa9123SJean-Christophe PLAGNIOL-VILLARD at91_chip->ops = (struct at91_pinctrl_mux_ops *) 17456732ae5cSJean-Christophe PLAGNIOL-VILLARD of_match_device(at91_gpio_of_match, &pdev->dev)->data; 17466732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_chip->pioc_virq = irq; 17476732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_chip->pioc_idx = alias_idx; 17486732ae5cSJean-Christophe PLAGNIOL-VILLARD 174902b837ffSPramod Gurav at91_chip->clock = devm_clk_get(&pdev->dev, NULL); 17506732ae5cSJean-Christophe PLAGNIOL-VILLARD if (IS_ERR(at91_chip->clock)) { 17516732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(&pdev->dev, "failed to get clock, ignoring.\n"); 175270e41974SPramod Gurav ret = PTR_ERR(at91_chip->clock); 17536732ae5cSJean-Christophe PLAGNIOL-VILLARD goto err; 17546732ae5cSJean-Christophe PLAGNIOL-VILLARD } 17556732ae5cSJean-Christophe PLAGNIOL-VILLARD 175670e41974SPramod Gurav ret = clk_prepare(at91_chip->clock); 175770e41974SPramod Gurav if (ret) 175870e41974SPramod Gurav goto clk_prepare_err; 17596732ae5cSJean-Christophe PLAGNIOL-VILLARD 17606732ae5cSJean-Christophe PLAGNIOL-VILLARD /* enable PIO controller's clock */ 176170e41974SPramod Gurav ret = clk_enable(at91_chip->clock); 176270e41974SPramod Gurav if (ret) { 17636732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(&pdev->dev, "failed to enable clock, ignoring.\n"); 176470e41974SPramod Gurav goto clk_enable_err; 17656732ae5cSJean-Christophe PLAGNIOL-VILLARD } 17666732ae5cSJean-Christophe PLAGNIOL-VILLARD 17676732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_chip->chip = at91_gpio_template; 17686732ae5cSJean-Christophe PLAGNIOL-VILLARD 17696732ae5cSJean-Christophe PLAGNIOL-VILLARD chip = &at91_chip->chip; 17706732ae5cSJean-Christophe PLAGNIOL-VILLARD chip->of_node = np; 17716732ae5cSJean-Christophe PLAGNIOL-VILLARD chip->label = dev_name(&pdev->dev); 17726732ae5cSJean-Christophe PLAGNIOL-VILLARD chip->dev = &pdev->dev; 17736732ae5cSJean-Christophe PLAGNIOL-VILLARD chip->owner = THIS_MODULE; 17746732ae5cSJean-Christophe PLAGNIOL-VILLARD chip->base = alias_idx * MAX_NB_GPIO_PER_BANK; 17756732ae5cSJean-Christophe PLAGNIOL-VILLARD 17766732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) { 17776732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ngpio >= MAX_NB_GPIO_PER_BANK) 17786732ae5cSJean-Christophe PLAGNIOL-VILLARD pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n", 17796732ae5cSJean-Christophe PLAGNIOL-VILLARD alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK); 17806732ae5cSJean-Christophe PLAGNIOL-VILLARD else 17816732ae5cSJean-Christophe PLAGNIOL-VILLARD chip->ngpio = ngpio; 17826732ae5cSJean-Christophe PLAGNIOL-VILLARD } 17836732ae5cSJean-Christophe PLAGNIOL-VILLARD 17843c93600dSSachin Kamat names = devm_kzalloc(&pdev->dev, sizeof(char *) * chip->ngpio, 17853c93600dSSachin Kamat GFP_KERNEL); 178632b01a36SJean-Christophe PLAGNIOL-VILLARD 178732b01a36SJean-Christophe PLAGNIOL-VILLARD if (!names) { 178832b01a36SJean-Christophe PLAGNIOL-VILLARD ret = -ENOMEM; 178970e41974SPramod Gurav goto clk_enable_err; 179032b01a36SJean-Christophe PLAGNIOL-VILLARD } 179132b01a36SJean-Christophe PLAGNIOL-VILLARD 179232b01a36SJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < chip->ngpio; i++) 179332b01a36SJean-Christophe PLAGNIOL-VILLARD names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i); 179432b01a36SJean-Christophe PLAGNIOL-VILLARD 179532b01a36SJean-Christophe PLAGNIOL-VILLARD chip->names = (const char *const *)names; 179632b01a36SJean-Christophe PLAGNIOL-VILLARD 17976732ae5cSJean-Christophe PLAGNIOL-VILLARD range = &at91_chip->range; 17986732ae5cSJean-Christophe PLAGNIOL-VILLARD range->name = chip->label; 17996732ae5cSJean-Christophe PLAGNIOL-VILLARD range->id = alias_idx; 18006732ae5cSJean-Christophe PLAGNIOL-VILLARD range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK; 18016732ae5cSJean-Christophe PLAGNIOL-VILLARD 18026732ae5cSJean-Christophe PLAGNIOL-VILLARD range->npins = chip->ngpio; 18036732ae5cSJean-Christophe PLAGNIOL-VILLARD range->gc = chip; 18046732ae5cSJean-Christophe PLAGNIOL-VILLARD 18056732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = gpiochip_add(chip); 18066732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ret) 180770e41974SPramod Gurav goto gpiochip_add_err; 18086732ae5cSJean-Christophe PLAGNIOL-VILLARD 18096732ae5cSJean-Christophe PLAGNIOL-VILLARD gpio_chips[alias_idx] = at91_chip; 18106732ae5cSJean-Christophe PLAGNIOL-VILLARD gpio_banks = max(gpio_banks, alias_idx + 1); 18116732ae5cSJean-Christophe PLAGNIOL-VILLARD 1812834e1678SPramod Gurav ret = at91_gpio_of_irq_setup(pdev, at91_chip); 1813834e1678SPramod Gurav if (ret) 1814834e1678SPramod Gurav goto irq_setup_err; 18156732ae5cSJean-Christophe PLAGNIOL-VILLARD 18166732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase); 18176732ae5cSJean-Christophe PLAGNIOL-VILLARD 18186732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 18196732ae5cSJean-Christophe PLAGNIOL-VILLARD 1820834e1678SPramod Gurav irq_setup_err: 1821834e1678SPramod Gurav gpiochip_remove(chip); 182270e41974SPramod Gurav gpiochip_add_err: 182370e41974SPramod Gurav clk_disable(at91_chip->clock); 182470e41974SPramod Gurav clk_enable_err: 18256732ae5cSJean-Christophe PLAGNIOL-VILLARD clk_unprepare(at91_chip->clock); 182670e41974SPramod Gurav clk_prepare_err: 18276732ae5cSJean-Christophe PLAGNIOL-VILLARD err: 18286732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx); 18296732ae5cSJean-Christophe PLAGNIOL-VILLARD 18306732ae5cSJean-Christophe PLAGNIOL-VILLARD return ret; 18316732ae5cSJean-Christophe PLAGNIOL-VILLARD } 18326732ae5cSJean-Christophe PLAGNIOL-VILLARD 18336732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct platform_driver at91_gpio_driver = { 18346732ae5cSJean-Christophe PLAGNIOL-VILLARD .driver = { 18356732ae5cSJean-Christophe PLAGNIOL-VILLARD .name = "gpio-at91", 1836606fca94SSachin Kamat .of_match_table = at91_gpio_of_match, 18376732ae5cSJean-Christophe PLAGNIOL-VILLARD }, 18386732ae5cSJean-Christophe PLAGNIOL-VILLARD .probe = at91_gpio_probe, 18396732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 18406732ae5cSJean-Christophe PLAGNIOL-VILLARD 18416732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct platform_driver at91_pinctrl_driver = { 18426732ae5cSJean-Christophe PLAGNIOL-VILLARD .driver = { 18436732ae5cSJean-Christophe PLAGNIOL-VILLARD .name = "pinctrl-at91", 1844606fca94SSachin Kamat .of_match_table = at91_pinctrl_of_match, 18456732ae5cSJean-Christophe PLAGNIOL-VILLARD }, 18466732ae5cSJean-Christophe PLAGNIOL-VILLARD .probe = at91_pinctrl_probe, 1847150632b0SGreg Kroah-Hartman .remove = at91_pinctrl_remove, 18486732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 18496732ae5cSJean-Christophe PLAGNIOL-VILLARD 18506732ae5cSJean-Christophe PLAGNIOL-VILLARD static int __init at91_pinctrl_init(void) 18516732ae5cSJean-Christophe PLAGNIOL-VILLARD { 18526732ae5cSJean-Christophe PLAGNIOL-VILLARD int ret; 18536732ae5cSJean-Christophe PLAGNIOL-VILLARD 18546732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = platform_driver_register(&at91_gpio_driver); 18556732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ret) 18566732ae5cSJean-Christophe PLAGNIOL-VILLARD return ret; 18576732ae5cSJean-Christophe PLAGNIOL-VILLARD return platform_driver_register(&at91_pinctrl_driver); 18586732ae5cSJean-Christophe PLAGNIOL-VILLARD } 18596732ae5cSJean-Christophe PLAGNIOL-VILLARD arch_initcall(at91_pinctrl_init); 18606732ae5cSJean-Christophe PLAGNIOL-VILLARD 18616732ae5cSJean-Christophe PLAGNIOL-VILLARD static void __exit at91_pinctrl_exit(void) 18626732ae5cSJean-Christophe PLAGNIOL-VILLARD { 18636732ae5cSJean-Christophe PLAGNIOL-VILLARD platform_driver_unregister(&at91_pinctrl_driver); 18646732ae5cSJean-Christophe PLAGNIOL-VILLARD } 18656732ae5cSJean-Christophe PLAGNIOL-VILLARD 18666732ae5cSJean-Christophe PLAGNIOL-VILLARD module_exit(at91_pinctrl_exit); 18676732ae5cSJean-Christophe PLAGNIOL-VILLARD MODULE_AUTHOR("Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>"); 18686732ae5cSJean-Christophe PLAGNIOL-VILLARD MODULE_DESCRIPTION("Atmel AT91 pinctrl driver"); 18696732ae5cSJean-Christophe PLAGNIOL-VILLARD MODULE_LICENSE("GPL v2"); 1870