16732ae5cSJean-Christophe PLAGNIOL-VILLARD /* 26732ae5cSJean-Christophe PLAGNIOL-VILLARD * at91 pinctrl driver based on at91 pinmux core 36732ae5cSJean-Christophe PLAGNIOL-VILLARD * 46732ae5cSJean-Christophe PLAGNIOL-VILLARD * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 56732ae5cSJean-Christophe PLAGNIOL-VILLARD * 66732ae5cSJean-Christophe PLAGNIOL-VILLARD * Under GPLv2 only 76732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 86732ae5cSJean-Christophe PLAGNIOL-VILLARD 96732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/clk.h> 106732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/err.h> 116732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/init.h> 126732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/module.h> 136732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/of.h> 146732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/of_device.h> 156732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/of_address.h> 166732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/of_irq.h> 176732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/slab.h> 186732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/interrupt.h> 196732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/irq.h> 206732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/irqdomain.h> 216732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/io.h> 226732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/gpio.h> 236732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/irqdomain.h> 246732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/pinctrl/machine.h> 256732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/pinctrl/pinconf.h> 266732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/pinctrl/pinctrl.h> 276732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/pinctrl/pinmux.h> 286732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Since we request GPIOs from ourself */ 296732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/pinctrl/consumer.h> 306732ae5cSJean-Christophe PLAGNIOL-VILLARD 316732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <asm/mach/irq.h> 326732ae5cSJean-Christophe PLAGNIOL-VILLARD 336732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <mach/hardware.h> 346732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <mach/at91_pio.h> 356732ae5cSJean-Christophe PLAGNIOL-VILLARD 366732ae5cSJean-Christophe PLAGNIOL-VILLARD #include "core.h" 376732ae5cSJean-Christophe PLAGNIOL-VILLARD 386732ae5cSJean-Christophe PLAGNIOL-VILLARD #define MAX_NB_GPIO_PER_BANK 32 396732ae5cSJean-Christophe PLAGNIOL-VILLARD 406732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl_mux_ops; 416732ae5cSJean-Christophe PLAGNIOL-VILLARD 426732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip { 436732ae5cSJean-Christophe PLAGNIOL-VILLARD struct gpio_chip chip; 446732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_gpio_range range; 456732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *next; /* Bank sharing same clock */ 466732ae5cSJean-Christophe PLAGNIOL-VILLARD int pioc_hwirq; /* PIO bank interrupt identifier on AIC */ 476732ae5cSJean-Christophe PLAGNIOL-VILLARD int pioc_virq; /* PIO bank Linux virtual interrupt */ 486732ae5cSJean-Christophe PLAGNIOL-VILLARD int pioc_idx; /* PIO bank index */ 496732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *regbase; /* PIO bank virtual address */ 506732ae5cSJean-Christophe PLAGNIOL-VILLARD struct clk *clock; /* associated clock */ 516732ae5cSJean-Christophe PLAGNIOL-VILLARD struct irq_domain *domain; /* associated irq domain */ 526732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl_mux_ops *ops; /* ops */ 536732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 546732ae5cSJean-Christophe PLAGNIOL-VILLARD 556732ae5cSJean-Christophe PLAGNIOL-VILLARD #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip) 566732ae5cSJean-Christophe PLAGNIOL-VILLARD 576732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS]; 586732ae5cSJean-Christophe PLAGNIOL-VILLARD 596732ae5cSJean-Christophe PLAGNIOL-VILLARD static int gpio_banks; 606732ae5cSJean-Christophe PLAGNIOL-VILLARD 61525fae21SJean-Christophe PLAGNIOL-VILLARD #define PULL_UP (1 << 0) 626732ae5cSJean-Christophe PLAGNIOL-VILLARD #define MULTI_DRIVE (1 << 1) 636732ae5cSJean-Christophe PLAGNIOL-VILLARD 646732ae5cSJean-Christophe PLAGNIOL-VILLARD /** 656732ae5cSJean-Christophe PLAGNIOL-VILLARD * struct at91_pmx_func - describes AT91 pinmux functions 666732ae5cSJean-Christophe PLAGNIOL-VILLARD * @name: the name of this specific function 676732ae5cSJean-Christophe PLAGNIOL-VILLARD * @groups: corresponding pin groups 686732ae5cSJean-Christophe PLAGNIOL-VILLARD * @ngroups: the number of groups 696732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 706732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pmx_func { 716732ae5cSJean-Christophe PLAGNIOL-VILLARD const char *name; 726732ae5cSJean-Christophe PLAGNIOL-VILLARD const char **groups; 736732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned ngroups; 746732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 756732ae5cSJean-Christophe PLAGNIOL-VILLARD 766732ae5cSJean-Christophe PLAGNIOL-VILLARD enum at91_mux { 776732ae5cSJean-Christophe PLAGNIOL-VILLARD AT91_MUX_GPIO = 0, 786732ae5cSJean-Christophe PLAGNIOL-VILLARD AT91_MUX_PERIPH_A = 1, 796732ae5cSJean-Christophe PLAGNIOL-VILLARD AT91_MUX_PERIPH_B = 2, 806732ae5cSJean-Christophe PLAGNIOL-VILLARD AT91_MUX_PERIPH_C = 3, 816732ae5cSJean-Christophe PLAGNIOL-VILLARD AT91_MUX_PERIPH_D = 4, 826732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 836732ae5cSJean-Christophe PLAGNIOL-VILLARD 846732ae5cSJean-Christophe PLAGNIOL-VILLARD /** 856732ae5cSJean-Christophe PLAGNIOL-VILLARD * struct at91_pmx_pin - describes an At91 pin mux 866732ae5cSJean-Christophe PLAGNIOL-VILLARD * @bank: the bank of the pin 876732ae5cSJean-Christophe PLAGNIOL-VILLARD * @pin: the pin number in the @bank 886732ae5cSJean-Christophe PLAGNIOL-VILLARD * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function. 896732ae5cSJean-Christophe PLAGNIOL-VILLARD * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc... 906732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 916732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pmx_pin { 926732ae5cSJean-Christophe PLAGNIOL-VILLARD uint32_t bank; 936732ae5cSJean-Christophe PLAGNIOL-VILLARD uint32_t pin; 946732ae5cSJean-Christophe PLAGNIOL-VILLARD enum at91_mux mux; 956732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned long conf; 966732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 976732ae5cSJean-Christophe PLAGNIOL-VILLARD 986732ae5cSJean-Christophe PLAGNIOL-VILLARD /** 996732ae5cSJean-Christophe PLAGNIOL-VILLARD * struct at91_pin_group - describes an At91 pin group 1006732ae5cSJean-Christophe PLAGNIOL-VILLARD * @name: the name of this specific pin group 1016732ae5cSJean-Christophe PLAGNIOL-VILLARD * @pins_conf: the mux mode for each pin in this group. The size of this 1026732ae5cSJean-Christophe PLAGNIOL-VILLARD * array is the same as pins. 1036732ae5cSJean-Christophe PLAGNIOL-VILLARD * @pins: an array of discrete physical pins used in this group, taken 1046732ae5cSJean-Christophe PLAGNIOL-VILLARD * from the driver-local pin enumeration space 1056732ae5cSJean-Christophe PLAGNIOL-VILLARD * @npins: the number of pins in this group array, i.e. the number of 1066732ae5cSJean-Christophe PLAGNIOL-VILLARD * elements in .pins so we can iterate over that array 1076732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 1086732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pin_group { 1096732ae5cSJean-Christophe PLAGNIOL-VILLARD const char *name; 1106732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pmx_pin *pins_conf; 1116732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned int *pins; 1126732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned npins; 1136732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 1146732ae5cSJean-Christophe PLAGNIOL-VILLARD 1156732ae5cSJean-Christophe PLAGNIOL-VILLARD /** 1166732ae5cSJean-Christophe PLAGNIOL-VILLARD * struct at91_pinctrl_mux_ops - describes an At91 mux ops group 1176732ae5cSJean-Christophe PLAGNIOL-VILLARD * on new IP with support for periph C and D the way to mux in 1186732ae5cSJean-Christophe PLAGNIOL-VILLARD * periph A and B has changed 1196732ae5cSJean-Christophe PLAGNIOL-VILLARD * So provide the right call back 1206732ae5cSJean-Christophe PLAGNIOL-VILLARD * if not present means the IP does not support it 1216732ae5cSJean-Christophe PLAGNIOL-VILLARD * @get_periph: return the periph mode configured 1226732ae5cSJean-Christophe PLAGNIOL-VILLARD * @mux_A_periph: mux as periph A 1236732ae5cSJean-Christophe PLAGNIOL-VILLARD * @mux_B_periph: mux as periph B 1246732ae5cSJean-Christophe PLAGNIOL-VILLARD * @mux_C_periph: mux as periph C 1256732ae5cSJean-Christophe PLAGNIOL-VILLARD * @mux_D_periph: mux as periph D 1266732ae5cSJean-Christophe PLAGNIOL-VILLARD * @irq_type: return irq type 1276732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 1286732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl_mux_ops { 1296732ae5cSJean-Christophe PLAGNIOL-VILLARD enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask); 1306732ae5cSJean-Christophe PLAGNIOL-VILLARD void (*mux_A_periph)(void __iomem *pio, unsigned mask); 1316732ae5cSJean-Christophe PLAGNIOL-VILLARD void (*mux_B_periph)(void __iomem *pio, unsigned mask); 1326732ae5cSJean-Christophe PLAGNIOL-VILLARD void (*mux_C_periph)(void __iomem *pio, unsigned mask); 1336732ae5cSJean-Christophe PLAGNIOL-VILLARD void (*mux_D_periph)(void __iomem *pio, unsigned mask); 1346732ae5cSJean-Christophe PLAGNIOL-VILLARD /* irq */ 1356732ae5cSJean-Christophe PLAGNIOL-VILLARD int (*irq_type)(struct irq_data *d, unsigned type); 1366732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 1376732ae5cSJean-Christophe PLAGNIOL-VILLARD 1386732ae5cSJean-Christophe PLAGNIOL-VILLARD static int gpio_irq_type(struct irq_data *d, unsigned type); 1396732ae5cSJean-Christophe PLAGNIOL-VILLARD static int alt_gpio_irq_type(struct irq_data *d, unsigned type); 1406732ae5cSJean-Christophe PLAGNIOL-VILLARD 1416732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl { 1426732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device *dev; 1436732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_dev *pctl; 1446732ae5cSJean-Christophe PLAGNIOL-VILLARD 1456732ae5cSJean-Christophe PLAGNIOL-VILLARD int nbanks; 1466732ae5cSJean-Christophe PLAGNIOL-VILLARD 1476732ae5cSJean-Christophe PLAGNIOL-VILLARD uint32_t *mux_mask; 1486732ae5cSJean-Christophe PLAGNIOL-VILLARD int nmux; 1496732ae5cSJean-Christophe PLAGNIOL-VILLARD 1506732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pmx_func *functions; 1516732ae5cSJean-Christophe PLAGNIOL-VILLARD int nfunctions; 1526732ae5cSJean-Christophe PLAGNIOL-VILLARD 1536732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pin_group *groups; 1546732ae5cSJean-Christophe PLAGNIOL-VILLARD int ngroups; 1556732ae5cSJean-Christophe PLAGNIOL-VILLARD 1566732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl_mux_ops *ops; 1576732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 1586732ae5cSJean-Christophe PLAGNIOL-VILLARD 1596732ae5cSJean-Christophe PLAGNIOL-VILLARD static const inline struct at91_pin_group *at91_pinctrl_find_group_by_name( 1606732ae5cSJean-Christophe PLAGNIOL-VILLARD const struct at91_pinctrl *info, 1616732ae5cSJean-Christophe PLAGNIOL-VILLARD const char *name) 1626732ae5cSJean-Christophe PLAGNIOL-VILLARD { 1636732ae5cSJean-Christophe PLAGNIOL-VILLARD const struct at91_pin_group *grp = NULL; 1646732ae5cSJean-Christophe PLAGNIOL-VILLARD int i; 1656732ae5cSJean-Christophe PLAGNIOL-VILLARD 1666732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < info->ngroups; i++) { 1676732ae5cSJean-Christophe PLAGNIOL-VILLARD if (strcmp(info->groups[i].name, name)) 1686732ae5cSJean-Christophe PLAGNIOL-VILLARD continue; 1696732ae5cSJean-Christophe PLAGNIOL-VILLARD 1706732ae5cSJean-Christophe PLAGNIOL-VILLARD grp = &info->groups[i]; 1716732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]); 1726732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 1736732ae5cSJean-Christophe PLAGNIOL-VILLARD } 1746732ae5cSJean-Christophe PLAGNIOL-VILLARD 1756732ae5cSJean-Christophe PLAGNIOL-VILLARD return grp; 1766732ae5cSJean-Christophe PLAGNIOL-VILLARD } 1776732ae5cSJean-Christophe PLAGNIOL-VILLARD 1786732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_get_groups_count(struct pinctrl_dev *pctldev) 1796732ae5cSJean-Christophe PLAGNIOL-VILLARD { 1806732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1816732ae5cSJean-Christophe PLAGNIOL-VILLARD 1826732ae5cSJean-Christophe PLAGNIOL-VILLARD return info->ngroups; 1836732ae5cSJean-Christophe PLAGNIOL-VILLARD } 1846732ae5cSJean-Christophe PLAGNIOL-VILLARD 1856732ae5cSJean-Christophe PLAGNIOL-VILLARD static const char *at91_get_group_name(struct pinctrl_dev *pctldev, 1866732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned selector) 1876732ae5cSJean-Christophe PLAGNIOL-VILLARD { 1886732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1896732ae5cSJean-Christophe PLAGNIOL-VILLARD 1906732ae5cSJean-Christophe PLAGNIOL-VILLARD return info->groups[selector].name; 1916732ae5cSJean-Christophe PLAGNIOL-VILLARD } 1926732ae5cSJean-Christophe PLAGNIOL-VILLARD 1936732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, 1946732ae5cSJean-Christophe PLAGNIOL-VILLARD const unsigned **pins, 1956732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned *npins) 1966732ae5cSJean-Christophe PLAGNIOL-VILLARD { 1976732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1986732ae5cSJean-Christophe PLAGNIOL-VILLARD 1996732ae5cSJean-Christophe PLAGNIOL-VILLARD if (selector >= info->ngroups) 2006732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 2016732ae5cSJean-Christophe PLAGNIOL-VILLARD 2026732ae5cSJean-Christophe PLAGNIOL-VILLARD *pins = info->groups[selector].pins; 2036732ae5cSJean-Christophe PLAGNIOL-VILLARD *npins = info->groups[selector].npins; 2046732ae5cSJean-Christophe PLAGNIOL-VILLARD 2056732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 2066732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2076732ae5cSJean-Christophe PLAGNIOL-VILLARD 2086732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 2096732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned offset) 2106732ae5cSJean-Christophe PLAGNIOL-VILLARD { 2116732ae5cSJean-Christophe PLAGNIOL-VILLARD seq_printf(s, "%s", dev_name(pctldev->dev)); 2126732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2136732ae5cSJean-Christophe PLAGNIOL-VILLARD 2146732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_dt_node_to_map(struct pinctrl_dev *pctldev, 2156732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *np, 2166732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_map **map, unsigned *num_maps) 2176732ae5cSJean-Christophe PLAGNIOL-VILLARD { 2186732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2196732ae5cSJean-Christophe PLAGNIOL-VILLARD const struct at91_pin_group *grp; 2206732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_map *new_map; 2216732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *parent; 2226732ae5cSJean-Christophe PLAGNIOL-VILLARD int map_num = 1; 2236732ae5cSJean-Christophe PLAGNIOL-VILLARD int i; 2246732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pmx_pin *pin; 2256732ae5cSJean-Christophe PLAGNIOL-VILLARD 2266732ae5cSJean-Christophe PLAGNIOL-VILLARD /* 2276732ae5cSJean-Christophe PLAGNIOL-VILLARD * first find the group of this node and check if we need create 2286732ae5cSJean-Christophe PLAGNIOL-VILLARD * config maps for pins 2296732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 2306732ae5cSJean-Christophe PLAGNIOL-VILLARD grp = at91_pinctrl_find_group_by_name(info, np->name); 2316732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!grp) { 2326732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "unable to find group for node %s\n", 2336732ae5cSJean-Christophe PLAGNIOL-VILLARD np->name); 2346732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 2356732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2366732ae5cSJean-Christophe PLAGNIOL-VILLARD 2376732ae5cSJean-Christophe PLAGNIOL-VILLARD map_num += grp->npins; 2386732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, GFP_KERNEL); 2396732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!new_map) 2406732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENOMEM; 2416732ae5cSJean-Christophe PLAGNIOL-VILLARD 2426732ae5cSJean-Christophe PLAGNIOL-VILLARD *map = new_map; 2436732ae5cSJean-Christophe PLAGNIOL-VILLARD *num_maps = map_num; 2446732ae5cSJean-Christophe PLAGNIOL-VILLARD 2456732ae5cSJean-Christophe PLAGNIOL-VILLARD /* create mux map */ 2466732ae5cSJean-Christophe PLAGNIOL-VILLARD parent = of_get_parent(np); 2476732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!parent) { 2486732ae5cSJean-Christophe PLAGNIOL-VILLARD kfree(new_map); 2496732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 2506732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2516732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 2526732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map[0].data.mux.function = parent->name; 2536732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map[0].data.mux.group = np->name; 2546732ae5cSJean-Christophe PLAGNIOL-VILLARD of_node_put(parent); 2556732ae5cSJean-Christophe PLAGNIOL-VILLARD 2566732ae5cSJean-Christophe PLAGNIOL-VILLARD /* create config map */ 2576732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map++; 2586732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < grp->npins; i++) { 2596732ae5cSJean-Christophe PLAGNIOL-VILLARD pin = &grp->pins_conf[i]; 2606732ae5cSJean-Christophe PLAGNIOL-VILLARD 2616732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 2626732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map[i].data.configs.group_or_pin = 2636732ae5cSJean-Christophe PLAGNIOL-VILLARD pin_get_name(pctldev, grp->pins[i]); 2646732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map[i].data.configs.configs = &grp->pins_conf[i].conf; 2656732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map[i].data.configs.num_configs = 1; 2666732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2676732ae5cSJean-Christophe PLAGNIOL-VILLARD 2686732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 2696732ae5cSJean-Christophe PLAGNIOL-VILLARD (*map)->data.mux.function, (*map)->data.mux.group, map_num); 2706732ae5cSJean-Christophe PLAGNIOL-VILLARD 2716732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 2726732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2736732ae5cSJean-Christophe PLAGNIOL-VILLARD 2746732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_dt_free_map(struct pinctrl_dev *pctldev, 2756732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_map *map, unsigned num_maps) 2766732ae5cSJean-Christophe PLAGNIOL-VILLARD { 2776732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2786732ae5cSJean-Christophe PLAGNIOL-VILLARD 2796732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct pinctrl_ops at91_pctrl_ops = { 2806732ae5cSJean-Christophe PLAGNIOL-VILLARD .get_groups_count = at91_get_groups_count, 2816732ae5cSJean-Christophe PLAGNIOL-VILLARD .get_group_name = at91_get_group_name, 2826732ae5cSJean-Christophe PLAGNIOL-VILLARD .get_group_pins = at91_get_group_pins, 2836732ae5cSJean-Christophe PLAGNIOL-VILLARD .pin_dbg_show = at91_pin_dbg_show, 2846732ae5cSJean-Christophe PLAGNIOL-VILLARD .dt_node_to_map = at91_dt_node_to_map, 2856732ae5cSJean-Christophe PLAGNIOL-VILLARD .dt_free_map = at91_dt_free_map, 2866732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 2876732ae5cSJean-Christophe PLAGNIOL-VILLARD 2886732ae5cSJean-Christophe PLAGNIOL-VILLARD static void __iomem * pin_to_controller(struct at91_pinctrl *info, 2896732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned int bank) 2906732ae5cSJean-Christophe PLAGNIOL-VILLARD { 2916732ae5cSJean-Christophe PLAGNIOL-VILLARD return gpio_chips[bank]->regbase; 2926732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2936732ae5cSJean-Christophe PLAGNIOL-VILLARD 2946732ae5cSJean-Christophe PLAGNIOL-VILLARD static inline int pin_to_bank(unsigned pin) 2956732ae5cSJean-Christophe PLAGNIOL-VILLARD { 2966732ae5cSJean-Christophe PLAGNIOL-VILLARD return pin /= MAX_NB_GPIO_PER_BANK; 2976732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2986732ae5cSJean-Christophe PLAGNIOL-VILLARD 2996732ae5cSJean-Christophe PLAGNIOL-VILLARD static unsigned pin_to_mask(unsigned int pin) 3006732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3016732ae5cSJean-Christophe PLAGNIOL-VILLARD return 1 << pin; 3026732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3036732ae5cSJean-Christophe PLAGNIOL-VILLARD 3046732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask) 3056732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3066732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_IDR); 3076732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3086732ae5cSJean-Christophe PLAGNIOL-VILLARD 3096732ae5cSJean-Christophe PLAGNIOL-VILLARD static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin) 3106732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3116732ae5cSJean-Christophe PLAGNIOL-VILLARD return (readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1; 3126732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3136732ae5cSJean-Christophe PLAGNIOL-VILLARD 3146732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on) 3156732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3166732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR)); 3176732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3186732ae5cSJean-Christophe PLAGNIOL-VILLARD 3196732ae5cSJean-Christophe PLAGNIOL-VILLARD static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin) 3206732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3216732ae5cSJean-Christophe PLAGNIOL-VILLARD return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1; 3226732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3236732ae5cSJean-Christophe PLAGNIOL-VILLARD 3246732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on) 3256732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3266732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR)); 3276732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3286732ae5cSJean-Christophe PLAGNIOL-VILLARD 3296732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask) 3306732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3316732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_ASR); 3326732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3336732ae5cSJean-Christophe PLAGNIOL-VILLARD 3346732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask) 3356732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3366732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_BSR); 3376732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3386732ae5cSJean-Christophe PLAGNIOL-VILLARD 3396732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask) 3406732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3416732ae5cSJean-Christophe PLAGNIOL-VILLARD 3426732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, 3436732ae5cSJean-Christophe PLAGNIOL-VILLARD pio + PIO_ABCDSR1); 3446732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, 3456732ae5cSJean-Christophe PLAGNIOL-VILLARD pio + PIO_ABCDSR2); 3466732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3476732ae5cSJean-Christophe PLAGNIOL-VILLARD 3486732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask) 3496732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3506732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, 3516732ae5cSJean-Christophe PLAGNIOL-VILLARD pio + PIO_ABCDSR1); 3526732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, 3536732ae5cSJean-Christophe PLAGNIOL-VILLARD pio + PIO_ABCDSR2); 3546732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3556732ae5cSJean-Christophe PLAGNIOL-VILLARD 3566732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask) 3576732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3586732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1); 3596732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); 3606732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3616732ae5cSJean-Christophe PLAGNIOL-VILLARD 3626732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask) 3636732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3646732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1); 3656732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); 3666732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3676732ae5cSJean-Christophe PLAGNIOL-VILLARD 3686732ae5cSJean-Christophe PLAGNIOL-VILLARD static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask) 3696732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3706732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned select; 3716732ae5cSJean-Christophe PLAGNIOL-VILLARD 3726732ae5cSJean-Christophe PLAGNIOL-VILLARD if (readl_relaxed(pio + PIO_PSR) & mask) 3736732ae5cSJean-Christophe PLAGNIOL-VILLARD return AT91_MUX_GPIO; 3746732ae5cSJean-Christophe PLAGNIOL-VILLARD 3756732ae5cSJean-Christophe PLAGNIOL-VILLARD select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask); 3766732ae5cSJean-Christophe PLAGNIOL-VILLARD select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1); 3776732ae5cSJean-Christophe PLAGNIOL-VILLARD 3786732ae5cSJean-Christophe PLAGNIOL-VILLARD return select + 1; 3796732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3806732ae5cSJean-Christophe PLAGNIOL-VILLARD 3816732ae5cSJean-Christophe PLAGNIOL-VILLARD static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask) 3826732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3836732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned select; 3846732ae5cSJean-Christophe PLAGNIOL-VILLARD 3856732ae5cSJean-Christophe PLAGNIOL-VILLARD if (readl_relaxed(pio + PIO_PSR) & mask) 3866732ae5cSJean-Christophe PLAGNIOL-VILLARD return AT91_MUX_GPIO; 3876732ae5cSJean-Christophe PLAGNIOL-VILLARD 3886732ae5cSJean-Christophe PLAGNIOL-VILLARD select = readl_relaxed(pio + PIO_ABSR) & mask; 3896732ae5cSJean-Christophe PLAGNIOL-VILLARD 3906732ae5cSJean-Christophe PLAGNIOL-VILLARD return select + 1; 3916732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3926732ae5cSJean-Christophe PLAGNIOL-VILLARD 3936732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct at91_pinctrl_mux_ops at91rm9200_ops = { 3946732ae5cSJean-Christophe PLAGNIOL-VILLARD .get_periph = at91_mux_get_periph, 3956732ae5cSJean-Christophe PLAGNIOL-VILLARD .mux_A_periph = at91_mux_set_A_periph, 3966732ae5cSJean-Christophe PLAGNIOL-VILLARD .mux_B_periph = at91_mux_set_B_periph, 3976732ae5cSJean-Christophe PLAGNIOL-VILLARD .irq_type = gpio_irq_type, 3986732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 3996732ae5cSJean-Christophe PLAGNIOL-VILLARD 4006732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct at91_pinctrl_mux_ops at91sam9x5_ops = { 4016732ae5cSJean-Christophe PLAGNIOL-VILLARD .get_periph = at91_mux_pio3_get_periph, 4026732ae5cSJean-Christophe PLAGNIOL-VILLARD .mux_A_periph = at91_mux_pio3_set_A_periph, 4036732ae5cSJean-Christophe PLAGNIOL-VILLARD .mux_B_periph = at91_mux_pio3_set_B_periph, 4046732ae5cSJean-Christophe PLAGNIOL-VILLARD .mux_C_periph = at91_mux_pio3_set_C_periph, 4056732ae5cSJean-Christophe PLAGNIOL-VILLARD .mux_D_periph = at91_mux_pio3_set_D_periph, 4066732ae5cSJean-Christophe PLAGNIOL-VILLARD .irq_type = alt_gpio_irq_type, 4076732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 4086732ae5cSJean-Christophe PLAGNIOL-VILLARD 4096732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin) 4106732ae5cSJean-Christophe PLAGNIOL-VILLARD { 4116732ae5cSJean-Christophe PLAGNIOL-VILLARD if (pin->mux) { 4126732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lu\n", 4136732ae5cSJean-Christophe PLAGNIOL-VILLARD pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf); 4146732ae5cSJean-Christophe PLAGNIOL-VILLARD } else { 4156732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lu\n", 4166732ae5cSJean-Christophe PLAGNIOL-VILLARD pin->bank + 'A', pin->pin, pin->conf); 4176732ae5cSJean-Christophe PLAGNIOL-VILLARD } 4186732ae5cSJean-Christophe PLAGNIOL-VILLARD } 4196732ae5cSJean-Christophe PLAGNIOL-VILLARD 4206732ae5cSJean-Christophe PLAGNIOL-VILLARD static int pin_check_config(struct at91_pinctrl *info, const char* name, 4216732ae5cSJean-Christophe PLAGNIOL-VILLARD int index, const struct at91_pmx_pin *pin) 4226732ae5cSJean-Christophe PLAGNIOL-VILLARD { 4236732ae5cSJean-Christophe PLAGNIOL-VILLARD int mux; 4246732ae5cSJean-Christophe PLAGNIOL-VILLARD 4256732ae5cSJean-Christophe PLAGNIOL-VILLARD /* check if it's a valid config */ 4266732ae5cSJean-Christophe PLAGNIOL-VILLARD if (pin->bank >= info->nbanks) { 4276732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n", 4286732ae5cSJean-Christophe PLAGNIOL-VILLARD name, index, pin->bank, info->nbanks); 4296732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 4306732ae5cSJean-Christophe PLAGNIOL-VILLARD } 4316732ae5cSJean-Christophe PLAGNIOL-VILLARD 4326732ae5cSJean-Christophe PLAGNIOL-VILLARD if (pin->pin >= MAX_NB_GPIO_PER_BANK) { 4336732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n", 4346732ae5cSJean-Christophe PLAGNIOL-VILLARD name, index, pin->pin, MAX_NB_GPIO_PER_BANK); 4356732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 4366732ae5cSJean-Christophe PLAGNIOL-VILLARD } 4376732ae5cSJean-Christophe PLAGNIOL-VILLARD 4386732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!pin->mux) 4396732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 4406732ae5cSJean-Christophe PLAGNIOL-VILLARD 4416732ae5cSJean-Christophe PLAGNIOL-VILLARD mux = pin->mux - 1; 4426732ae5cSJean-Christophe PLAGNIOL-VILLARD 4436732ae5cSJean-Christophe PLAGNIOL-VILLARD if (mux >= info->nmux) { 4446732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n", 4456732ae5cSJean-Christophe PLAGNIOL-VILLARD name, index, mux, info->nmux); 4466732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 4476732ae5cSJean-Christophe PLAGNIOL-VILLARD } 4486732ae5cSJean-Christophe PLAGNIOL-VILLARD 4496732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) { 4506732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n", 4516732ae5cSJean-Christophe PLAGNIOL-VILLARD name, index, mux, pin->bank + 'A', pin->pin); 4526732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 4536732ae5cSJean-Christophe PLAGNIOL-VILLARD } 4546732ae5cSJean-Christophe PLAGNIOL-VILLARD 4556732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 4566732ae5cSJean-Christophe PLAGNIOL-VILLARD } 4576732ae5cSJean-Christophe PLAGNIOL-VILLARD 4586732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask) 4596732ae5cSJean-Christophe PLAGNIOL-VILLARD { 4606732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_PDR); 4616732ae5cSJean-Christophe PLAGNIOL-VILLARD } 4626732ae5cSJean-Christophe PLAGNIOL-VILLARD 4636732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input) 4646732ae5cSJean-Christophe PLAGNIOL-VILLARD { 4656732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_PER); 4666732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER)); 4676732ae5cSJean-Christophe PLAGNIOL-VILLARD } 4686732ae5cSJean-Christophe PLAGNIOL-VILLARD 4696732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, 4706732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned group) 4716732ae5cSJean-Christophe PLAGNIOL-VILLARD { 4726732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 4736732ae5cSJean-Christophe PLAGNIOL-VILLARD const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf; 4746732ae5cSJean-Christophe PLAGNIOL-VILLARD const struct at91_pmx_pin *pin; 4756732ae5cSJean-Christophe PLAGNIOL-VILLARD uint32_t npins = info->groups[group].npins; 4766732ae5cSJean-Christophe PLAGNIOL-VILLARD int i, ret; 4776732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask; 4786732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio; 4796732ae5cSJean-Christophe PLAGNIOL-VILLARD 4806732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(info->dev, "enable function %s group %s\n", 4816732ae5cSJean-Christophe PLAGNIOL-VILLARD info->functions[selector].name, info->groups[group].name); 4826732ae5cSJean-Christophe PLAGNIOL-VILLARD 4836732ae5cSJean-Christophe PLAGNIOL-VILLARD /* first check that all the pins of the group are valid with a valid 4846732ae5cSJean-Christophe PLAGNIOL-VILLARD * paramter */ 4856732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < npins; i++) { 4866732ae5cSJean-Christophe PLAGNIOL-VILLARD pin = &pins_conf[i]; 4876732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = pin_check_config(info, info->groups[group].name, i, pin); 4886732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ret) 4896732ae5cSJean-Christophe PLAGNIOL-VILLARD return ret; 4906732ae5cSJean-Christophe PLAGNIOL-VILLARD } 4916732ae5cSJean-Christophe PLAGNIOL-VILLARD 4926732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < npins; i++) { 4936732ae5cSJean-Christophe PLAGNIOL-VILLARD pin = &pins_conf[i]; 4946732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_pin_dbg(info->dev, pin); 4956732ae5cSJean-Christophe PLAGNIOL-VILLARD pio = pin_to_controller(info, pin->bank); 4966732ae5cSJean-Christophe PLAGNIOL-VILLARD mask = pin_to_mask(pin->pin); 4976732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_mux_disable_interrupt(pio, mask); 4986732ae5cSJean-Christophe PLAGNIOL-VILLARD switch(pin->mux) { 4996732ae5cSJean-Christophe PLAGNIOL-VILLARD case AT91_MUX_GPIO: 5006732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_mux_gpio_enable(pio, mask, 1); 5016732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 5026732ae5cSJean-Christophe PLAGNIOL-VILLARD case AT91_MUX_PERIPH_A: 5036732ae5cSJean-Christophe PLAGNIOL-VILLARD info->ops->mux_A_periph(pio, mask); 5046732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 5056732ae5cSJean-Christophe PLAGNIOL-VILLARD case AT91_MUX_PERIPH_B: 5066732ae5cSJean-Christophe PLAGNIOL-VILLARD info->ops->mux_B_periph(pio, mask); 5076732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 5086732ae5cSJean-Christophe PLAGNIOL-VILLARD case AT91_MUX_PERIPH_C: 5096732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!info->ops->mux_C_periph) 5106732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 5116732ae5cSJean-Christophe PLAGNIOL-VILLARD info->ops->mux_C_periph(pio, mask); 5126732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 5136732ae5cSJean-Christophe PLAGNIOL-VILLARD case AT91_MUX_PERIPH_D: 5146732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!info->ops->mux_D_periph) 5156732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 5166732ae5cSJean-Christophe PLAGNIOL-VILLARD info->ops->mux_D_periph(pio, mask); 5176732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 5186732ae5cSJean-Christophe PLAGNIOL-VILLARD } 5196732ae5cSJean-Christophe PLAGNIOL-VILLARD if (pin->mux) 5206732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_mux_gpio_disable(pio, mask); 5216732ae5cSJean-Christophe PLAGNIOL-VILLARD } 5226732ae5cSJean-Christophe PLAGNIOL-VILLARD 5236732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 5246732ae5cSJean-Christophe PLAGNIOL-VILLARD } 5256732ae5cSJean-Christophe PLAGNIOL-VILLARD 5266732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector, 5276732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned group) 5286732ae5cSJean-Christophe PLAGNIOL-VILLARD { 5296732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 5306732ae5cSJean-Christophe PLAGNIOL-VILLARD const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf; 5316732ae5cSJean-Christophe PLAGNIOL-VILLARD const struct at91_pmx_pin *pin; 5326732ae5cSJean-Christophe PLAGNIOL-VILLARD uint32_t npins = info->groups[group].npins; 5336732ae5cSJean-Christophe PLAGNIOL-VILLARD int i; 5346732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask; 5356732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio; 5366732ae5cSJean-Christophe PLAGNIOL-VILLARD 5376732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < npins; i++) { 5386732ae5cSJean-Christophe PLAGNIOL-VILLARD pin = &pins_conf[i]; 5396732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_pin_dbg(info->dev, pin); 5406732ae5cSJean-Christophe PLAGNIOL-VILLARD pio = pin_to_controller(info, pin->bank); 5416732ae5cSJean-Christophe PLAGNIOL-VILLARD mask = pin_to_mask(pin->pin); 5426732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_mux_gpio_enable(pio, mask, 1); 5436732ae5cSJean-Christophe PLAGNIOL-VILLARD } 5446732ae5cSJean-Christophe PLAGNIOL-VILLARD } 5456732ae5cSJean-Christophe PLAGNIOL-VILLARD 5466732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 5476732ae5cSJean-Christophe PLAGNIOL-VILLARD { 5486732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 5496732ae5cSJean-Christophe PLAGNIOL-VILLARD 5506732ae5cSJean-Christophe PLAGNIOL-VILLARD return info->nfunctions; 5516732ae5cSJean-Christophe PLAGNIOL-VILLARD } 5526732ae5cSJean-Christophe PLAGNIOL-VILLARD 5536732ae5cSJean-Christophe PLAGNIOL-VILLARD static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev, 5546732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned selector) 5556732ae5cSJean-Christophe PLAGNIOL-VILLARD { 5566732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 5576732ae5cSJean-Christophe PLAGNIOL-VILLARD 5586732ae5cSJean-Christophe PLAGNIOL-VILLARD return info->functions[selector].name; 5596732ae5cSJean-Christophe PLAGNIOL-VILLARD } 5606732ae5cSJean-Christophe PLAGNIOL-VILLARD 5616732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, 5626732ae5cSJean-Christophe PLAGNIOL-VILLARD const char * const **groups, 5636732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned * const num_groups) 5646732ae5cSJean-Christophe PLAGNIOL-VILLARD { 5656732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 5666732ae5cSJean-Christophe PLAGNIOL-VILLARD 5676732ae5cSJean-Christophe PLAGNIOL-VILLARD *groups = info->functions[selector].groups; 5686732ae5cSJean-Christophe PLAGNIOL-VILLARD *num_groups = info->functions[selector].ngroups; 5696732ae5cSJean-Christophe PLAGNIOL-VILLARD 5706732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 5716732ae5cSJean-Christophe PLAGNIOL-VILLARD } 5726732ae5cSJean-Christophe PLAGNIOL-VILLARD 5736732ae5cSJean-Christophe PLAGNIOL-VILLARD int at91_gpio_request_enable(struct pinctrl_dev *pctldev, 5746732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_gpio_range *range, 5756732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned offset) 5766732ae5cSJean-Christophe PLAGNIOL-VILLARD { 5776732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 5786732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_chip; 5796732ae5cSJean-Christophe PLAGNIOL-VILLARD struct gpio_chip *chip; 5806732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask; 5816732ae5cSJean-Christophe PLAGNIOL-VILLARD 5826732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!range) { 5836732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(npct->dev, "invalid range\n"); 5846732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 5856732ae5cSJean-Christophe PLAGNIOL-VILLARD } 5866732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!range->gc) { 5876732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(npct->dev, "missing GPIO chip in range\n"); 5886732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 5896732ae5cSJean-Christophe PLAGNIOL-VILLARD } 5906732ae5cSJean-Christophe PLAGNIOL-VILLARD chip = range->gc; 5916732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_chip = container_of(chip, struct at91_gpio_chip, chip); 5926732ae5cSJean-Christophe PLAGNIOL-VILLARD 5936732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); 5946732ae5cSJean-Christophe PLAGNIOL-VILLARD 5956732ae5cSJean-Christophe PLAGNIOL-VILLARD mask = 1 << (offset - chip->base); 5966732ae5cSJean-Christophe PLAGNIOL-VILLARD 5976732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n", 5986732ae5cSJean-Christophe PLAGNIOL-VILLARD offset, 'A' + range->id, offset - chip->base, mask); 5996732ae5cSJean-Christophe PLAGNIOL-VILLARD 6006732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, at91_chip->regbase + PIO_PER); 6016732ae5cSJean-Christophe PLAGNIOL-VILLARD 6026732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 6036732ae5cSJean-Christophe PLAGNIOL-VILLARD } 6046732ae5cSJean-Christophe PLAGNIOL-VILLARD 6056732ae5cSJean-Christophe PLAGNIOL-VILLARD void at91_gpio_disable_free(struct pinctrl_dev *pctldev, 6066732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_gpio_range *range, 6076732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned offset) 6086732ae5cSJean-Christophe PLAGNIOL-VILLARD { 6096732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 6106732ae5cSJean-Christophe PLAGNIOL-VILLARD 6116732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); 6126732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Set the pin to some default state, GPIO is usually default */ 6136732ae5cSJean-Christophe PLAGNIOL-VILLARD } 6146732ae5cSJean-Christophe PLAGNIOL-VILLARD 6156732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct pinmux_ops at91_pmx_ops = { 6166732ae5cSJean-Christophe PLAGNIOL-VILLARD .get_functions_count = at91_pmx_get_funcs_count, 6176732ae5cSJean-Christophe PLAGNIOL-VILLARD .get_function_name = at91_pmx_get_func_name, 6186732ae5cSJean-Christophe PLAGNIOL-VILLARD .get_function_groups = at91_pmx_get_groups, 6196732ae5cSJean-Christophe PLAGNIOL-VILLARD .enable = at91_pmx_enable, 6206732ae5cSJean-Christophe PLAGNIOL-VILLARD .disable = at91_pmx_disable, 6216732ae5cSJean-Christophe PLAGNIOL-VILLARD .gpio_request_enable = at91_gpio_request_enable, 6226732ae5cSJean-Christophe PLAGNIOL-VILLARD .gpio_disable_free = at91_gpio_disable_free, 6236732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 6246732ae5cSJean-Christophe PLAGNIOL-VILLARD 6256732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_pinconf_get(struct pinctrl_dev *pctldev, 6266732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned pin_id, unsigned long *config) 6276732ae5cSJean-Christophe PLAGNIOL-VILLARD { 6286732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 6296732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio; 6306732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned pin; 6316732ae5cSJean-Christophe PLAGNIOL-VILLARD 6326732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, *config); 6336732ae5cSJean-Christophe PLAGNIOL-VILLARD pio = pin_to_controller(info, pin_to_bank(pin_id)); 6346732ae5cSJean-Christophe PLAGNIOL-VILLARD pin = pin_id % MAX_NB_GPIO_PER_BANK; 6356732ae5cSJean-Christophe PLAGNIOL-VILLARD 6366732ae5cSJean-Christophe PLAGNIOL-VILLARD if (at91_mux_get_multidrive(pio, pin)) 6376732ae5cSJean-Christophe PLAGNIOL-VILLARD *config |= MULTI_DRIVE; 6386732ae5cSJean-Christophe PLAGNIOL-VILLARD 6396732ae5cSJean-Christophe PLAGNIOL-VILLARD if (at91_mux_get_pullup(pio, pin)) 6406732ae5cSJean-Christophe PLAGNIOL-VILLARD *config |= PULL_UP; 6416732ae5cSJean-Christophe PLAGNIOL-VILLARD 6426732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 6436732ae5cSJean-Christophe PLAGNIOL-VILLARD } 6446732ae5cSJean-Christophe PLAGNIOL-VILLARD 6456732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_pinconf_set(struct pinctrl_dev *pctldev, 6466732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned pin_id, unsigned long config) 6476732ae5cSJean-Christophe PLAGNIOL-VILLARD { 6486732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 6496732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask; 6506732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio; 6516732ae5cSJean-Christophe PLAGNIOL-VILLARD 6526732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, config); 6536732ae5cSJean-Christophe PLAGNIOL-VILLARD pio = pin_to_controller(info, pin_to_bank(pin_id)); 6546732ae5cSJean-Christophe PLAGNIOL-VILLARD mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK); 6556732ae5cSJean-Christophe PLAGNIOL-VILLARD 6566732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_mux_set_pullup(pio, mask, config & PULL_UP); 6576732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE); 6586732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 6596732ae5cSJean-Christophe PLAGNIOL-VILLARD } 6606732ae5cSJean-Christophe PLAGNIOL-VILLARD 6616732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev, 6626732ae5cSJean-Christophe PLAGNIOL-VILLARD struct seq_file *s, unsigned pin_id) 6636732ae5cSJean-Christophe PLAGNIOL-VILLARD { 6646732ae5cSJean-Christophe PLAGNIOL-VILLARD 6656732ae5cSJean-Christophe PLAGNIOL-VILLARD } 6666732ae5cSJean-Christophe PLAGNIOL-VILLARD 6676732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 6686732ae5cSJean-Christophe PLAGNIOL-VILLARD struct seq_file *s, unsigned group) 6696732ae5cSJean-Christophe PLAGNIOL-VILLARD { 6706732ae5cSJean-Christophe PLAGNIOL-VILLARD } 6716732ae5cSJean-Christophe PLAGNIOL-VILLARD 6726732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinconf_ops at91_pinconf_ops = { 6736732ae5cSJean-Christophe PLAGNIOL-VILLARD .pin_config_get = at91_pinconf_get, 6746732ae5cSJean-Christophe PLAGNIOL-VILLARD .pin_config_set = at91_pinconf_set, 6756732ae5cSJean-Christophe PLAGNIOL-VILLARD .pin_config_dbg_show = at91_pinconf_dbg_show, 6766732ae5cSJean-Christophe PLAGNIOL-VILLARD .pin_config_group_dbg_show = at91_pinconf_group_dbg_show, 6776732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 6786732ae5cSJean-Christophe PLAGNIOL-VILLARD 6796732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct pinctrl_desc at91_pinctrl_desc = { 6806732ae5cSJean-Christophe PLAGNIOL-VILLARD .pctlops = &at91_pctrl_ops, 6816732ae5cSJean-Christophe PLAGNIOL-VILLARD .pmxops = &at91_pmx_ops, 6826732ae5cSJean-Christophe PLAGNIOL-VILLARD .confops = &at91_pinconf_ops, 6836732ae5cSJean-Christophe PLAGNIOL-VILLARD .owner = THIS_MODULE, 6846732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 6856732ae5cSJean-Christophe PLAGNIOL-VILLARD 6866732ae5cSJean-Christophe PLAGNIOL-VILLARD static const char *gpio_compat = "atmel,at91rm9200-gpio"; 6876732ae5cSJean-Christophe PLAGNIOL-VILLARD 6886732ae5cSJean-Christophe PLAGNIOL-VILLARD static void __devinit at91_pinctrl_child_count(struct at91_pinctrl *info, 6896732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *np) 6906732ae5cSJean-Christophe PLAGNIOL-VILLARD { 6916732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *child; 6926732ae5cSJean-Christophe PLAGNIOL-VILLARD 6936732ae5cSJean-Christophe PLAGNIOL-VILLARD for_each_child_of_node(np, child) { 6946732ae5cSJean-Christophe PLAGNIOL-VILLARD if (of_device_is_compatible(child, gpio_compat)) { 6956732ae5cSJean-Christophe PLAGNIOL-VILLARD info->nbanks++; 6966732ae5cSJean-Christophe PLAGNIOL-VILLARD } else { 6976732ae5cSJean-Christophe PLAGNIOL-VILLARD info->nfunctions++; 6986732ae5cSJean-Christophe PLAGNIOL-VILLARD info->ngroups += of_get_child_count(child); 6996732ae5cSJean-Christophe PLAGNIOL-VILLARD } 7006732ae5cSJean-Christophe PLAGNIOL-VILLARD } 7016732ae5cSJean-Christophe PLAGNIOL-VILLARD } 7026732ae5cSJean-Christophe PLAGNIOL-VILLARD 7036732ae5cSJean-Christophe PLAGNIOL-VILLARD static int __devinit at91_pinctrl_mux_mask(struct at91_pinctrl *info, 7046732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *np) 7056732ae5cSJean-Christophe PLAGNIOL-VILLARD { 7066732ae5cSJean-Christophe PLAGNIOL-VILLARD int ret = 0; 7076732ae5cSJean-Christophe PLAGNIOL-VILLARD int size; 7086732ae5cSJean-Christophe PLAGNIOL-VILLARD const const __be32 *list; 7096732ae5cSJean-Christophe PLAGNIOL-VILLARD 7106732ae5cSJean-Christophe PLAGNIOL-VILLARD list = of_get_property(np, "atmel,mux-mask", &size); 7116732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!list) { 7126732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "can not read the mux-mask of %d\n", size); 7136732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 7146732ae5cSJean-Christophe PLAGNIOL-VILLARD } 7156732ae5cSJean-Christophe PLAGNIOL-VILLARD 7166732ae5cSJean-Christophe PLAGNIOL-VILLARD size /= sizeof(*list); 7176732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!size || size % info->nbanks) { 7186732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "wrong mux mask array should be by %d\n", info->nbanks); 7196732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 7206732ae5cSJean-Christophe PLAGNIOL-VILLARD } 7216732ae5cSJean-Christophe PLAGNIOL-VILLARD info->nmux = size / info->nbanks; 7226732ae5cSJean-Christophe PLAGNIOL-VILLARD 7236732ae5cSJean-Christophe PLAGNIOL-VILLARD info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL); 7246732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!info->mux_mask) { 7256732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "could not alloc mux_mask\n"); 7266732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENOMEM; 7276732ae5cSJean-Christophe PLAGNIOL-VILLARD } 7286732ae5cSJean-Christophe PLAGNIOL-VILLARD 7296732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = of_property_read_u32_array(np, "atmel,mux-mask", 7306732ae5cSJean-Christophe PLAGNIOL-VILLARD info->mux_mask, size); 7316732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ret) 7326732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "can not read the mux-mask of %d\n", size); 7336732ae5cSJean-Christophe PLAGNIOL-VILLARD return ret; 7346732ae5cSJean-Christophe PLAGNIOL-VILLARD } 7356732ae5cSJean-Christophe PLAGNIOL-VILLARD 7366732ae5cSJean-Christophe PLAGNIOL-VILLARD static int __devinit at91_pinctrl_parse_groups(struct device_node *np, 7376732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pin_group *grp, 7386732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info, 7396732ae5cSJean-Christophe PLAGNIOL-VILLARD u32 index) 7406732ae5cSJean-Christophe PLAGNIOL-VILLARD { 7416732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pmx_pin *pin; 7426732ae5cSJean-Christophe PLAGNIOL-VILLARD int size; 7436732ae5cSJean-Christophe PLAGNIOL-VILLARD const const __be32 *list; 7446732ae5cSJean-Christophe PLAGNIOL-VILLARD int i, j; 7456732ae5cSJean-Christophe PLAGNIOL-VILLARD 7466732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(info->dev, "group(%d): %s\n", index, np->name); 7476732ae5cSJean-Christophe PLAGNIOL-VILLARD 7486732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Initialise group */ 7496732ae5cSJean-Christophe PLAGNIOL-VILLARD grp->name = np->name; 7506732ae5cSJean-Christophe PLAGNIOL-VILLARD 7516732ae5cSJean-Christophe PLAGNIOL-VILLARD /* 7526732ae5cSJean-Christophe PLAGNIOL-VILLARD * the binding format is atmel,pins = <bank pin mux CONFIG ...>, 7536732ae5cSJean-Christophe PLAGNIOL-VILLARD * do sanity check and calculate pins number 7546732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 7556732ae5cSJean-Christophe PLAGNIOL-VILLARD list = of_get_property(np, "atmel,pins", &size); 7566732ae5cSJean-Christophe PLAGNIOL-VILLARD /* we do not check return since it's safe node passed down */ 7576732ae5cSJean-Christophe PLAGNIOL-VILLARD size /= sizeof(*list); 7586732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!size || size % 4) { 7596732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); 7606732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 7616732ae5cSJean-Christophe PLAGNIOL-VILLARD } 7626732ae5cSJean-Christophe PLAGNIOL-VILLARD 7636732ae5cSJean-Christophe PLAGNIOL-VILLARD grp->npins = size / 4; 7646732ae5cSJean-Christophe PLAGNIOL-VILLARD pin = grp->pins_conf = devm_kzalloc(info->dev, grp->npins * sizeof(struct at91_pmx_pin), 7656732ae5cSJean-Christophe PLAGNIOL-VILLARD GFP_KERNEL); 7666732ae5cSJean-Christophe PLAGNIOL-VILLARD grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), 7676732ae5cSJean-Christophe PLAGNIOL-VILLARD GFP_KERNEL); 7686732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!grp->pins_conf || !grp->pins) 7696732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENOMEM; 7706732ae5cSJean-Christophe PLAGNIOL-VILLARD 7716732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0, j = 0; i < size; i += 4, j++) { 7726732ae5cSJean-Christophe PLAGNIOL-VILLARD pin->bank = be32_to_cpu(*list++); 7736732ae5cSJean-Christophe PLAGNIOL-VILLARD pin->pin = be32_to_cpu(*list++); 7746732ae5cSJean-Christophe PLAGNIOL-VILLARD grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin; 7756732ae5cSJean-Christophe PLAGNIOL-VILLARD pin->mux = be32_to_cpu(*list++); 7766732ae5cSJean-Christophe PLAGNIOL-VILLARD pin->conf = be32_to_cpu(*list++); 7776732ae5cSJean-Christophe PLAGNIOL-VILLARD 7786732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_pin_dbg(info->dev, pin); 7796732ae5cSJean-Christophe PLAGNIOL-VILLARD pin++; 7806732ae5cSJean-Christophe PLAGNIOL-VILLARD } 7816732ae5cSJean-Christophe PLAGNIOL-VILLARD 7826732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 7836732ae5cSJean-Christophe PLAGNIOL-VILLARD } 7846732ae5cSJean-Christophe PLAGNIOL-VILLARD 7856732ae5cSJean-Christophe PLAGNIOL-VILLARD static int __devinit at91_pinctrl_parse_functions(struct device_node *np, 7866732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info, u32 index) 7876732ae5cSJean-Christophe PLAGNIOL-VILLARD { 7886732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *child; 7896732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pmx_func *func; 7906732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pin_group *grp; 7916732ae5cSJean-Christophe PLAGNIOL-VILLARD int ret; 7926732ae5cSJean-Christophe PLAGNIOL-VILLARD static u32 grp_index; 7936732ae5cSJean-Christophe PLAGNIOL-VILLARD u32 i = 0; 7946732ae5cSJean-Christophe PLAGNIOL-VILLARD 7956732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); 7966732ae5cSJean-Christophe PLAGNIOL-VILLARD 7976732ae5cSJean-Christophe PLAGNIOL-VILLARD func = &info->functions[index]; 7986732ae5cSJean-Christophe PLAGNIOL-VILLARD 7996732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Initialise function */ 8006732ae5cSJean-Christophe PLAGNIOL-VILLARD func->name = np->name; 8016732ae5cSJean-Christophe PLAGNIOL-VILLARD func->ngroups = of_get_child_count(np); 8026732ae5cSJean-Christophe PLAGNIOL-VILLARD if (func->ngroups <= 0) { 8036732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "no groups defined\n"); 8046732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 8056732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8066732ae5cSJean-Christophe PLAGNIOL-VILLARD func->groups = devm_kzalloc(info->dev, 8076732ae5cSJean-Christophe PLAGNIOL-VILLARD func->ngroups * sizeof(char *), GFP_KERNEL); 8086732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!func->groups) 8096732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENOMEM; 8106732ae5cSJean-Christophe PLAGNIOL-VILLARD 8116732ae5cSJean-Christophe PLAGNIOL-VILLARD for_each_child_of_node(np, child) { 8126732ae5cSJean-Christophe PLAGNIOL-VILLARD func->groups[i] = child->name; 8136732ae5cSJean-Christophe PLAGNIOL-VILLARD grp = &info->groups[grp_index++]; 8146732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = at91_pinctrl_parse_groups(child, grp, info, i++); 8156732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ret) 8166732ae5cSJean-Christophe PLAGNIOL-VILLARD return ret; 8176732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8186732ae5cSJean-Christophe PLAGNIOL-VILLARD 8196732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 8206732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8216732ae5cSJean-Christophe PLAGNIOL-VILLARD 8226732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct of_device_id at91_pinctrl_of_match[] __devinitdata = { 8236732ae5cSJean-Christophe PLAGNIOL-VILLARD { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops }, 8246732ae5cSJean-Christophe PLAGNIOL-VILLARD { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops }, 8256732ae5cSJean-Christophe PLAGNIOL-VILLARD { /* sentinel */ } 8266732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 8276732ae5cSJean-Christophe PLAGNIOL-VILLARD 8286732ae5cSJean-Christophe PLAGNIOL-VILLARD static int __devinit at91_pinctrl_probe_dt(struct platform_device *pdev, 8296732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info) 8306732ae5cSJean-Christophe PLAGNIOL-VILLARD { 8316732ae5cSJean-Christophe PLAGNIOL-VILLARD int ret = 0; 8326732ae5cSJean-Christophe PLAGNIOL-VILLARD int i, j; 8336732ae5cSJean-Christophe PLAGNIOL-VILLARD uint32_t *tmp; 8346732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *np = pdev->dev.of_node; 8356732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *child; 8366732ae5cSJean-Christophe PLAGNIOL-VILLARD 8376732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!np) 8386732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENODEV; 8396732ae5cSJean-Christophe PLAGNIOL-VILLARD 8406732ae5cSJean-Christophe PLAGNIOL-VILLARD info->dev = &pdev->dev; 8416732ae5cSJean-Christophe PLAGNIOL-VILLARD info->ops = 8426732ae5cSJean-Christophe PLAGNIOL-VILLARD of_match_device(at91_pinctrl_of_match, &pdev->dev)->data; 8436732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_pinctrl_child_count(info, np); 8446732ae5cSJean-Christophe PLAGNIOL-VILLARD 8456732ae5cSJean-Christophe PLAGNIOL-VILLARD if (info->nbanks < 1) { 8466732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(&pdev->dev, "you need to specify atleast one gpio-controller\n"); 8476732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 8486732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8496732ae5cSJean-Christophe PLAGNIOL-VILLARD 8506732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = at91_pinctrl_mux_mask(info, np); 8516732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ret) 8526732ae5cSJean-Christophe PLAGNIOL-VILLARD return ret; 8536732ae5cSJean-Christophe PLAGNIOL-VILLARD 8546732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux); 8556732ae5cSJean-Christophe PLAGNIOL-VILLARD 8566732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(&pdev->dev, "mux-mask\n"); 8576732ae5cSJean-Christophe PLAGNIOL-VILLARD tmp = info->mux_mask; 8586732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < info->nbanks; i++) { 8596732ae5cSJean-Christophe PLAGNIOL-VILLARD for (j = 0; j < info->nmux; j++, tmp++) { 8606732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]); 8616732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8626732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8636732ae5cSJean-Christophe PLAGNIOL-VILLARD 8646732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 8656732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 8666732ae5cSJean-Christophe PLAGNIOL-VILLARD info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * sizeof(struct at91_pmx_func), 8676732ae5cSJean-Christophe PLAGNIOL-VILLARD GFP_KERNEL); 8686732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!info->functions) 8696732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENOMEM; 8706732ae5cSJean-Christophe PLAGNIOL-VILLARD 8716732ae5cSJean-Christophe PLAGNIOL-VILLARD info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct at91_pin_group), 8726732ae5cSJean-Christophe PLAGNIOL-VILLARD GFP_KERNEL); 8736732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!info->groups) 8746732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENOMEM; 8756732ae5cSJean-Christophe PLAGNIOL-VILLARD 8766732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks); 8776732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 8786732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 8796732ae5cSJean-Christophe PLAGNIOL-VILLARD 8806732ae5cSJean-Christophe PLAGNIOL-VILLARD i = 0; 8816732ae5cSJean-Christophe PLAGNIOL-VILLARD 8826732ae5cSJean-Christophe PLAGNIOL-VILLARD for_each_child_of_node(np, child) { 8836732ae5cSJean-Christophe PLAGNIOL-VILLARD if (of_device_is_compatible(child, gpio_compat)) 8846732ae5cSJean-Christophe PLAGNIOL-VILLARD continue; 8856732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = at91_pinctrl_parse_functions(child, info, i++); 8866732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ret) { 8876732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(&pdev->dev, "failed to parse function\n"); 8886732ae5cSJean-Christophe PLAGNIOL-VILLARD return ret; 8896732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8906732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8916732ae5cSJean-Christophe PLAGNIOL-VILLARD 8926732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 8936732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8946732ae5cSJean-Christophe PLAGNIOL-VILLARD 8956732ae5cSJean-Christophe PLAGNIOL-VILLARD static int __devinit at91_pinctrl_probe(struct platform_device *pdev) 8966732ae5cSJean-Christophe PLAGNIOL-VILLARD { 8976732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info; 8986732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_pin_desc *pdesc; 8996732ae5cSJean-Christophe PLAGNIOL-VILLARD int ret, i, j ,k; 9006732ae5cSJean-Christophe PLAGNIOL-VILLARD 9016732ae5cSJean-Christophe PLAGNIOL-VILLARD info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); 9026732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!info) 9036732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENOMEM; 9046732ae5cSJean-Christophe PLAGNIOL-VILLARD 9056732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = at91_pinctrl_probe_dt(pdev, info); 9066732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ret) 9076732ae5cSJean-Christophe PLAGNIOL-VILLARD return ret; 9086732ae5cSJean-Christophe PLAGNIOL-VILLARD 9096732ae5cSJean-Christophe PLAGNIOL-VILLARD /* 9106732ae5cSJean-Christophe PLAGNIOL-VILLARD * We need all the GPIO drivers to probe FIRST, or we will not be able 9116732ae5cSJean-Christophe PLAGNIOL-VILLARD * to obtain references to the struct gpio_chip * for them, and we 9126732ae5cSJean-Christophe PLAGNIOL-VILLARD * need this to proceed. 9136732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 9146732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < info->nbanks; i++) { 9156732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!gpio_chips[i]) { 9166732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i); 9176732ae5cSJean-Christophe PLAGNIOL-VILLARD devm_kfree(&pdev->dev, info); 9186732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EPROBE_DEFER; 9196732ae5cSJean-Christophe PLAGNIOL-VILLARD } 9206732ae5cSJean-Christophe PLAGNIOL-VILLARD } 9216732ae5cSJean-Christophe PLAGNIOL-VILLARD 9226732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_pinctrl_desc.name = dev_name(&pdev->dev); 9236732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK; 9246732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_pinctrl_desc.pins = pdesc = 9256732ae5cSJean-Christophe PLAGNIOL-VILLARD devm_kzalloc(&pdev->dev, sizeof(*pdesc) * at91_pinctrl_desc.npins, GFP_KERNEL); 9266732ae5cSJean-Christophe PLAGNIOL-VILLARD 9276732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!at91_pinctrl_desc.pins) 9286732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENOMEM; 9296732ae5cSJean-Christophe PLAGNIOL-VILLARD 9306732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0 , k = 0; i < info->nbanks; i++) { 9316732ae5cSJean-Christophe PLAGNIOL-VILLARD for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) { 9326732ae5cSJean-Christophe PLAGNIOL-VILLARD pdesc->number = k; 9336732ae5cSJean-Christophe PLAGNIOL-VILLARD pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j); 9346732ae5cSJean-Christophe PLAGNIOL-VILLARD pdesc++; 9356732ae5cSJean-Christophe PLAGNIOL-VILLARD } 9366732ae5cSJean-Christophe PLAGNIOL-VILLARD } 9376732ae5cSJean-Christophe PLAGNIOL-VILLARD 9386732ae5cSJean-Christophe PLAGNIOL-VILLARD platform_set_drvdata(pdev, info); 9396732ae5cSJean-Christophe PLAGNIOL-VILLARD info->pctl = pinctrl_register(&at91_pinctrl_desc, &pdev->dev, info); 9406732ae5cSJean-Christophe PLAGNIOL-VILLARD 9416732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!info->pctl) { 9426732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n"); 9436732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = -EINVAL; 9446732ae5cSJean-Christophe PLAGNIOL-VILLARD goto err; 9456732ae5cSJean-Christophe PLAGNIOL-VILLARD } 9466732ae5cSJean-Christophe PLAGNIOL-VILLARD 9476732ae5cSJean-Christophe PLAGNIOL-VILLARD /* We will handle a range of GPIO pins */ 9486732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < info->nbanks; i++) 9496732ae5cSJean-Christophe PLAGNIOL-VILLARD pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range); 9506732ae5cSJean-Christophe PLAGNIOL-VILLARD 9516732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n"); 9526732ae5cSJean-Christophe PLAGNIOL-VILLARD 9536732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 9546732ae5cSJean-Christophe PLAGNIOL-VILLARD 9556732ae5cSJean-Christophe PLAGNIOL-VILLARD err: 9566732ae5cSJean-Christophe PLAGNIOL-VILLARD return ret; 9576732ae5cSJean-Christophe PLAGNIOL-VILLARD } 9586732ae5cSJean-Christophe PLAGNIOL-VILLARD 9596732ae5cSJean-Christophe PLAGNIOL-VILLARD int __devexit at91_pinctrl_remove(struct platform_device *pdev) 9606732ae5cSJean-Christophe PLAGNIOL-VILLARD { 9616732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = platform_get_drvdata(pdev); 9626732ae5cSJean-Christophe PLAGNIOL-VILLARD 9636732ae5cSJean-Christophe PLAGNIOL-VILLARD pinctrl_unregister(info->pctl); 9646732ae5cSJean-Christophe PLAGNIOL-VILLARD 9656732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 9666732ae5cSJean-Christophe PLAGNIOL-VILLARD } 9676732ae5cSJean-Christophe PLAGNIOL-VILLARD 9686732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_gpio_request(struct gpio_chip *chip, unsigned offset) 9696732ae5cSJean-Christophe PLAGNIOL-VILLARD { 9706732ae5cSJean-Christophe PLAGNIOL-VILLARD /* 9716732ae5cSJean-Christophe PLAGNIOL-VILLARD * Map back to global GPIO space and request muxing, the direction 9726732ae5cSJean-Christophe PLAGNIOL-VILLARD * parameter does not matter for this controller. 9736732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 9746732ae5cSJean-Christophe PLAGNIOL-VILLARD int gpio = chip->base + offset; 9756732ae5cSJean-Christophe PLAGNIOL-VILLARD int bank = chip->base / chip->ngpio; 9766732ae5cSJean-Christophe PLAGNIOL-VILLARD 9776732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(chip->dev, "%s:%d pio%c%d(%d)\n", __func__, __LINE__, 9786732ae5cSJean-Christophe PLAGNIOL-VILLARD 'A' + bank, offset, gpio); 9796732ae5cSJean-Christophe PLAGNIOL-VILLARD 9806732ae5cSJean-Christophe PLAGNIOL-VILLARD return pinctrl_request_gpio(gpio); 9816732ae5cSJean-Christophe PLAGNIOL-VILLARD } 9826732ae5cSJean-Christophe PLAGNIOL-VILLARD 9836732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_gpio_free(struct gpio_chip *chip, unsigned offset) 9846732ae5cSJean-Christophe PLAGNIOL-VILLARD { 9856732ae5cSJean-Christophe PLAGNIOL-VILLARD int gpio = chip->base + offset; 9866732ae5cSJean-Christophe PLAGNIOL-VILLARD 9876732ae5cSJean-Christophe PLAGNIOL-VILLARD pinctrl_free_gpio(gpio); 9886732ae5cSJean-Christophe PLAGNIOL-VILLARD } 9896732ae5cSJean-Christophe PLAGNIOL-VILLARD 9906732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 9916732ae5cSJean-Christophe PLAGNIOL-VILLARD { 9926732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 9936732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 9946732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask = 1 << offset; 9956732ae5cSJean-Christophe PLAGNIOL-VILLARD 9966732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_ODR); 9976732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 9986732ae5cSJean-Christophe PLAGNIOL-VILLARD } 9996732ae5cSJean-Christophe PLAGNIOL-VILLARD 10006732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_gpio_get(struct gpio_chip *chip, unsigned offset) 10016732ae5cSJean-Christophe PLAGNIOL-VILLARD { 10026732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 10036732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 10046732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask = 1 << offset; 10056732ae5cSJean-Christophe PLAGNIOL-VILLARD u32 pdsr; 10066732ae5cSJean-Christophe PLAGNIOL-VILLARD 10076732ae5cSJean-Christophe PLAGNIOL-VILLARD pdsr = readl_relaxed(pio + PIO_PDSR); 10086732ae5cSJean-Christophe PLAGNIOL-VILLARD return (pdsr & mask) != 0; 10096732ae5cSJean-Christophe PLAGNIOL-VILLARD } 10106732ae5cSJean-Christophe PLAGNIOL-VILLARD 10116732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_gpio_set(struct gpio_chip *chip, unsigned offset, 10126732ae5cSJean-Christophe PLAGNIOL-VILLARD int val) 10136732ae5cSJean-Christophe PLAGNIOL-VILLARD { 10146732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 10156732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 10166732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask = 1 << offset; 10176732ae5cSJean-Christophe PLAGNIOL-VILLARD 10186732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); 10196732ae5cSJean-Christophe PLAGNIOL-VILLARD } 10206732ae5cSJean-Christophe PLAGNIOL-VILLARD 10216732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 10226732ae5cSJean-Christophe PLAGNIOL-VILLARD int val) 10236732ae5cSJean-Christophe PLAGNIOL-VILLARD { 10246732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 10256732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 10266732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask = 1 << offset; 10276732ae5cSJean-Christophe PLAGNIOL-VILLARD 10286732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); 10296732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_OER); 10306732ae5cSJean-Christophe PLAGNIOL-VILLARD 10316732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 10326732ae5cSJean-Christophe PLAGNIOL-VILLARD } 10336732ae5cSJean-Christophe PLAGNIOL-VILLARD 10346732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 10356732ae5cSJean-Christophe PLAGNIOL-VILLARD { 10366732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 10376732ae5cSJean-Christophe PLAGNIOL-VILLARD int virq; 10386732ae5cSJean-Christophe PLAGNIOL-VILLARD 10396732ae5cSJean-Christophe PLAGNIOL-VILLARD if (offset < chip->ngpio) 10406732ae5cSJean-Christophe PLAGNIOL-VILLARD virq = irq_create_mapping(at91_gpio->domain, offset); 10416732ae5cSJean-Christophe PLAGNIOL-VILLARD else 10426732ae5cSJean-Christophe PLAGNIOL-VILLARD virq = -ENXIO; 10436732ae5cSJean-Christophe PLAGNIOL-VILLARD 10446732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n", 10456732ae5cSJean-Christophe PLAGNIOL-VILLARD chip->label, offset + chip->base, virq); 10466732ae5cSJean-Christophe PLAGNIOL-VILLARD return virq; 10476732ae5cSJean-Christophe PLAGNIOL-VILLARD } 10486732ae5cSJean-Christophe PLAGNIOL-VILLARD 10496732ae5cSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_DEBUG_FS 10506732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 10516732ae5cSJean-Christophe PLAGNIOL-VILLARD { 10526732ae5cSJean-Christophe PLAGNIOL-VILLARD enum at91_mux mode; 10536732ae5cSJean-Christophe PLAGNIOL-VILLARD int i; 10546732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 10556732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 10566732ae5cSJean-Christophe PLAGNIOL-VILLARD 10576732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < chip->ngpio; i++) { 10586732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned pin = chip->base + i; 10596732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask = pin_to_mask(pin); 10606732ae5cSJean-Christophe PLAGNIOL-VILLARD const char *gpio_label; 10616732ae5cSJean-Christophe PLAGNIOL-VILLARD u32 pdsr; 10626732ae5cSJean-Christophe PLAGNIOL-VILLARD 10636732ae5cSJean-Christophe PLAGNIOL-VILLARD gpio_label = gpiochip_is_requested(chip, i); 10646732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!gpio_label) 10656732ae5cSJean-Christophe PLAGNIOL-VILLARD continue; 10666732ae5cSJean-Christophe PLAGNIOL-VILLARD mode = at91_gpio->ops->get_periph(pio, mask); 10676732ae5cSJean-Christophe PLAGNIOL-VILLARD seq_printf(s, "[%s] GPIO%s%d: ", 10686732ae5cSJean-Christophe PLAGNIOL-VILLARD gpio_label, chip->label, i); 10696732ae5cSJean-Christophe PLAGNIOL-VILLARD if (mode == AT91_MUX_GPIO) { 10706732ae5cSJean-Christophe PLAGNIOL-VILLARD pdsr = readl_relaxed(pio + PIO_PDSR); 10716732ae5cSJean-Christophe PLAGNIOL-VILLARD 10726732ae5cSJean-Christophe PLAGNIOL-VILLARD seq_printf(s, "[gpio] %s\n", 10736732ae5cSJean-Christophe PLAGNIOL-VILLARD pdsr & mask ? 10746732ae5cSJean-Christophe PLAGNIOL-VILLARD "set" : "clear"); 10756732ae5cSJean-Christophe PLAGNIOL-VILLARD } else { 10766732ae5cSJean-Christophe PLAGNIOL-VILLARD seq_printf(s, "[periph %c]\n", 10776732ae5cSJean-Christophe PLAGNIOL-VILLARD mode + 'A' - 1); 10786732ae5cSJean-Christophe PLAGNIOL-VILLARD } 10796732ae5cSJean-Christophe PLAGNIOL-VILLARD } 10806732ae5cSJean-Christophe PLAGNIOL-VILLARD } 10816732ae5cSJean-Christophe PLAGNIOL-VILLARD #else 10826732ae5cSJean-Christophe PLAGNIOL-VILLARD #define at91_gpio_dbg_show NULL 10836732ae5cSJean-Christophe PLAGNIOL-VILLARD #endif 10846732ae5cSJean-Christophe PLAGNIOL-VILLARD 10856732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Several AIC controller irqs are dispatched through this GPIO handler. 10866732ae5cSJean-Christophe PLAGNIOL-VILLARD * To use any AT91_PIN_* as an externally triggered IRQ, first call 10876732ae5cSJean-Christophe PLAGNIOL-VILLARD * at91_set_gpio_input() then maybe enable its glitch filter. 10886732ae5cSJean-Christophe PLAGNIOL-VILLARD * Then just request_irq() with the pin ID; it works like any ARM IRQ 10896732ae5cSJean-Christophe PLAGNIOL-VILLARD * handler. 10906732ae5cSJean-Christophe PLAGNIOL-VILLARD * First implementation always triggers on rising and falling edges 10916732ae5cSJean-Christophe PLAGNIOL-VILLARD * whereas the newer PIO3 can be additionally configured to trigger on 10926732ae5cSJean-Christophe PLAGNIOL-VILLARD * level, edge with any polarity. 10936732ae5cSJean-Christophe PLAGNIOL-VILLARD * 10946732ae5cSJean-Christophe PLAGNIOL-VILLARD * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after 10956732ae5cSJean-Christophe PLAGNIOL-VILLARD * configuring them with at91_set_a_periph() or at91_set_b_periph(). 10966732ae5cSJean-Christophe PLAGNIOL-VILLARD * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering. 10976732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 10986732ae5cSJean-Christophe PLAGNIOL-VILLARD 10996732ae5cSJean-Christophe PLAGNIOL-VILLARD static void gpio_irq_mask(struct irq_data *d) 11006732ae5cSJean-Christophe PLAGNIOL-VILLARD { 11016732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 11026732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 11036732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask = 1 << d->hwirq; 11046732ae5cSJean-Christophe PLAGNIOL-VILLARD 11056732ae5cSJean-Christophe PLAGNIOL-VILLARD if (pio) 11066732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_IDR); 11076732ae5cSJean-Christophe PLAGNIOL-VILLARD } 11086732ae5cSJean-Christophe PLAGNIOL-VILLARD 11096732ae5cSJean-Christophe PLAGNIOL-VILLARD static void gpio_irq_unmask(struct irq_data *d) 11106732ae5cSJean-Christophe PLAGNIOL-VILLARD { 11116732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 11126732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 11136732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask = 1 << d->hwirq; 11146732ae5cSJean-Christophe PLAGNIOL-VILLARD 11156732ae5cSJean-Christophe PLAGNIOL-VILLARD if (pio) 11166732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_IER); 11176732ae5cSJean-Christophe PLAGNIOL-VILLARD } 11186732ae5cSJean-Christophe PLAGNIOL-VILLARD 11196732ae5cSJean-Christophe PLAGNIOL-VILLARD static int gpio_irq_type(struct irq_data *d, unsigned type) 11206732ae5cSJean-Christophe PLAGNIOL-VILLARD { 11216732ae5cSJean-Christophe PLAGNIOL-VILLARD switch (type) { 11226732ae5cSJean-Christophe PLAGNIOL-VILLARD case IRQ_TYPE_NONE: 11236732ae5cSJean-Christophe PLAGNIOL-VILLARD case IRQ_TYPE_EDGE_BOTH: 11246732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 11256732ae5cSJean-Christophe PLAGNIOL-VILLARD default: 11266732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 11276732ae5cSJean-Christophe PLAGNIOL-VILLARD } 11286732ae5cSJean-Christophe PLAGNIOL-VILLARD } 11296732ae5cSJean-Christophe PLAGNIOL-VILLARD 11306732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Alternate irq type for PIO3 support */ 11316732ae5cSJean-Christophe PLAGNIOL-VILLARD static int alt_gpio_irq_type(struct irq_data *d, unsigned type) 11326732ae5cSJean-Christophe PLAGNIOL-VILLARD { 11336732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 11346732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 11356732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask = 1 << d->hwirq; 11366732ae5cSJean-Christophe PLAGNIOL-VILLARD 11376732ae5cSJean-Christophe PLAGNIOL-VILLARD switch (type) { 11386732ae5cSJean-Christophe PLAGNIOL-VILLARD case IRQ_TYPE_EDGE_RISING: 11396732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_ESR); 11406732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_REHLSR); 11416732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 11426732ae5cSJean-Christophe PLAGNIOL-VILLARD case IRQ_TYPE_EDGE_FALLING: 11436732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_ESR); 11446732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_FELLSR); 11456732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 11466732ae5cSJean-Christophe PLAGNIOL-VILLARD case IRQ_TYPE_LEVEL_LOW: 11476732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_LSR); 11486732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_FELLSR); 11496732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 11506732ae5cSJean-Christophe PLAGNIOL-VILLARD case IRQ_TYPE_LEVEL_HIGH: 11516732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_LSR); 11526732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_REHLSR); 11536732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 11546732ae5cSJean-Christophe PLAGNIOL-VILLARD case IRQ_TYPE_EDGE_BOTH: 11556732ae5cSJean-Christophe PLAGNIOL-VILLARD /* 11566732ae5cSJean-Christophe PLAGNIOL-VILLARD * disable additional interrupt modes: 11576732ae5cSJean-Christophe PLAGNIOL-VILLARD * fall back to default behavior 11586732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 11596732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_AIMDR); 11606732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 11616732ae5cSJean-Christophe PLAGNIOL-VILLARD case IRQ_TYPE_NONE: 11626732ae5cSJean-Christophe PLAGNIOL-VILLARD default: 11636732ae5cSJean-Christophe PLAGNIOL-VILLARD pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq)); 11646732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 11656732ae5cSJean-Christophe PLAGNIOL-VILLARD } 11666732ae5cSJean-Christophe PLAGNIOL-VILLARD 11676732ae5cSJean-Christophe PLAGNIOL-VILLARD /* enable additional interrupt modes */ 11686732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_AIMER); 11696732ae5cSJean-Christophe PLAGNIOL-VILLARD 11706732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 11716732ae5cSJean-Christophe PLAGNIOL-VILLARD } 11726732ae5cSJean-Christophe PLAGNIOL-VILLARD 11736732ae5cSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_PM 11746732ae5cSJean-Christophe PLAGNIOL-VILLARD static int gpio_irq_set_wake(struct irq_data *d, unsigned state) 11756732ae5cSJean-Christophe PLAGNIOL-VILLARD { 11766732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 11776732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned bank = at91_gpio->pioc_idx; 11786732ae5cSJean-Christophe PLAGNIOL-VILLARD 11796732ae5cSJean-Christophe PLAGNIOL-VILLARD if (unlikely(bank >= MAX_GPIO_BANKS)) 11806732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 11816732ae5cSJean-Christophe PLAGNIOL-VILLARD 11826732ae5cSJean-Christophe PLAGNIOL-VILLARD irq_set_irq_wake(at91_gpio->pioc_virq, state); 11836732ae5cSJean-Christophe PLAGNIOL-VILLARD 11846732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 11856732ae5cSJean-Christophe PLAGNIOL-VILLARD } 11866732ae5cSJean-Christophe PLAGNIOL-VILLARD #else 11876732ae5cSJean-Christophe PLAGNIOL-VILLARD #define gpio_irq_set_wake NULL 11886732ae5cSJean-Christophe PLAGNIOL-VILLARD #endif 11896732ae5cSJean-Christophe PLAGNIOL-VILLARD 11906732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct irq_chip gpio_irqchip = { 11916732ae5cSJean-Christophe PLAGNIOL-VILLARD .name = "GPIO", 11926732ae5cSJean-Christophe PLAGNIOL-VILLARD .irq_disable = gpio_irq_mask, 11936732ae5cSJean-Christophe PLAGNIOL-VILLARD .irq_mask = gpio_irq_mask, 11946732ae5cSJean-Christophe PLAGNIOL-VILLARD .irq_unmask = gpio_irq_unmask, 11956732ae5cSJean-Christophe PLAGNIOL-VILLARD /* .irq_set_type is set dynamically */ 11966732ae5cSJean-Christophe PLAGNIOL-VILLARD .irq_set_wake = gpio_irq_set_wake, 11976732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 11986732ae5cSJean-Christophe PLAGNIOL-VILLARD 11996732ae5cSJean-Christophe PLAGNIOL-VILLARD static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) 12006732ae5cSJean-Christophe PLAGNIOL-VILLARD { 12016732ae5cSJean-Christophe PLAGNIOL-VILLARD struct irq_chip *chip = irq_desc_get_chip(desc); 12026732ae5cSJean-Christophe PLAGNIOL-VILLARD struct irq_data *idata = irq_desc_get_irq_data(desc); 12036732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata); 12046732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 12056732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned long isr; 12066732ae5cSJean-Christophe PLAGNIOL-VILLARD int n; 12076732ae5cSJean-Christophe PLAGNIOL-VILLARD 12086732ae5cSJean-Christophe PLAGNIOL-VILLARD chained_irq_enter(chip, desc); 12096732ae5cSJean-Christophe PLAGNIOL-VILLARD for (;;) { 12106732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Reading ISR acks pending (edge triggered) GPIO interrupts. 12116732ae5cSJean-Christophe PLAGNIOL-VILLARD * When there none are pending, we're finished unless we need 12126732ae5cSJean-Christophe PLAGNIOL-VILLARD * to process multiple banks (like ID_PIOCDE on sam9263). 12136732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 12146732ae5cSJean-Christophe PLAGNIOL-VILLARD isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR); 12156732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!isr) { 12166732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!at91_gpio->next) 12176732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 12186732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_gpio = at91_gpio->next; 12196732ae5cSJean-Christophe PLAGNIOL-VILLARD pio = at91_gpio->regbase; 12206732ae5cSJean-Christophe PLAGNIOL-VILLARD continue; 12216732ae5cSJean-Christophe PLAGNIOL-VILLARD } 12226732ae5cSJean-Christophe PLAGNIOL-VILLARD 12236732ae5cSJean-Christophe PLAGNIOL-VILLARD n = find_first_bit(&isr, BITS_PER_LONG); 12246732ae5cSJean-Christophe PLAGNIOL-VILLARD while (n < BITS_PER_LONG) { 12256732ae5cSJean-Christophe PLAGNIOL-VILLARD generic_handle_irq(irq_find_mapping(at91_gpio->domain, n)); 12266732ae5cSJean-Christophe PLAGNIOL-VILLARD n = find_next_bit(&isr, BITS_PER_LONG, n + 1); 12276732ae5cSJean-Christophe PLAGNIOL-VILLARD } 12286732ae5cSJean-Christophe PLAGNIOL-VILLARD } 12296732ae5cSJean-Christophe PLAGNIOL-VILLARD chained_irq_exit(chip, desc); 12306732ae5cSJean-Christophe PLAGNIOL-VILLARD /* now it may re-trigger */ 12316732ae5cSJean-Christophe PLAGNIOL-VILLARD } 12326732ae5cSJean-Christophe PLAGNIOL-VILLARD 12336732ae5cSJean-Christophe PLAGNIOL-VILLARD /* 12346732ae5cSJean-Christophe PLAGNIOL-VILLARD * This lock class tells lockdep that GPIO irqs are in a different 12356732ae5cSJean-Christophe PLAGNIOL-VILLARD * category than their parents, so it won't report false recursion. 12366732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 12376732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct lock_class_key gpio_lock_class; 12386732ae5cSJean-Christophe PLAGNIOL-VILLARD 12396732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq, 12406732ae5cSJean-Christophe PLAGNIOL-VILLARD irq_hw_number_t hw) 12416732ae5cSJean-Christophe PLAGNIOL-VILLARD { 12426732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = h->host_data; 12436732ae5cSJean-Christophe PLAGNIOL-VILLARD 12446732ae5cSJean-Christophe PLAGNIOL-VILLARD irq_set_lockdep_class(virq, &gpio_lock_class); 12456732ae5cSJean-Christophe PLAGNIOL-VILLARD 12466732ae5cSJean-Christophe PLAGNIOL-VILLARD /* 12476732ae5cSJean-Christophe PLAGNIOL-VILLARD * Can use the "simple" and not "edge" handler since it's 12486732ae5cSJean-Christophe PLAGNIOL-VILLARD * shorter, and the AIC handles interrupts sanely. 12496732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 12506732ae5cSJean-Christophe PLAGNIOL-VILLARD irq_set_chip_and_handler(virq, &gpio_irqchip, 12516732ae5cSJean-Christophe PLAGNIOL-VILLARD handle_simple_irq); 12526732ae5cSJean-Christophe PLAGNIOL-VILLARD set_irq_flags(virq, IRQF_VALID); 12536732ae5cSJean-Christophe PLAGNIOL-VILLARD irq_set_chip_data(virq, at91_gpio); 12546732ae5cSJean-Christophe PLAGNIOL-VILLARD 12556732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 12566732ae5cSJean-Christophe PLAGNIOL-VILLARD } 12576732ae5cSJean-Christophe PLAGNIOL-VILLARD 1258a728c7cdSJean-Christophe PLAGNIOL-VILLARD int at91_gpio_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr, 1259a728c7cdSJean-Christophe PLAGNIOL-VILLARD const u32 *intspec, unsigned int intsize, 1260a728c7cdSJean-Christophe PLAGNIOL-VILLARD irq_hw_number_t *out_hwirq, unsigned int *out_type) 1261a728c7cdSJean-Christophe PLAGNIOL-VILLARD { 1262a728c7cdSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = d->host_data; 1263a728c7cdSJean-Christophe PLAGNIOL-VILLARD int ret; 1264a728c7cdSJean-Christophe PLAGNIOL-VILLARD int pin = at91_gpio->chip.base + intspec[0]; 1265a728c7cdSJean-Christophe PLAGNIOL-VILLARD 1266a728c7cdSJean-Christophe PLAGNIOL-VILLARD if (WARN_ON(intsize < 2)) 1267a728c7cdSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 1268a728c7cdSJean-Christophe PLAGNIOL-VILLARD *out_hwirq = intspec[0]; 1269a728c7cdSJean-Christophe PLAGNIOL-VILLARD *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK; 1270a728c7cdSJean-Christophe PLAGNIOL-VILLARD 1271a728c7cdSJean-Christophe PLAGNIOL-VILLARD ret = gpio_request(pin, ctrlr->full_name); 1272a728c7cdSJean-Christophe PLAGNIOL-VILLARD if (ret) 1273a728c7cdSJean-Christophe PLAGNIOL-VILLARD return ret; 1274a728c7cdSJean-Christophe PLAGNIOL-VILLARD 1275a728c7cdSJean-Christophe PLAGNIOL-VILLARD ret = gpio_direction_input(pin); 1276a728c7cdSJean-Christophe PLAGNIOL-VILLARD if (ret) 1277a728c7cdSJean-Christophe PLAGNIOL-VILLARD return ret; 1278a728c7cdSJean-Christophe PLAGNIOL-VILLARD 1279a728c7cdSJean-Christophe PLAGNIOL-VILLARD return 0; 1280a728c7cdSJean-Christophe PLAGNIOL-VILLARD } 1281a728c7cdSJean-Christophe PLAGNIOL-VILLARD 12826732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct irq_domain_ops at91_gpio_ops = { 12836732ae5cSJean-Christophe PLAGNIOL-VILLARD .map = at91_gpio_irq_map, 1284a728c7cdSJean-Christophe PLAGNIOL-VILLARD .xlate = at91_gpio_irq_domain_xlate, 12856732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 12866732ae5cSJean-Christophe PLAGNIOL-VILLARD 12876732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_gpio_of_irq_setup(struct device_node *node, 12886732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio) 12896732ae5cSJean-Christophe PLAGNIOL-VILLARD { 12906732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *prev = NULL; 12916732ae5cSJean-Christophe PLAGNIOL-VILLARD struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq); 12926732ae5cSJean-Christophe PLAGNIOL-VILLARD 12936732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_gpio->pioc_hwirq = irqd_to_hwirq(d); 12946732ae5cSJean-Christophe PLAGNIOL-VILLARD 12956732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Setup proper .irq_set_type function */ 12966732ae5cSJean-Christophe PLAGNIOL-VILLARD gpio_irqchip.irq_set_type = at91_gpio->ops->irq_type; 12976732ae5cSJean-Christophe PLAGNIOL-VILLARD 12986732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Disable irqs of this PIO controller */ 12996732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(~0, at91_gpio->regbase + PIO_IDR); 13006732ae5cSJean-Christophe PLAGNIOL-VILLARD 13016732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Setup irq domain */ 13026732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio, 13036732ae5cSJean-Christophe PLAGNIOL-VILLARD &at91_gpio_ops, at91_gpio); 13046732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!at91_gpio->domain) 13056732ae5cSJean-Christophe PLAGNIOL-VILLARD panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n", 13066732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_gpio->pioc_idx); 13076732ae5cSJean-Christophe PLAGNIOL-VILLARD 13086732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Setup chained handler */ 13096732ae5cSJean-Christophe PLAGNIOL-VILLARD if (at91_gpio->pioc_idx) 13106732ae5cSJean-Christophe PLAGNIOL-VILLARD prev = gpio_chips[at91_gpio->pioc_idx - 1]; 13116732ae5cSJean-Christophe PLAGNIOL-VILLARD 13126732ae5cSJean-Christophe PLAGNIOL-VILLARD /* The toplevel handler handles one bank of GPIOs, except 13136732ae5cSJean-Christophe PLAGNIOL-VILLARD * on some SoC it can handles up to three... 13146732ae5cSJean-Christophe PLAGNIOL-VILLARD * We only set up the handler for the first of the list. 13156732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 13166732ae5cSJean-Christophe PLAGNIOL-VILLARD if (prev && prev->next == at91_gpio) 13176732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 13186732ae5cSJean-Christophe PLAGNIOL-VILLARD 13196732ae5cSJean-Christophe PLAGNIOL-VILLARD irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio); 13206732ae5cSJean-Christophe PLAGNIOL-VILLARD irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler); 13216732ae5cSJean-Christophe PLAGNIOL-VILLARD 13226732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 13236732ae5cSJean-Christophe PLAGNIOL-VILLARD } 13246732ae5cSJean-Christophe PLAGNIOL-VILLARD 13256732ae5cSJean-Christophe PLAGNIOL-VILLARD /* This structure is replicated for each GPIO block allocated at probe time */ 13266732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct gpio_chip at91_gpio_template = { 13276732ae5cSJean-Christophe PLAGNIOL-VILLARD .request = at91_gpio_request, 13286732ae5cSJean-Christophe PLAGNIOL-VILLARD .free = at91_gpio_free, 13296732ae5cSJean-Christophe PLAGNIOL-VILLARD .direction_input = at91_gpio_direction_input, 13306732ae5cSJean-Christophe PLAGNIOL-VILLARD .get = at91_gpio_get, 13316732ae5cSJean-Christophe PLAGNIOL-VILLARD .direction_output = at91_gpio_direction_output, 13326732ae5cSJean-Christophe PLAGNIOL-VILLARD .set = at91_gpio_set, 13336732ae5cSJean-Christophe PLAGNIOL-VILLARD .to_irq = at91_gpio_to_irq, 13346732ae5cSJean-Christophe PLAGNIOL-VILLARD .dbg_show = at91_gpio_dbg_show, 13356732ae5cSJean-Christophe PLAGNIOL-VILLARD .can_sleep = 0, 13366732ae5cSJean-Christophe PLAGNIOL-VILLARD .ngpio = MAX_NB_GPIO_PER_BANK, 13376732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 13386732ae5cSJean-Christophe PLAGNIOL-VILLARD 13396732ae5cSJean-Christophe PLAGNIOL-VILLARD static void __devinit at91_gpio_probe_fixup(void) 13406732ae5cSJean-Christophe PLAGNIOL-VILLARD { 13416732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned i; 13426732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio, *last = NULL; 13436732ae5cSJean-Christophe PLAGNIOL-VILLARD 13446732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < gpio_banks; i++) { 13456732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_gpio = gpio_chips[i]; 13466732ae5cSJean-Christophe PLAGNIOL-VILLARD 13476732ae5cSJean-Christophe PLAGNIOL-VILLARD /* 13486732ae5cSJean-Christophe PLAGNIOL-VILLARD * GPIO controller are grouped on some SoC: 13496732ae5cSJean-Christophe PLAGNIOL-VILLARD * PIOC, PIOD and PIOE can share the same IRQ line 13506732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 13516732ae5cSJean-Christophe PLAGNIOL-VILLARD if (last && last->pioc_virq == at91_gpio->pioc_virq) 13526732ae5cSJean-Christophe PLAGNIOL-VILLARD last->next = at91_gpio; 13536732ae5cSJean-Christophe PLAGNIOL-VILLARD last = at91_gpio; 13546732ae5cSJean-Christophe PLAGNIOL-VILLARD } 13556732ae5cSJean-Christophe PLAGNIOL-VILLARD } 13566732ae5cSJean-Christophe PLAGNIOL-VILLARD 13576732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct of_device_id at91_gpio_of_match[] __devinitdata = { 13586732ae5cSJean-Christophe PLAGNIOL-VILLARD { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, }, 13596732ae5cSJean-Christophe PLAGNIOL-VILLARD { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops }, 13606732ae5cSJean-Christophe PLAGNIOL-VILLARD { /* sentinel */ } 13616732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 13626732ae5cSJean-Christophe PLAGNIOL-VILLARD 13636732ae5cSJean-Christophe PLAGNIOL-VILLARD static int __devinit at91_gpio_probe(struct platform_device *pdev) 13646732ae5cSJean-Christophe PLAGNIOL-VILLARD { 13656732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *np = pdev->dev.of_node; 13666732ae5cSJean-Christophe PLAGNIOL-VILLARD struct resource *res; 13676732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_chip = NULL; 13686732ae5cSJean-Christophe PLAGNIOL-VILLARD struct gpio_chip *chip; 13696732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_gpio_range *range; 13706732ae5cSJean-Christophe PLAGNIOL-VILLARD int ret = 0; 13716732ae5cSJean-Christophe PLAGNIOL-VILLARD int irq; 13726732ae5cSJean-Christophe PLAGNIOL-VILLARD int alias_idx = of_alias_get_id(np, "gpio"); 13736732ae5cSJean-Christophe PLAGNIOL-VILLARD uint32_t ngpio; 13746732ae5cSJean-Christophe PLAGNIOL-VILLARD 13756732ae5cSJean-Christophe PLAGNIOL-VILLARD BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips)); 13766732ae5cSJean-Christophe PLAGNIOL-VILLARD if (gpio_chips[alias_idx]) { 13776732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = -EBUSY; 13786732ae5cSJean-Christophe PLAGNIOL-VILLARD goto err; 13796732ae5cSJean-Christophe PLAGNIOL-VILLARD } 13806732ae5cSJean-Christophe PLAGNIOL-VILLARD 13816732ae5cSJean-Christophe PLAGNIOL-VILLARD res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 13826732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!res) { 13836732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = -ENOENT; 13846732ae5cSJean-Christophe PLAGNIOL-VILLARD goto err; 13856732ae5cSJean-Christophe PLAGNIOL-VILLARD } 13866732ae5cSJean-Christophe PLAGNIOL-VILLARD 13876732ae5cSJean-Christophe PLAGNIOL-VILLARD irq = platform_get_irq(pdev, 0); 13886732ae5cSJean-Christophe PLAGNIOL-VILLARD if (irq < 0) { 13896732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = irq; 13906732ae5cSJean-Christophe PLAGNIOL-VILLARD goto err; 13916732ae5cSJean-Christophe PLAGNIOL-VILLARD } 13926732ae5cSJean-Christophe PLAGNIOL-VILLARD 13936732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL); 13946732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!at91_chip) { 13956732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = -ENOMEM; 13966732ae5cSJean-Christophe PLAGNIOL-VILLARD goto err; 13976732ae5cSJean-Christophe PLAGNIOL-VILLARD } 13986732ae5cSJean-Christophe PLAGNIOL-VILLARD 13996732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_chip->regbase = devm_request_and_ioremap(&pdev->dev, res); 14006732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!at91_chip->regbase) { 14016732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(&pdev->dev, "failed to map registers, ignoring.\n"); 14026732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = -EBUSY; 14036732ae5cSJean-Christophe PLAGNIOL-VILLARD goto err; 14046732ae5cSJean-Christophe PLAGNIOL-VILLARD } 14056732ae5cSJean-Christophe PLAGNIOL-VILLARD 14066732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_chip->ops = 14076732ae5cSJean-Christophe PLAGNIOL-VILLARD of_match_device(at91_gpio_of_match, &pdev->dev)->data; 14086732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_chip->pioc_virq = irq; 14096732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_chip->pioc_idx = alias_idx; 14106732ae5cSJean-Christophe PLAGNIOL-VILLARD 14116732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_chip->clock = clk_get(&pdev->dev, NULL); 14126732ae5cSJean-Christophe PLAGNIOL-VILLARD if (IS_ERR(at91_chip->clock)) { 14136732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(&pdev->dev, "failed to get clock, ignoring.\n"); 14146732ae5cSJean-Christophe PLAGNIOL-VILLARD goto err; 14156732ae5cSJean-Christophe PLAGNIOL-VILLARD } 14166732ae5cSJean-Christophe PLAGNIOL-VILLARD 14176732ae5cSJean-Christophe PLAGNIOL-VILLARD if (clk_prepare(at91_chip->clock)) 14186732ae5cSJean-Christophe PLAGNIOL-VILLARD goto clk_prep_err; 14196732ae5cSJean-Christophe PLAGNIOL-VILLARD 14206732ae5cSJean-Christophe PLAGNIOL-VILLARD /* enable PIO controller's clock */ 14216732ae5cSJean-Christophe PLAGNIOL-VILLARD if (clk_enable(at91_chip->clock)) { 14226732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(&pdev->dev, "failed to enable clock, ignoring.\n"); 14236732ae5cSJean-Christophe PLAGNIOL-VILLARD goto clk_err; 14246732ae5cSJean-Christophe PLAGNIOL-VILLARD } 14256732ae5cSJean-Christophe PLAGNIOL-VILLARD 14266732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_chip->chip = at91_gpio_template; 14276732ae5cSJean-Christophe PLAGNIOL-VILLARD 14286732ae5cSJean-Christophe PLAGNIOL-VILLARD chip = &at91_chip->chip; 14296732ae5cSJean-Christophe PLAGNIOL-VILLARD chip->of_node = np; 14306732ae5cSJean-Christophe PLAGNIOL-VILLARD chip->label = dev_name(&pdev->dev); 14316732ae5cSJean-Christophe PLAGNIOL-VILLARD chip->dev = &pdev->dev; 14326732ae5cSJean-Christophe PLAGNIOL-VILLARD chip->owner = THIS_MODULE; 14336732ae5cSJean-Christophe PLAGNIOL-VILLARD chip->base = alias_idx * MAX_NB_GPIO_PER_BANK; 14346732ae5cSJean-Christophe PLAGNIOL-VILLARD 14356732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) { 14366732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ngpio >= MAX_NB_GPIO_PER_BANK) 14376732ae5cSJean-Christophe PLAGNIOL-VILLARD pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n", 14386732ae5cSJean-Christophe PLAGNIOL-VILLARD alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK); 14396732ae5cSJean-Christophe PLAGNIOL-VILLARD else 14406732ae5cSJean-Christophe PLAGNIOL-VILLARD chip->ngpio = ngpio; 14416732ae5cSJean-Christophe PLAGNIOL-VILLARD } 14426732ae5cSJean-Christophe PLAGNIOL-VILLARD 14436732ae5cSJean-Christophe PLAGNIOL-VILLARD range = &at91_chip->range; 14446732ae5cSJean-Christophe PLAGNIOL-VILLARD range->name = chip->label; 14456732ae5cSJean-Christophe PLAGNIOL-VILLARD range->id = alias_idx; 14466732ae5cSJean-Christophe PLAGNIOL-VILLARD range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK; 14476732ae5cSJean-Christophe PLAGNIOL-VILLARD 14486732ae5cSJean-Christophe PLAGNIOL-VILLARD range->npins = chip->ngpio; 14496732ae5cSJean-Christophe PLAGNIOL-VILLARD range->gc = chip; 14506732ae5cSJean-Christophe PLAGNIOL-VILLARD 14516732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = gpiochip_add(chip); 14526732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ret) 14536732ae5cSJean-Christophe PLAGNIOL-VILLARD goto clk_err; 14546732ae5cSJean-Christophe PLAGNIOL-VILLARD 14556732ae5cSJean-Christophe PLAGNIOL-VILLARD gpio_chips[alias_idx] = at91_chip; 14566732ae5cSJean-Christophe PLAGNIOL-VILLARD gpio_banks = max(gpio_banks, alias_idx + 1); 14576732ae5cSJean-Christophe PLAGNIOL-VILLARD 14586732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_gpio_probe_fixup(); 14596732ae5cSJean-Christophe PLAGNIOL-VILLARD 14606732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_gpio_of_irq_setup(np, at91_chip); 14616732ae5cSJean-Christophe PLAGNIOL-VILLARD 14626732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase); 14636732ae5cSJean-Christophe PLAGNIOL-VILLARD 14646732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 14656732ae5cSJean-Christophe PLAGNIOL-VILLARD 14666732ae5cSJean-Christophe PLAGNIOL-VILLARD clk_err: 14676732ae5cSJean-Christophe PLAGNIOL-VILLARD clk_unprepare(at91_chip->clock); 14686732ae5cSJean-Christophe PLAGNIOL-VILLARD clk_prep_err: 14696732ae5cSJean-Christophe PLAGNIOL-VILLARD clk_put(at91_chip->clock); 14706732ae5cSJean-Christophe PLAGNIOL-VILLARD err: 14716732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx); 14726732ae5cSJean-Christophe PLAGNIOL-VILLARD 14736732ae5cSJean-Christophe PLAGNIOL-VILLARD return ret; 14746732ae5cSJean-Christophe PLAGNIOL-VILLARD } 14756732ae5cSJean-Christophe PLAGNIOL-VILLARD 14766732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct platform_driver at91_gpio_driver = { 14776732ae5cSJean-Christophe PLAGNIOL-VILLARD .driver = { 14786732ae5cSJean-Christophe PLAGNIOL-VILLARD .name = "gpio-at91", 14796732ae5cSJean-Christophe PLAGNIOL-VILLARD .owner = THIS_MODULE, 14806732ae5cSJean-Christophe PLAGNIOL-VILLARD .of_match_table = of_match_ptr(at91_gpio_of_match), 14816732ae5cSJean-Christophe PLAGNIOL-VILLARD }, 14826732ae5cSJean-Christophe PLAGNIOL-VILLARD .probe = at91_gpio_probe, 14836732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 14846732ae5cSJean-Christophe PLAGNIOL-VILLARD 14856732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct platform_driver at91_pinctrl_driver = { 14866732ae5cSJean-Christophe PLAGNIOL-VILLARD .driver = { 14876732ae5cSJean-Christophe PLAGNIOL-VILLARD .name = "pinctrl-at91", 14886732ae5cSJean-Christophe PLAGNIOL-VILLARD .owner = THIS_MODULE, 14896732ae5cSJean-Christophe PLAGNIOL-VILLARD .of_match_table = of_match_ptr(at91_pinctrl_of_match), 14906732ae5cSJean-Christophe PLAGNIOL-VILLARD }, 14916732ae5cSJean-Christophe PLAGNIOL-VILLARD .probe = at91_pinctrl_probe, 14926732ae5cSJean-Christophe PLAGNIOL-VILLARD .remove = __devexit_p(at91_pinctrl_remove), 14936732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 14946732ae5cSJean-Christophe PLAGNIOL-VILLARD 14956732ae5cSJean-Christophe PLAGNIOL-VILLARD static int __init at91_pinctrl_init(void) 14966732ae5cSJean-Christophe PLAGNIOL-VILLARD { 14976732ae5cSJean-Christophe PLAGNIOL-VILLARD int ret; 14986732ae5cSJean-Christophe PLAGNIOL-VILLARD 14996732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = platform_driver_register(&at91_gpio_driver); 15006732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ret) 15016732ae5cSJean-Christophe PLAGNIOL-VILLARD return ret; 15026732ae5cSJean-Christophe PLAGNIOL-VILLARD return platform_driver_register(&at91_pinctrl_driver); 15036732ae5cSJean-Christophe PLAGNIOL-VILLARD } 15046732ae5cSJean-Christophe PLAGNIOL-VILLARD arch_initcall(at91_pinctrl_init); 15056732ae5cSJean-Christophe PLAGNIOL-VILLARD 15066732ae5cSJean-Christophe PLAGNIOL-VILLARD static void __exit at91_pinctrl_exit(void) 15076732ae5cSJean-Christophe PLAGNIOL-VILLARD { 15086732ae5cSJean-Christophe PLAGNIOL-VILLARD platform_driver_unregister(&at91_pinctrl_driver); 15096732ae5cSJean-Christophe PLAGNIOL-VILLARD } 15106732ae5cSJean-Christophe PLAGNIOL-VILLARD 15116732ae5cSJean-Christophe PLAGNIOL-VILLARD module_exit(at91_pinctrl_exit); 15126732ae5cSJean-Christophe PLAGNIOL-VILLARD MODULE_AUTHOR("Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>"); 15136732ae5cSJean-Christophe PLAGNIOL-VILLARD MODULE_DESCRIPTION("Atmel AT91 pinctrl driver"); 15146732ae5cSJean-Christophe PLAGNIOL-VILLARD MODULE_LICENSE("GPL v2"); 1515