16732ae5cSJean-Christophe PLAGNIOL-VILLARD /* 26732ae5cSJean-Christophe PLAGNIOL-VILLARD * at91 pinctrl driver based on at91 pinmux core 36732ae5cSJean-Christophe PLAGNIOL-VILLARD * 46732ae5cSJean-Christophe PLAGNIOL-VILLARD * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 56732ae5cSJean-Christophe PLAGNIOL-VILLARD * 66732ae5cSJean-Christophe PLAGNIOL-VILLARD * Under GPLv2 only 76732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 86732ae5cSJean-Christophe PLAGNIOL-VILLARD 96732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/clk.h> 106732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/err.h> 116732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/init.h> 126732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/module.h> 136732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/of.h> 146732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/of_device.h> 156732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/of_address.h> 166732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/of_irq.h> 176732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/slab.h> 186732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/interrupt.h> 196732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/irq.h> 206732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/irqdomain.h> 21de88cbb7SCatalin Marinas #include <linux/irqchip/chained_irq.h> 226732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/io.h> 236732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/gpio.h> 246732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/pinctrl/machine.h> 256732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/pinctrl/pinconf.h> 266732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/pinctrl/pinctrl.h> 276732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/pinctrl/pinmux.h> 286732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Since we request GPIOs from ourself */ 296732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/pinctrl/consumer.h> 306732ae5cSJean-Christophe PLAGNIOL-VILLARD 316732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <mach/hardware.h> 326732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <mach/at91_pio.h> 336732ae5cSJean-Christophe PLAGNIOL-VILLARD 346732ae5cSJean-Christophe PLAGNIOL-VILLARD #include "core.h" 356732ae5cSJean-Christophe PLAGNIOL-VILLARD 366732ae5cSJean-Christophe PLAGNIOL-VILLARD #define MAX_NB_GPIO_PER_BANK 32 376732ae5cSJean-Christophe PLAGNIOL-VILLARD 386732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl_mux_ops; 396732ae5cSJean-Christophe PLAGNIOL-VILLARD 406732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip { 416732ae5cSJean-Christophe PLAGNIOL-VILLARD struct gpio_chip chip; 426732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_gpio_range range; 436732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *next; /* Bank sharing same clock */ 446732ae5cSJean-Christophe PLAGNIOL-VILLARD int pioc_hwirq; /* PIO bank interrupt identifier on AIC */ 456732ae5cSJean-Christophe PLAGNIOL-VILLARD int pioc_virq; /* PIO bank Linux virtual interrupt */ 466732ae5cSJean-Christophe PLAGNIOL-VILLARD int pioc_idx; /* PIO bank index */ 476732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *regbase; /* PIO bank virtual address */ 486732ae5cSJean-Christophe PLAGNIOL-VILLARD struct clk *clock; /* associated clock */ 496732ae5cSJean-Christophe PLAGNIOL-VILLARD struct irq_domain *domain; /* associated irq domain */ 506732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl_mux_ops *ops; /* ops */ 516732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 526732ae5cSJean-Christophe PLAGNIOL-VILLARD 536732ae5cSJean-Christophe PLAGNIOL-VILLARD #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip) 546732ae5cSJean-Christophe PLAGNIOL-VILLARD 556732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS]; 566732ae5cSJean-Christophe PLAGNIOL-VILLARD 576732ae5cSJean-Christophe PLAGNIOL-VILLARD static int gpio_banks; 586732ae5cSJean-Christophe PLAGNIOL-VILLARD 59525fae21SJean-Christophe PLAGNIOL-VILLARD #define PULL_UP (1 << 0) 606732ae5cSJean-Christophe PLAGNIOL-VILLARD #define MULTI_DRIVE (1 << 1) 617ebd7a3aSJean-Christophe PLAGNIOL-VILLARD #define DEGLITCH (1 << 2) 627ebd7a3aSJean-Christophe PLAGNIOL-VILLARD #define PULL_DOWN (1 << 3) 637ebd7a3aSJean-Christophe PLAGNIOL-VILLARD #define DIS_SCHMIT (1 << 4) 647ebd7a3aSJean-Christophe PLAGNIOL-VILLARD #define DEBOUNCE (1 << 16) 657ebd7a3aSJean-Christophe PLAGNIOL-VILLARD #define DEBOUNCE_VAL_SHIFT 17 667ebd7a3aSJean-Christophe PLAGNIOL-VILLARD #define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT) 676732ae5cSJean-Christophe PLAGNIOL-VILLARD 686732ae5cSJean-Christophe PLAGNIOL-VILLARD /** 696732ae5cSJean-Christophe PLAGNIOL-VILLARD * struct at91_pmx_func - describes AT91 pinmux functions 706732ae5cSJean-Christophe PLAGNIOL-VILLARD * @name: the name of this specific function 716732ae5cSJean-Christophe PLAGNIOL-VILLARD * @groups: corresponding pin groups 726732ae5cSJean-Christophe PLAGNIOL-VILLARD * @ngroups: the number of groups 736732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 746732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pmx_func { 756732ae5cSJean-Christophe PLAGNIOL-VILLARD const char *name; 766732ae5cSJean-Christophe PLAGNIOL-VILLARD const char **groups; 776732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned ngroups; 786732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 796732ae5cSJean-Christophe PLAGNIOL-VILLARD 806732ae5cSJean-Christophe PLAGNIOL-VILLARD enum at91_mux { 816732ae5cSJean-Christophe PLAGNIOL-VILLARD AT91_MUX_GPIO = 0, 826732ae5cSJean-Christophe PLAGNIOL-VILLARD AT91_MUX_PERIPH_A = 1, 836732ae5cSJean-Christophe PLAGNIOL-VILLARD AT91_MUX_PERIPH_B = 2, 846732ae5cSJean-Christophe PLAGNIOL-VILLARD AT91_MUX_PERIPH_C = 3, 856732ae5cSJean-Christophe PLAGNIOL-VILLARD AT91_MUX_PERIPH_D = 4, 866732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 876732ae5cSJean-Christophe PLAGNIOL-VILLARD 886732ae5cSJean-Christophe PLAGNIOL-VILLARD /** 896732ae5cSJean-Christophe PLAGNIOL-VILLARD * struct at91_pmx_pin - describes an At91 pin mux 906732ae5cSJean-Christophe PLAGNIOL-VILLARD * @bank: the bank of the pin 916732ae5cSJean-Christophe PLAGNIOL-VILLARD * @pin: the pin number in the @bank 926732ae5cSJean-Christophe PLAGNIOL-VILLARD * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function. 936732ae5cSJean-Christophe PLAGNIOL-VILLARD * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc... 946732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 956732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pmx_pin { 966732ae5cSJean-Christophe PLAGNIOL-VILLARD uint32_t bank; 976732ae5cSJean-Christophe PLAGNIOL-VILLARD uint32_t pin; 986732ae5cSJean-Christophe PLAGNIOL-VILLARD enum at91_mux mux; 996732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned long conf; 1006732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 1016732ae5cSJean-Christophe PLAGNIOL-VILLARD 1026732ae5cSJean-Christophe PLAGNIOL-VILLARD /** 1036732ae5cSJean-Christophe PLAGNIOL-VILLARD * struct at91_pin_group - describes an At91 pin group 1046732ae5cSJean-Christophe PLAGNIOL-VILLARD * @name: the name of this specific pin group 1056732ae5cSJean-Christophe PLAGNIOL-VILLARD * @pins_conf: the mux mode for each pin in this group. The size of this 1066732ae5cSJean-Christophe PLAGNIOL-VILLARD * array is the same as pins. 1076732ae5cSJean-Christophe PLAGNIOL-VILLARD * @pins: an array of discrete physical pins used in this group, taken 1086732ae5cSJean-Christophe PLAGNIOL-VILLARD * from the driver-local pin enumeration space 1096732ae5cSJean-Christophe PLAGNIOL-VILLARD * @npins: the number of pins in this group array, i.e. the number of 1106732ae5cSJean-Christophe PLAGNIOL-VILLARD * elements in .pins so we can iterate over that array 1116732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 1126732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pin_group { 1136732ae5cSJean-Christophe PLAGNIOL-VILLARD const char *name; 1146732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pmx_pin *pins_conf; 1156732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned int *pins; 1166732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned npins; 1176732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 1186732ae5cSJean-Christophe PLAGNIOL-VILLARD 1196732ae5cSJean-Christophe PLAGNIOL-VILLARD /** 1206732ae5cSJean-Christophe PLAGNIOL-VILLARD * struct at91_pinctrl_mux_ops - describes an At91 mux ops group 1216732ae5cSJean-Christophe PLAGNIOL-VILLARD * on new IP with support for periph C and D the way to mux in 1226732ae5cSJean-Christophe PLAGNIOL-VILLARD * periph A and B has changed 1236732ae5cSJean-Christophe PLAGNIOL-VILLARD * So provide the right call back 1246732ae5cSJean-Christophe PLAGNIOL-VILLARD * if not present means the IP does not support it 1256732ae5cSJean-Christophe PLAGNIOL-VILLARD * @get_periph: return the periph mode configured 1266732ae5cSJean-Christophe PLAGNIOL-VILLARD * @mux_A_periph: mux as periph A 1276732ae5cSJean-Christophe PLAGNIOL-VILLARD * @mux_B_periph: mux as periph B 1286732ae5cSJean-Christophe PLAGNIOL-VILLARD * @mux_C_periph: mux as periph C 1296732ae5cSJean-Christophe PLAGNIOL-VILLARD * @mux_D_periph: mux as periph D 1307ebd7a3aSJean-Christophe PLAGNIOL-VILLARD * @get_deglitch: get deglitch status 1317ebd7a3aSJean-Christophe PLAGNIOL-VILLARD * @set_deglitch: enable/disable deglitch 1327ebd7a3aSJean-Christophe PLAGNIOL-VILLARD * @get_debounce: get debounce status 1337ebd7a3aSJean-Christophe PLAGNIOL-VILLARD * @set_debounce: enable/disable debounce 1347ebd7a3aSJean-Christophe PLAGNIOL-VILLARD * @get_pulldown: get pulldown status 1357ebd7a3aSJean-Christophe PLAGNIOL-VILLARD * @set_pulldown: enable/disable pulldown 1367ebd7a3aSJean-Christophe PLAGNIOL-VILLARD * @get_schmitt_trig: get schmitt trigger status 1377ebd7a3aSJean-Christophe PLAGNIOL-VILLARD * @disable_schmitt_trig: disable schmitt trigger 1386732ae5cSJean-Christophe PLAGNIOL-VILLARD * @irq_type: return irq type 1396732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 1406732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl_mux_ops { 1416732ae5cSJean-Christophe PLAGNIOL-VILLARD enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask); 1426732ae5cSJean-Christophe PLAGNIOL-VILLARD void (*mux_A_periph)(void __iomem *pio, unsigned mask); 1436732ae5cSJean-Christophe PLAGNIOL-VILLARD void (*mux_B_periph)(void __iomem *pio, unsigned mask); 1446732ae5cSJean-Christophe PLAGNIOL-VILLARD void (*mux_C_periph)(void __iomem *pio, unsigned mask); 1456732ae5cSJean-Christophe PLAGNIOL-VILLARD void (*mux_D_periph)(void __iomem *pio, unsigned mask); 1467ebd7a3aSJean-Christophe PLAGNIOL-VILLARD bool (*get_deglitch)(void __iomem *pio, unsigned pin); 1477ebd7a3aSJean-Christophe PLAGNIOL-VILLARD void (*set_deglitch)(void __iomem *pio, unsigned mask, bool in_on); 1487ebd7a3aSJean-Christophe PLAGNIOL-VILLARD bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div); 1497ebd7a3aSJean-Christophe PLAGNIOL-VILLARD void (*set_debounce)(void __iomem *pio, unsigned mask, bool in_on, u32 div); 1507ebd7a3aSJean-Christophe PLAGNIOL-VILLARD bool (*get_pulldown)(void __iomem *pio, unsigned pin); 1517ebd7a3aSJean-Christophe PLAGNIOL-VILLARD void (*set_pulldown)(void __iomem *pio, unsigned mask, bool in_on); 1527ebd7a3aSJean-Christophe PLAGNIOL-VILLARD bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin); 1537ebd7a3aSJean-Christophe PLAGNIOL-VILLARD void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask); 1546732ae5cSJean-Christophe PLAGNIOL-VILLARD /* irq */ 1556732ae5cSJean-Christophe PLAGNIOL-VILLARD int (*irq_type)(struct irq_data *d, unsigned type); 1566732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 1576732ae5cSJean-Christophe PLAGNIOL-VILLARD 1586732ae5cSJean-Christophe PLAGNIOL-VILLARD static int gpio_irq_type(struct irq_data *d, unsigned type); 1596732ae5cSJean-Christophe PLAGNIOL-VILLARD static int alt_gpio_irq_type(struct irq_data *d, unsigned type); 1606732ae5cSJean-Christophe PLAGNIOL-VILLARD 1616732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl { 1626732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device *dev; 1636732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_dev *pctl; 1646732ae5cSJean-Christophe PLAGNIOL-VILLARD 1656732ae5cSJean-Christophe PLAGNIOL-VILLARD int nbanks; 1666732ae5cSJean-Christophe PLAGNIOL-VILLARD 1676732ae5cSJean-Christophe PLAGNIOL-VILLARD uint32_t *mux_mask; 1686732ae5cSJean-Christophe PLAGNIOL-VILLARD int nmux; 1696732ae5cSJean-Christophe PLAGNIOL-VILLARD 1706732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pmx_func *functions; 1716732ae5cSJean-Christophe PLAGNIOL-VILLARD int nfunctions; 1726732ae5cSJean-Christophe PLAGNIOL-VILLARD 1736732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pin_group *groups; 1746732ae5cSJean-Christophe PLAGNIOL-VILLARD int ngroups; 1756732ae5cSJean-Christophe PLAGNIOL-VILLARD 1766732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl_mux_ops *ops; 1776732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 1786732ae5cSJean-Christophe PLAGNIOL-VILLARD 1796732ae5cSJean-Christophe PLAGNIOL-VILLARD static const inline struct at91_pin_group *at91_pinctrl_find_group_by_name( 1806732ae5cSJean-Christophe PLAGNIOL-VILLARD const struct at91_pinctrl *info, 1816732ae5cSJean-Christophe PLAGNIOL-VILLARD const char *name) 1826732ae5cSJean-Christophe PLAGNIOL-VILLARD { 1836732ae5cSJean-Christophe PLAGNIOL-VILLARD const struct at91_pin_group *grp = NULL; 1846732ae5cSJean-Christophe PLAGNIOL-VILLARD int i; 1856732ae5cSJean-Christophe PLAGNIOL-VILLARD 1866732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < info->ngroups; i++) { 1876732ae5cSJean-Christophe PLAGNIOL-VILLARD if (strcmp(info->groups[i].name, name)) 1886732ae5cSJean-Christophe PLAGNIOL-VILLARD continue; 1896732ae5cSJean-Christophe PLAGNIOL-VILLARD 1906732ae5cSJean-Christophe PLAGNIOL-VILLARD grp = &info->groups[i]; 1916732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]); 1926732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 1936732ae5cSJean-Christophe PLAGNIOL-VILLARD } 1946732ae5cSJean-Christophe PLAGNIOL-VILLARD 1956732ae5cSJean-Christophe PLAGNIOL-VILLARD return grp; 1966732ae5cSJean-Christophe PLAGNIOL-VILLARD } 1976732ae5cSJean-Christophe PLAGNIOL-VILLARD 1986732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_get_groups_count(struct pinctrl_dev *pctldev) 1996732ae5cSJean-Christophe PLAGNIOL-VILLARD { 2006732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2016732ae5cSJean-Christophe PLAGNIOL-VILLARD 2026732ae5cSJean-Christophe PLAGNIOL-VILLARD return info->ngroups; 2036732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2046732ae5cSJean-Christophe PLAGNIOL-VILLARD 2056732ae5cSJean-Christophe PLAGNIOL-VILLARD static const char *at91_get_group_name(struct pinctrl_dev *pctldev, 2066732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned selector) 2076732ae5cSJean-Christophe PLAGNIOL-VILLARD { 2086732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2096732ae5cSJean-Christophe PLAGNIOL-VILLARD 2106732ae5cSJean-Christophe PLAGNIOL-VILLARD return info->groups[selector].name; 2116732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2126732ae5cSJean-Christophe PLAGNIOL-VILLARD 2136732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, 2146732ae5cSJean-Christophe PLAGNIOL-VILLARD const unsigned **pins, 2156732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned *npins) 2166732ae5cSJean-Christophe PLAGNIOL-VILLARD { 2176732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2186732ae5cSJean-Christophe PLAGNIOL-VILLARD 2196732ae5cSJean-Christophe PLAGNIOL-VILLARD if (selector >= info->ngroups) 2206732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 2216732ae5cSJean-Christophe PLAGNIOL-VILLARD 2226732ae5cSJean-Christophe PLAGNIOL-VILLARD *pins = info->groups[selector].pins; 2236732ae5cSJean-Christophe PLAGNIOL-VILLARD *npins = info->groups[selector].npins; 2246732ae5cSJean-Christophe PLAGNIOL-VILLARD 2256732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 2266732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2276732ae5cSJean-Christophe PLAGNIOL-VILLARD 2286732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 2296732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned offset) 2306732ae5cSJean-Christophe PLAGNIOL-VILLARD { 2316732ae5cSJean-Christophe PLAGNIOL-VILLARD seq_printf(s, "%s", dev_name(pctldev->dev)); 2326732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2336732ae5cSJean-Christophe PLAGNIOL-VILLARD 2346732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_dt_node_to_map(struct pinctrl_dev *pctldev, 2356732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *np, 2366732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_map **map, unsigned *num_maps) 2376732ae5cSJean-Christophe PLAGNIOL-VILLARD { 2386732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2396732ae5cSJean-Christophe PLAGNIOL-VILLARD const struct at91_pin_group *grp; 2406732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_map *new_map; 2416732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *parent; 2426732ae5cSJean-Christophe PLAGNIOL-VILLARD int map_num = 1; 2436732ae5cSJean-Christophe PLAGNIOL-VILLARD int i; 2446732ae5cSJean-Christophe PLAGNIOL-VILLARD 2456732ae5cSJean-Christophe PLAGNIOL-VILLARD /* 2466732ae5cSJean-Christophe PLAGNIOL-VILLARD * first find the group of this node and check if we need create 2476732ae5cSJean-Christophe PLAGNIOL-VILLARD * config maps for pins 2486732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 2496732ae5cSJean-Christophe PLAGNIOL-VILLARD grp = at91_pinctrl_find_group_by_name(info, np->name); 2506732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!grp) { 2516732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "unable to find group for node %s\n", 2526732ae5cSJean-Christophe PLAGNIOL-VILLARD np->name); 2536732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 2546732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2556732ae5cSJean-Christophe PLAGNIOL-VILLARD 2566732ae5cSJean-Christophe PLAGNIOL-VILLARD map_num += grp->npins; 2576732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, GFP_KERNEL); 2586732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!new_map) 2596732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENOMEM; 2606732ae5cSJean-Christophe PLAGNIOL-VILLARD 2616732ae5cSJean-Christophe PLAGNIOL-VILLARD *map = new_map; 2626732ae5cSJean-Christophe PLAGNIOL-VILLARD *num_maps = map_num; 2636732ae5cSJean-Christophe PLAGNIOL-VILLARD 2646732ae5cSJean-Christophe PLAGNIOL-VILLARD /* create mux map */ 2656732ae5cSJean-Christophe PLAGNIOL-VILLARD parent = of_get_parent(np); 2666732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!parent) { 267c62b2b34SJulia Lawall devm_kfree(pctldev->dev, new_map); 2686732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 2696732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2706732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 2716732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map[0].data.mux.function = parent->name; 2726732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map[0].data.mux.group = np->name; 2736732ae5cSJean-Christophe PLAGNIOL-VILLARD of_node_put(parent); 2746732ae5cSJean-Christophe PLAGNIOL-VILLARD 2756732ae5cSJean-Christophe PLAGNIOL-VILLARD /* create config map */ 2766732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map++; 2776732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < grp->npins; i++) { 2786732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 2796732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map[i].data.configs.group_or_pin = 2806732ae5cSJean-Christophe PLAGNIOL-VILLARD pin_get_name(pctldev, grp->pins[i]); 2816732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map[i].data.configs.configs = &grp->pins_conf[i].conf; 2826732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map[i].data.configs.num_configs = 1; 2836732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2846732ae5cSJean-Christophe PLAGNIOL-VILLARD 2856732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 2866732ae5cSJean-Christophe PLAGNIOL-VILLARD (*map)->data.mux.function, (*map)->data.mux.group, map_num); 2876732ae5cSJean-Christophe PLAGNIOL-VILLARD 2886732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 2896732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2906732ae5cSJean-Christophe PLAGNIOL-VILLARD 2916732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_dt_free_map(struct pinctrl_dev *pctldev, 2926732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_map *map, unsigned num_maps) 2936732ae5cSJean-Christophe PLAGNIOL-VILLARD { 2946732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2956732ae5cSJean-Christophe PLAGNIOL-VILLARD 296022ab148SLaurent Pinchart static const struct pinctrl_ops at91_pctrl_ops = { 2976732ae5cSJean-Christophe PLAGNIOL-VILLARD .get_groups_count = at91_get_groups_count, 2986732ae5cSJean-Christophe PLAGNIOL-VILLARD .get_group_name = at91_get_group_name, 2996732ae5cSJean-Christophe PLAGNIOL-VILLARD .get_group_pins = at91_get_group_pins, 3006732ae5cSJean-Christophe PLAGNIOL-VILLARD .pin_dbg_show = at91_pin_dbg_show, 3016732ae5cSJean-Christophe PLAGNIOL-VILLARD .dt_node_to_map = at91_dt_node_to_map, 3026732ae5cSJean-Christophe PLAGNIOL-VILLARD .dt_free_map = at91_dt_free_map, 3036732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 3046732ae5cSJean-Christophe PLAGNIOL-VILLARD 3056732ae5cSJean-Christophe PLAGNIOL-VILLARD static void __iomem *pin_to_controller(struct at91_pinctrl *info, 3066732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned int bank) 3076732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3086732ae5cSJean-Christophe PLAGNIOL-VILLARD return gpio_chips[bank]->regbase; 3096732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3106732ae5cSJean-Christophe PLAGNIOL-VILLARD 3116732ae5cSJean-Christophe PLAGNIOL-VILLARD static inline int pin_to_bank(unsigned pin) 3126732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3136732ae5cSJean-Christophe PLAGNIOL-VILLARD return pin /= MAX_NB_GPIO_PER_BANK; 3146732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3156732ae5cSJean-Christophe PLAGNIOL-VILLARD 3166732ae5cSJean-Christophe PLAGNIOL-VILLARD static unsigned pin_to_mask(unsigned int pin) 3176732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3186732ae5cSJean-Christophe PLAGNIOL-VILLARD return 1 << pin; 3196732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3206732ae5cSJean-Christophe PLAGNIOL-VILLARD 3216732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask) 3226732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3236732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_IDR); 3246732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3256732ae5cSJean-Christophe PLAGNIOL-VILLARD 3266732ae5cSJean-Christophe PLAGNIOL-VILLARD static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin) 3276732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3286732ae5cSJean-Christophe PLAGNIOL-VILLARD return (readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1; 3296732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3306732ae5cSJean-Christophe PLAGNIOL-VILLARD 3316732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on) 3326732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3336732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR)); 3346732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3356732ae5cSJean-Christophe PLAGNIOL-VILLARD 3366732ae5cSJean-Christophe PLAGNIOL-VILLARD static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin) 3376732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3386732ae5cSJean-Christophe PLAGNIOL-VILLARD return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1; 3396732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3406732ae5cSJean-Christophe PLAGNIOL-VILLARD 3416732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on) 3426732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3436732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR)); 3446732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3456732ae5cSJean-Christophe PLAGNIOL-VILLARD 3466732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask) 3476732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3486732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_ASR); 3496732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3506732ae5cSJean-Christophe PLAGNIOL-VILLARD 3516732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask) 3526732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3536732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_BSR); 3546732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3556732ae5cSJean-Christophe PLAGNIOL-VILLARD 3566732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask) 3576732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3586732ae5cSJean-Christophe PLAGNIOL-VILLARD 3596732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, 3606732ae5cSJean-Christophe PLAGNIOL-VILLARD pio + PIO_ABCDSR1); 3616732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, 3626732ae5cSJean-Christophe PLAGNIOL-VILLARD pio + PIO_ABCDSR2); 3636732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3646732ae5cSJean-Christophe PLAGNIOL-VILLARD 3656732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask) 3666732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3676732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, 3686732ae5cSJean-Christophe PLAGNIOL-VILLARD pio + PIO_ABCDSR1); 3696732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, 3706732ae5cSJean-Christophe PLAGNIOL-VILLARD pio + PIO_ABCDSR2); 3716732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3726732ae5cSJean-Christophe PLAGNIOL-VILLARD 3736732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask) 3746732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3756732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1); 3766732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); 3776732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3786732ae5cSJean-Christophe PLAGNIOL-VILLARD 3796732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask) 3806732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3816732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1); 3826732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); 3836732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3846732ae5cSJean-Christophe PLAGNIOL-VILLARD 3856732ae5cSJean-Christophe PLAGNIOL-VILLARD static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask) 3866732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3876732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned select; 3886732ae5cSJean-Christophe PLAGNIOL-VILLARD 3896732ae5cSJean-Christophe PLAGNIOL-VILLARD if (readl_relaxed(pio + PIO_PSR) & mask) 3906732ae5cSJean-Christophe PLAGNIOL-VILLARD return AT91_MUX_GPIO; 3916732ae5cSJean-Christophe PLAGNIOL-VILLARD 3926732ae5cSJean-Christophe PLAGNIOL-VILLARD select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask); 3936732ae5cSJean-Christophe PLAGNIOL-VILLARD select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1); 3946732ae5cSJean-Christophe PLAGNIOL-VILLARD 3956732ae5cSJean-Christophe PLAGNIOL-VILLARD return select + 1; 3966732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3976732ae5cSJean-Christophe PLAGNIOL-VILLARD 3986732ae5cSJean-Christophe PLAGNIOL-VILLARD static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask) 3996732ae5cSJean-Christophe PLAGNIOL-VILLARD { 4006732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned select; 4016732ae5cSJean-Christophe PLAGNIOL-VILLARD 4026732ae5cSJean-Christophe PLAGNIOL-VILLARD if (readl_relaxed(pio + PIO_PSR) & mask) 4036732ae5cSJean-Christophe PLAGNIOL-VILLARD return AT91_MUX_GPIO; 4046732ae5cSJean-Christophe PLAGNIOL-VILLARD 4056732ae5cSJean-Christophe PLAGNIOL-VILLARD select = readl_relaxed(pio + PIO_ABSR) & mask; 4066732ae5cSJean-Christophe PLAGNIOL-VILLARD 4076732ae5cSJean-Christophe PLAGNIOL-VILLARD return select + 1; 4086732ae5cSJean-Christophe PLAGNIOL-VILLARD } 4096732ae5cSJean-Christophe PLAGNIOL-VILLARD 4107ebd7a3aSJean-Christophe PLAGNIOL-VILLARD static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin) 4117ebd7a3aSJean-Christophe PLAGNIOL-VILLARD { 4127ebd7a3aSJean-Christophe PLAGNIOL-VILLARD return (__raw_readl(pio + PIO_IFSR) >> pin) & 0x1; 4137ebd7a3aSJean-Christophe PLAGNIOL-VILLARD } 4147ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 4157ebd7a3aSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) 4167ebd7a3aSJean-Christophe PLAGNIOL-VILLARD { 4177ebd7a3aSJean-Christophe PLAGNIOL-VILLARD __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); 4187ebd7a3aSJean-Christophe PLAGNIOL-VILLARD } 4197ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 4207ebd7a3aSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) 4217ebd7a3aSJean-Christophe PLAGNIOL-VILLARD { 4227ebd7a3aSJean-Christophe PLAGNIOL-VILLARD if (is_on) 4237ebd7a3aSJean-Christophe PLAGNIOL-VILLARD __raw_writel(mask, pio + PIO_IFSCDR); 4247ebd7a3aSJean-Christophe PLAGNIOL-VILLARD at91_mux_set_deglitch(pio, mask, is_on); 4257ebd7a3aSJean-Christophe PLAGNIOL-VILLARD } 4267ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 4277ebd7a3aSJean-Christophe PLAGNIOL-VILLARD static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div) 4287ebd7a3aSJean-Christophe PLAGNIOL-VILLARD { 4297ebd7a3aSJean-Christophe PLAGNIOL-VILLARD *div = __raw_readl(pio + PIO_SCDR); 4307ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 4317ebd7a3aSJean-Christophe PLAGNIOL-VILLARD return (__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1; 4327ebd7a3aSJean-Christophe PLAGNIOL-VILLARD } 4337ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 4347ebd7a3aSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask, 4357ebd7a3aSJean-Christophe PLAGNIOL-VILLARD bool is_on, u32 div) 4367ebd7a3aSJean-Christophe PLAGNIOL-VILLARD { 4377ebd7a3aSJean-Christophe PLAGNIOL-VILLARD if (is_on) { 4387ebd7a3aSJean-Christophe PLAGNIOL-VILLARD __raw_writel(mask, pio + PIO_IFSCER); 4397ebd7a3aSJean-Christophe PLAGNIOL-VILLARD __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR); 4407ebd7a3aSJean-Christophe PLAGNIOL-VILLARD __raw_writel(mask, pio + PIO_IFER); 4417ebd7a3aSJean-Christophe PLAGNIOL-VILLARD } else { 4427ebd7a3aSJean-Christophe PLAGNIOL-VILLARD __raw_writel(mask, pio + PIO_IFDR); 4437ebd7a3aSJean-Christophe PLAGNIOL-VILLARD } 4447ebd7a3aSJean-Christophe PLAGNIOL-VILLARD } 4457ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 4467ebd7a3aSJean-Christophe PLAGNIOL-VILLARD static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin) 4477ebd7a3aSJean-Christophe PLAGNIOL-VILLARD { 4487ebd7a3aSJean-Christophe PLAGNIOL-VILLARD return (__raw_readl(pio + PIO_PPDSR) >> pin) & 0x1; 4497ebd7a3aSJean-Christophe PLAGNIOL-VILLARD } 4507ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 4517ebd7a3aSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on) 4527ebd7a3aSJean-Christophe PLAGNIOL-VILLARD { 4537ebd7a3aSJean-Christophe PLAGNIOL-VILLARD __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR)); 4547ebd7a3aSJean-Christophe PLAGNIOL-VILLARD } 4557ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 4567ebd7a3aSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask) 4577ebd7a3aSJean-Christophe PLAGNIOL-VILLARD { 4587ebd7a3aSJean-Christophe PLAGNIOL-VILLARD __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT); 4597ebd7a3aSJean-Christophe PLAGNIOL-VILLARD } 4607ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 4617ebd7a3aSJean-Christophe PLAGNIOL-VILLARD static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin) 4627ebd7a3aSJean-Christophe PLAGNIOL-VILLARD { 4637ebd7a3aSJean-Christophe PLAGNIOL-VILLARD return (__raw_readl(pio + PIO_SCHMITT) >> pin) & 0x1; 4647ebd7a3aSJean-Christophe PLAGNIOL-VILLARD } 4657ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 4666732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct at91_pinctrl_mux_ops at91rm9200_ops = { 4676732ae5cSJean-Christophe PLAGNIOL-VILLARD .get_periph = at91_mux_get_periph, 4686732ae5cSJean-Christophe PLAGNIOL-VILLARD .mux_A_periph = at91_mux_set_A_periph, 4696732ae5cSJean-Christophe PLAGNIOL-VILLARD .mux_B_periph = at91_mux_set_B_periph, 4707ebd7a3aSJean-Christophe PLAGNIOL-VILLARD .get_deglitch = at91_mux_get_deglitch, 4717ebd7a3aSJean-Christophe PLAGNIOL-VILLARD .set_deglitch = at91_mux_set_deglitch, 4726732ae5cSJean-Christophe PLAGNIOL-VILLARD .irq_type = gpio_irq_type, 4736732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 4746732ae5cSJean-Christophe PLAGNIOL-VILLARD 4756732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct at91_pinctrl_mux_ops at91sam9x5_ops = { 4766732ae5cSJean-Christophe PLAGNIOL-VILLARD .get_periph = at91_mux_pio3_get_periph, 4776732ae5cSJean-Christophe PLAGNIOL-VILLARD .mux_A_periph = at91_mux_pio3_set_A_periph, 4786732ae5cSJean-Christophe PLAGNIOL-VILLARD .mux_B_periph = at91_mux_pio3_set_B_periph, 4796732ae5cSJean-Christophe PLAGNIOL-VILLARD .mux_C_periph = at91_mux_pio3_set_C_periph, 4806732ae5cSJean-Christophe PLAGNIOL-VILLARD .mux_D_periph = at91_mux_pio3_set_D_periph, 4817ebd7a3aSJean-Christophe PLAGNIOL-VILLARD .get_deglitch = at91_mux_get_deglitch, 4827ebd7a3aSJean-Christophe PLAGNIOL-VILLARD .set_deglitch = at91_mux_pio3_set_deglitch, 4837ebd7a3aSJean-Christophe PLAGNIOL-VILLARD .get_debounce = at91_mux_pio3_get_debounce, 4847ebd7a3aSJean-Christophe PLAGNIOL-VILLARD .set_debounce = at91_mux_pio3_set_debounce, 4857ebd7a3aSJean-Christophe PLAGNIOL-VILLARD .get_pulldown = at91_mux_pio3_get_pulldown, 4867ebd7a3aSJean-Christophe PLAGNIOL-VILLARD .set_pulldown = at91_mux_pio3_set_pulldown, 4877ebd7a3aSJean-Christophe PLAGNIOL-VILLARD .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig, 4887ebd7a3aSJean-Christophe PLAGNIOL-VILLARD .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig, 4896732ae5cSJean-Christophe PLAGNIOL-VILLARD .irq_type = alt_gpio_irq_type, 4906732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 4916732ae5cSJean-Christophe PLAGNIOL-VILLARD 4926732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin) 4936732ae5cSJean-Christophe PLAGNIOL-VILLARD { 4946732ae5cSJean-Christophe PLAGNIOL-VILLARD if (pin->mux) { 4956732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lu\n", 4966732ae5cSJean-Christophe PLAGNIOL-VILLARD pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf); 4976732ae5cSJean-Christophe PLAGNIOL-VILLARD } else { 4986732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lu\n", 4996732ae5cSJean-Christophe PLAGNIOL-VILLARD pin->bank + 'A', pin->pin, pin->conf); 5006732ae5cSJean-Christophe PLAGNIOL-VILLARD } 5016732ae5cSJean-Christophe PLAGNIOL-VILLARD } 5026732ae5cSJean-Christophe PLAGNIOL-VILLARD 5036732ae5cSJean-Christophe PLAGNIOL-VILLARD static int pin_check_config(struct at91_pinctrl *info, const char *name, 5046732ae5cSJean-Christophe PLAGNIOL-VILLARD int index, const struct at91_pmx_pin *pin) 5056732ae5cSJean-Christophe PLAGNIOL-VILLARD { 5066732ae5cSJean-Christophe PLAGNIOL-VILLARD int mux; 5076732ae5cSJean-Christophe PLAGNIOL-VILLARD 5086732ae5cSJean-Christophe PLAGNIOL-VILLARD /* check if it's a valid config */ 5096732ae5cSJean-Christophe PLAGNIOL-VILLARD if (pin->bank >= info->nbanks) { 5106732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n", 5116732ae5cSJean-Christophe PLAGNIOL-VILLARD name, index, pin->bank, info->nbanks); 5126732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 5136732ae5cSJean-Christophe PLAGNIOL-VILLARD } 5146732ae5cSJean-Christophe PLAGNIOL-VILLARD 5156732ae5cSJean-Christophe PLAGNIOL-VILLARD if (pin->pin >= MAX_NB_GPIO_PER_BANK) { 5166732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n", 5176732ae5cSJean-Christophe PLAGNIOL-VILLARD name, index, pin->pin, MAX_NB_GPIO_PER_BANK); 5186732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 5196732ae5cSJean-Christophe PLAGNIOL-VILLARD } 5206732ae5cSJean-Christophe PLAGNIOL-VILLARD 5216732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!pin->mux) 5226732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 5236732ae5cSJean-Christophe PLAGNIOL-VILLARD 5246732ae5cSJean-Christophe PLAGNIOL-VILLARD mux = pin->mux - 1; 5256732ae5cSJean-Christophe PLAGNIOL-VILLARD 5266732ae5cSJean-Christophe PLAGNIOL-VILLARD if (mux >= info->nmux) { 5276732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n", 5286732ae5cSJean-Christophe PLAGNIOL-VILLARD name, index, mux, info->nmux); 5296732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 5306732ae5cSJean-Christophe PLAGNIOL-VILLARD } 5316732ae5cSJean-Christophe PLAGNIOL-VILLARD 5326732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) { 5336732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n", 5346732ae5cSJean-Christophe PLAGNIOL-VILLARD name, index, mux, pin->bank + 'A', pin->pin); 5356732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 5366732ae5cSJean-Christophe PLAGNIOL-VILLARD } 5376732ae5cSJean-Christophe PLAGNIOL-VILLARD 5386732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 5396732ae5cSJean-Christophe PLAGNIOL-VILLARD } 5406732ae5cSJean-Christophe PLAGNIOL-VILLARD 5416732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask) 5426732ae5cSJean-Christophe PLAGNIOL-VILLARD { 5436732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_PDR); 5446732ae5cSJean-Christophe PLAGNIOL-VILLARD } 5456732ae5cSJean-Christophe PLAGNIOL-VILLARD 5466732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input) 5476732ae5cSJean-Christophe PLAGNIOL-VILLARD { 5486732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_PER); 5496732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER)); 5506732ae5cSJean-Christophe PLAGNIOL-VILLARD } 5516732ae5cSJean-Christophe PLAGNIOL-VILLARD 5526732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, 5536732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned group) 5546732ae5cSJean-Christophe PLAGNIOL-VILLARD { 5556732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 5566732ae5cSJean-Christophe PLAGNIOL-VILLARD const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf; 5576732ae5cSJean-Christophe PLAGNIOL-VILLARD const struct at91_pmx_pin *pin; 5586732ae5cSJean-Christophe PLAGNIOL-VILLARD uint32_t npins = info->groups[group].npins; 5596732ae5cSJean-Christophe PLAGNIOL-VILLARD int i, ret; 5606732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask; 5616732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio; 5626732ae5cSJean-Christophe PLAGNIOL-VILLARD 5636732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(info->dev, "enable function %s group %s\n", 5646732ae5cSJean-Christophe PLAGNIOL-VILLARD info->functions[selector].name, info->groups[group].name); 5656732ae5cSJean-Christophe PLAGNIOL-VILLARD 5666732ae5cSJean-Christophe PLAGNIOL-VILLARD /* first check that all the pins of the group are valid with a valid 5676732ae5cSJean-Christophe PLAGNIOL-VILLARD * paramter */ 5686732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < npins; i++) { 5696732ae5cSJean-Christophe PLAGNIOL-VILLARD pin = &pins_conf[i]; 5706732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = pin_check_config(info, info->groups[group].name, i, pin); 5716732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ret) 5726732ae5cSJean-Christophe PLAGNIOL-VILLARD return ret; 5736732ae5cSJean-Christophe PLAGNIOL-VILLARD } 5746732ae5cSJean-Christophe PLAGNIOL-VILLARD 5756732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < npins; i++) { 5766732ae5cSJean-Christophe PLAGNIOL-VILLARD pin = &pins_conf[i]; 5776732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_pin_dbg(info->dev, pin); 5786732ae5cSJean-Christophe PLAGNIOL-VILLARD pio = pin_to_controller(info, pin->bank); 5796732ae5cSJean-Christophe PLAGNIOL-VILLARD mask = pin_to_mask(pin->pin); 5806732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_mux_disable_interrupt(pio, mask); 5816732ae5cSJean-Christophe PLAGNIOL-VILLARD switch (pin->mux) { 5826732ae5cSJean-Christophe PLAGNIOL-VILLARD case AT91_MUX_GPIO: 5836732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_mux_gpio_enable(pio, mask, 1); 5846732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 5856732ae5cSJean-Christophe PLAGNIOL-VILLARD case AT91_MUX_PERIPH_A: 5866732ae5cSJean-Christophe PLAGNIOL-VILLARD info->ops->mux_A_periph(pio, mask); 5876732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 5886732ae5cSJean-Christophe PLAGNIOL-VILLARD case AT91_MUX_PERIPH_B: 5896732ae5cSJean-Christophe PLAGNIOL-VILLARD info->ops->mux_B_periph(pio, mask); 5906732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 5916732ae5cSJean-Christophe PLAGNIOL-VILLARD case AT91_MUX_PERIPH_C: 5926732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!info->ops->mux_C_periph) 5936732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 5946732ae5cSJean-Christophe PLAGNIOL-VILLARD info->ops->mux_C_periph(pio, mask); 5956732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 5966732ae5cSJean-Christophe PLAGNIOL-VILLARD case AT91_MUX_PERIPH_D: 5976732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!info->ops->mux_D_periph) 5986732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 5996732ae5cSJean-Christophe PLAGNIOL-VILLARD info->ops->mux_D_periph(pio, mask); 6006732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 6016732ae5cSJean-Christophe PLAGNIOL-VILLARD } 6026732ae5cSJean-Christophe PLAGNIOL-VILLARD if (pin->mux) 6036732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_mux_gpio_disable(pio, mask); 6046732ae5cSJean-Christophe PLAGNIOL-VILLARD } 6056732ae5cSJean-Christophe PLAGNIOL-VILLARD 6066732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 6076732ae5cSJean-Christophe PLAGNIOL-VILLARD } 6086732ae5cSJean-Christophe PLAGNIOL-VILLARD 6096732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector, 6106732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned group) 6116732ae5cSJean-Christophe PLAGNIOL-VILLARD { 6126732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 6136732ae5cSJean-Christophe PLAGNIOL-VILLARD const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf; 6146732ae5cSJean-Christophe PLAGNIOL-VILLARD const struct at91_pmx_pin *pin; 6156732ae5cSJean-Christophe PLAGNIOL-VILLARD uint32_t npins = info->groups[group].npins; 6166732ae5cSJean-Christophe PLAGNIOL-VILLARD int i; 6176732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask; 6186732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio; 6196732ae5cSJean-Christophe PLAGNIOL-VILLARD 6206732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < npins; i++) { 6216732ae5cSJean-Christophe PLAGNIOL-VILLARD pin = &pins_conf[i]; 6226732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_pin_dbg(info->dev, pin); 6236732ae5cSJean-Christophe PLAGNIOL-VILLARD pio = pin_to_controller(info, pin->bank); 6246732ae5cSJean-Christophe PLAGNIOL-VILLARD mask = pin_to_mask(pin->pin); 6256732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_mux_gpio_enable(pio, mask, 1); 6266732ae5cSJean-Christophe PLAGNIOL-VILLARD } 6276732ae5cSJean-Christophe PLAGNIOL-VILLARD } 6286732ae5cSJean-Christophe PLAGNIOL-VILLARD 6296732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 6306732ae5cSJean-Christophe PLAGNIOL-VILLARD { 6316732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 6326732ae5cSJean-Christophe PLAGNIOL-VILLARD 6336732ae5cSJean-Christophe PLAGNIOL-VILLARD return info->nfunctions; 6346732ae5cSJean-Christophe PLAGNIOL-VILLARD } 6356732ae5cSJean-Christophe PLAGNIOL-VILLARD 6366732ae5cSJean-Christophe PLAGNIOL-VILLARD static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev, 6376732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned selector) 6386732ae5cSJean-Christophe PLAGNIOL-VILLARD { 6396732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 6406732ae5cSJean-Christophe PLAGNIOL-VILLARD 6416732ae5cSJean-Christophe PLAGNIOL-VILLARD return info->functions[selector].name; 6426732ae5cSJean-Christophe PLAGNIOL-VILLARD } 6436732ae5cSJean-Christophe PLAGNIOL-VILLARD 6446732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, 6456732ae5cSJean-Christophe PLAGNIOL-VILLARD const char * const **groups, 6466732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned * const num_groups) 6476732ae5cSJean-Christophe PLAGNIOL-VILLARD { 6486732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 6496732ae5cSJean-Christophe PLAGNIOL-VILLARD 6506732ae5cSJean-Christophe PLAGNIOL-VILLARD *groups = info->functions[selector].groups; 6516732ae5cSJean-Christophe PLAGNIOL-VILLARD *num_groups = info->functions[selector].ngroups; 6526732ae5cSJean-Christophe PLAGNIOL-VILLARD 6536732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 6546732ae5cSJean-Christophe PLAGNIOL-VILLARD } 6556732ae5cSJean-Christophe PLAGNIOL-VILLARD 656f6f94f66SAxel Lin static int at91_gpio_request_enable(struct pinctrl_dev *pctldev, 6576732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_gpio_range *range, 6586732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned offset) 6596732ae5cSJean-Christophe PLAGNIOL-VILLARD { 6606732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 6616732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_chip; 6626732ae5cSJean-Christophe PLAGNIOL-VILLARD struct gpio_chip *chip; 6636732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask; 6646732ae5cSJean-Christophe PLAGNIOL-VILLARD 6656732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!range) { 6666732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(npct->dev, "invalid range\n"); 6676732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 6686732ae5cSJean-Christophe PLAGNIOL-VILLARD } 6696732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!range->gc) { 6706732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(npct->dev, "missing GPIO chip in range\n"); 6716732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 6726732ae5cSJean-Christophe PLAGNIOL-VILLARD } 6736732ae5cSJean-Christophe PLAGNIOL-VILLARD chip = range->gc; 6746732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_chip = container_of(chip, struct at91_gpio_chip, chip); 6756732ae5cSJean-Christophe PLAGNIOL-VILLARD 6766732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); 6776732ae5cSJean-Christophe PLAGNIOL-VILLARD 6786732ae5cSJean-Christophe PLAGNIOL-VILLARD mask = 1 << (offset - chip->base); 6796732ae5cSJean-Christophe PLAGNIOL-VILLARD 6806732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n", 6816732ae5cSJean-Christophe PLAGNIOL-VILLARD offset, 'A' + range->id, offset - chip->base, mask); 6826732ae5cSJean-Christophe PLAGNIOL-VILLARD 6836732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, at91_chip->regbase + PIO_PER); 6846732ae5cSJean-Christophe PLAGNIOL-VILLARD 6856732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 6866732ae5cSJean-Christophe PLAGNIOL-VILLARD } 6876732ae5cSJean-Christophe PLAGNIOL-VILLARD 688f6f94f66SAxel Lin static void at91_gpio_disable_free(struct pinctrl_dev *pctldev, 6896732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_gpio_range *range, 6906732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned offset) 6916732ae5cSJean-Christophe PLAGNIOL-VILLARD { 6926732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 6936732ae5cSJean-Christophe PLAGNIOL-VILLARD 6946732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); 6956732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Set the pin to some default state, GPIO is usually default */ 6966732ae5cSJean-Christophe PLAGNIOL-VILLARD } 6976732ae5cSJean-Christophe PLAGNIOL-VILLARD 698022ab148SLaurent Pinchart static const struct pinmux_ops at91_pmx_ops = { 6996732ae5cSJean-Christophe PLAGNIOL-VILLARD .get_functions_count = at91_pmx_get_funcs_count, 7006732ae5cSJean-Christophe PLAGNIOL-VILLARD .get_function_name = at91_pmx_get_func_name, 7016732ae5cSJean-Christophe PLAGNIOL-VILLARD .get_function_groups = at91_pmx_get_groups, 7026732ae5cSJean-Christophe PLAGNIOL-VILLARD .enable = at91_pmx_enable, 7036732ae5cSJean-Christophe PLAGNIOL-VILLARD .disable = at91_pmx_disable, 7046732ae5cSJean-Christophe PLAGNIOL-VILLARD .gpio_request_enable = at91_gpio_request_enable, 7056732ae5cSJean-Christophe PLAGNIOL-VILLARD .gpio_disable_free = at91_gpio_disable_free, 7066732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 7076732ae5cSJean-Christophe PLAGNIOL-VILLARD 7086732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_pinconf_get(struct pinctrl_dev *pctldev, 7096732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned pin_id, unsigned long *config) 7106732ae5cSJean-Christophe PLAGNIOL-VILLARD { 7116732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 7126732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio; 7136732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned pin; 7147ebd7a3aSJean-Christophe PLAGNIOL-VILLARD int div; 7156732ae5cSJean-Christophe PLAGNIOL-VILLARD 7166732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, *config); 7176732ae5cSJean-Christophe PLAGNIOL-VILLARD pio = pin_to_controller(info, pin_to_bank(pin_id)); 7186732ae5cSJean-Christophe PLAGNIOL-VILLARD pin = pin_id % MAX_NB_GPIO_PER_BANK; 7196732ae5cSJean-Christophe PLAGNIOL-VILLARD 7206732ae5cSJean-Christophe PLAGNIOL-VILLARD if (at91_mux_get_multidrive(pio, pin)) 7216732ae5cSJean-Christophe PLAGNIOL-VILLARD *config |= MULTI_DRIVE; 7226732ae5cSJean-Christophe PLAGNIOL-VILLARD 7236732ae5cSJean-Christophe PLAGNIOL-VILLARD if (at91_mux_get_pullup(pio, pin)) 7246732ae5cSJean-Christophe PLAGNIOL-VILLARD *config |= PULL_UP; 7256732ae5cSJean-Christophe PLAGNIOL-VILLARD 7267ebd7a3aSJean-Christophe PLAGNIOL-VILLARD if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin)) 7277ebd7a3aSJean-Christophe PLAGNIOL-VILLARD *config |= DEGLITCH; 7287ebd7a3aSJean-Christophe PLAGNIOL-VILLARD if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div)) 7297ebd7a3aSJean-Christophe PLAGNIOL-VILLARD *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT); 7307ebd7a3aSJean-Christophe PLAGNIOL-VILLARD if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin)) 7317ebd7a3aSJean-Christophe PLAGNIOL-VILLARD *config |= PULL_DOWN; 7327ebd7a3aSJean-Christophe PLAGNIOL-VILLARD if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin)) 7337ebd7a3aSJean-Christophe PLAGNIOL-VILLARD *config |= DIS_SCHMIT; 7347ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 7356732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 7366732ae5cSJean-Christophe PLAGNIOL-VILLARD } 7376732ae5cSJean-Christophe PLAGNIOL-VILLARD 7386732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_pinconf_set(struct pinctrl_dev *pctldev, 7396732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned pin_id, unsigned long config) 7406732ae5cSJean-Christophe PLAGNIOL-VILLARD { 7416732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 7426732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask; 7436732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio; 7446732ae5cSJean-Christophe PLAGNIOL-VILLARD 7456732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, config); 7466732ae5cSJean-Christophe PLAGNIOL-VILLARD pio = pin_to_controller(info, pin_to_bank(pin_id)); 7476732ae5cSJean-Christophe PLAGNIOL-VILLARD mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK); 7486732ae5cSJean-Christophe PLAGNIOL-VILLARD 7497ebd7a3aSJean-Christophe PLAGNIOL-VILLARD if (config & PULL_UP && config & PULL_DOWN) 7507ebd7a3aSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 7517ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 7526732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_mux_set_pullup(pio, mask, config & PULL_UP); 7536732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE); 7547ebd7a3aSJean-Christophe PLAGNIOL-VILLARD if (info->ops->set_deglitch) 7557ebd7a3aSJean-Christophe PLAGNIOL-VILLARD info->ops->set_deglitch(pio, mask, config & DEGLITCH); 7567ebd7a3aSJean-Christophe PLAGNIOL-VILLARD if (info->ops->set_debounce) 7577ebd7a3aSJean-Christophe PLAGNIOL-VILLARD info->ops->set_debounce(pio, mask, config & DEBOUNCE, 7587ebd7a3aSJean-Christophe PLAGNIOL-VILLARD (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT); 7597ebd7a3aSJean-Christophe PLAGNIOL-VILLARD if (info->ops->set_pulldown) 7607ebd7a3aSJean-Christophe PLAGNIOL-VILLARD info->ops->set_pulldown(pio, mask, config & PULL_DOWN); 7617ebd7a3aSJean-Christophe PLAGNIOL-VILLARD if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT) 7627ebd7a3aSJean-Christophe PLAGNIOL-VILLARD info->ops->disable_schmitt_trig(pio, mask); 7637ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 7646732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 7656732ae5cSJean-Christophe PLAGNIOL-VILLARD } 7666732ae5cSJean-Christophe PLAGNIOL-VILLARD 7676732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev, 7686732ae5cSJean-Christophe PLAGNIOL-VILLARD struct seq_file *s, unsigned pin_id) 7696732ae5cSJean-Christophe PLAGNIOL-VILLARD { 7706732ae5cSJean-Christophe PLAGNIOL-VILLARD 7716732ae5cSJean-Christophe PLAGNIOL-VILLARD } 7726732ae5cSJean-Christophe PLAGNIOL-VILLARD 7736732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 7746732ae5cSJean-Christophe PLAGNIOL-VILLARD struct seq_file *s, unsigned group) 7756732ae5cSJean-Christophe PLAGNIOL-VILLARD { 7766732ae5cSJean-Christophe PLAGNIOL-VILLARD } 7776732ae5cSJean-Christophe PLAGNIOL-VILLARD 778022ab148SLaurent Pinchart static const struct pinconf_ops at91_pinconf_ops = { 7796732ae5cSJean-Christophe PLAGNIOL-VILLARD .pin_config_get = at91_pinconf_get, 7806732ae5cSJean-Christophe PLAGNIOL-VILLARD .pin_config_set = at91_pinconf_set, 7816732ae5cSJean-Christophe PLAGNIOL-VILLARD .pin_config_dbg_show = at91_pinconf_dbg_show, 7826732ae5cSJean-Christophe PLAGNIOL-VILLARD .pin_config_group_dbg_show = at91_pinconf_group_dbg_show, 7836732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 7846732ae5cSJean-Christophe PLAGNIOL-VILLARD 7856732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct pinctrl_desc at91_pinctrl_desc = { 7866732ae5cSJean-Christophe PLAGNIOL-VILLARD .pctlops = &at91_pctrl_ops, 7876732ae5cSJean-Christophe PLAGNIOL-VILLARD .pmxops = &at91_pmx_ops, 7886732ae5cSJean-Christophe PLAGNIOL-VILLARD .confops = &at91_pinconf_ops, 7896732ae5cSJean-Christophe PLAGNIOL-VILLARD .owner = THIS_MODULE, 7906732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 7916732ae5cSJean-Christophe PLAGNIOL-VILLARD 7926732ae5cSJean-Christophe PLAGNIOL-VILLARD static const char *gpio_compat = "atmel,at91rm9200-gpio"; 7936732ae5cSJean-Christophe PLAGNIOL-VILLARD 794150632b0SGreg Kroah-Hartman static void at91_pinctrl_child_count(struct at91_pinctrl *info, 7956732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *np) 7966732ae5cSJean-Christophe PLAGNIOL-VILLARD { 7976732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *child; 7986732ae5cSJean-Christophe PLAGNIOL-VILLARD 7996732ae5cSJean-Christophe PLAGNIOL-VILLARD for_each_child_of_node(np, child) { 8006732ae5cSJean-Christophe PLAGNIOL-VILLARD if (of_device_is_compatible(child, gpio_compat)) { 8016732ae5cSJean-Christophe PLAGNIOL-VILLARD info->nbanks++; 8026732ae5cSJean-Christophe PLAGNIOL-VILLARD } else { 8036732ae5cSJean-Christophe PLAGNIOL-VILLARD info->nfunctions++; 8046732ae5cSJean-Christophe PLAGNIOL-VILLARD info->ngroups += of_get_child_count(child); 8056732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8066732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8076732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8086732ae5cSJean-Christophe PLAGNIOL-VILLARD 809150632b0SGreg Kroah-Hartman static int at91_pinctrl_mux_mask(struct at91_pinctrl *info, 8106732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *np) 8116732ae5cSJean-Christophe PLAGNIOL-VILLARD { 8126732ae5cSJean-Christophe PLAGNIOL-VILLARD int ret = 0; 8136732ae5cSJean-Christophe PLAGNIOL-VILLARD int size; 8141164d73aSSachin Kamat const __be32 *list; 8156732ae5cSJean-Christophe PLAGNIOL-VILLARD 8166732ae5cSJean-Christophe PLAGNIOL-VILLARD list = of_get_property(np, "atmel,mux-mask", &size); 8176732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!list) { 8186732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "can not read the mux-mask of %d\n", size); 8196732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 8206732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8216732ae5cSJean-Christophe PLAGNIOL-VILLARD 8226732ae5cSJean-Christophe PLAGNIOL-VILLARD size /= sizeof(*list); 8236732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!size || size % info->nbanks) { 8246732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "wrong mux mask array should be by %d\n", info->nbanks); 8256732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 8266732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8276732ae5cSJean-Christophe PLAGNIOL-VILLARD info->nmux = size / info->nbanks; 8286732ae5cSJean-Christophe PLAGNIOL-VILLARD 8296732ae5cSJean-Christophe PLAGNIOL-VILLARD info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL); 8306732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!info->mux_mask) { 8316732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "could not alloc mux_mask\n"); 8326732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENOMEM; 8336732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8346732ae5cSJean-Christophe PLAGNIOL-VILLARD 8356732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = of_property_read_u32_array(np, "atmel,mux-mask", 8366732ae5cSJean-Christophe PLAGNIOL-VILLARD info->mux_mask, size); 8376732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ret) 8386732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "can not read the mux-mask of %d\n", size); 8396732ae5cSJean-Christophe PLAGNIOL-VILLARD return ret; 8406732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8416732ae5cSJean-Christophe PLAGNIOL-VILLARD 842150632b0SGreg Kroah-Hartman static int at91_pinctrl_parse_groups(struct device_node *np, 8436732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pin_group *grp, 844150632b0SGreg Kroah-Hartman struct at91_pinctrl *info, u32 index) 8456732ae5cSJean-Christophe PLAGNIOL-VILLARD { 8466732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pmx_pin *pin; 8476732ae5cSJean-Christophe PLAGNIOL-VILLARD int size; 8481164d73aSSachin Kamat const __be32 *list; 8496732ae5cSJean-Christophe PLAGNIOL-VILLARD int i, j; 8506732ae5cSJean-Christophe PLAGNIOL-VILLARD 8516732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(info->dev, "group(%d): %s\n", index, np->name); 8526732ae5cSJean-Christophe PLAGNIOL-VILLARD 8536732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Initialise group */ 8546732ae5cSJean-Christophe PLAGNIOL-VILLARD grp->name = np->name; 8556732ae5cSJean-Christophe PLAGNIOL-VILLARD 8566732ae5cSJean-Christophe PLAGNIOL-VILLARD /* 8576732ae5cSJean-Christophe PLAGNIOL-VILLARD * the binding format is atmel,pins = <bank pin mux CONFIG ...>, 8586732ae5cSJean-Christophe PLAGNIOL-VILLARD * do sanity check and calculate pins number 8596732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 8606732ae5cSJean-Christophe PLAGNIOL-VILLARD list = of_get_property(np, "atmel,pins", &size); 8616732ae5cSJean-Christophe PLAGNIOL-VILLARD /* we do not check return since it's safe node passed down */ 8626732ae5cSJean-Christophe PLAGNIOL-VILLARD size /= sizeof(*list); 8636732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!size || size % 4) { 8646732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); 8656732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 8666732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8676732ae5cSJean-Christophe PLAGNIOL-VILLARD 8686732ae5cSJean-Christophe PLAGNIOL-VILLARD grp->npins = size / 4; 8696732ae5cSJean-Christophe PLAGNIOL-VILLARD pin = grp->pins_conf = devm_kzalloc(info->dev, grp->npins * sizeof(struct at91_pmx_pin), 8706732ae5cSJean-Christophe PLAGNIOL-VILLARD GFP_KERNEL); 8716732ae5cSJean-Christophe PLAGNIOL-VILLARD grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), 8726732ae5cSJean-Christophe PLAGNIOL-VILLARD GFP_KERNEL); 8736732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!grp->pins_conf || !grp->pins) 8746732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENOMEM; 8756732ae5cSJean-Christophe PLAGNIOL-VILLARD 8766732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0, j = 0; i < size; i += 4, j++) { 8776732ae5cSJean-Christophe PLAGNIOL-VILLARD pin->bank = be32_to_cpu(*list++); 8786732ae5cSJean-Christophe PLAGNIOL-VILLARD pin->pin = be32_to_cpu(*list++); 8796732ae5cSJean-Christophe PLAGNIOL-VILLARD grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin; 8806732ae5cSJean-Christophe PLAGNIOL-VILLARD pin->mux = be32_to_cpu(*list++); 8816732ae5cSJean-Christophe PLAGNIOL-VILLARD pin->conf = be32_to_cpu(*list++); 8826732ae5cSJean-Christophe PLAGNIOL-VILLARD 8836732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_pin_dbg(info->dev, pin); 8846732ae5cSJean-Christophe PLAGNIOL-VILLARD pin++; 8856732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8866732ae5cSJean-Christophe PLAGNIOL-VILLARD 8876732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 8886732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8896732ae5cSJean-Christophe PLAGNIOL-VILLARD 890150632b0SGreg Kroah-Hartman static int at91_pinctrl_parse_functions(struct device_node *np, 8916732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info, u32 index) 8926732ae5cSJean-Christophe PLAGNIOL-VILLARD { 8936732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *child; 8946732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pmx_func *func; 8956732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pin_group *grp; 8966732ae5cSJean-Christophe PLAGNIOL-VILLARD int ret; 8976732ae5cSJean-Christophe PLAGNIOL-VILLARD static u32 grp_index; 8986732ae5cSJean-Christophe PLAGNIOL-VILLARD u32 i = 0; 8996732ae5cSJean-Christophe PLAGNIOL-VILLARD 9006732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); 9016732ae5cSJean-Christophe PLAGNIOL-VILLARD 9026732ae5cSJean-Christophe PLAGNIOL-VILLARD func = &info->functions[index]; 9036732ae5cSJean-Christophe PLAGNIOL-VILLARD 9046732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Initialise function */ 9056732ae5cSJean-Christophe PLAGNIOL-VILLARD func->name = np->name; 9066732ae5cSJean-Christophe PLAGNIOL-VILLARD func->ngroups = of_get_child_count(np); 9076732ae5cSJean-Christophe PLAGNIOL-VILLARD if (func->ngroups <= 0) { 9086732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "no groups defined\n"); 9096732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 9106732ae5cSJean-Christophe PLAGNIOL-VILLARD } 9116732ae5cSJean-Christophe PLAGNIOL-VILLARD func->groups = devm_kzalloc(info->dev, 9126732ae5cSJean-Christophe PLAGNIOL-VILLARD func->ngroups * sizeof(char *), GFP_KERNEL); 9136732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!func->groups) 9146732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENOMEM; 9156732ae5cSJean-Christophe PLAGNIOL-VILLARD 9166732ae5cSJean-Christophe PLAGNIOL-VILLARD for_each_child_of_node(np, child) { 9176732ae5cSJean-Christophe PLAGNIOL-VILLARD func->groups[i] = child->name; 9186732ae5cSJean-Christophe PLAGNIOL-VILLARD grp = &info->groups[grp_index++]; 9196732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = at91_pinctrl_parse_groups(child, grp, info, i++); 9206732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ret) 9216732ae5cSJean-Christophe PLAGNIOL-VILLARD return ret; 9226732ae5cSJean-Christophe PLAGNIOL-VILLARD } 9236732ae5cSJean-Christophe PLAGNIOL-VILLARD 9246732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 9256732ae5cSJean-Christophe PLAGNIOL-VILLARD } 9266732ae5cSJean-Christophe PLAGNIOL-VILLARD 927150632b0SGreg Kroah-Hartman static struct of_device_id at91_pinctrl_of_match[] = { 9286732ae5cSJean-Christophe PLAGNIOL-VILLARD { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops }, 9296732ae5cSJean-Christophe PLAGNIOL-VILLARD { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops }, 9306732ae5cSJean-Christophe PLAGNIOL-VILLARD { /* sentinel */ } 9316732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 9326732ae5cSJean-Christophe PLAGNIOL-VILLARD 933150632b0SGreg Kroah-Hartman static int at91_pinctrl_probe_dt(struct platform_device *pdev, 9346732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info) 9356732ae5cSJean-Christophe PLAGNIOL-VILLARD { 9366732ae5cSJean-Christophe PLAGNIOL-VILLARD int ret = 0; 9376732ae5cSJean-Christophe PLAGNIOL-VILLARD int i, j; 9386732ae5cSJean-Christophe PLAGNIOL-VILLARD uint32_t *tmp; 9396732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *np = pdev->dev.of_node; 9406732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *child; 9416732ae5cSJean-Christophe PLAGNIOL-VILLARD 9426732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!np) 9436732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENODEV; 9446732ae5cSJean-Christophe PLAGNIOL-VILLARD 9456732ae5cSJean-Christophe PLAGNIOL-VILLARD info->dev = &pdev->dev; 946dffa9123SJean-Christophe PLAGNIOL-VILLARD info->ops = (struct at91_pinctrl_mux_ops *) 9476732ae5cSJean-Christophe PLAGNIOL-VILLARD of_match_device(at91_pinctrl_of_match, &pdev->dev)->data; 9486732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_pinctrl_child_count(info, np); 9496732ae5cSJean-Christophe PLAGNIOL-VILLARD 9506732ae5cSJean-Christophe PLAGNIOL-VILLARD if (info->nbanks < 1) { 9516732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(&pdev->dev, "you need to specify atleast one gpio-controller\n"); 9526732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 9536732ae5cSJean-Christophe PLAGNIOL-VILLARD } 9546732ae5cSJean-Christophe PLAGNIOL-VILLARD 9556732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = at91_pinctrl_mux_mask(info, np); 9566732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ret) 9576732ae5cSJean-Christophe PLAGNIOL-VILLARD return ret; 9586732ae5cSJean-Christophe PLAGNIOL-VILLARD 9596732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux); 9606732ae5cSJean-Christophe PLAGNIOL-VILLARD 9616732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(&pdev->dev, "mux-mask\n"); 9626732ae5cSJean-Christophe PLAGNIOL-VILLARD tmp = info->mux_mask; 9636732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < info->nbanks; i++) { 9646732ae5cSJean-Christophe PLAGNIOL-VILLARD for (j = 0; j < info->nmux; j++, tmp++) { 9656732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]); 9666732ae5cSJean-Christophe PLAGNIOL-VILLARD } 9676732ae5cSJean-Christophe PLAGNIOL-VILLARD } 9686732ae5cSJean-Christophe PLAGNIOL-VILLARD 9696732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 9706732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 9716732ae5cSJean-Christophe PLAGNIOL-VILLARD info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * sizeof(struct at91_pmx_func), 9726732ae5cSJean-Christophe PLAGNIOL-VILLARD GFP_KERNEL); 9736732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!info->functions) 9746732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENOMEM; 9756732ae5cSJean-Christophe PLAGNIOL-VILLARD 9766732ae5cSJean-Christophe PLAGNIOL-VILLARD info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct at91_pin_group), 9776732ae5cSJean-Christophe PLAGNIOL-VILLARD GFP_KERNEL); 9786732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!info->groups) 9796732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENOMEM; 9806732ae5cSJean-Christophe PLAGNIOL-VILLARD 9816732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks); 9826732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 9836732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 9846732ae5cSJean-Christophe PLAGNIOL-VILLARD 9856732ae5cSJean-Christophe PLAGNIOL-VILLARD i = 0; 9866732ae5cSJean-Christophe PLAGNIOL-VILLARD 9876732ae5cSJean-Christophe PLAGNIOL-VILLARD for_each_child_of_node(np, child) { 9886732ae5cSJean-Christophe PLAGNIOL-VILLARD if (of_device_is_compatible(child, gpio_compat)) 9896732ae5cSJean-Christophe PLAGNIOL-VILLARD continue; 9906732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = at91_pinctrl_parse_functions(child, info, i++); 9916732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ret) { 9926732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(&pdev->dev, "failed to parse function\n"); 9936732ae5cSJean-Christophe PLAGNIOL-VILLARD return ret; 9946732ae5cSJean-Christophe PLAGNIOL-VILLARD } 9956732ae5cSJean-Christophe PLAGNIOL-VILLARD } 9966732ae5cSJean-Christophe PLAGNIOL-VILLARD 9976732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 9986732ae5cSJean-Christophe PLAGNIOL-VILLARD } 9996732ae5cSJean-Christophe PLAGNIOL-VILLARD 1000150632b0SGreg Kroah-Hartman static int at91_pinctrl_probe(struct platform_device *pdev) 10016732ae5cSJean-Christophe PLAGNIOL-VILLARD { 10026732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info; 10036732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_pin_desc *pdesc; 10046732ae5cSJean-Christophe PLAGNIOL-VILLARD int ret, i, j, k; 10056732ae5cSJean-Christophe PLAGNIOL-VILLARD 10066732ae5cSJean-Christophe PLAGNIOL-VILLARD info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); 10076732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!info) 10086732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENOMEM; 10096732ae5cSJean-Christophe PLAGNIOL-VILLARD 10106732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = at91_pinctrl_probe_dt(pdev, info); 10116732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ret) 10126732ae5cSJean-Christophe PLAGNIOL-VILLARD return ret; 10136732ae5cSJean-Christophe PLAGNIOL-VILLARD 10146732ae5cSJean-Christophe PLAGNIOL-VILLARD /* 10156732ae5cSJean-Christophe PLAGNIOL-VILLARD * We need all the GPIO drivers to probe FIRST, or we will not be able 10166732ae5cSJean-Christophe PLAGNIOL-VILLARD * to obtain references to the struct gpio_chip * for them, and we 10176732ae5cSJean-Christophe PLAGNIOL-VILLARD * need this to proceed. 10186732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 10196732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < info->nbanks; i++) { 10206732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!gpio_chips[i]) { 10216732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i); 10226732ae5cSJean-Christophe PLAGNIOL-VILLARD devm_kfree(&pdev->dev, info); 10236732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EPROBE_DEFER; 10246732ae5cSJean-Christophe PLAGNIOL-VILLARD } 10256732ae5cSJean-Christophe PLAGNIOL-VILLARD } 10266732ae5cSJean-Christophe PLAGNIOL-VILLARD 10276732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_pinctrl_desc.name = dev_name(&pdev->dev); 10286732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK; 10296732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_pinctrl_desc.pins = pdesc = 10306732ae5cSJean-Christophe PLAGNIOL-VILLARD devm_kzalloc(&pdev->dev, sizeof(*pdesc) * at91_pinctrl_desc.npins, GFP_KERNEL); 10316732ae5cSJean-Christophe PLAGNIOL-VILLARD 10326732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!at91_pinctrl_desc.pins) 10336732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENOMEM; 10346732ae5cSJean-Christophe PLAGNIOL-VILLARD 10356732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0 , k = 0; i < info->nbanks; i++) { 10366732ae5cSJean-Christophe PLAGNIOL-VILLARD for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) { 10376732ae5cSJean-Christophe PLAGNIOL-VILLARD pdesc->number = k; 10386732ae5cSJean-Christophe PLAGNIOL-VILLARD pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j); 10396732ae5cSJean-Christophe PLAGNIOL-VILLARD pdesc++; 10406732ae5cSJean-Christophe PLAGNIOL-VILLARD } 10416732ae5cSJean-Christophe PLAGNIOL-VILLARD } 10426732ae5cSJean-Christophe PLAGNIOL-VILLARD 10436732ae5cSJean-Christophe PLAGNIOL-VILLARD platform_set_drvdata(pdev, info); 10446732ae5cSJean-Christophe PLAGNIOL-VILLARD info->pctl = pinctrl_register(&at91_pinctrl_desc, &pdev->dev, info); 10456732ae5cSJean-Christophe PLAGNIOL-VILLARD 10466732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!info->pctl) { 10476732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n"); 10486732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = -EINVAL; 10496732ae5cSJean-Christophe PLAGNIOL-VILLARD goto err; 10506732ae5cSJean-Christophe PLAGNIOL-VILLARD } 10516732ae5cSJean-Christophe PLAGNIOL-VILLARD 10526732ae5cSJean-Christophe PLAGNIOL-VILLARD /* We will handle a range of GPIO pins */ 10536732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < info->nbanks; i++) 10546732ae5cSJean-Christophe PLAGNIOL-VILLARD pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range); 10556732ae5cSJean-Christophe PLAGNIOL-VILLARD 10566732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n"); 10576732ae5cSJean-Christophe PLAGNIOL-VILLARD 10586732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 10596732ae5cSJean-Christophe PLAGNIOL-VILLARD 10606732ae5cSJean-Christophe PLAGNIOL-VILLARD err: 10616732ae5cSJean-Christophe PLAGNIOL-VILLARD return ret; 10626732ae5cSJean-Christophe PLAGNIOL-VILLARD } 10636732ae5cSJean-Christophe PLAGNIOL-VILLARD 1064150632b0SGreg Kroah-Hartman static int at91_pinctrl_remove(struct platform_device *pdev) 10656732ae5cSJean-Christophe PLAGNIOL-VILLARD { 10666732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = platform_get_drvdata(pdev); 10676732ae5cSJean-Christophe PLAGNIOL-VILLARD 10686732ae5cSJean-Christophe PLAGNIOL-VILLARD pinctrl_unregister(info->pctl); 10696732ae5cSJean-Christophe PLAGNIOL-VILLARD 10706732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 10716732ae5cSJean-Christophe PLAGNIOL-VILLARD } 10726732ae5cSJean-Christophe PLAGNIOL-VILLARD 10736732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_gpio_request(struct gpio_chip *chip, unsigned offset) 10746732ae5cSJean-Christophe PLAGNIOL-VILLARD { 10756732ae5cSJean-Christophe PLAGNIOL-VILLARD /* 10766732ae5cSJean-Christophe PLAGNIOL-VILLARD * Map back to global GPIO space and request muxing, the direction 10776732ae5cSJean-Christophe PLAGNIOL-VILLARD * parameter does not matter for this controller. 10786732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 10796732ae5cSJean-Christophe PLAGNIOL-VILLARD int gpio = chip->base + offset; 10806732ae5cSJean-Christophe PLAGNIOL-VILLARD int bank = chip->base / chip->ngpio; 10816732ae5cSJean-Christophe PLAGNIOL-VILLARD 10826732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(chip->dev, "%s:%d pio%c%d(%d)\n", __func__, __LINE__, 10836732ae5cSJean-Christophe PLAGNIOL-VILLARD 'A' + bank, offset, gpio); 10846732ae5cSJean-Christophe PLAGNIOL-VILLARD 10856732ae5cSJean-Christophe PLAGNIOL-VILLARD return pinctrl_request_gpio(gpio); 10866732ae5cSJean-Christophe PLAGNIOL-VILLARD } 10876732ae5cSJean-Christophe PLAGNIOL-VILLARD 10886732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_gpio_free(struct gpio_chip *chip, unsigned offset) 10896732ae5cSJean-Christophe PLAGNIOL-VILLARD { 10906732ae5cSJean-Christophe PLAGNIOL-VILLARD int gpio = chip->base + offset; 10916732ae5cSJean-Christophe PLAGNIOL-VILLARD 10926732ae5cSJean-Christophe PLAGNIOL-VILLARD pinctrl_free_gpio(gpio); 10936732ae5cSJean-Christophe PLAGNIOL-VILLARD } 10946732ae5cSJean-Christophe PLAGNIOL-VILLARD 10956732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 10966732ae5cSJean-Christophe PLAGNIOL-VILLARD { 10976732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 10986732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 10996732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask = 1 << offset; 11006732ae5cSJean-Christophe PLAGNIOL-VILLARD 11016732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_ODR); 11026732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 11036732ae5cSJean-Christophe PLAGNIOL-VILLARD } 11046732ae5cSJean-Christophe PLAGNIOL-VILLARD 11056732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_gpio_get(struct gpio_chip *chip, unsigned offset) 11066732ae5cSJean-Christophe PLAGNIOL-VILLARD { 11076732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 11086732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 11096732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask = 1 << offset; 11106732ae5cSJean-Christophe PLAGNIOL-VILLARD u32 pdsr; 11116732ae5cSJean-Christophe PLAGNIOL-VILLARD 11126732ae5cSJean-Christophe PLAGNIOL-VILLARD pdsr = readl_relaxed(pio + PIO_PDSR); 11136732ae5cSJean-Christophe PLAGNIOL-VILLARD return (pdsr & mask) != 0; 11146732ae5cSJean-Christophe PLAGNIOL-VILLARD } 11156732ae5cSJean-Christophe PLAGNIOL-VILLARD 11166732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_gpio_set(struct gpio_chip *chip, unsigned offset, 11176732ae5cSJean-Christophe PLAGNIOL-VILLARD int val) 11186732ae5cSJean-Christophe PLAGNIOL-VILLARD { 11196732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 11206732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 11216732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask = 1 << offset; 11226732ae5cSJean-Christophe PLAGNIOL-VILLARD 11236732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); 11246732ae5cSJean-Christophe PLAGNIOL-VILLARD } 11256732ae5cSJean-Christophe PLAGNIOL-VILLARD 11266732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 11276732ae5cSJean-Christophe PLAGNIOL-VILLARD int val) 11286732ae5cSJean-Christophe PLAGNIOL-VILLARD { 11296732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 11306732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 11316732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask = 1 << offset; 11326732ae5cSJean-Christophe PLAGNIOL-VILLARD 11336732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); 11346732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_OER); 11356732ae5cSJean-Christophe PLAGNIOL-VILLARD 11366732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 11376732ae5cSJean-Christophe PLAGNIOL-VILLARD } 11386732ae5cSJean-Christophe PLAGNIOL-VILLARD 11396732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 11406732ae5cSJean-Christophe PLAGNIOL-VILLARD { 11416732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 11426732ae5cSJean-Christophe PLAGNIOL-VILLARD int virq; 11436732ae5cSJean-Christophe PLAGNIOL-VILLARD 11446732ae5cSJean-Christophe PLAGNIOL-VILLARD if (offset < chip->ngpio) 11456732ae5cSJean-Christophe PLAGNIOL-VILLARD virq = irq_create_mapping(at91_gpio->domain, offset); 11466732ae5cSJean-Christophe PLAGNIOL-VILLARD else 11476732ae5cSJean-Christophe PLAGNIOL-VILLARD virq = -ENXIO; 11486732ae5cSJean-Christophe PLAGNIOL-VILLARD 11496732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n", 11506732ae5cSJean-Christophe PLAGNIOL-VILLARD chip->label, offset + chip->base, virq); 11516732ae5cSJean-Christophe PLAGNIOL-VILLARD return virq; 11526732ae5cSJean-Christophe PLAGNIOL-VILLARD } 11536732ae5cSJean-Christophe PLAGNIOL-VILLARD 11546732ae5cSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_DEBUG_FS 11556732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 11566732ae5cSJean-Christophe PLAGNIOL-VILLARD { 11576732ae5cSJean-Christophe PLAGNIOL-VILLARD enum at91_mux mode; 11586732ae5cSJean-Christophe PLAGNIOL-VILLARD int i; 11596732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 11606732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 11616732ae5cSJean-Christophe PLAGNIOL-VILLARD 11626732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < chip->ngpio; i++) { 11636732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned pin = chip->base + i; 11646732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask = pin_to_mask(pin); 11656732ae5cSJean-Christophe PLAGNIOL-VILLARD const char *gpio_label; 11666732ae5cSJean-Christophe PLAGNIOL-VILLARD u32 pdsr; 11676732ae5cSJean-Christophe PLAGNIOL-VILLARD 11686732ae5cSJean-Christophe PLAGNIOL-VILLARD gpio_label = gpiochip_is_requested(chip, i); 11696732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!gpio_label) 11706732ae5cSJean-Christophe PLAGNIOL-VILLARD continue; 11716732ae5cSJean-Christophe PLAGNIOL-VILLARD mode = at91_gpio->ops->get_periph(pio, mask); 11726732ae5cSJean-Christophe PLAGNIOL-VILLARD seq_printf(s, "[%s] GPIO%s%d: ", 11736732ae5cSJean-Christophe PLAGNIOL-VILLARD gpio_label, chip->label, i); 11746732ae5cSJean-Christophe PLAGNIOL-VILLARD if (mode == AT91_MUX_GPIO) { 11756732ae5cSJean-Christophe PLAGNIOL-VILLARD pdsr = readl_relaxed(pio + PIO_PDSR); 11766732ae5cSJean-Christophe PLAGNIOL-VILLARD 11776732ae5cSJean-Christophe PLAGNIOL-VILLARD seq_printf(s, "[gpio] %s\n", 11786732ae5cSJean-Christophe PLAGNIOL-VILLARD pdsr & mask ? 11796732ae5cSJean-Christophe PLAGNIOL-VILLARD "set" : "clear"); 11806732ae5cSJean-Christophe PLAGNIOL-VILLARD } else { 11816732ae5cSJean-Christophe PLAGNIOL-VILLARD seq_printf(s, "[periph %c]\n", 11826732ae5cSJean-Christophe PLAGNIOL-VILLARD mode + 'A' - 1); 11836732ae5cSJean-Christophe PLAGNIOL-VILLARD } 11846732ae5cSJean-Christophe PLAGNIOL-VILLARD } 11856732ae5cSJean-Christophe PLAGNIOL-VILLARD } 11866732ae5cSJean-Christophe PLAGNIOL-VILLARD #else 11876732ae5cSJean-Christophe PLAGNIOL-VILLARD #define at91_gpio_dbg_show NULL 11886732ae5cSJean-Christophe PLAGNIOL-VILLARD #endif 11896732ae5cSJean-Christophe PLAGNIOL-VILLARD 11906732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Several AIC controller irqs are dispatched through this GPIO handler. 11916732ae5cSJean-Christophe PLAGNIOL-VILLARD * To use any AT91_PIN_* as an externally triggered IRQ, first call 11926732ae5cSJean-Christophe PLAGNIOL-VILLARD * at91_set_gpio_input() then maybe enable its glitch filter. 11936732ae5cSJean-Christophe PLAGNIOL-VILLARD * Then just request_irq() with the pin ID; it works like any ARM IRQ 11946732ae5cSJean-Christophe PLAGNIOL-VILLARD * handler. 11956732ae5cSJean-Christophe PLAGNIOL-VILLARD * First implementation always triggers on rising and falling edges 11966732ae5cSJean-Christophe PLAGNIOL-VILLARD * whereas the newer PIO3 can be additionally configured to trigger on 11976732ae5cSJean-Christophe PLAGNIOL-VILLARD * level, edge with any polarity. 11986732ae5cSJean-Christophe PLAGNIOL-VILLARD * 11996732ae5cSJean-Christophe PLAGNIOL-VILLARD * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after 12006732ae5cSJean-Christophe PLAGNIOL-VILLARD * configuring them with at91_set_a_periph() or at91_set_b_periph(). 12016732ae5cSJean-Christophe PLAGNIOL-VILLARD * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering. 12026732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 12036732ae5cSJean-Christophe PLAGNIOL-VILLARD 12046732ae5cSJean-Christophe PLAGNIOL-VILLARD static void gpio_irq_mask(struct irq_data *d) 12056732ae5cSJean-Christophe PLAGNIOL-VILLARD { 12066732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 12076732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 12086732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask = 1 << d->hwirq; 12096732ae5cSJean-Christophe PLAGNIOL-VILLARD 12106732ae5cSJean-Christophe PLAGNIOL-VILLARD if (pio) 12116732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_IDR); 12126732ae5cSJean-Christophe PLAGNIOL-VILLARD } 12136732ae5cSJean-Christophe PLAGNIOL-VILLARD 12146732ae5cSJean-Christophe PLAGNIOL-VILLARD static void gpio_irq_unmask(struct irq_data *d) 12156732ae5cSJean-Christophe PLAGNIOL-VILLARD { 12166732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 12176732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 12186732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask = 1 << d->hwirq; 12196732ae5cSJean-Christophe PLAGNIOL-VILLARD 12206732ae5cSJean-Christophe PLAGNIOL-VILLARD if (pio) 12216732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_IER); 12226732ae5cSJean-Christophe PLAGNIOL-VILLARD } 12236732ae5cSJean-Christophe PLAGNIOL-VILLARD 12246732ae5cSJean-Christophe PLAGNIOL-VILLARD static int gpio_irq_type(struct irq_data *d, unsigned type) 12256732ae5cSJean-Christophe PLAGNIOL-VILLARD { 12266732ae5cSJean-Christophe PLAGNIOL-VILLARD switch (type) { 12276732ae5cSJean-Christophe PLAGNIOL-VILLARD case IRQ_TYPE_NONE: 12286732ae5cSJean-Christophe PLAGNIOL-VILLARD case IRQ_TYPE_EDGE_BOTH: 12296732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 12306732ae5cSJean-Christophe PLAGNIOL-VILLARD default: 12316732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 12326732ae5cSJean-Christophe PLAGNIOL-VILLARD } 12336732ae5cSJean-Christophe PLAGNIOL-VILLARD } 12346732ae5cSJean-Christophe PLAGNIOL-VILLARD 12356732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Alternate irq type for PIO3 support */ 12366732ae5cSJean-Christophe PLAGNIOL-VILLARD static int alt_gpio_irq_type(struct irq_data *d, unsigned type) 12376732ae5cSJean-Christophe PLAGNIOL-VILLARD { 12386732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 12396732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 12406732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask = 1 << d->hwirq; 12416732ae5cSJean-Christophe PLAGNIOL-VILLARD 12426732ae5cSJean-Christophe PLAGNIOL-VILLARD switch (type) { 12436732ae5cSJean-Christophe PLAGNIOL-VILLARD case IRQ_TYPE_EDGE_RISING: 124499fce029SBoris BREZILLON irq_set_handler(d->irq, handle_simple_irq); 12456732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_ESR); 12466732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_REHLSR); 12476732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 12486732ae5cSJean-Christophe PLAGNIOL-VILLARD case IRQ_TYPE_EDGE_FALLING: 124999fce029SBoris BREZILLON irq_set_handler(d->irq, handle_simple_irq); 12506732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_ESR); 12516732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_FELLSR); 12526732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 12536732ae5cSJean-Christophe PLAGNIOL-VILLARD case IRQ_TYPE_LEVEL_LOW: 125499fce029SBoris BREZILLON irq_set_handler(d->irq, handle_level_irq); 12556732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_LSR); 12566732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_FELLSR); 12576732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 12586732ae5cSJean-Christophe PLAGNIOL-VILLARD case IRQ_TYPE_LEVEL_HIGH: 125999fce029SBoris BREZILLON irq_set_handler(d->irq, handle_level_irq); 12606732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_LSR); 12616732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_REHLSR); 12626732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 12636732ae5cSJean-Christophe PLAGNIOL-VILLARD case IRQ_TYPE_EDGE_BOTH: 12646732ae5cSJean-Christophe PLAGNIOL-VILLARD /* 12656732ae5cSJean-Christophe PLAGNIOL-VILLARD * disable additional interrupt modes: 12666732ae5cSJean-Christophe PLAGNIOL-VILLARD * fall back to default behavior 12676732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 126899fce029SBoris BREZILLON irq_set_handler(d->irq, handle_simple_irq); 12696732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_AIMDR); 12706732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 12716732ae5cSJean-Christophe PLAGNIOL-VILLARD case IRQ_TYPE_NONE: 12726732ae5cSJean-Christophe PLAGNIOL-VILLARD default: 12736732ae5cSJean-Christophe PLAGNIOL-VILLARD pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq)); 12746732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 12756732ae5cSJean-Christophe PLAGNIOL-VILLARD } 12766732ae5cSJean-Christophe PLAGNIOL-VILLARD 12776732ae5cSJean-Christophe PLAGNIOL-VILLARD /* enable additional interrupt modes */ 12786732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_AIMER); 12796732ae5cSJean-Christophe PLAGNIOL-VILLARD 12806732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 12816732ae5cSJean-Christophe PLAGNIOL-VILLARD } 12826732ae5cSJean-Christophe PLAGNIOL-VILLARD 12836732ae5cSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_PM 1284647f8d94SLudovic Desroches 1285647f8d94SLudovic Desroches static u32 wakeups[MAX_GPIO_BANKS]; 1286647f8d94SLudovic Desroches static u32 backups[MAX_GPIO_BANKS]; 1287647f8d94SLudovic Desroches 12886732ae5cSJean-Christophe PLAGNIOL-VILLARD static int gpio_irq_set_wake(struct irq_data *d, unsigned state) 12896732ae5cSJean-Christophe PLAGNIOL-VILLARD { 12906732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 12916732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned bank = at91_gpio->pioc_idx; 1292647f8d94SLudovic Desroches unsigned mask = 1 << d->hwirq; 12936732ae5cSJean-Christophe PLAGNIOL-VILLARD 12946732ae5cSJean-Christophe PLAGNIOL-VILLARD if (unlikely(bank >= MAX_GPIO_BANKS)) 12956732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 12966732ae5cSJean-Christophe PLAGNIOL-VILLARD 1297647f8d94SLudovic Desroches if (state) 1298647f8d94SLudovic Desroches wakeups[bank] |= mask; 1299647f8d94SLudovic Desroches else 1300647f8d94SLudovic Desroches wakeups[bank] &= ~mask; 1301647f8d94SLudovic Desroches 13026732ae5cSJean-Christophe PLAGNIOL-VILLARD irq_set_irq_wake(at91_gpio->pioc_virq, state); 13036732ae5cSJean-Christophe PLAGNIOL-VILLARD 13046732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 13056732ae5cSJean-Christophe PLAGNIOL-VILLARD } 1306647f8d94SLudovic Desroches 1307647f8d94SLudovic Desroches void at91_pinctrl_gpio_suspend(void) 1308647f8d94SLudovic Desroches { 1309647f8d94SLudovic Desroches int i; 1310647f8d94SLudovic Desroches 1311647f8d94SLudovic Desroches for (i = 0; i < gpio_banks; i++) { 1312647f8d94SLudovic Desroches void __iomem *pio; 1313647f8d94SLudovic Desroches 1314647f8d94SLudovic Desroches if (!gpio_chips[i]) 1315647f8d94SLudovic Desroches continue; 1316647f8d94SLudovic Desroches 1317647f8d94SLudovic Desroches pio = gpio_chips[i]->regbase; 1318647f8d94SLudovic Desroches 1319647f8d94SLudovic Desroches backups[i] = __raw_readl(pio + PIO_IMR); 1320647f8d94SLudovic Desroches __raw_writel(backups[i], pio + PIO_IDR); 1321647f8d94SLudovic Desroches __raw_writel(wakeups[i], pio + PIO_IER); 1322647f8d94SLudovic Desroches 1323647f8d94SLudovic Desroches if (!wakeups[i]) { 1324647f8d94SLudovic Desroches clk_unprepare(gpio_chips[i]->clock); 1325647f8d94SLudovic Desroches clk_disable(gpio_chips[i]->clock); 1326647f8d94SLudovic Desroches } else { 1327647f8d94SLudovic Desroches printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 1328647f8d94SLudovic Desroches 'A'+i, wakeups[i]); 1329647f8d94SLudovic Desroches } 1330647f8d94SLudovic Desroches } 1331647f8d94SLudovic Desroches } 1332647f8d94SLudovic Desroches 1333647f8d94SLudovic Desroches void at91_pinctrl_gpio_resume(void) 1334647f8d94SLudovic Desroches { 1335647f8d94SLudovic Desroches int i; 1336647f8d94SLudovic Desroches 1337647f8d94SLudovic Desroches for (i = 0; i < gpio_banks; i++) { 1338647f8d94SLudovic Desroches void __iomem *pio; 1339647f8d94SLudovic Desroches 1340647f8d94SLudovic Desroches if (!gpio_chips[i]) 1341647f8d94SLudovic Desroches continue; 1342647f8d94SLudovic Desroches 1343647f8d94SLudovic Desroches pio = gpio_chips[i]->regbase; 1344647f8d94SLudovic Desroches 1345647f8d94SLudovic Desroches if (!wakeups[i]) { 1346647f8d94SLudovic Desroches if (clk_prepare(gpio_chips[i]->clock) == 0) 1347647f8d94SLudovic Desroches clk_enable(gpio_chips[i]->clock); 1348647f8d94SLudovic Desroches } 1349647f8d94SLudovic Desroches 1350647f8d94SLudovic Desroches __raw_writel(wakeups[i], pio + PIO_IDR); 1351647f8d94SLudovic Desroches __raw_writel(backups[i], pio + PIO_IER); 1352647f8d94SLudovic Desroches } 1353647f8d94SLudovic Desroches } 1354647f8d94SLudovic Desroches 13556732ae5cSJean-Christophe PLAGNIOL-VILLARD #else 13566732ae5cSJean-Christophe PLAGNIOL-VILLARD #define gpio_irq_set_wake NULL 1357647f8d94SLudovic Desroches #endif /* CONFIG_PM */ 13586732ae5cSJean-Christophe PLAGNIOL-VILLARD 13596732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct irq_chip gpio_irqchip = { 13606732ae5cSJean-Christophe PLAGNIOL-VILLARD .name = "GPIO", 13616732ae5cSJean-Christophe PLAGNIOL-VILLARD .irq_disable = gpio_irq_mask, 13626732ae5cSJean-Christophe PLAGNIOL-VILLARD .irq_mask = gpio_irq_mask, 13636732ae5cSJean-Christophe PLAGNIOL-VILLARD .irq_unmask = gpio_irq_unmask, 13646732ae5cSJean-Christophe PLAGNIOL-VILLARD /* .irq_set_type is set dynamically */ 13656732ae5cSJean-Christophe PLAGNIOL-VILLARD .irq_set_wake = gpio_irq_set_wake, 13666732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 13676732ae5cSJean-Christophe PLAGNIOL-VILLARD 13686732ae5cSJean-Christophe PLAGNIOL-VILLARD static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) 13696732ae5cSJean-Christophe PLAGNIOL-VILLARD { 13706732ae5cSJean-Christophe PLAGNIOL-VILLARD struct irq_chip *chip = irq_desc_get_chip(desc); 13716732ae5cSJean-Christophe PLAGNIOL-VILLARD struct irq_data *idata = irq_desc_get_irq_data(desc); 13726732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata); 13736732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 13746732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned long isr; 13756732ae5cSJean-Christophe PLAGNIOL-VILLARD int n; 13766732ae5cSJean-Christophe PLAGNIOL-VILLARD 13776732ae5cSJean-Christophe PLAGNIOL-VILLARD chained_irq_enter(chip, desc); 13786732ae5cSJean-Christophe PLAGNIOL-VILLARD for (;;) { 13796732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Reading ISR acks pending (edge triggered) GPIO interrupts. 13806732ae5cSJean-Christophe PLAGNIOL-VILLARD * When there none are pending, we're finished unless we need 13816732ae5cSJean-Christophe PLAGNIOL-VILLARD * to process multiple banks (like ID_PIOCDE on sam9263). 13826732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 13836732ae5cSJean-Christophe PLAGNIOL-VILLARD isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR); 13846732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!isr) { 13856732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!at91_gpio->next) 13866732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 13876732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_gpio = at91_gpio->next; 13886732ae5cSJean-Christophe PLAGNIOL-VILLARD pio = at91_gpio->regbase; 13896732ae5cSJean-Christophe PLAGNIOL-VILLARD continue; 13906732ae5cSJean-Christophe PLAGNIOL-VILLARD } 13916732ae5cSJean-Christophe PLAGNIOL-VILLARD 139205daa16aSWei Yongjun for_each_set_bit(n, &isr, BITS_PER_LONG) { 13936732ae5cSJean-Christophe PLAGNIOL-VILLARD generic_handle_irq(irq_find_mapping(at91_gpio->domain, n)); 13946732ae5cSJean-Christophe PLAGNIOL-VILLARD } 13956732ae5cSJean-Christophe PLAGNIOL-VILLARD } 13966732ae5cSJean-Christophe PLAGNIOL-VILLARD chained_irq_exit(chip, desc); 13976732ae5cSJean-Christophe PLAGNIOL-VILLARD /* now it may re-trigger */ 13986732ae5cSJean-Christophe PLAGNIOL-VILLARD } 13996732ae5cSJean-Christophe PLAGNIOL-VILLARD 14006732ae5cSJean-Christophe PLAGNIOL-VILLARD /* 14016732ae5cSJean-Christophe PLAGNIOL-VILLARD * This lock class tells lockdep that GPIO irqs are in a different 14026732ae5cSJean-Christophe PLAGNIOL-VILLARD * category than their parents, so it won't report false recursion. 14036732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 14046732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct lock_class_key gpio_lock_class; 14056732ae5cSJean-Christophe PLAGNIOL-VILLARD 14066732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq, 14076732ae5cSJean-Christophe PLAGNIOL-VILLARD irq_hw_number_t hw) 14086732ae5cSJean-Christophe PLAGNIOL-VILLARD { 14096732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = h->host_data; 141099fce029SBoris BREZILLON void __iomem *pio = at91_gpio->regbase; 141199fce029SBoris BREZILLON u32 mask = 1 << hw; 14126732ae5cSJean-Christophe PLAGNIOL-VILLARD 14136732ae5cSJean-Christophe PLAGNIOL-VILLARD irq_set_lockdep_class(virq, &gpio_lock_class); 14146732ae5cSJean-Christophe PLAGNIOL-VILLARD 14156732ae5cSJean-Christophe PLAGNIOL-VILLARD /* 14166732ae5cSJean-Christophe PLAGNIOL-VILLARD * Can use the "simple" and not "edge" handler since it's 14176732ae5cSJean-Christophe PLAGNIOL-VILLARD * shorter, and the AIC handles interrupts sanely. 14186732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 141999fce029SBoris BREZILLON irq_set_chip(virq, &gpio_irqchip); 142099fce029SBoris BREZILLON if ((at91_gpio->ops == &at91sam9x5_ops) && 142199fce029SBoris BREZILLON (readl_relaxed(pio + PIO_AIMMR) & mask) && 142299fce029SBoris BREZILLON (readl_relaxed(pio + PIO_ELSR) & mask)) 142399fce029SBoris BREZILLON irq_set_handler(virq, handle_level_irq); 142499fce029SBoris BREZILLON else 142599fce029SBoris BREZILLON irq_set_handler(virq, handle_simple_irq); 14266732ae5cSJean-Christophe PLAGNIOL-VILLARD set_irq_flags(virq, IRQF_VALID); 14276732ae5cSJean-Christophe PLAGNIOL-VILLARD irq_set_chip_data(virq, at91_gpio); 14286732ae5cSJean-Christophe PLAGNIOL-VILLARD 14296732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 14306732ae5cSJean-Christophe PLAGNIOL-VILLARD } 14316732ae5cSJean-Christophe PLAGNIOL-VILLARD 1432f6f94f66SAxel Lin static int at91_gpio_irq_domain_xlate(struct irq_domain *d, 1433f6f94f66SAxel Lin struct device_node *ctrlr, 1434a728c7cdSJean-Christophe PLAGNIOL-VILLARD const u32 *intspec, unsigned int intsize, 1435f6f94f66SAxel Lin irq_hw_number_t *out_hwirq, 1436f6f94f66SAxel Lin unsigned int *out_type) 1437a728c7cdSJean-Christophe PLAGNIOL-VILLARD { 1438a728c7cdSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = d->host_data; 1439a728c7cdSJean-Christophe PLAGNIOL-VILLARD int ret; 1440a728c7cdSJean-Christophe PLAGNIOL-VILLARD int pin = at91_gpio->chip.base + intspec[0]; 1441a728c7cdSJean-Christophe PLAGNIOL-VILLARD 1442a728c7cdSJean-Christophe PLAGNIOL-VILLARD if (WARN_ON(intsize < 2)) 1443a728c7cdSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 1444a728c7cdSJean-Christophe PLAGNIOL-VILLARD *out_hwirq = intspec[0]; 1445a728c7cdSJean-Christophe PLAGNIOL-VILLARD *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK; 1446a728c7cdSJean-Christophe PLAGNIOL-VILLARD 1447a728c7cdSJean-Christophe PLAGNIOL-VILLARD ret = gpio_request(pin, ctrlr->full_name); 1448a728c7cdSJean-Christophe PLAGNIOL-VILLARD if (ret) 1449a728c7cdSJean-Christophe PLAGNIOL-VILLARD return ret; 1450a728c7cdSJean-Christophe PLAGNIOL-VILLARD 1451a728c7cdSJean-Christophe PLAGNIOL-VILLARD ret = gpio_direction_input(pin); 1452a728c7cdSJean-Christophe PLAGNIOL-VILLARD if (ret) 1453a728c7cdSJean-Christophe PLAGNIOL-VILLARD return ret; 1454a728c7cdSJean-Christophe PLAGNIOL-VILLARD 1455a728c7cdSJean-Christophe PLAGNIOL-VILLARD return 0; 1456a728c7cdSJean-Christophe PLAGNIOL-VILLARD } 1457a728c7cdSJean-Christophe PLAGNIOL-VILLARD 14586732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct irq_domain_ops at91_gpio_ops = { 14596732ae5cSJean-Christophe PLAGNIOL-VILLARD .map = at91_gpio_irq_map, 1460a728c7cdSJean-Christophe PLAGNIOL-VILLARD .xlate = at91_gpio_irq_domain_xlate, 14616732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 14626732ae5cSJean-Christophe PLAGNIOL-VILLARD 14636732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_gpio_of_irq_setup(struct device_node *node, 14646732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio) 14656732ae5cSJean-Christophe PLAGNIOL-VILLARD { 14666732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *prev = NULL; 14676732ae5cSJean-Christophe PLAGNIOL-VILLARD struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq); 14686732ae5cSJean-Christophe PLAGNIOL-VILLARD 14696732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_gpio->pioc_hwirq = irqd_to_hwirq(d); 14706732ae5cSJean-Christophe PLAGNIOL-VILLARD 14716732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Setup proper .irq_set_type function */ 14726732ae5cSJean-Christophe PLAGNIOL-VILLARD gpio_irqchip.irq_set_type = at91_gpio->ops->irq_type; 14736732ae5cSJean-Christophe PLAGNIOL-VILLARD 14746732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Disable irqs of this PIO controller */ 14756732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(~0, at91_gpio->regbase + PIO_IDR); 14766732ae5cSJean-Christophe PLAGNIOL-VILLARD 14776732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Setup irq domain */ 14786732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio, 14796732ae5cSJean-Christophe PLAGNIOL-VILLARD &at91_gpio_ops, at91_gpio); 14806732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!at91_gpio->domain) 14816732ae5cSJean-Christophe PLAGNIOL-VILLARD panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n", 14826732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_gpio->pioc_idx); 14836732ae5cSJean-Christophe PLAGNIOL-VILLARD 14846732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Setup chained handler */ 14856732ae5cSJean-Christophe PLAGNIOL-VILLARD if (at91_gpio->pioc_idx) 14866732ae5cSJean-Christophe PLAGNIOL-VILLARD prev = gpio_chips[at91_gpio->pioc_idx - 1]; 14876732ae5cSJean-Christophe PLAGNIOL-VILLARD 14886732ae5cSJean-Christophe PLAGNIOL-VILLARD /* The toplevel handler handles one bank of GPIOs, except 14896732ae5cSJean-Christophe PLAGNIOL-VILLARD * on some SoC it can handles up to three... 14906732ae5cSJean-Christophe PLAGNIOL-VILLARD * We only set up the handler for the first of the list. 14916732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 14926732ae5cSJean-Christophe PLAGNIOL-VILLARD if (prev && prev->next == at91_gpio) 14936732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 14946732ae5cSJean-Christophe PLAGNIOL-VILLARD 14956732ae5cSJean-Christophe PLAGNIOL-VILLARD irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio); 14966732ae5cSJean-Christophe PLAGNIOL-VILLARD irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler); 14976732ae5cSJean-Christophe PLAGNIOL-VILLARD 14986732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 14996732ae5cSJean-Christophe PLAGNIOL-VILLARD } 15006732ae5cSJean-Christophe PLAGNIOL-VILLARD 15016732ae5cSJean-Christophe PLAGNIOL-VILLARD /* This structure is replicated for each GPIO block allocated at probe time */ 15026732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct gpio_chip at91_gpio_template = { 15036732ae5cSJean-Christophe PLAGNIOL-VILLARD .request = at91_gpio_request, 15046732ae5cSJean-Christophe PLAGNIOL-VILLARD .free = at91_gpio_free, 15056732ae5cSJean-Christophe PLAGNIOL-VILLARD .direction_input = at91_gpio_direction_input, 15066732ae5cSJean-Christophe PLAGNIOL-VILLARD .get = at91_gpio_get, 15076732ae5cSJean-Christophe PLAGNIOL-VILLARD .direction_output = at91_gpio_direction_output, 15086732ae5cSJean-Christophe PLAGNIOL-VILLARD .set = at91_gpio_set, 15096732ae5cSJean-Christophe PLAGNIOL-VILLARD .to_irq = at91_gpio_to_irq, 15106732ae5cSJean-Christophe PLAGNIOL-VILLARD .dbg_show = at91_gpio_dbg_show, 15116732ae5cSJean-Christophe PLAGNIOL-VILLARD .can_sleep = 0, 15126732ae5cSJean-Christophe PLAGNIOL-VILLARD .ngpio = MAX_NB_GPIO_PER_BANK, 15136732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 15146732ae5cSJean-Christophe PLAGNIOL-VILLARD 1515150632b0SGreg Kroah-Hartman static void at91_gpio_probe_fixup(void) 15166732ae5cSJean-Christophe PLAGNIOL-VILLARD { 15176732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned i; 15186732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio, *last = NULL; 15196732ae5cSJean-Christophe PLAGNIOL-VILLARD 15206732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < gpio_banks; i++) { 15216732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_gpio = gpio_chips[i]; 15226732ae5cSJean-Christophe PLAGNIOL-VILLARD 15236732ae5cSJean-Christophe PLAGNIOL-VILLARD /* 15246732ae5cSJean-Christophe PLAGNIOL-VILLARD * GPIO controller are grouped on some SoC: 15256732ae5cSJean-Christophe PLAGNIOL-VILLARD * PIOC, PIOD and PIOE can share the same IRQ line 15266732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 15276732ae5cSJean-Christophe PLAGNIOL-VILLARD if (last && last->pioc_virq == at91_gpio->pioc_virq) 15286732ae5cSJean-Christophe PLAGNIOL-VILLARD last->next = at91_gpio; 15296732ae5cSJean-Christophe PLAGNIOL-VILLARD last = at91_gpio; 15306732ae5cSJean-Christophe PLAGNIOL-VILLARD } 15316732ae5cSJean-Christophe PLAGNIOL-VILLARD } 15326732ae5cSJean-Christophe PLAGNIOL-VILLARD 1533150632b0SGreg Kroah-Hartman static struct of_device_id at91_gpio_of_match[] = { 15346732ae5cSJean-Christophe PLAGNIOL-VILLARD { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, }, 15356732ae5cSJean-Christophe PLAGNIOL-VILLARD { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops }, 15366732ae5cSJean-Christophe PLAGNIOL-VILLARD { /* sentinel */ } 15376732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 15386732ae5cSJean-Christophe PLAGNIOL-VILLARD 1539150632b0SGreg Kroah-Hartman static int at91_gpio_probe(struct platform_device *pdev) 15406732ae5cSJean-Christophe PLAGNIOL-VILLARD { 15416732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *np = pdev->dev.of_node; 15426732ae5cSJean-Christophe PLAGNIOL-VILLARD struct resource *res; 15436732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_chip = NULL; 15446732ae5cSJean-Christophe PLAGNIOL-VILLARD struct gpio_chip *chip; 15456732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_gpio_range *range; 15466732ae5cSJean-Christophe PLAGNIOL-VILLARD int ret = 0; 154732b01a36SJean-Christophe PLAGNIOL-VILLARD int irq, i; 15486732ae5cSJean-Christophe PLAGNIOL-VILLARD int alias_idx = of_alias_get_id(np, "gpio"); 15496732ae5cSJean-Christophe PLAGNIOL-VILLARD uint32_t ngpio; 155032b01a36SJean-Christophe PLAGNIOL-VILLARD char **names; 15516732ae5cSJean-Christophe PLAGNIOL-VILLARD 15526732ae5cSJean-Christophe PLAGNIOL-VILLARD BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips)); 15536732ae5cSJean-Christophe PLAGNIOL-VILLARD if (gpio_chips[alias_idx]) { 15546732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = -EBUSY; 15556732ae5cSJean-Christophe PLAGNIOL-VILLARD goto err; 15566732ae5cSJean-Christophe PLAGNIOL-VILLARD } 15576732ae5cSJean-Christophe PLAGNIOL-VILLARD 15586732ae5cSJean-Christophe PLAGNIOL-VILLARD irq = platform_get_irq(pdev, 0); 15596732ae5cSJean-Christophe PLAGNIOL-VILLARD if (irq < 0) { 15606732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = irq; 15616732ae5cSJean-Christophe PLAGNIOL-VILLARD goto err; 15626732ae5cSJean-Christophe PLAGNIOL-VILLARD } 15636732ae5cSJean-Christophe PLAGNIOL-VILLARD 15646732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL); 15656732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!at91_chip) { 15666732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = -ENOMEM; 15676732ae5cSJean-Christophe PLAGNIOL-VILLARD goto err; 15686732ae5cSJean-Christophe PLAGNIOL-VILLARD } 15696732ae5cSJean-Christophe PLAGNIOL-VILLARD 1570f50b9e12SWolfram Sang res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 15719e0c1fb2SThierry Reding at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res); 15729e0c1fb2SThierry Reding if (IS_ERR(at91_chip->regbase)) { 15739e0c1fb2SThierry Reding ret = PTR_ERR(at91_chip->regbase); 15746732ae5cSJean-Christophe PLAGNIOL-VILLARD goto err; 15756732ae5cSJean-Christophe PLAGNIOL-VILLARD } 15766732ae5cSJean-Christophe PLAGNIOL-VILLARD 1577dffa9123SJean-Christophe PLAGNIOL-VILLARD at91_chip->ops = (struct at91_pinctrl_mux_ops *) 15786732ae5cSJean-Christophe PLAGNIOL-VILLARD of_match_device(at91_gpio_of_match, &pdev->dev)->data; 15796732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_chip->pioc_virq = irq; 15806732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_chip->pioc_idx = alias_idx; 15816732ae5cSJean-Christophe PLAGNIOL-VILLARD 15826732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_chip->clock = clk_get(&pdev->dev, NULL); 15836732ae5cSJean-Christophe PLAGNIOL-VILLARD if (IS_ERR(at91_chip->clock)) { 15846732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(&pdev->dev, "failed to get clock, ignoring.\n"); 15856732ae5cSJean-Christophe PLAGNIOL-VILLARD goto err; 15866732ae5cSJean-Christophe PLAGNIOL-VILLARD } 15876732ae5cSJean-Christophe PLAGNIOL-VILLARD 15886732ae5cSJean-Christophe PLAGNIOL-VILLARD if (clk_prepare(at91_chip->clock)) 15896732ae5cSJean-Christophe PLAGNIOL-VILLARD goto clk_prep_err; 15906732ae5cSJean-Christophe PLAGNIOL-VILLARD 15916732ae5cSJean-Christophe PLAGNIOL-VILLARD /* enable PIO controller's clock */ 15926732ae5cSJean-Christophe PLAGNIOL-VILLARD if (clk_enable(at91_chip->clock)) { 15936732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(&pdev->dev, "failed to enable clock, ignoring.\n"); 15946732ae5cSJean-Christophe PLAGNIOL-VILLARD goto clk_err; 15956732ae5cSJean-Christophe PLAGNIOL-VILLARD } 15966732ae5cSJean-Christophe PLAGNIOL-VILLARD 15976732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_chip->chip = at91_gpio_template; 15986732ae5cSJean-Christophe PLAGNIOL-VILLARD 15996732ae5cSJean-Christophe PLAGNIOL-VILLARD chip = &at91_chip->chip; 16006732ae5cSJean-Christophe PLAGNIOL-VILLARD chip->of_node = np; 16016732ae5cSJean-Christophe PLAGNIOL-VILLARD chip->label = dev_name(&pdev->dev); 16026732ae5cSJean-Christophe PLAGNIOL-VILLARD chip->dev = &pdev->dev; 16036732ae5cSJean-Christophe PLAGNIOL-VILLARD chip->owner = THIS_MODULE; 16046732ae5cSJean-Christophe PLAGNIOL-VILLARD chip->base = alias_idx * MAX_NB_GPIO_PER_BANK; 16056732ae5cSJean-Christophe PLAGNIOL-VILLARD 16066732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) { 16076732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ngpio >= MAX_NB_GPIO_PER_BANK) 16086732ae5cSJean-Christophe PLAGNIOL-VILLARD pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n", 16096732ae5cSJean-Christophe PLAGNIOL-VILLARD alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK); 16106732ae5cSJean-Christophe PLAGNIOL-VILLARD else 16116732ae5cSJean-Christophe PLAGNIOL-VILLARD chip->ngpio = ngpio; 16126732ae5cSJean-Christophe PLAGNIOL-VILLARD } 16136732ae5cSJean-Christophe PLAGNIOL-VILLARD 16143c93600dSSachin Kamat names = devm_kzalloc(&pdev->dev, sizeof(char *) * chip->ngpio, 16153c93600dSSachin Kamat GFP_KERNEL); 161632b01a36SJean-Christophe PLAGNIOL-VILLARD 161732b01a36SJean-Christophe PLAGNIOL-VILLARD if (!names) { 161832b01a36SJean-Christophe PLAGNIOL-VILLARD ret = -ENOMEM; 161932b01a36SJean-Christophe PLAGNIOL-VILLARD goto clk_err; 162032b01a36SJean-Christophe PLAGNIOL-VILLARD } 162132b01a36SJean-Christophe PLAGNIOL-VILLARD 162232b01a36SJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < chip->ngpio; i++) 162332b01a36SJean-Christophe PLAGNIOL-VILLARD names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i); 162432b01a36SJean-Christophe PLAGNIOL-VILLARD 162532b01a36SJean-Christophe PLAGNIOL-VILLARD chip->names = (const char *const *)names; 162632b01a36SJean-Christophe PLAGNIOL-VILLARD 16276732ae5cSJean-Christophe PLAGNIOL-VILLARD range = &at91_chip->range; 16286732ae5cSJean-Christophe PLAGNIOL-VILLARD range->name = chip->label; 16296732ae5cSJean-Christophe PLAGNIOL-VILLARD range->id = alias_idx; 16306732ae5cSJean-Christophe PLAGNIOL-VILLARD range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK; 16316732ae5cSJean-Christophe PLAGNIOL-VILLARD 16326732ae5cSJean-Christophe PLAGNIOL-VILLARD range->npins = chip->ngpio; 16336732ae5cSJean-Christophe PLAGNIOL-VILLARD range->gc = chip; 16346732ae5cSJean-Christophe PLAGNIOL-VILLARD 16356732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = gpiochip_add(chip); 16366732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ret) 16376732ae5cSJean-Christophe PLAGNIOL-VILLARD goto clk_err; 16386732ae5cSJean-Christophe PLAGNIOL-VILLARD 16396732ae5cSJean-Christophe PLAGNIOL-VILLARD gpio_chips[alias_idx] = at91_chip; 16406732ae5cSJean-Christophe PLAGNIOL-VILLARD gpio_banks = max(gpio_banks, alias_idx + 1); 16416732ae5cSJean-Christophe PLAGNIOL-VILLARD 16426732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_gpio_probe_fixup(); 16436732ae5cSJean-Christophe PLAGNIOL-VILLARD 16446732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_gpio_of_irq_setup(np, at91_chip); 16456732ae5cSJean-Christophe PLAGNIOL-VILLARD 16466732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase); 16476732ae5cSJean-Christophe PLAGNIOL-VILLARD 16486732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 16496732ae5cSJean-Christophe PLAGNIOL-VILLARD 16506732ae5cSJean-Christophe PLAGNIOL-VILLARD clk_err: 16516732ae5cSJean-Christophe PLAGNIOL-VILLARD clk_unprepare(at91_chip->clock); 16526732ae5cSJean-Christophe PLAGNIOL-VILLARD clk_prep_err: 16536732ae5cSJean-Christophe PLAGNIOL-VILLARD clk_put(at91_chip->clock); 16546732ae5cSJean-Christophe PLAGNIOL-VILLARD err: 16556732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx); 16566732ae5cSJean-Christophe PLAGNIOL-VILLARD 16576732ae5cSJean-Christophe PLAGNIOL-VILLARD return ret; 16586732ae5cSJean-Christophe PLAGNIOL-VILLARD } 16596732ae5cSJean-Christophe PLAGNIOL-VILLARD 16606732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct platform_driver at91_gpio_driver = { 16616732ae5cSJean-Christophe PLAGNIOL-VILLARD .driver = { 16626732ae5cSJean-Christophe PLAGNIOL-VILLARD .name = "gpio-at91", 16636732ae5cSJean-Christophe PLAGNIOL-VILLARD .owner = THIS_MODULE, 16646732ae5cSJean-Christophe PLAGNIOL-VILLARD .of_match_table = of_match_ptr(at91_gpio_of_match), 16656732ae5cSJean-Christophe PLAGNIOL-VILLARD }, 16666732ae5cSJean-Christophe PLAGNIOL-VILLARD .probe = at91_gpio_probe, 16676732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 16686732ae5cSJean-Christophe PLAGNIOL-VILLARD 16696732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct platform_driver at91_pinctrl_driver = { 16706732ae5cSJean-Christophe PLAGNIOL-VILLARD .driver = { 16716732ae5cSJean-Christophe PLAGNIOL-VILLARD .name = "pinctrl-at91", 16726732ae5cSJean-Christophe PLAGNIOL-VILLARD .owner = THIS_MODULE, 16736732ae5cSJean-Christophe PLAGNIOL-VILLARD .of_match_table = of_match_ptr(at91_pinctrl_of_match), 16746732ae5cSJean-Christophe PLAGNIOL-VILLARD }, 16756732ae5cSJean-Christophe PLAGNIOL-VILLARD .probe = at91_pinctrl_probe, 1676150632b0SGreg Kroah-Hartman .remove = at91_pinctrl_remove, 16776732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 16786732ae5cSJean-Christophe PLAGNIOL-VILLARD 16796732ae5cSJean-Christophe PLAGNIOL-VILLARD static int __init at91_pinctrl_init(void) 16806732ae5cSJean-Christophe PLAGNIOL-VILLARD { 16816732ae5cSJean-Christophe PLAGNIOL-VILLARD int ret; 16826732ae5cSJean-Christophe PLAGNIOL-VILLARD 16836732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = platform_driver_register(&at91_gpio_driver); 16846732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ret) 16856732ae5cSJean-Christophe PLAGNIOL-VILLARD return ret; 16866732ae5cSJean-Christophe PLAGNIOL-VILLARD return platform_driver_register(&at91_pinctrl_driver); 16876732ae5cSJean-Christophe PLAGNIOL-VILLARD } 16886732ae5cSJean-Christophe PLAGNIOL-VILLARD arch_initcall(at91_pinctrl_init); 16896732ae5cSJean-Christophe PLAGNIOL-VILLARD 16906732ae5cSJean-Christophe PLAGNIOL-VILLARD static void __exit at91_pinctrl_exit(void) 16916732ae5cSJean-Christophe PLAGNIOL-VILLARD { 16926732ae5cSJean-Christophe PLAGNIOL-VILLARD platform_driver_unregister(&at91_pinctrl_driver); 16936732ae5cSJean-Christophe PLAGNIOL-VILLARD } 16946732ae5cSJean-Christophe PLAGNIOL-VILLARD 16956732ae5cSJean-Christophe PLAGNIOL-VILLARD module_exit(at91_pinctrl_exit); 16966732ae5cSJean-Christophe PLAGNIOL-VILLARD MODULE_AUTHOR("Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>"); 16976732ae5cSJean-Christophe PLAGNIOL-VILLARD MODULE_DESCRIPTION("Atmel AT91 pinctrl driver"); 16986732ae5cSJean-Christophe PLAGNIOL-VILLARD MODULE_LICENSE("GPL v2"); 1699