1*28b665f6SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 26732ae5cSJean-Christophe PLAGNIOL-VILLARD /* 36732ae5cSJean-Christophe PLAGNIOL-VILLARD * at91 pinctrl driver based on at91 pinmux core 46732ae5cSJean-Christophe PLAGNIOL-VILLARD * 56732ae5cSJean-Christophe PLAGNIOL-VILLARD * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 66732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 76732ae5cSJean-Christophe PLAGNIOL-VILLARD 86732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/clk.h> 96732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/err.h> 106732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/init.h> 116732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/of.h> 126732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/of_device.h> 136732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/of_address.h> 146732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/of_irq.h> 156732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/slab.h> 166732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/interrupt.h> 176732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/io.h> 181c5fb66aSLinus Walleij #include <linux/gpio/driver.h> 196732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/pinctrl/machine.h> 206732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/pinctrl/pinconf.h> 216732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/pinctrl/pinctrl.h> 226732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/pinctrl/pinmux.h> 236732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Since we request GPIOs from ourself */ 246732ae5cSJean-Christophe PLAGNIOL-VILLARD #include <linux/pinctrl/consumer.h> 256732ae5cSJean-Christophe PLAGNIOL-VILLARD 26c654b6bfSAlexandre Belloni #include "pinctrl-at91.h" 276732ae5cSJean-Christophe PLAGNIOL-VILLARD #include "core.h" 286732ae5cSJean-Christophe PLAGNIOL-VILLARD 2994daf85eSLinus Walleij #define MAX_GPIO_BANKS 5 306732ae5cSJean-Christophe PLAGNIOL-VILLARD #define MAX_NB_GPIO_PER_BANK 32 316732ae5cSJean-Christophe PLAGNIOL-VILLARD 326732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl_mux_ops; 336732ae5cSJean-Christophe PLAGNIOL-VILLARD 346732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip { 356732ae5cSJean-Christophe PLAGNIOL-VILLARD struct gpio_chip chip; 366732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_gpio_range range; 376732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *next; /* Bank sharing same clock */ 386732ae5cSJean-Christophe PLAGNIOL-VILLARD int pioc_hwirq; /* PIO bank interrupt identifier on AIC */ 396732ae5cSJean-Christophe PLAGNIOL-VILLARD int pioc_virq; /* PIO bank Linux virtual interrupt */ 406732ae5cSJean-Christophe PLAGNIOL-VILLARD int pioc_idx; /* PIO bank index */ 416732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *regbase; /* PIO bank virtual address */ 426732ae5cSJean-Christophe PLAGNIOL-VILLARD struct clk *clock; /* associated clock */ 436732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl_mux_ops *ops; /* ops */ 446732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 456732ae5cSJean-Christophe PLAGNIOL-VILLARD 466732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS]; 476732ae5cSJean-Christophe PLAGNIOL-VILLARD 486732ae5cSJean-Christophe PLAGNIOL-VILLARD static int gpio_banks; 496732ae5cSJean-Christophe PLAGNIOL-VILLARD 50525fae21SJean-Christophe PLAGNIOL-VILLARD #define PULL_UP (1 << 0) 516732ae5cSJean-Christophe PLAGNIOL-VILLARD #define MULTI_DRIVE (1 << 1) 527ebd7a3aSJean-Christophe PLAGNIOL-VILLARD #define DEGLITCH (1 << 2) 537ebd7a3aSJean-Christophe PLAGNIOL-VILLARD #define PULL_DOWN (1 << 3) 547ebd7a3aSJean-Christophe PLAGNIOL-VILLARD #define DIS_SCHMIT (1 << 4) 554334ac2dSMarek Roszko #define DRIVE_STRENGTH_SHIFT 5 564334ac2dSMarek Roszko #define DRIVE_STRENGTH_MASK 0x3 574334ac2dSMarek Roszko #define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT) 5896bb12deSBoris BREZILLON #define OUTPUT (1 << 7) 5996bb12deSBoris BREZILLON #define OUTPUT_VAL_SHIFT 8 6096bb12deSBoris BREZILLON #define OUTPUT_VAL (0x1 << OUTPUT_VAL_SHIFT) 6164e21addSClaudiu Beznea #define SLEWRATE_SHIFT 9 6264e21addSClaudiu Beznea #define SLEWRATE_MASK 0x1 6364e21addSClaudiu Beznea #define SLEWRATE (SLEWRATE_MASK << SLEWRATE_SHIFT) 647ebd7a3aSJean-Christophe PLAGNIOL-VILLARD #define DEBOUNCE (1 << 16) 657ebd7a3aSJean-Christophe PLAGNIOL-VILLARD #define DEBOUNCE_VAL_SHIFT 17 667ebd7a3aSJean-Christophe PLAGNIOL-VILLARD #define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT) 676732ae5cSJean-Christophe PLAGNIOL-VILLARD 686732ae5cSJean-Christophe PLAGNIOL-VILLARD /** 694334ac2dSMarek Roszko * These defines will translated the dt binding settings to our internal 704334ac2dSMarek Roszko * settings. They are not necessarily the same value as the register setting. 714334ac2dSMarek Roszko * The actual drive strength current of low, medium and high must be looked up 724334ac2dSMarek Roszko * from the corresponding device datasheet. This value is different for pins 734334ac2dSMarek Roszko * that are even in the same banks. It is also dependent on VCC. 744334ac2dSMarek Roszko * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive 754334ac2dSMarek Roszko * strength when there is no dt config for it. 764334ac2dSMarek Roszko */ 77b67328e1SClaudiu Beznea enum drive_strength_bit { 78b67328e1SClaudiu Beznea DRIVE_STRENGTH_BIT_DEF, 79b67328e1SClaudiu Beznea DRIVE_STRENGTH_BIT_LOW, 80b67328e1SClaudiu Beznea DRIVE_STRENGTH_BIT_MED, 81b67328e1SClaudiu Beznea DRIVE_STRENGTH_BIT_HI, 82b67328e1SClaudiu Beznea }; 83b67328e1SClaudiu Beznea 84b67328e1SClaudiu Beznea #define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \ 85b67328e1SClaudiu Beznea DRIVE_STRENGTH_SHIFT) 864334ac2dSMarek Roszko 8764e21addSClaudiu Beznea enum slewrate_bit { 8864e21addSClaudiu Beznea SLEWRATE_BIT_DIS, 8964e21addSClaudiu Beznea SLEWRATE_BIT_ENA, 9064e21addSClaudiu Beznea }; 9164e21addSClaudiu Beznea 9264e21addSClaudiu Beznea #define SLEWRATE_BIT_MSK(name) (SLEWRATE_BIT_##name << SLEWRATE_SHIFT) 9364e21addSClaudiu Beznea 944334ac2dSMarek Roszko /** 956732ae5cSJean-Christophe PLAGNIOL-VILLARD * struct at91_pmx_func - describes AT91 pinmux functions 966732ae5cSJean-Christophe PLAGNIOL-VILLARD * @name: the name of this specific function 976732ae5cSJean-Christophe PLAGNIOL-VILLARD * @groups: corresponding pin groups 986732ae5cSJean-Christophe PLAGNIOL-VILLARD * @ngroups: the number of groups 996732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 1006732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pmx_func { 1016732ae5cSJean-Christophe PLAGNIOL-VILLARD const char *name; 1026732ae5cSJean-Christophe PLAGNIOL-VILLARD const char **groups; 1036732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned ngroups; 1046732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 1056732ae5cSJean-Christophe PLAGNIOL-VILLARD 1066732ae5cSJean-Christophe PLAGNIOL-VILLARD enum at91_mux { 1076732ae5cSJean-Christophe PLAGNIOL-VILLARD AT91_MUX_GPIO = 0, 1086732ae5cSJean-Christophe PLAGNIOL-VILLARD AT91_MUX_PERIPH_A = 1, 1096732ae5cSJean-Christophe PLAGNIOL-VILLARD AT91_MUX_PERIPH_B = 2, 1106732ae5cSJean-Christophe PLAGNIOL-VILLARD AT91_MUX_PERIPH_C = 3, 1116732ae5cSJean-Christophe PLAGNIOL-VILLARD AT91_MUX_PERIPH_D = 4, 1126732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 1136732ae5cSJean-Christophe PLAGNIOL-VILLARD 1146732ae5cSJean-Christophe PLAGNIOL-VILLARD /** 1156732ae5cSJean-Christophe PLAGNIOL-VILLARD * struct at91_pmx_pin - describes an At91 pin mux 1166732ae5cSJean-Christophe PLAGNIOL-VILLARD * @bank: the bank of the pin 1176732ae5cSJean-Christophe PLAGNIOL-VILLARD * @pin: the pin number in the @bank 1186732ae5cSJean-Christophe PLAGNIOL-VILLARD * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function. 1196732ae5cSJean-Christophe PLAGNIOL-VILLARD * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc... 1206732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 1216732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pmx_pin { 1226732ae5cSJean-Christophe PLAGNIOL-VILLARD uint32_t bank; 1236732ae5cSJean-Christophe PLAGNIOL-VILLARD uint32_t pin; 1246732ae5cSJean-Christophe PLAGNIOL-VILLARD enum at91_mux mux; 1256732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned long conf; 1266732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 1276732ae5cSJean-Christophe PLAGNIOL-VILLARD 1286732ae5cSJean-Christophe PLAGNIOL-VILLARD /** 1296732ae5cSJean-Christophe PLAGNIOL-VILLARD * struct at91_pin_group - describes an At91 pin group 1306732ae5cSJean-Christophe PLAGNIOL-VILLARD * @name: the name of this specific pin group 1316732ae5cSJean-Christophe PLAGNIOL-VILLARD * @pins_conf: the mux mode for each pin in this group. The size of this 1326732ae5cSJean-Christophe PLAGNIOL-VILLARD * array is the same as pins. 1336732ae5cSJean-Christophe PLAGNIOL-VILLARD * @pins: an array of discrete physical pins used in this group, taken 1346732ae5cSJean-Christophe PLAGNIOL-VILLARD * from the driver-local pin enumeration space 1356732ae5cSJean-Christophe PLAGNIOL-VILLARD * @npins: the number of pins in this group array, i.e. the number of 1366732ae5cSJean-Christophe PLAGNIOL-VILLARD * elements in .pins so we can iterate over that array 1376732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 1386732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pin_group { 1396732ae5cSJean-Christophe PLAGNIOL-VILLARD const char *name; 1406732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pmx_pin *pins_conf; 1416732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned int *pins; 1426732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned npins; 1436732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 1446732ae5cSJean-Christophe PLAGNIOL-VILLARD 1456732ae5cSJean-Christophe PLAGNIOL-VILLARD /** 146c2eb9e7fSAlexandre Belloni * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group 1476732ae5cSJean-Christophe PLAGNIOL-VILLARD * on new IP with support for periph C and D the way to mux in 1486732ae5cSJean-Christophe PLAGNIOL-VILLARD * periph A and B has changed 1496732ae5cSJean-Christophe PLAGNIOL-VILLARD * So provide the right call back 1506732ae5cSJean-Christophe PLAGNIOL-VILLARD * if not present means the IP does not support it 1516732ae5cSJean-Christophe PLAGNIOL-VILLARD * @get_periph: return the periph mode configured 1526732ae5cSJean-Christophe PLAGNIOL-VILLARD * @mux_A_periph: mux as periph A 1536732ae5cSJean-Christophe PLAGNIOL-VILLARD * @mux_B_periph: mux as periph B 1546732ae5cSJean-Christophe PLAGNIOL-VILLARD * @mux_C_periph: mux as periph C 1556732ae5cSJean-Christophe PLAGNIOL-VILLARD * @mux_D_periph: mux as periph D 1567ebd7a3aSJean-Christophe PLAGNIOL-VILLARD * @get_deglitch: get deglitch status 1577ebd7a3aSJean-Christophe PLAGNIOL-VILLARD * @set_deglitch: enable/disable deglitch 1587ebd7a3aSJean-Christophe PLAGNIOL-VILLARD * @get_debounce: get debounce status 1597ebd7a3aSJean-Christophe PLAGNIOL-VILLARD * @set_debounce: enable/disable debounce 1607ebd7a3aSJean-Christophe PLAGNIOL-VILLARD * @get_pulldown: get pulldown status 1617ebd7a3aSJean-Christophe PLAGNIOL-VILLARD * @set_pulldown: enable/disable pulldown 1627ebd7a3aSJean-Christophe PLAGNIOL-VILLARD * @get_schmitt_trig: get schmitt trigger status 1637ebd7a3aSJean-Christophe PLAGNIOL-VILLARD * @disable_schmitt_trig: disable schmitt trigger 1646732ae5cSJean-Christophe PLAGNIOL-VILLARD * @irq_type: return irq type 1656732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 1666732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl_mux_ops { 1676732ae5cSJean-Christophe PLAGNIOL-VILLARD enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask); 1686732ae5cSJean-Christophe PLAGNIOL-VILLARD void (*mux_A_periph)(void __iomem *pio, unsigned mask); 1696732ae5cSJean-Christophe PLAGNIOL-VILLARD void (*mux_B_periph)(void __iomem *pio, unsigned mask); 1706732ae5cSJean-Christophe PLAGNIOL-VILLARD void (*mux_C_periph)(void __iomem *pio, unsigned mask); 1716732ae5cSJean-Christophe PLAGNIOL-VILLARD void (*mux_D_periph)(void __iomem *pio, unsigned mask); 1727ebd7a3aSJean-Christophe PLAGNIOL-VILLARD bool (*get_deglitch)(void __iomem *pio, unsigned pin); 17377966ad7SBoris BREZILLON void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on); 1747ebd7a3aSJean-Christophe PLAGNIOL-VILLARD bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div); 17577966ad7SBoris BREZILLON void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div); 1767ebd7a3aSJean-Christophe PLAGNIOL-VILLARD bool (*get_pulldown)(void __iomem *pio, unsigned pin); 17777966ad7SBoris BREZILLON void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on); 1787ebd7a3aSJean-Christophe PLAGNIOL-VILLARD bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin); 1797ebd7a3aSJean-Christophe PLAGNIOL-VILLARD void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask); 1804334ac2dSMarek Roszko unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin); 1814334ac2dSMarek Roszko void (*set_drivestrength)(void __iomem *pio, unsigned pin, 1824334ac2dSMarek Roszko u32 strength); 18364e21addSClaudiu Beznea unsigned (*get_slewrate)(void __iomem *pio, unsigned pin); 18464e21addSClaudiu Beznea void (*set_slewrate)(void __iomem *pio, unsigned pin, u32 slewrate); 1856732ae5cSJean-Christophe PLAGNIOL-VILLARD /* irq */ 1866732ae5cSJean-Christophe PLAGNIOL-VILLARD int (*irq_type)(struct irq_data *d, unsigned type); 1876732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 1886732ae5cSJean-Christophe PLAGNIOL-VILLARD 1896732ae5cSJean-Christophe PLAGNIOL-VILLARD static int gpio_irq_type(struct irq_data *d, unsigned type); 1906732ae5cSJean-Christophe PLAGNIOL-VILLARD static int alt_gpio_irq_type(struct irq_data *d, unsigned type); 1916732ae5cSJean-Christophe PLAGNIOL-VILLARD 1926732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl { 1936732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device *dev; 1946732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_dev *pctl; 1956732ae5cSJean-Christophe PLAGNIOL-VILLARD 196a0b957f3SJean-Christophe PLAGNIOL-VILLARD int nactive_banks; 1976732ae5cSJean-Christophe PLAGNIOL-VILLARD 1986732ae5cSJean-Christophe PLAGNIOL-VILLARD uint32_t *mux_mask; 1996732ae5cSJean-Christophe PLAGNIOL-VILLARD int nmux; 2006732ae5cSJean-Christophe PLAGNIOL-VILLARD 2016732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pmx_func *functions; 2026732ae5cSJean-Christophe PLAGNIOL-VILLARD int nfunctions; 2036732ae5cSJean-Christophe PLAGNIOL-VILLARD 2046732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pin_group *groups; 2056732ae5cSJean-Christophe PLAGNIOL-VILLARD int ngroups; 2066732ae5cSJean-Christophe PLAGNIOL-VILLARD 2076732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl_mux_ops *ops; 2086732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 2096732ae5cSJean-Christophe PLAGNIOL-VILLARD 21056411f3cSArnd Bergmann static inline const struct at91_pin_group *at91_pinctrl_find_group_by_name( 2116732ae5cSJean-Christophe PLAGNIOL-VILLARD const struct at91_pinctrl *info, 2126732ae5cSJean-Christophe PLAGNIOL-VILLARD const char *name) 2136732ae5cSJean-Christophe PLAGNIOL-VILLARD { 2146732ae5cSJean-Christophe PLAGNIOL-VILLARD const struct at91_pin_group *grp = NULL; 2156732ae5cSJean-Christophe PLAGNIOL-VILLARD int i; 2166732ae5cSJean-Christophe PLAGNIOL-VILLARD 2176732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < info->ngroups; i++) { 2186732ae5cSJean-Christophe PLAGNIOL-VILLARD if (strcmp(info->groups[i].name, name)) 2196732ae5cSJean-Christophe PLAGNIOL-VILLARD continue; 2206732ae5cSJean-Christophe PLAGNIOL-VILLARD 2216732ae5cSJean-Christophe PLAGNIOL-VILLARD grp = &info->groups[i]; 2226732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]); 2236732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 2246732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2256732ae5cSJean-Christophe PLAGNIOL-VILLARD 2266732ae5cSJean-Christophe PLAGNIOL-VILLARD return grp; 2276732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2286732ae5cSJean-Christophe PLAGNIOL-VILLARD 2296732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_get_groups_count(struct pinctrl_dev *pctldev) 2306732ae5cSJean-Christophe PLAGNIOL-VILLARD { 2316732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2326732ae5cSJean-Christophe PLAGNIOL-VILLARD 2336732ae5cSJean-Christophe PLAGNIOL-VILLARD return info->ngroups; 2346732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2356732ae5cSJean-Christophe PLAGNIOL-VILLARD 2366732ae5cSJean-Christophe PLAGNIOL-VILLARD static const char *at91_get_group_name(struct pinctrl_dev *pctldev, 2376732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned selector) 2386732ae5cSJean-Christophe PLAGNIOL-VILLARD { 2396732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2406732ae5cSJean-Christophe PLAGNIOL-VILLARD 2416732ae5cSJean-Christophe PLAGNIOL-VILLARD return info->groups[selector].name; 2426732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2436732ae5cSJean-Christophe PLAGNIOL-VILLARD 2446732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, 2456732ae5cSJean-Christophe PLAGNIOL-VILLARD const unsigned **pins, 2466732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned *npins) 2476732ae5cSJean-Christophe PLAGNIOL-VILLARD { 2486732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2496732ae5cSJean-Christophe PLAGNIOL-VILLARD 2506732ae5cSJean-Christophe PLAGNIOL-VILLARD if (selector >= info->ngroups) 2516732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 2526732ae5cSJean-Christophe PLAGNIOL-VILLARD 2536732ae5cSJean-Christophe PLAGNIOL-VILLARD *pins = info->groups[selector].pins; 2546732ae5cSJean-Christophe PLAGNIOL-VILLARD *npins = info->groups[selector].npins; 2556732ae5cSJean-Christophe PLAGNIOL-VILLARD 2566732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 2576732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2586732ae5cSJean-Christophe PLAGNIOL-VILLARD 2596732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 2606732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned offset) 2616732ae5cSJean-Christophe PLAGNIOL-VILLARD { 2626732ae5cSJean-Christophe PLAGNIOL-VILLARD seq_printf(s, "%s", dev_name(pctldev->dev)); 2636732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2646732ae5cSJean-Christophe PLAGNIOL-VILLARD 2656732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_dt_node_to_map(struct pinctrl_dev *pctldev, 2666732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *np, 2676732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_map **map, unsigned *num_maps) 2686732ae5cSJean-Christophe PLAGNIOL-VILLARD { 2696732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2706732ae5cSJean-Christophe PLAGNIOL-VILLARD const struct at91_pin_group *grp; 2716732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_map *new_map; 2726732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *parent; 2736732ae5cSJean-Christophe PLAGNIOL-VILLARD int map_num = 1; 2746732ae5cSJean-Christophe PLAGNIOL-VILLARD int i; 2756732ae5cSJean-Christophe PLAGNIOL-VILLARD 2766732ae5cSJean-Christophe PLAGNIOL-VILLARD /* 27761e310a1SAlexandre Belloni * first find the group of this node and check if we need to create 2786732ae5cSJean-Christophe PLAGNIOL-VILLARD * config maps for pins 2796732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 2806732ae5cSJean-Christophe PLAGNIOL-VILLARD grp = at91_pinctrl_find_group_by_name(info, np->name); 2816732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!grp) { 28294f4e54cSRob Herring dev_err(info->dev, "unable to find group for node %pOFn\n", 28394f4e54cSRob Herring np); 2846732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 2856732ae5cSJean-Christophe PLAGNIOL-VILLARD } 2866732ae5cSJean-Christophe PLAGNIOL-VILLARD 2876732ae5cSJean-Christophe PLAGNIOL-VILLARD map_num += grp->npins; 288a86854d0SKees Cook new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map), 289a86854d0SKees Cook GFP_KERNEL); 2906732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!new_map) 2916732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENOMEM; 2926732ae5cSJean-Christophe PLAGNIOL-VILLARD 2936732ae5cSJean-Christophe PLAGNIOL-VILLARD *map = new_map; 2946732ae5cSJean-Christophe PLAGNIOL-VILLARD *num_maps = map_num; 2956732ae5cSJean-Christophe PLAGNIOL-VILLARD 2966732ae5cSJean-Christophe PLAGNIOL-VILLARD /* create mux map */ 2976732ae5cSJean-Christophe PLAGNIOL-VILLARD parent = of_get_parent(np); 2986732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!parent) { 299c62b2b34SJulia Lawall devm_kfree(pctldev->dev, new_map); 3006732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 3016732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3026732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 3036732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map[0].data.mux.function = parent->name; 3046732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map[0].data.mux.group = np->name; 3056732ae5cSJean-Christophe PLAGNIOL-VILLARD of_node_put(parent); 3066732ae5cSJean-Christophe PLAGNIOL-VILLARD 3076732ae5cSJean-Christophe PLAGNIOL-VILLARD /* create config map */ 3086732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map++; 3096732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < grp->npins; i++) { 3106732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 3116732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map[i].data.configs.group_or_pin = 3126732ae5cSJean-Christophe PLAGNIOL-VILLARD pin_get_name(pctldev, grp->pins[i]); 3136732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map[i].data.configs.configs = &grp->pins_conf[i].conf; 3146732ae5cSJean-Christophe PLAGNIOL-VILLARD new_map[i].data.configs.num_configs = 1; 3156732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3166732ae5cSJean-Christophe PLAGNIOL-VILLARD 3176732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 3186732ae5cSJean-Christophe PLAGNIOL-VILLARD (*map)->data.mux.function, (*map)->data.mux.group, map_num); 3196732ae5cSJean-Christophe PLAGNIOL-VILLARD 3206732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 3216732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3226732ae5cSJean-Christophe PLAGNIOL-VILLARD 3236732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_dt_free_map(struct pinctrl_dev *pctldev, 3246732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_map *map, unsigned num_maps) 3256732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3266732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3276732ae5cSJean-Christophe PLAGNIOL-VILLARD 328022ab148SLaurent Pinchart static const struct pinctrl_ops at91_pctrl_ops = { 3296732ae5cSJean-Christophe PLAGNIOL-VILLARD .get_groups_count = at91_get_groups_count, 3306732ae5cSJean-Christophe PLAGNIOL-VILLARD .get_group_name = at91_get_group_name, 3316732ae5cSJean-Christophe PLAGNIOL-VILLARD .get_group_pins = at91_get_group_pins, 3326732ae5cSJean-Christophe PLAGNIOL-VILLARD .pin_dbg_show = at91_pin_dbg_show, 3336732ae5cSJean-Christophe PLAGNIOL-VILLARD .dt_node_to_map = at91_dt_node_to_map, 3346732ae5cSJean-Christophe PLAGNIOL-VILLARD .dt_free_map = at91_dt_free_map, 3356732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 3366732ae5cSJean-Christophe PLAGNIOL-VILLARD 3376732ae5cSJean-Christophe PLAGNIOL-VILLARD static void __iomem *pin_to_controller(struct at91_pinctrl *info, 3386732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned int bank) 3396732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3401ab36387SDavid Dueck if (!gpio_chips[bank]) 3411ab36387SDavid Dueck return NULL; 3421ab36387SDavid Dueck 3436732ae5cSJean-Christophe PLAGNIOL-VILLARD return gpio_chips[bank]->regbase; 3446732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3456732ae5cSJean-Christophe PLAGNIOL-VILLARD 3466732ae5cSJean-Christophe PLAGNIOL-VILLARD static inline int pin_to_bank(unsigned pin) 3476732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3486732ae5cSJean-Christophe PLAGNIOL-VILLARD return pin /= MAX_NB_GPIO_PER_BANK; 3496732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3506732ae5cSJean-Christophe PLAGNIOL-VILLARD 3516732ae5cSJean-Christophe PLAGNIOL-VILLARD static unsigned pin_to_mask(unsigned int pin) 3526732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3536732ae5cSJean-Christophe PLAGNIOL-VILLARD return 1 << pin; 3546732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3556732ae5cSJean-Christophe PLAGNIOL-VILLARD 3564334ac2dSMarek Roszko static unsigned two_bit_pin_value_shift_amount(unsigned int pin) 3574334ac2dSMarek Roszko { 3584334ac2dSMarek Roszko /* return the shift value for a pin for "two bit" per pin registers, 3594334ac2dSMarek Roszko * i.e. drive strength */ 3604334ac2dSMarek Roszko return 2*((pin >= MAX_NB_GPIO_PER_BANK/2) 3614334ac2dSMarek Roszko ? pin - MAX_NB_GPIO_PER_BANK/2 : pin); 3624334ac2dSMarek Roszko } 3634334ac2dSMarek Roszko 3644334ac2dSMarek Roszko static unsigned sama5d3_get_drive_register(unsigned int pin) 3654334ac2dSMarek Roszko { 3664334ac2dSMarek Roszko /* drive strength is split between two registers 3674334ac2dSMarek Roszko * with two bits per pin */ 3684334ac2dSMarek Roszko return (pin >= MAX_NB_GPIO_PER_BANK/2) 3694334ac2dSMarek Roszko ? SAMA5D3_PIO_DRIVER2 : SAMA5D3_PIO_DRIVER1; 3704334ac2dSMarek Roszko } 3714334ac2dSMarek Roszko 3724334ac2dSMarek Roszko static unsigned at91sam9x5_get_drive_register(unsigned int pin) 3734334ac2dSMarek Roszko { 3744334ac2dSMarek Roszko /* drive strength is split between two registers 3754334ac2dSMarek Roszko * with two bits per pin */ 3764334ac2dSMarek Roszko return (pin >= MAX_NB_GPIO_PER_BANK/2) 3774334ac2dSMarek Roszko ? AT91SAM9X5_PIO_DRIVER2 : AT91SAM9X5_PIO_DRIVER1; 3784334ac2dSMarek Roszko } 3794334ac2dSMarek Roszko 3806732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask) 3816732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3826732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_IDR); 3836732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3846732ae5cSJean-Christophe PLAGNIOL-VILLARD 3856732ae5cSJean-Christophe PLAGNIOL-VILLARD static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin) 3866732ae5cSJean-Christophe PLAGNIOL-VILLARD { 38705d3534aSBoris BREZILLON return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1); 3886732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3896732ae5cSJean-Christophe PLAGNIOL-VILLARD 3906732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on) 3916732ae5cSJean-Christophe PLAGNIOL-VILLARD { 3923d784273SWenyou Yang if (on) 3933d784273SWenyou Yang writel_relaxed(mask, pio + PIO_PPDDR); 3943d784273SWenyou Yang 3956732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR)); 3966732ae5cSJean-Christophe PLAGNIOL-VILLARD } 3976732ae5cSJean-Christophe PLAGNIOL-VILLARD 39896bb12deSBoris BREZILLON static bool at91_mux_get_output(void __iomem *pio, unsigned int pin, bool *val) 39996bb12deSBoris BREZILLON { 40096bb12deSBoris BREZILLON *val = (readl_relaxed(pio + PIO_ODSR) >> pin) & 0x1; 40196bb12deSBoris BREZILLON return (readl_relaxed(pio + PIO_OSR) >> pin) & 0x1; 40296bb12deSBoris BREZILLON } 40396bb12deSBoris BREZILLON 40496bb12deSBoris BREZILLON static void at91_mux_set_output(void __iomem *pio, unsigned int mask, 40596bb12deSBoris BREZILLON bool is_on, bool val) 40696bb12deSBoris BREZILLON { 40796bb12deSBoris BREZILLON writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); 40896bb12deSBoris BREZILLON writel_relaxed(mask, pio + (is_on ? PIO_OER : PIO_ODR)); 40996bb12deSBoris BREZILLON } 41096bb12deSBoris BREZILLON 4116732ae5cSJean-Christophe PLAGNIOL-VILLARD static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin) 4126732ae5cSJean-Christophe PLAGNIOL-VILLARD { 4136732ae5cSJean-Christophe PLAGNIOL-VILLARD return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1; 4146732ae5cSJean-Christophe PLAGNIOL-VILLARD } 4156732ae5cSJean-Christophe PLAGNIOL-VILLARD 4166732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on) 4176732ae5cSJean-Christophe PLAGNIOL-VILLARD { 4186732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR)); 4196732ae5cSJean-Christophe PLAGNIOL-VILLARD } 4206732ae5cSJean-Christophe PLAGNIOL-VILLARD 4216732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask) 4226732ae5cSJean-Christophe PLAGNIOL-VILLARD { 4236732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_ASR); 4246732ae5cSJean-Christophe PLAGNIOL-VILLARD } 4256732ae5cSJean-Christophe PLAGNIOL-VILLARD 4266732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask) 4276732ae5cSJean-Christophe PLAGNIOL-VILLARD { 4286732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_BSR); 4296732ae5cSJean-Christophe PLAGNIOL-VILLARD } 4306732ae5cSJean-Christophe PLAGNIOL-VILLARD 4316732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask) 4326732ae5cSJean-Christophe PLAGNIOL-VILLARD { 4336732ae5cSJean-Christophe PLAGNIOL-VILLARD 4346732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, 4356732ae5cSJean-Christophe PLAGNIOL-VILLARD pio + PIO_ABCDSR1); 4366732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, 4376732ae5cSJean-Christophe PLAGNIOL-VILLARD pio + PIO_ABCDSR2); 4386732ae5cSJean-Christophe PLAGNIOL-VILLARD } 4396732ae5cSJean-Christophe PLAGNIOL-VILLARD 4406732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask) 4416732ae5cSJean-Christophe PLAGNIOL-VILLARD { 4426732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, 4436732ae5cSJean-Christophe PLAGNIOL-VILLARD pio + PIO_ABCDSR1); 4446732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, 4456732ae5cSJean-Christophe PLAGNIOL-VILLARD pio + PIO_ABCDSR2); 4466732ae5cSJean-Christophe PLAGNIOL-VILLARD } 4476732ae5cSJean-Christophe PLAGNIOL-VILLARD 4486732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask) 4496732ae5cSJean-Christophe PLAGNIOL-VILLARD { 4506732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1); 4516732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); 4526732ae5cSJean-Christophe PLAGNIOL-VILLARD } 4536732ae5cSJean-Christophe PLAGNIOL-VILLARD 4546732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask) 4556732ae5cSJean-Christophe PLAGNIOL-VILLARD { 4566732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1); 4576732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); 4586732ae5cSJean-Christophe PLAGNIOL-VILLARD } 4596732ae5cSJean-Christophe PLAGNIOL-VILLARD 4606732ae5cSJean-Christophe PLAGNIOL-VILLARD static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask) 4616732ae5cSJean-Christophe PLAGNIOL-VILLARD { 4626732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned select; 4636732ae5cSJean-Christophe PLAGNIOL-VILLARD 4646732ae5cSJean-Christophe PLAGNIOL-VILLARD if (readl_relaxed(pio + PIO_PSR) & mask) 4656732ae5cSJean-Christophe PLAGNIOL-VILLARD return AT91_MUX_GPIO; 4666732ae5cSJean-Christophe PLAGNIOL-VILLARD 4676732ae5cSJean-Christophe PLAGNIOL-VILLARD select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask); 4686732ae5cSJean-Christophe PLAGNIOL-VILLARD select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1); 4696732ae5cSJean-Christophe PLAGNIOL-VILLARD 4706732ae5cSJean-Christophe PLAGNIOL-VILLARD return select + 1; 4716732ae5cSJean-Christophe PLAGNIOL-VILLARD } 4726732ae5cSJean-Christophe PLAGNIOL-VILLARD 4736732ae5cSJean-Christophe PLAGNIOL-VILLARD static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask) 4746732ae5cSJean-Christophe PLAGNIOL-VILLARD { 4756732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned select; 4766732ae5cSJean-Christophe PLAGNIOL-VILLARD 4776732ae5cSJean-Christophe PLAGNIOL-VILLARD if (readl_relaxed(pio + PIO_PSR) & mask) 4786732ae5cSJean-Christophe PLAGNIOL-VILLARD return AT91_MUX_GPIO; 4796732ae5cSJean-Christophe PLAGNIOL-VILLARD 4806732ae5cSJean-Christophe PLAGNIOL-VILLARD select = readl_relaxed(pio + PIO_ABSR) & mask; 4816732ae5cSJean-Christophe PLAGNIOL-VILLARD 4826732ae5cSJean-Christophe PLAGNIOL-VILLARD return select + 1; 4836732ae5cSJean-Christophe PLAGNIOL-VILLARD } 4846732ae5cSJean-Christophe PLAGNIOL-VILLARD 4857ebd7a3aSJean-Christophe PLAGNIOL-VILLARD static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin) 4867ebd7a3aSJean-Christophe PLAGNIOL-VILLARD { 487d480239bSBen Dooks return (readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1; 4887ebd7a3aSJean-Christophe PLAGNIOL-VILLARD } 4897ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 4907ebd7a3aSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) 4917ebd7a3aSJean-Christophe PLAGNIOL-VILLARD { 492d480239bSBen Dooks writel_relaxed(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); 4937ebd7a3aSJean-Christophe PLAGNIOL-VILLARD } 4947ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 495c8dba02eSBoris BREZILLON static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin) 496c8dba02eSBoris BREZILLON { 497d480239bSBen Dooks if ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) 498d480239bSBen Dooks return !((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1); 499c8dba02eSBoris BREZILLON 500c8dba02eSBoris BREZILLON return false; 501c8dba02eSBoris BREZILLON } 502c8dba02eSBoris BREZILLON 5037ebd7a3aSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) 5047ebd7a3aSJean-Christophe PLAGNIOL-VILLARD { 5057ebd7a3aSJean-Christophe PLAGNIOL-VILLARD if (is_on) 506d480239bSBen Dooks writel_relaxed(mask, pio + PIO_IFSCDR); 5077ebd7a3aSJean-Christophe PLAGNIOL-VILLARD at91_mux_set_deglitch(pio, mask, is_on); 5087ebd7a3aSJean-Christophe PLAGNIOL-VILLARD } 5097ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 5107ebd7a3aSJean-Christophe PLAGNIOL-VILLARD static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div) 5117ebd7a3aSJean-Christophe PLAGNIOL-VILLARD { 512d480239bSBen Dooks *div = readl_relaxed(pio + PIO_SCDR); 5137ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 514d480239bSBen Dooks return ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) && 515d480239bSBen Dooks ((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1); 5167ebd7a3aSJean-Christophe PLAGNIOL-VILLARD } 5177ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 5187ebd7a3aSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask, 5197ebd7a3aSJean-Christophe PLAGNIOL-VILLARD bool is_on, u32 div) 5207ebd7a3aSJean-Christophe PLAGNIOL-VILLARD { 5217ebd7a3aSJean-Christophe PLAGNIOL-VILLARD if (is_on) { 522d480239bSBen Dooks writel_relaxed(mask, pio + PIO_IFSCER); 523d480239bSBen Dooks writel_relaxed(div & PIO_SCDR_DIV, pio + PIO_SCDR); 524d480239bSBen Dooks writel_relaxed(mask, pio + PIO_IFER); 525c8dba02eSBoris BREZILLON } else 526d480239bSBen Dooks writel_relaxed(mask, pio + PIO_IFSCDR); 5277ebd7a3aSJean-Christophe PLAGNIOL-VILLARD } 5287ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 5297ebd7a3aSJean-Christophe PLAGNIOL-VILLARD static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin) 5307ebd7a3aSJean-Christophe PLAGNIOL-VILLARD { 531d480239bSBen Dooks return !((readl_relaxed(pio + PIO_PPDSR) >> pin) & 0x1); 5327ebd7a3aSJean-Christophe PLAGNIOL-VILLARD } 5337ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 5347ebd7a3aSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on) 5357ebd7a3aSJean-Christophe PLAGNIOL-VILLARD { 5363d784273SWenyou Yang if (is_on) 537d480239bSBen Dooks writel_relaxed(mask, pio + PIO_PUDR); 5383d784273SWenyou Yang 539d480239bSBen Dooks writel_relaxed(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR)); 5407ebd7a3aSJean-Christophe PLAGNIOL-VILLARD } 5417ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 5427ebd7a3aSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask) 5437ebd7a3aSJean-Christophe PLAGNIOL-VILLARD { 544d480239bSBen Dooks writel_relaxed(readl_relaxed(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT); 5457ebd7a3aSJean-Christophe PLAGNIOL-VILLARD } 5467ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 5477ebd7a3aSJean-Christophe PLAGNIOL-VILLARD static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin) 5487ebd7a3aSJean-Christophe PLAGNIOL-VILLARD { 549d480239bSBen Dooks return (readl_relaxed(pio + PIO_SCHMITT) >> pin) & 0x1; 5507ebd7a3aSJean-Christophe PLAGNIOL-VILLARD } 5517ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 5524334ac2dSMarek Roszko static inline u32 read_drive_strength(void __iomem *reg, unsigned pin) 5534334ac2dSMarek Roszko { 554d480239bSBen Dooks unsigned tmp = readl_relaxed(reg); 5554334ac2dSMarek Roszko 5564334ac2dSMarek Roszko tmp = tmp >> two_bit_pin_value_shift_amount(pin); 5574334ac2dSMarek Roszko 5584334ac2dSMarek Roszko return tmp & DRIVE_STRENGTH_MASK; 5594334ac2dSMarek Roszko } 5604334ac2dSMarek Roszko 5614334ac2dSMarek Roszko static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio, 5624334ac2dSMarek Roszko unsigned pin) 5634334ac2dSMarek Roszko { 5644334ac2dSMarek Roszko unsigned tmp = read_drive_strength(pio + 5654334ac2dSMarek Roszko sama5d3_get_drive_register(pin), pin); 5664334ac2dSMarek Roszko 5674334ac2dSMarek Roszko /* SAMA5 strength is 1:1 with our defines, 5684334ac2dSMarek Roszko * except 0 is equivalent to low per datasheet */ 5694334ac2dSMarek Roszko if (!tmp) 570b67328e1SClaudiu Beznea tmp = DRIVE_STRENGTH_BIT_MSK(LOW); 5714334ac2dSMarek Roszko 5724334ac2dSMarek Roszko return tmp; 5734334ac2dSMarek Roszko } 5744334ac2dSMarek Roszko 5754334ac2dSMarek Roszko static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio, 5764334ac2dSMarek Roszko unsigned pin) 5774334ac2dSMarek Roszko { 5784334ac2dSMarek Roszko unsigned tmp = read_drive_strength(pio + 5794334ac2dSMarek Roszko at91sam9x5_get_drive_register(pin), pin); 5804334ac2dSMarek Roszko 5814334ac2dSMarek Roszko /* strength is inverse in SAM9x5s hardware with the pinctrl defines 5824334ac2dSMarek Roszko * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */ 583b67328e1SClaudiu Beznea tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp; 5844334ac2dSMarek Roszko 5854334ac2dSMarek Roszko return tmp; 5864334ac2dSMarek Roszko } 5874334ac2dSMarek Roszko 58842ef7557SClaudiu Beznea static unsigned at91_mux_sam9x60_get_drivestrength(void __iomem *pio, 58942ef7557SClaudiu Beznea unsigned pin) 59042ef7557SClaudiu Beznea { 59142ef7557SClaudiu Beznea unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1); 59242ef7557SClaudiu Beznea 59342ef7557SClaudiu Beznea if (tmp & BIT(pin)) 59442ef7557SClaudiu Beznea return DRIVE_STRENGTH_BIT_HI; 59542ef7557SClaudiu Beznea 59642ef7557SClaudiu Beznea return DRIVE_STRENGTH_BIT_LOW; 59742ef7557SClaudiu Beznea } 59842ef7557SClaudiu Beznea 59964e21addSClaudiu Beznea static unsigned at91_mux_sam9x60_get_slewrate(void __iomem *pio, unsigned pin) 60064e21addSClaudiu Beznea { 60164e21addSClaudiu Beznea unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR); 60264e21addSClaudiu Beznea 60364e21addSClaudiu Beznea if ((tmp & BIT(pin))) 60464e21addSClaudiu Beznea return SLEWRATE_BIT_ENA; 60564e21addSClaudiu Beznea 60664e21addSClaudiu Beznea return SLEWRATE_BIT_DIS; 60764e21addSClaudiu Beznea } 60864e21addSClaudiu Beznea 6094334ac2dSMarek Roszko static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength) 6104334ac2dSMarek Roszko { 611d480239bSBen Dooks unsigned tmp = readl_relaxed(reg); 6124334ac2dSMarek Roszko unsigned shift = two_bit_pin_value_shift_amount(pin); 6134334ac2dSMarek Roszko 6144334ac2dSMarek Roszko tmp &= ~(DRIVE_STRENGTH_MASK << shift); 6154334ac2dSMarek Roszko tmp |= strength << shift; 6164334ac2dSMarek Roszko 617d480239bSBen Dooks writel_relaxed(tmp, reg); 6184334ac2dSMarek Roszko } 6194334ac2dSMarek Roszko 6204334ac2dSMarek Roszko static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin, 6214334ac2dSMarek Roszko u32 setting) 6224334ac2dSMarek Roszko { 6234334ac2dSMarek Roszko /* do nothing if setting is zero */ 6244334ac2dSMarek Roszko if (!setting) 6254334ac2dSMarek Roszko return; 6264334ac2dSMarek Roszko 6274334ac2dSMarek Roszko /* strength is 1 to 1 with setting for SAMA5 */ 6284334ac2dSMarek Roszko set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting); 6294334ac2dSMarek Roszko } 6304334ac2dSMarek Roszko 6314334ac2dSMarek Roszko static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin, 6324334ac2dSMarek Roszko u32 setting) 6334334ac2dSMarek Roszko { 6344334ac2dSMarek Roszko /* do nothing if setting is zero */ 6354334ac2dSMarek Roszko if (!setting) 6364334ac2dSMarek Roszko return; 6374334ac2dSMarek Roszko 6384334ac2dSMarek Roszko /* strength is inverse on SAM9x5s with our defines 6394334ac2dSMarek Roszko * 0 = hi, 1 = med, 2 = low, 3 = rsvd */ 640b67328e1SClaudiu Beznea setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting; 6414334ac2dSMarek Roszko 6424334ac2dSMarek Roszko set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin, 6434334ac2dSMarek Roszko setting); 6444334ac2dSMarek Roszko } 6454334ac2dSMarek Roszko 64642ef7557SClaudiu Beznea static void at91_mux_sam9x60_set_drivestrength(void __iomem *pio, unsigned pin, 64742ef7557SClaudiu Beznea u32 setting) 64842ef7557SClaudiu Beznea { 64942ef7557SClaudiu Beznea unsigned int tmp; 65042ef7557SClaudiu Beznea 65142ef7557SClaudiu Beznea if (setting <= DRIVE_STRENGTH_BIT_DEF || 65242ef7557SClaudiu Beznea setting == DRIVE_STRENGTH_BIT_MED || 65342ef7557SClaudiu Beznea setting > DRIVE_STRENGTH_BIT_HI) 65442ef7557SClaudiu Beznea return; 65542ef7557SClaudiu Beznea 65642ef7557SClaudiu Beznea tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1); 65742ef7557SClaudiu Beznea 65842ef7557SClaudiu Beznea /* Strength is 0: low, 1: hi */ 65942ef7557SClaudiu Beznea if (setting == DRIVE_STRENGTH_BIT_LOW) 66042ef7557SClaudiu Beznea tmp &= ~BIT(pin); 66142ef7557SClaudiu Beznea else 66242ef7557SClaudiu Beznea tmp |= BIT(pin); 66342ef7557SClaudiu Beznea 66442ef7557SClaudiu Beznea writel_relaxed(tmp, pio + SAM9X60_PIO_DRIVER1); 66542ef7557SClaudiu Beznea } 66642ef7557SClaudiu Beznea 66764e21addSClaudiu Beznea static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin, 66864e21addSClaudiu Beznea u32 setting) 66964e21addSClaudiu Beznea { 67064e21addSClaudiu Beznea unsigned int tmp; 67164e21addSClaudiu Beznea 67264e21addSClaudiu Beznea if (setting < SLEWRATE_BIT_DIS || setting > SLEWRATE_BIT_ENA) 67364e21addSClaudiu Beznea return; 67464e21addSClaudiu Beznea 67564e21addSClaudiu Beznea tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR); 67664e21addSClaudiu Beznea 67764e21addSClaudiu Beznea if (setting == SLEWRATE_BIT_DIS) 67864e21addSClaudiu Beznea tmp &= ~BIT(pin); 67964e21addSClaudiu Beznea else 68064e21addSClaudiu Beznea tmp |= BIT(pin); 68164e21addSClaudiu Beznea 68264e21addSClaudiu Beznea writel_relaxed(tmp, pio + SAM9X60_PIO_SLEWR); 68364e21addSClaudiu Beznea } 68464e21addSClaudiu Beznea 6856732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct at91_pinctrl_mux_ops at91rm9200_ops = { 6866732ae5cSJean-Christophe PLAGNIOL-VILLARD .get_periph = at91_mux_get_periph, 6876732ae5cSJean-Christophe PLAGNIOL-VILLARD .mux_A_periph = at91_mux_set_A_periph, 6886732ae5cSJean-Christophe PLAGNIOL-VILLARD .mux_B_periph = at91_mux_set_B_periph, 6897ebd7a3aSJean-Christophe PLAGNIOL-VILLARD .get_deglitch = at91_mux_get_deglitch, 6907ebd7a3aSJean-Christophe PLAGNIOL-VILLARD .set_deglitch = at91_mux_set_deglitch, 6916732ae5cSJean-Christophe PLAGNIOL-VILLARD .irq_type = gpio_irq_type, 6926732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 6936732ae5cSJean-Christophe PLAGNIOL-VILLARD 6946732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct at91_pinctrl_mux_ops at91sam9x5_ops = { 6956732ae5cSJean-Christophe PLAGNIOL-VILLARD .get_periph = at91_mux_pio3_get_periph, 6966732ae5cSJean-Christophe PLAGNIOL-VILLARD .mux_A_periph = at91_mux_pio3_set_A_periph, 6976732ae5cSJean-Christophe PLAGNIOL-VILLARD .mux_B_periph = at91_mux_pio3_set_B_periph, 6986732ae5cSJean-Christophe PLAGNIOL-VILLARD .mux_C_periph = at91_mux_pio3_set_C_periph, 6996732ae5cSJean-Christophe PLAGNIOL-VILLARD .mux_D_periph = at91_mux_pio3_set_D_periph, 700c8dba02eSBoris BREZILLON .get_deglitch = at91_mux_pio3_get_deglitch, 7017ebd7a3aSJean-Christophe PLAGNIOL-VILLARD .set_deglitch = at91_mux_pio3_set_deglitch, 7027ebd7a3aSJean-Christophe PLAGNIOL-VILLARD .get_debounce = at91_mux_pio3_get_debounce, 7037ebd7a3aSJean-Christophe PLAGNIOL-VILLARD .set_debounce = at91_mux_pio3_set_debounce, 7047ebd7a3aSJean-Christophe PLAGNIOL-VILLARD .get_pulldown = at91_mux_pio3_get_pulldown, 7057ebd7a3aSJean-Christophe PLAGNIOL-VILLARD .set_pulldown = at91_mux_pio3_set_pulldown, 7067ebd7a3aSJean-Christophe PLAGNIOL-VILLARD .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig, 7077ebd7a3aSJean-Christophe PLAGNIOL-VILLARD .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig, 7084334ac2dSMarek Roszko .get_drivestrength = at91_mux_sam9x5_get_drivestrength, 7094334ac2dSMarek Roszko .set_drivestrength = at91_mux_sam9x5_set_drivestrength, 7104334ac2dSMarek Roszko .irq_type = alt_gpio_irq_type, 7114334ac2dSMarek Roszko }; 7124334ac2dSMarek Roszko 71342ef7557SClaudiu Beznea static const struct at91_pinctrl_mux_ops sam9x60_ops = { 71442ef7557SClaudiu Beznea .get_periph = at91_mux_pio3_get_periph, 71542ef7557SClaudiu Beznea .mux_A_periph = at91_mux_pio3_set_A_periph, 71642ef7557SClaudiu Beznea .mux_B_periph = at91_mux_pio3_set_B_periph, 71742ef7557SClaudiu Beznea .mux_C_periph = at91_mux_pio3_set_C_periph, 71842ef7557SClaudiu Beznea .mux_D_periph = at91_mux_pio3_set_D_periph, 71942ef7557SClaudiu Beznea .get_deglitch = at91_mux_pio3_get_deglitch, 72042ef7557SClaudiu Beznea .set_deglitch = at91_mux_pio3_set_deglitch, 72142ef7557SClaudiu Beznea .get_debounce = at91_mux_pio3_get_debounce, 72242ef7557SClaudiu Beznea .set_debounce = at91_mux_pio3_set_debounce, 72342ef7557SClaudiu Beznea .get_pulldown = at91_mux_pio3_get_pulldown, 72442ef7557SClaudiu Beznea .set_pulldown = at91_mux_pio3_set_pulldown, 72542ef7557SClaudiu Beznea .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig, 72642ef7557SClaudiu Beznea .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig, 72742ef7557SClaudiu Beznea .get_drivestrength = at91_mux_sam9x60_get_drivestrength, 72842ef7557SClaudiu Beznea .set_drivestrength = at91_mux_sam9x60_set_drivestrength, 72964e21addSClaudiu Beznea .get_slewrate = at91_mux_sam9x60_get_slewrate, 73064e21addSClaudiu Beznea .set_slewrate = at91_mux_sam9x60_set_slewrate, 73142ef7557SClaudiu Beznea .irq_type = alt_gpio_irq_type, 73242ef7557SClaudiu Beznea 73342ef7557SClaudiu Beznea }; 73442ef7557SClaudiu Beznea 7354334ac2dSMarek Roszko static struct at91_pinctrl_mux_ops sama5d3_ops = { 7364334ac2dSMarek Roszko .get_periph = at91_mux_pio3_get_periph, 7374334ac2dSMarek Roszko .mux_A_periph = at91_mux_pio3_set_A_periph, 7384334ac2dSMarek Roszko .mux_B_periph = at91_mux_pio3_set_B_periph, 7394334ac2dSMarek Roszko .mux_C_periph = at91_mux_pio3_set_C_periph, 7404334ac2dSMarek Roszko .mux_D_periph = at91_mux_pio3_set_D_periph, 7414334ac2dSMarek Roszko .get_deglitch = at91_mux_pio3_get_deglitch, 7424334ac2dSMarek Roszko .set_deglitch = at91_mux_pio3_set_deglitch, 7434334ac2dSMarek Roszko .get_debounce = at91_mux_pio3_get_debounce, 7444334ac2dSMarek Roszko .set_debounce = at91_mux_pio3_set_debounce, 7454334ac2dSMarek Roszko .get_pulldown = at91_mux_pio3_get_pulldown, 7464334ac2dSMarek Roszko .set_pulldown = at91_mux_pio3_set_pulldown, 7474334ac2dSMarek Roszko .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig, 7484334ac2dSMarek Roszko .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig, 7494334ac2dSMarek Roszko .get_drivestrength = at91_mux_sama5d3_get_drivestrength, 7504334ac2dSMarek Roszko .set_drivestrength = at91_mux_sama5d3_set_drivestrength, 7516732ae5cSJean-Christophe PLAGNIOL-VILLARD .irq_type = alt_gpio_irq_type, 7526732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 7536732ae5cSJean-Christophe PLAGNIOL-VILLARD 7546732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin) 7556732ae5cSJean-Christophe PLAGNIOL-VILLARD { 7566732ae5cSJean-Christophe PLAGNIOL-VILLARD if (pin->mux) { 7574b6fe45aSHans Wennborg dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lx\n", 7586732ae5cSJean-Christophe PLAGNIOL-VILLARD pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf); 7596732ae5cSJean-Christophe PLAGNIOL-VILLARD } else { 7604b6fe45aSHans Wennborg dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lx\n", 7616732ae5cSJean-Christophe PLAGNIOL-VILLARD pin->bank + 'A', pin->pin, pin->conf); 7626732ae5cSJean-Christophe PLAGNIOL-VILLARD } 7636732ae5cSJean-Christophe PLAGNIOL-VILLARD } 7646732ae5cSJean-Christophe PLAGNIOL-VILLARD 7656732ae5cSJean-Christophe PLAGNIOL-VILLARD static int pin_check_config(struct at91_pinctrl *info, const char *name, 7666732ae5cSJean-Christophe PLAGNIOL-VILLARD int index, const struct at91_pmx_pin *pin) 7676732ae5cSJean-Christophe PLAGNIOL-VILLARD { 7686732ae5cSJean-Christophe PLAGNIOL-VILLARD int mux; 7696732ae5cSJean-Christophe PLAGNIOL-VILLARD 7706732ae5cSJean-Christophe PLAGNIOL-VILLARD /* check if it's a valid config */ 771a0b957f3SJean-Christophe PLAGNIOL-VILLARD if (pin->bank >= gpio_banks) { 7726732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n", 773a0b957f3SJean-Christophe PLAGNIOL-VILLARD name, index, pin->bank, gpio_banks); 7746732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 7756732ae5cSJean-Christophe PLAGNIOL-VILLARD } 7766732ae5cSJean-Christophe PLAGNIOL-VILLARD 777a0b957f3SJean-Christophe PLAGNIOL-VILLARD if (!gpio_chips[pin->bank]) { 778a0b957f3SJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "%s: pin conf %d bank_id %d not enabled\n", 779a0b957f3SJean-Christophe PLAGNIOL-VILLARD name, index, pin->bank); 780a0b957f3SJean-Christophe PLAGNIOL-VILLARD return -ENXIO; 781a0b957f3SJean-Christophe PLAGNIOL-VILLARD } 782a0b957f3SJean-Christophe PLAGNIOL-VILLARD 7836732ae5cSJean-Christophe PLAGNIOL-VILLARD if (pin->pin >= MAX_NB_GPIO_PER_BANK) { 7846732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n", 7856732ae5cSJean-Christophe PLAGNIOL-VILLARD name, index, pin->pin, MAX_NB_GPIO_PER_BANK); 7866732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 7876732ae5cSJean-Christophe PLAGNIOL-VILLARD } 7886732ae5cSJean-Christophe PLAGNIOL-VILLARD 7896732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!pin->mux) 7906732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 7916732ae5cSJean-Christophe PLAGNIOL-VILLARD 7926732ae5cSJean-Christophe PLAGNIOL-VILLARD mux = pin->mux - 1; 7936732ae5cSJean-Christophe PLAGNIOL-VILLARD 7946732ae5cSJean-Christophe PLAGNIOL-VILLARD if (mux >= info->nmux) { 7956732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n", 7966732ae5cSJean-Christophe PLAGNIOL-VILLARD name, index, mux, info->nmux); 7976732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 7986732ae5cSJean-Christophe PLAGNIOL-VILLARD } 7996732ae5cSJean-Christophe PLAGNIOL-VILLARD 8006732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) { 8016732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n", 8026732ae5cSJean-Christophe PLAGNIOL-VILLARD name, index, mux, pin->bank + 'A', pin->pin); 8036732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 8046732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8056732ae5cSJean-Christophe PLAGNIOL-VILLARD 8066732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 8076732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8086732ae5cSJean-Christophe PLAGNIOL-VILLARD 8096732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask) 8106732ae5cSJean-Christophe PLAGNIOL-VILLARD { 8116732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_PDR); 8126732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8136732ae5cSJean-Christophe PLAGNIOL-VILLARD 8146732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input) 8156732ae5cSJean-Christophe PLAGNIOL-VILLARD { 8166732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_PER); 8176732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER)); 8186732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8196732ae5cSJean-Christophe PLAGNIOL-VILLARD 82003e9f0caSLinus Walleij static int at91_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 8216732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned group) 8226732ae5cSJean-Christophe PLAGNIOL-VILLARD { 8236732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 8246732ae5cSJean-Christophe PLAGNIOL-VILLARD const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf; 8256732ae5cSJean-Christophe PLAGNIOL-VILLARD const struct at91_pmx_pin *pin; 8266732ae5cSJean-Christophe PLAGNIOL-VILLARD uint32_t npins = info->groups[group].npins; 8276732ae5cSJean-Christophe PLAGNIOL-VILLARD int i, ret; 8286732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask; 8296732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio; 8306732ae5cSJean-Christophe PLAGNIOL-VILLARD 8316732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(info->dev, "enable function %s group %s\n", 8326732ae5cSJean-Christophe PLAGNIOL-VILLARD info->functions[selector].name, info->groups[group].name); 8336732ae5cSJean-Christophe PLAGNIOL-VILLARD 8346732ae5cSJean-Christophe PLAGNIOL-VILLARD /* first check that all the pins of the group are valid with a valid 83561e310a1SAlexandre Belloni * parameter */ 8366732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < npins; i++) { 8376732ae5cSJean-Christophe PLAGNIOL-VILLARD pin = &pins_conf[i]; 8386732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = pin_check_config(info, info->groups[group].name, i, pin); 8396732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ret) 8406732ae5cSJean-Christophe PLAGNIOL-VILLARD return ret; 8416732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8426732ae5cSJean-Christophe PLAGNIOL-VILLARD 8436732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < npins; i++) { 8446732ae5cSJean-Christophe PLAGNIOL-VILLARD pin = &pins_conf[i]; 8456732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_pin_dbg(info->dev, pin); 8466732ae5cSJean-Christophe PLAGNIOL-VILLARD pio = pin_to_controller(info, pin->bank); 8471ab36387SDavid Dueck 8481ab36387SDavid Dueck if (!pio) 8491ab36387SDavid Dueck continue; 8501ab36387SDavid Dueck 8516732ae5cSJean-Christophe PLAGNIOL-VILLARD mask = pin_to_mask(pin->pin); 8526732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_mux_disable_interrupt(pio, mask); 8536732ae5cSJean-Christophe PLAGNIOL-VILLARD switch (pin->mux) { 8546732ae5cSJean-Christophe PLAGNIOL-VILLARD case AT91_MUX_GPIO: 8556732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_mux_gpio_enable(pio, mask, 1); 8566732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 8576732ae5cSJean-Christophe PLAGNIOL-VILLARD case AT91_MUX_PERIPH_A: 8586732ae5cSJean-Christophe PLAGNIOL-VILLARD info->ops->mux_A_periph(pio, mask); 8596732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 8606732ae5cSJean-Christophe PLAGNIOL-VILLARD case AT91_MUX_PERIPH_B: 8616732ae5cSJean-Christophe PLAGNIOL-VILLARD info->ops->mux_B_periph(pio, mask); 8626732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 8636732ae5cSJean-Christophe PLAGNIOL-VILLARD case AT91_MUX_PERIPH_C: 8646732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!info->ops->mux_C_periph) 8656732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 8666732ae5cSJean-Christophe PLAGNIOL-VILLARD info->ops->mux_C_periph(pio, mask); 8676732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 8686732ae5cSJean-Christophe PLAGNIOL-VILLARD case AT91_MUX_PERIPH_D: 8696732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!info->ops->mux_D_periph) 8706732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 8716732ae5cSJean-Christophe PLAGNIOL-VILLARD info->ops->mux_D_periph(pio, mask); 8726732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 8736732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8746732ae5cSJean-Christophe PLAGNIOL-VILLARD if (pin->mux) 8756732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_mux_gpio_disable(pio, mask); 8766732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8776732ae5cSJean-Christophe PLAGNIOL-VILLARD 8786732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 8796732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8806732ae5cSJean-Christophe PLAGNIOL-VILLARD 8816732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 8826732ae5cSJean-Christophe PLAGNIOL-VILLARD { 8836732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 8846732ae5cSJean-Christophe PLAGNIOL-VILLARD 8856732ae5cSJean-Christophe PLAGNIOL-VILLARD return info->nfunctions; 8866732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8876732ae5cSJean-Christophe PLAGNIOL-VILLARD 8886732ae5cSJean-Christophe PLAGNIOL-VILLARD static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev, 8896732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned selector) 8906732ae5cSJean-Christophe PLAGNIOL-VILLARD { 8916732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 8926732ae5cSJean-Christophe PLAGNIOL-VILLARD 8936732ae5cSJean-Christophe PLAGNIOL-VILLARD return info->functions[selector].name; 8946732ae5cSJean-Christophe PLAGNIOL-VILLARD } 8956732ae5cSJean-Christophe PLAGNIOL-VILLARD 8966732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, 8976732ae5cSJean-Christophe PLAGNIOL-VILLARD const char * const **groups, 8986732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned * const num_groups) 8996732ae5cSJean-Christophe PLAGNIOL-VILLARD { 9006732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 9016732ae5cSJean-Christophe PLAGNIOL-VILLARD 9026732ae5cSJean-Christophe PLAGNIOL-VILLARD *groups = info->functions[selector].groups; 9036732ae5cSJean-Christophe PLAGNIOL-VILLARD *num_groups = info->functions[selector].ngroups; 9046732ae5cSJean-Christophe PLAGNIOL-VILLARD 9056732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 9066732ae5cSJean-Christophe PLAGNIOL-VILLARD } 9076732ae5cSJean-Christophe PLAGNIOL-VILLARD 908f6f94f66SAxel Lin static int at91_gpio_request_enable(struct pinctrl_dev *pctldev, 9096732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_gpio_range *range, 9106732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned offset) 9116732ae5cSJean-Christophe PLAGNIOL-VILLARD { 9126732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 9136732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_chip; 9146732ae5cSJean-Christophe PLAGNIOL-VILLARD struct gpio_chip *chip; 9156732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask; 9166732ae5cSJean-Christophe PLAGNIOL-VILLARD 9176732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!range) { 9186732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(npct->dev, "invalid range\n"); 9196732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 9206732ae5cSJean-Christophe PLAGNIOL-VILLARD } 9216732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!range->gc) { 9226732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(npct->dev, "missing GPIO chip in range\n"); 9236732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 9246732ae5cSJean-Christophe PLAGNIOL-VILLARD } 9256732ae5cSJean-Christophe PLAGNIOL-VILLARD chip = range->gc; 926370ea611SLinus Walleij at91_chip = gpiochip_get_data(chip); 9276732ae5cSJean-Christophe PLAGNIOL-VILLARD 9286732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); 9296732ae5cSJean-Christophe PLAGNIOL-VILLARD 9306732ae5cSJean-Christophe PLAGNIOL-VILLARD mask = 1 << (offset - chip->base); 9316732ae5cSJean-Christophe PLAGNIOL-VILLARD 9326732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n", 9336732ae5cSJean-Christophe PLAGNIOL-VILLARD offset, 'A' + range->id, offset - chip->base, mask); 9346732ae5cSJean-Christophe PLAGNIOL-VILLARD 9356732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, at91_chip->regbase + PIO_PER); 9366732ae5cSJean-Christophe PLAGNIOL-VILLARD 9376732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 9386732ae5cSJean-Christophe PLAGNIOL-VILLARD } 9396732ae5cSJean-Christophe PLAGNIOL-VILLARD 940f6f94f66SAxel Lin static void at91_gpio_disable_free(struct pinctrl_dev *pctldev, 9416732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_gpio_range *range, 9426732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned offset) 9436732ae5cSJean-Christophe PLAGNIOL-VILLARD { 9446732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 9456732ae5cSJean-Christophe PLAGNIOL-VILLARD 9466732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); 9476732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Set the pin to some default state, GPIO is usually default */ 9486732ae5cSJean-Christophe PLAGNIOL-VILLARD } 9496732ae5cSJean-Christophe PLAGNIOL-VILLARD 950022ab148SLaurent Pinchart static const struct pinmux_ops at91_pmx_ops = { 9516732ae5cSJean-Christophe PLAGNIOL-VILLARD .get_functions_count = at91_pmx_get_funcs_count, 9526732ae5cSJean-Christophe PLAGNIOL-VILLARD .get_function_name = at91_pmx_get_func_name, 9536732ae5cSJean-Christophe PLAGNIOL-VILLARD .get_function_groups = at91_pmx_get_groups, 95403e9f0caSLinus Walleij .set_mux = at91_pmx_set, 9556732ae5cSJean-Christophe PLAGNIOL-VILLARD .gpio_request_enable = at91_gpio_request_enable, 9566732ae5cSJean-Christophe PLAGNIOL-VILLARD .gpio_disable_free = at91_gpio_disable_free, 9576732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 9586732ae5cSJean-Christophe PLAGNIOL-VILLARD 9596732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_pinconf_get(struct pinctrl_dev *pctldev, 9606732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned pin_id, unsigned long *config) 9616732ae5cSJean-Christophe PLAGNIOL-VILLARD { 9626732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 9636732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio; 9646732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned pin; 9657ebd7a3aSJean-Christophe PLAGNIOL-VILLARD int div; 96696bb12deSBoris BREZILLON bool out; 9676732ae5cSJean-Christophe PLAGNIOL-VILLARD 9681292e693SAlexandre Belloni *config = 0; 9691292e693SAlexandre Belloni dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id); 9706732ae5cSJean-Christophe PLAGNIOL-VILLARD pio = pin_to_controller(info, pin_to_bank(pin_id)); 9711ab36387SDavid Dueck 9721ab36387SDavid Dueck if (!pio) 9731ab36387SDavid Dueck return -EINVAL; 9741ab36387SDavid Dueck 9756732ae5cSJean-Christophe PLAGNIOL-VILLARD pin = pin_id % MAX_NB_GPIO_PER_BANK; 9766732ae5cSJean-Christophe PLAGNIOL-VILLARD 9776732ae5cSJean-Christophe PLAGNIOL-VILLARD if (at91_mux_get_multidrive(pio, pin)) 9786732ae5cSJean-Christophe PLAGNIOL-VILLARD *config |= MULTI_DRIVE; 9796732ae5cSJean-Christophe PLAGNIOL-VILLARD 9806732ae5cSJean-Christophe PLAGNIOL-VILLARD if (at91_mux_get_pullup(pio, pin)) 9816732ae5cSJean-Christophe PLAGNIOL-VILLARD *config |= PULL_UP; 9826732ae5cSJean-Christophe PLAGNIOL-VILLARD 9837ebd7a3aSJean-Christophe PLAGNIOL-VILLARD if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin)) 9847ebd7a3aSJean-Christophe PLAGNIOL-VILLARD *config |= DEGLITCH; 9857ebd7a3aSJean-Christophe PLAGNIOL-VILLARD if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div)) 9867ebd7a3aSJean-Christophe PLAGNIOL-VILLARD *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT); 9877ebd7a3aSJean-Christophe PLAGNIOL-VILLARD if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin)) 9887ebd7a3aSJean-Christophe PLAGNIOL-VILLARD *config |= PULL_DOWN; 9897ebd7a3aSJean-Christophe PLAGNIOL-VILLARD if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin)) 9907ebd7a3aSJean-Christophe PLAGNIOL-VILLARD *config |= DIS_SCHMIT; 9914334ac2dSMarek Roszko if (info->ops->get_drivestrength) 9924334ac2dSMarek Roszko *config |= (info->ops->get_drivestrength(pio, pin) 9934334ac2dSMarek Roszko << DRIVE_STRENGTH_SHIFT); 99464e21addSClaudiu Beznea if (info->ops->get_slewrate) 99564e21addSClaudiu Beznea *config |= (info->ops->get_slewrate(pio, pin) << SLEWRATE_SHIFT); 99696bb12deSBoris BREZILLON if (at91_mux_get_output(pio, pin, &out)) 99796bb12deSBoris BREZILLON *config |= OUTPUT | (out << OUTPUT_VAL_SHIFT); 9987ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 9996732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 10006732ae5cSJean-Christophe PLAGNIOL-VILLARD } 10016732ae5cSJean-Christophe PLAGNIOL-VILLARD 10026732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_pinconf_set(struct pinctrl_dev *pctldev, 100303b054e9SSherman Yin unsigned pin_id, unsigned long *configs, 100403b054e9SSherman Yin unsigned num_configs) 10056732ae5cSJean-Christophe PLAGNIOL-VILLARD { 10066732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 10076732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask; 10086732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio; 100903b054e9SSherman Yin int i; 101003b054e9SSherman Yin unsigned long config; 10114334ac2dSMarek Roszko unsigned pin; 10126732ae5cSJean-Christophe PLAGNIOL-VILLARD 101303b054e9SSherman Yin for (i = 0; i < num_configs; i++) { 101403b054e9SSherman Yin config = configs[i]; 101503b054e9SSherman Yin 101603b054e9SSherman Yin dev_dbg(info->dev, 101703b054e9SSherman Yin "%s:%d, pin_id=%d, config=0x%lx", 101803b054e9SSherman Yin __func__, __LINE__, pin_id, config); 10196732ae5cSJean-Christophe PLAGNIOL-VILLARD pio = pin_to_controller(info, pin_to_bank(pin_id)); 10201ab36387SDavid Dueck 10211ab36387SDavid Dueck if (!pio) 10221ab36387SDavid Dueck return -EINVAL; 10231ab36387SDavid Dueck 10244334ac2dSMarek Roszko pin = pin_id % MAX_NB_GPIO_PER_BANK; 10254334ac2dSMarek Roszko mask = pin_to_mask(pin); 10266732ae5cSJean-Christophe PLAGNIOL-VILLARD 10277ebd7a3aSJean-Christophe PLAGNIOL-VILLARD if (config & PULL_UP && config & PULL_DOWN) 10287ebd7a3aSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 10297ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 103096bb12deSBoris BREZILLON at91_mux_set_output(pio, mask, config & OUTPUT, 103196bb12deSBoris BREZILLON (config & OUTPUT_VAL) >> OUTPUT_VAL_SHIFT); 10326732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_mux_set_pullup(pio, mask, config & PULL_UP); 10336732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE); 10347ebd7a3aSJean-Christophe PLAGNIOL-VILLARD if (info->ops->set_deglitch) 10357ebd7a3aSJean-Christophe PLAGNIOL-VILLARD info->ops->set_deglitch(pio, mask, config & DEGLITCH); 10367ebd7a3aSJean-Christophe PLAGNIOL-VILLARD if (info->ops->set_debounce) 10377ebd7a3aSJean-Christophe PLAGNIOL-VILLARD info->ops->set_debounce(pio, mask, config & DEBOUNCE, 10387ebd7a3aSJean-Christophe PLAGNIOL-VILLARD (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT); 10397ebd7a3aSJean-Christophe PLAGNIOL-VILLARD if (info->ops->set_pulldown) 10407ebd7a3aSJean-Christophe PLAGNIOL-VILLARD info->ops->set_pulldown(pio, mask, config & PULL_DOWN); 10417ebd7a3aSJean-Christophe PLAGNIOL-VILLARD if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT) 10427ebd7a3aSJean-Christophe PLAGNIOL-VILLARD info->ops->disable_schmitt_trig(pio, mask); 10434334ac2dSMarek Roszko if (info->ops->set_drivestrength) 10444334ac2dSMarek Roszko info->ops->set_drivestrength(pio, pin, 10454334ac2dSMarek Roszko (config & DRIVE_STRENGTH) 10464334ac2dSMarek Roszko >> DRIVE_STRENGTH_SHIFT); 104764e21addSClaudiu Beznea if (info->ops->set_slewrate) 104864e21addSClaudiu Beznea info->ops->set_slewrate(pio, pin, 104964e21addSClaudiu Beznea (config & SLEWRATE) >> SLEWRATE_SHIFT); 10507ebd7a3aSJean-Christophe PLAGNIOL-VILLARD 105103b054e9SSherman Yin } /* for each config */ 105203b054e9SSherman Yin 10536732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 10546732ae5cSJean-Christophe PLAGNIOL-VILLARD } 10556732ae5cSJean-Christophe PLAGNIOL-VILLARD 10564d9b8a8eSAlexandre Belloni #define DBG_SHOW_FLAG(flag) do { \ 10574d9b8a8eSAlexandre Belloni if (config & flag) { \ 10584d9b8a8eSAlexandre Belloni if (num_conf) \ 10594d9b8a8eSAlexandre Belloni seq_puts(s, "|"); \ 10604d9b8a8eSAlexandre Belloni seq_puts(s, #flag); \ 10614d9b8a8eSAlexandre Belloni num_conf++; \ 10624d9b8a8eSAlexandre Belloni } \ 10634d9b8a8eSAlexandre Belloni } while (0) 10644d9b8a8eSAlexandre Belloni 1065b67328e1SClaudiu Beznea #define DBG_SHOW_FLAG_MASKED(mask, flag, name) do { \ 10664334ac2dSMarek Roszko if ((config & mask) == flag) { \ 10674334ac2dSMarek Roszko if (num_conf) \ 10684334ac2dSMarek Roszko seq_puts(s, "|"); \ 1069b67328e1SClaudiu Beznea seq_puts(s, #name); \ 10704334ac2dSMarek Roszko num_conf++; \ 10714334ac2dSMarek Roszko } \ 10724334ac2dSMarek Roszko } while (0) 10734334ac2dSMarek Roszko 10746732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev, 10756732ae5cSJean-Christophe PLAGNIOL-VILLARD struct seq_file *s, unsigned pin_id) 10766732ae5cSJean-Christophe PLAGNIOL-VILLARD { 10774d9b8a8eSAlexandre Belloni unsigned long config; 1078445d2026SRickard Strandqvist int val, num_conf = 0; 10796732ae5cSJean-Christophe PLAGNIOL-VILLARD 1080445d2026SRickard Strandqvist at91_pinconf_get(pctldev, pin_id, &config); 10814d9b8a8eSAlexandre Belloni 10824d9b8a8eSAlexandre Belloni DBG_SHOW_FLAG(MULTI_DRIVE); 10834d9b8a8eSAlexandre Belloni DBG_SHOW_FLAG(PULL_UP); 10844d9b8a8eSAlexandre Belloni DBG_SHOW_FLAG(PULL_DOWN); 10854d9b8a8eSAlexandre Belloni DBG_SHOW_FLAG(DIS_SCHMIT); 10864d9b8a8eSAlexandre Belloni DBG_SHOW_FLAG(DEGLITCH); 1087b67328e1SClaudiu Beznea DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW), 1088b67328e1SClaudiu Beznea DRIVE_STRENGTH_LOW); 1089b67328e1SClaudiu Beznea DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED), 1090b67328e1SClaudiu Beznea DRIVE_STRENGTH_MED); 1091b67328e1SClaudiu Beznea DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI), 1092b67328e1SClaudiu Beznea DRIVE_STRENGTH_HI); 109364e21addSClaudiu Beznea DBG_SHOW_FLAG(SLEWRATE); 10944d9b8a8eSAlexandre Belloni DBG_SHOW_FLAG(DEBOUNCE); 10954d9b8a8eSAlexandre Belloni if (config & DEBOUNCE) { 10964d9b8a8eSAlexandre Belloni val = config >> DEBOUNCE_VAL_SHIFT; 10974d9b8a8eSAlexandre Belloni seq_printf(s, "(%d)", val); 10984d9b8a8eSAlexandre Belloni } 10994d9b8a8eSAlexandre Belloni 11004d9b8a8eSAlexandre Belloni return; 11016732ae5cSJean-Christophe PLAGNIOL-VILLARD } 11026732ae5cSJean-Christophe PLAGNIOL-VILLARD 11036732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 11046732ae5cSJean-Christophe PLAGNIOL-VILLARD struct seq_file *s, unsigned group) 11056732ae5cSJean-Christophe PLAGNIOL-VILLARD { 11066732ae5cSJean-Christophe PLAGNIOL-VILLARD } 11076732ae5cSJean-Christophe PLAGNIOL-VILLARD 1108022ab148SLaurent Pinchart static const struct pinconf_ops at91_pinconf_ops = { 11096732ae5cSJean-Christophe PLAGNIOL-VILLARD .pin_config_get = at91_pinconf_get, 11106732ae5cSJean-Christophe PLAGNIOL-VILLARD .pin_config_set = at91_pinconf_set, 11116732ae5cSJean-Christophe PLAGNIOL-VILLARD .pin_config_dbg_show = at91_pinconf_dbg_show, 11126732ae5cSJean-Christophe PLAGNIOL-VILLARD .pin_config_group_dbg_show = at91_pinconf_group_dbg_show, 11136732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 11146732ae5cSJean-Christophe PLAGNIOL-VILLARD 11156732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct pinctrl_desc at91_pinctrl_desc = { 11166732ae5cSJean-Christophe PLAGNIOL-VILLARD .pctlops = &at91_pctrl_ops, 11176732ae5cSJean-Christophe PLAGNIOL-VILLARD .pmxops = &at91_pmx_ops, 11186732ae5cSJean-Christophe PLAGNIOL-VILLARD .confops = &at91_pinconf_ops, 11196732ae5cSJean-Christophe PLAGNIOL-VILLARD .owner = THIS_MODULE, 11206732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 11216732ae5cSJean-Christophe PLAGNIOL-VILLARD 11226732ae5cSJean-Christophe PLAGNIOL-VILLARD static const char *gpio_compat = "atmel,at91rm9200-gpio"; 11236732ae5cSJean-Christophe PLAGNIOL-VILLARD 1124150632b0SGreg Kroah-Hartman static void at91_pinctrl_child_count(struct at91_pinctrl *info, 11256732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *np) 11266732ae5cSJean-Christophe PLAGNIOL-VILLARD { 11276732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *child; 11286732ae5cSJean-Christophe PLAGNIOL-VILLARD 11296732ae5cSJean-Christophe PLAGNIOL-VILLARD for_each_child_of_node(np, child) { 11306732ae5cSJean-Christophe PLAGNIOL-VILLARD if (of_device_is_compatible(child, gpio_compat)) { 1131a0b957f3SJean-Christophe PLAGNIOL-VILLARD if (of_device_is_available(child)) 1132a0b957f3SJean-Christophe PLAGNIOL-VILLARD info->nactive_banks++; 11336732ae5cSJean-Christophe PLAGNIOL-VILLARD } else { 11346732ae5cSJean-Christophe PLAGNIOL-VILLARD info->nfunctions++; 11356732ae5cSJean-Christophe PLAGNIOL-VILLARD info->ngroups += of_get_child_count(child); 11366732ae5cSJean-Christophe PLAGNIOL-VILLARD } 11376732ae5cSJean-Christophe PLAGNIOL-VILLARD } 11386732ae5cSJean-Christophe PLAGNIOL-VILLARD } 11396732ae5cSJean-Christophe PLAGNIOL-VILLARD 1140150632b0SGreg Kroah-Hartman static int at91_pinctrl_mux_mask(struct at91_pinctrl *info, 11416732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *np) 11426732ae5cSJean-Christophe PLAGNIOL-VILLARD { 11436732ae5cSJean-Christophe PLAGNIOL-VILLARD int ret = 0; 11446732ae5cSJean-Christophe PLAGNIOL-VILLARD int size; 11451164d73aSSachin Kamat const __be32 *list; 11466732ae5cSJean-Christophe PLAGNIOL-VILLARD 11476732ae5cSJean-Christophe PLAGNIOL-VILLARD list = of_get_property(np, "atmel,mux-mask", &size); 11486732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!list) { 11496732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "can not read the mux-mask of %d\n", size); 11506732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 11516732ae5cSJean-Christophe PLAGNIOL-VILLARD } 11526732ae5cSJean-Christophe PLAGNIOL-VILLARD 11536732ae5cSJean-Christophe PLAGNIOL-VILLARD size /= sizeof(*list); 1154a0b957f3SJean-Christophe PLAGNIOL-VILLARD if (!size || size % gpio_banks) { 1155a0b957f3SJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "wrong mux mask array should be by %d\n", gpio_banks); 11566732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 11576732ae5cSJean-Christophe PLAGNIOL-VILLARD } 1158a0b957f3SJean-Christophe PLAGNIOL-VILLARD info->nmux = size / gpio_banks; 11596732ae5cSJean-Christophe PLAGNIOL-VILLARD 1160a86854d0SKees Cook info->mux_mask = devm_kcalloc(info->dev, size, sizeof(u32), 1161a86854d0SKees Cook GFP_KERNEL); 11623da941b0SMarkus Elfring if (!info->mux_mask) 11636732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENOMEM; 11646732ae5cSJean-Christophe PLAGNIOL-VILLARD 11656732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = of_property_read_u32_array(np, "atmel,mux-mask", 11666732ae5cSJean-Christophe PLAGNIOL-VILLARD info->mux_mask, size); 11676732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ret) 11686732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "can not read the mux-mask of %d\n", size); 11696732ae5cSJean-Christophe PLAGNIOL-VILLARD return ret; 11706732ae5cSJean-Christophe PLAGNIOL-VILLARD } 11716732ae5cSJean-Christophe PLAGNIOL-VILLARD 1172150632b0SGreg Kroah-Hartman static int at91_pinctrl_parse_groups(struct device_node *np, 11736732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pin_group *grp, 1174150632b0SGreg Kroah-Hartman struct at91_pinctrl *info, u32 index) 11756732ae5cSJean-Christophe PLAGNIOL-VILLARD { 11766732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pmx_pin *pin; 11776732ae5cSJean-Christophe PLAGNIOL-VILLARD int size; 11781164d73aSSachin Kamat const __be32 *list; 11796732ae5cSJean-Christophe PLAGNIOL-VILLARD int i, j; 11806732ae5cSJean-Christophe PLAGNIOL-VILLARD 118194f4e54cSRob Herring dev_dbg(info->dev, "group(%d): %pOFn\n", index, np); 11826732ae5cSJean-Christophe PLAGNIOL-VILLARD 11836732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Initialise group */ 11846732ae5cSJean-Christophe PLAGNIOL-VILLARD grp->name = np->name; 11856732ae5cSJean-Christophe PLAGNIOL-VILLARD 11866732ae5cSJean-Christophe PLAGNIOL-VILLARD /* 11876732ae5cSJean-Christophe PLAGNIOL-VILLARD * the binding format is atmel,pins = <bank pin mux CONFIG ...>, 11886732ae5cSJean-Christophe PLAGNIOL-VILLARD * do sanity check and calculate pins number 11896732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 11906732ae5cSJean-Christophe PLAGNIOL-VILLARD list = of_get_property(np, "atmel,pins", &size); 11916732ae5cSJean-Christophe PLAGNIOL-VILLARD /* we do not check return since it's safe node passed down */ 11926732ae5cSJean-Christophe PLAGNIOL-VILLARD size /= sizeof(*list); 11936732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!size || size % 4) { 11946732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); 11956732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 11966732ae5cSJean-Christophe PLAGNIOL-VILLARD } 11976732ae5cSJean-Christophe PLAGNIOL-VILLARD 11986732ae5cSJean-Christophe PLAGNIOL-VILLARD grp->npins = size / 4; 1199a86854d0SKees Cook pin = grp->pins_conf = devm_kcalloc(info->dev, 1200a86854d0SKees Cook grp->npins, 1201a86854d0SKees Cook sizeof(struct at91_pmx_pin), 12026732ae5cSJean-Christophe PLAGNIOL-VILLARD GFP_KERNEL); 1203a86854d0SKees Cook grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int), 12046732ae5cSJean-Christophe PLAGNIOL-VILLARD GFP_KERNEL); 12056732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!grp->pins_conf || !grp->pins) 12066732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENOMEM; 12076732ae5cSJean-Christophe PLAGNIOL-VILLARD 12086732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0, j = 0; i < size; i += 4, j++) { 12096732ae5cSJean-Christophe PLAGNIOL-VILLARD pin->bank = be32_to_cpu(*list++); 12106732ae5cSJean-Christophe PLAGNIOL-VILLARD pin->pin = be32_to_cpu(*list++); 12116732ae5cSJean-Christophe PLAGNIOL-VILLARD grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin; 12126732ae5cSJean-Christophe PLAGNIOL-VILLARD pin->mux = be32_to_cpu(*list++); 12136732ae5cSJean-Christophe PLAGNIOL-VILLARD pin->conf = be32_to_cpu(*list++); 12146732ae5cSJean-Christophe PLAGNIOL-VILLARD 12156732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_pin_dbg(info->dev, pin); 12166732ae5cSJean-Christophe PLAGNIOL-VILLARD pin++; 12176732ae5cSJean-Christophe PLAGNIOL-VILLARD } 12186732ae5cSJean-Christophe PLAGNIOL-VILLARD 12196732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 12206732ae5cSJean-Christophe PLAGNIOL-VILLARD } 12216732ae5cSJean-Christophe PLAGNIOL-VILLARD 1222150632b0SGreg Kroah-Hartman static int at91_pinctrl_parse_functions(struct device_node *np, 12236732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info, u32 index) 12246732ae5cSJean-Christophe PLAGNIOL-VILLARD { 12256732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *child; 12266732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pmx_func *func; 12276732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pin_group *grp; 12286732ae5cSJean-Christophe PLAGNIOL-VILLARD int ret; 12296732ae5cSJean-Christophe PLAGNIOL-VILLARD static u32 grp_index; 12306732ae5cSJean-Christophe PLAGNIOL-VILLARD u32 i = 0; 12316732ae5cSJean-Christophe PLAGNIOL-VILLARD 123294f4e54cSRob Herring dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np); 12336732ae5cSJean-Christophe PLAGNIOL-VILLARD 12346732ae5cSJean-Christophe PLAGNIOL-VILLARD func = &info->functions[index]; 12356732ae5cSJean-Christophe PLAGNIOL-VILLARD 12366732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Initialise function */ 12376732ae5cSJean-Christophe PLAGNIOL-VILLARD func->name = np->name; 12386732ae5cSJean-Christophe PLAGNIOL-VILLARD func->ngroups = of_get_child_count(np); 1239ca7162adSRickard Strandqvist if (func->ngroups == 0) { 12406732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(info->dev, "no groups defined\n"); 12416732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 12426732ae5cSJean-Christophe PLAGNIOL-VILLARD } 1243a86854d0SKees Cook func->groups = devm_kcalloc(info->dev, 1244a86854d0SKees Cook func->ngroups, sizeof(char *), GFP_KERNEL); 12456732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!func->groups) 12466732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENOMEM; 12476732ae5cSJean-Christophe PLAGNIOL-VILLARD 12486732ae5cSJean-Christophe PLAGNIOL-VILLARD for_each_child_of_node(np, child) { 12496732ae5cSJean-Christophe PLAGNIOL-VILLARD func->groups[i] = child->name; 12506732ae5cSJean-Christophe PLAGNIOL-VILLARD grp = &info->groups[grp_index++]; 12516732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = at91_pinctrl_parse_groups(child, grp, info, i++); 1252d94b986aSJulia Lawall if (ret) { 1253d94b986aSJulia Lawall of_node_put(child); 12546732ae5cSJean-Christophe PLAGNIOL-VILLARD return ret; 12556732ae5cSJean-Christophe PLAGNIOL-VILLARD } 1256d94b986aSJulia Lawall } 12576732ae5cSJean-Christophe PLAGNIOL-VILLARD 12586732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 12596732ae5cSJean-Christophe PLAGNIOL-VILLARD } 12606732ae5cSJean-Christophe PLAGNIOL-VILLARD 1261baa9946eSFabian Frederick static const struct of_device_id at91_pinctrl_of_match[] = { 12624334ac2dSMarek Roszko { .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops }, 12636732ae5cSJean-Christophe PLAGNIOL-VILLARD { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops }, 12646732ae5cSJean-Christophe PLAGNIOL-VILLARD { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops }, 1265a2fcb1ceSClaudiu Beznea { .compatible = "microchip,sam9x60-pinctrl", .data = &sam9x60_ops }, 12666732ae5cSJean-Christophe PLAGNIOL-VILLARD { /* sentinel */ } 12676732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 12686732ae5cSJean-Christophe PLAGNIOL-VILLARD 1269150632b0SGreg Kroah-Hartman static int at91_pinctrl_probe_dt(struct platform_device *pdev, 12706732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info) 12716732ae5cSJean-Christophe PLAGNIOL-VILLARD { 12726732ae5cSJean-Christophe PLAGNIOL-VILLARD int ret = 0; 12736732ae5cSJean-Christophe PLAGNIOL-VILLARD int i, j; 12746732ae5cSJean-Christophe PLAGNIOL-VILLARD uint32_t *tmp; 12756732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *np = pdev->dev.of_node; 12766732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *child; 12776732ae5cSJean-Christophe PLAGNIOL-VILLARD 12786732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!np) 12796732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENODEV; 12806732ae5cSJean-Christophe PLAGNIOL-VILLARD 12816732ae5cSJean-Christophe PLAGNIOL-VILLARD info->dev = &pdev->dev; 1282dffa9123SJean-Christophe PLAGNIOL-VILLARD info->ops = (struct at91_pinctrl_mux_ops *) 12836732ae5cSJean-Christophe PLAGNIOL-VILLARD of_match_device(at91_pinctrl_of_match, &pdev->dev)->data; 12846732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_pinctrl_child_count(info, np); 12856732ae5cSJean-Christophe PLAGNIOL-VILLARD 1286a0b957f3SJean-Christophe PLAGNIOL-VILLARD if (gpio_banks < 1) { 12876732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n"); 12886732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 12896732ae5cSJean-Christophe PLAGNIOL-VILLARD } 12906732ae5cSJean-Christophe PLAGNIOL-VILLARD 12916732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = at91_pinctrl_mux_mask(info, np); 12926732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ret) 12936732ae5cSJean-Christophe PLAGNIOL-VILLARD return ret; 12946732ae5cSJean-Christophe PLAGNIOL-VILLARD 12956732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux); 12966732ae5cSJean-Christophe PLAGNIOL-VILLARD 12976732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(&pdev->dev, "mux-mask\n"); 12986732ae5cSJean-Christophe PLAGNIOL-VILLARD tmp = info->mux_mask; 1299a0b957f3SJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < gpio_banks; i++) { 13006732ae5cSJean-Christophe PLAGNIOL-VILLARD for (j = 0; j < info->nmux; j++, tmp++) { 13016732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]); 13026732ae5cSJean-Christophe PLAGNIOL-VILLARD } 13036732ae5cSJean-Christophe PLAGNIOL-VILLARD } 13046732ae5cSJean-Christophe PLAGNIOL-VILLARD 13056732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 13066732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 1307a86854d0SKees Cook info->functions = devm_kcalloc(&pdev->dev, 1308a86854d0SKees Cook info->nfunctions, 1309a86854d0SKees Cook sizeof(struct at91_pmx_func), 13106732ae5cSJean-Christophe PLAGNIOL-VILLARD GFP_KERNEL); 13116732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!info->functions) 13126732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENOMEM; 13136732ae5cSJean-Christophe PLAGNIOL-VILLARD 1314a86854d0SKees Cook info->groups = devm_kcalloc(&pdev->dev, 1315a86854d0SKees Cook info->ngroups, 1316a86854d0SKees Cook sizeof(struct at91_pin_group), 13176732ae5cSJean-Christophe PLAGNIOL-VILLARD GFP_KERNEL); 13186732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!info->groups) 13196732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENOMEM; 13206732ae5cSJean-Christophe PLAGNIOL-VILLARD 1321a0b957f3SJean-Christophe PLAGNIOL-VILLARD dev_dbg(&pdev->dev, "nbanks = %d\n", gpio_banks); 13226732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 13236732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 13246732ae5cSJean-Christophe PLAGNIOL-VILLARD 13256732ae5cSJean-Christophe PLAGNIOL-VILLARD i = 0; 13266732ae5cSJean-Christophe PLAGNIOL-VILLARD 13276732ae5cSJean-Christophe PLAGNIOL-VILLARD for_each_child_of_node(np, child) { 13286732ae5cSJean-Christophe PLAGNIOL-VILLARD if (of_device_is_compatible(child, gpio_compat)) 13296732ae5cSJean-Christophe PLAGNIOL-VILLARD continue; 13306732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = at91_pinctrl_parse_functions(child, info, i++); 13316732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ret) { 13326732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(&pdev->dev, "failed to parse function\n"); 1333d94b986aSJulia Lawall of_node_put(child); 13346732ae5cSJean-Christophe PLAGNIOL-VILLARD return ret; 13356732ae5cSJean-Christophe PLAGNIOL-VILLARD } 13366732ae5cSJean-Christophe PLAGNIOL-VILLARD } 13376732ae5cSJean-Christophe PLAGNIOL-VILLARD 13386732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 13396732ae5cSJean-Christophe PLAGNIOL-VILLARD } 13406732ae5cSJean-Christophe PLAGNIOL-VILLARD 1341150632b0SGreg Kroah-Hartman static int at91_pinctrl_probe(struct platform_device *pdev) 13426732ae5cSJean-Christophe PLAGNIOL-VILLARD { 13436732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_pinctrl *info; 13446732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_pin_desc *pdesc; 1345a0b957f3SJean-Christophe PLAGNIOL-VILLARD int ret, i, j, k, ngpio_chips_enabled = 0; 13466732ae5cSJean-Christophe PLAGNIOL-VILLARD 13476732ae5cSJean-Christophe PLAGNIOL-VILLARD info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); 13486732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!info) 13496732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENOMEM; 13506732ae5cSJean-Christophe PLAGNIOL-VILLARD 13516732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = at91_pinctrl_probe_dt(pdev, info); 13526732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ret) 13536732ae5cSJean-Christophe PLAGNIOL-VILLARD return ret; 13546732ae5cSJean-Christophe PLAGNIOL-VILLARD 13556732ae5cSJean-Christophe PLAGNIOL-VILLARD /* 13566732ae5cSJean-Christophe PLAGNIOL-VILLARD * We need all the GPIO drivers to probe FIRST, or we will not be able 13576732ae5cSJean-Christophe PLAGNIOL-VILLARD * to obtain references to the struct gpio_chip * for them, and we 13586732ae5cSJean-Christophe PLAGNIOL-VILLARD * need this to proceed. 13596732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 1360a0b957f3SJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < gpio_banks; i++) 1361a0b957f3SJean-Christophe PLAGNIOL-VILLARD if (gpio_chips[i]) 1362a0b957f3SJean-Christophe PLAGNIOL-VILLARD ngpio_chips_enabled++; 1363a0b957f3SJean-Christophe PLAGNIOL-VILLARD 1364a0b957f3SJean-Christophe PLAGNIOL-VILLARD if (ngpio_chips_enabled < info->nactive_banks) { 1365a0b957f3SJean-Christophe PLAGNIOL-VILLARD dev_warn(&pdev->dev, 1366a0b957f3SJean-Christophe PLAGNIOL-VILLARD "All GPIO chips are not registered yet (%d/%d)\n", 1367a0b957f3SJean-Christophe PLAGNIOL-VILLARD ngpio_chips_enabled, info->nactive_banks); 13686732ae5cSJean-Christophe PLAGNIOL-VILLARD devm_kfree(&pdev->dev, info); 13696732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EPROBE_DEFER; 13706732ae5cSJean-Christophe PLAGNIOL-VILLARD } 13716732ae5cSJean-Christophe PLAGNIOL-VILLARD 13726732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_pinctrl_desc.name = dev_name(&pdev->dev); 1373a0b957f3SJean-Christophe PLAGNIOL-VILLARD at91_pinctrl_desc.npins = gpio_banks * MAX_NB_GPIO_PER_BANK; 13746732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_pinctrl_desc.pins = pdesc = 1375a86854d0SKees Cook devm_kcalloc(&pdev->dev, 1376a86854d0SKees Cook at91_pinctrl_desc.npins, sizeof(*pdesc), 1377a86854d0SKees Cook GFP_KERNEL); 13786732ae5cSJean-Christophe PLAGNIOL-VILLARD 13796732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!at91_pinctrl_desc.pins) 13806732ae5cSJean-Christophe PLAGNIOL-VILLARD return -ENOMEM; 13816732ae5cSJean-Christophe PLAGNIOL-VILLARD 1382a0b957f3SJean-Christophe PLAGNIOL-VILLARD for (i = 0, k = 0; i < gpio_banks; i++) { 13836732ae5cSJean-Christophe PLAGNIOL-VILLARD for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) { 13846732ae5cSJean-Christophe PLAGNIOL-VILLARD pdesc->number = k; 13856732ae5cSJean-Christophe PLAGNIOL-VILLARD pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j); 13866732ae5cSJean-Christophe PLAGNIOL-VILLARD pdesc++; 13876732ae5cSJean-Christophe PLAGNIOL-VILLARD } 13886732ae5cSJean-Christophe PLAGNIOL-VILLARD } 13896732ae5cSJean-Christophe PLAGNIOL-VILLARD 13906732ae5cSJean-Christophe PLAGNIOL-VILLARD platform_set_drvdata(pdev, info); 13915c67425aSLaxman Dewangan info->pctl = devm_pinctrl_register(&pdev->dev, &at91_pinctrl_desc, 13925c67425aSLaxman Dewangan info); 13936732ae5cSJean-Christophe PLAGNIOL-VILLARD 1394323de9efSMasahiro Yamada if (IS_ERR(info->pctl)) { 13956732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n"); 1396323de9efSMasahiro Yamada return PTR_ERR(info->pctl); 13976732ae5cSJean-Christophe PLAGNIOL-VILLARD } 13986732ae5cSJean-Christophe PLAGNIOL-VILLARD 13996732ae5cSJean-Christophe PLAGNIOL-VILLARD /* We will handle a range of GPIO pins */ 1400a0b957f3SJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < gpio_banks; i++) 1401a0b957f3SJean-Christophe PLAGNIOL-VILLARD if (gpio_chips[i]) 14026732ae5cSJean-Christophe PLAGNIOL-VILLARD pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range); 14036732ae5cSJean-Christophe PLAGNIOL-VILLARD 14046732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n"); 14056732ae5cSJean-Christophe PLAGNIOL-VILLARD 14066732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 14076732ae5cSJean-Christophe PLAGNIOL-VILLARD } 14086732ae5cSJean-Christophe PLAGNIOL-VILLARD 14098af584b8SRichard Genoud static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 14108af584b8SRichard Genoud { 1411370ea611SLinus Walleij struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip); 14128af584b8SRichard Genoud void __iomem *pio = at91_gpio->regbase; 14138af584b8SRichard Genoud unsigned mask = 1 << offset; 14148af584b8SRichard Genoud u32 osr; 14158af584b8SRichard Genoud 14168af584b8SRichard Genoud osr = readl_relaxed(pio + PIO_OSR); 14178af584b8SRichard Genoud return !(osr & mask); 14188af584b8SRichard Genoud } 14198af584b8SRichard Genoud 14206732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 14216732ae5cSJean-Christophe PLAGNIOL-VILLARD { 1422370ea611SLinus Walleij struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip); 14236732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 14246732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask = 1 << offset; 14256732ae5cSJean-Christophe PLAGNIOL-VILLARD 14266732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_ODR); 14276732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 14286732ae5cSJean-Christophe PLAGNIOL-VILLARD } 14296732ae5cSJean-Christophe PLAGNIOL-VILLARD 14306732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_gpio_get(struct gpio_chip *chip, unsigned offset) 14316732ae5cSJean-Christophe PLAGNIOL-VILLARD { 1432370ea611SLinus Walleij struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip); 14336732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 14346732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask = 1 << offset; 14356732ae5cSJean-Christophe PLAGNIOL-VILLARD u32 pdsr; 14366732ae5cSJean-Christophe PLAGNIOL-VILLARD 14376732ae5cSJean-Christophe PLAGNIOL-VILLARD pdsr = readl_relaxed(pio + PIO_PDSR); 14386732ae5cSJean-Christophe PLAGNIOL-VILLARD return (pdsr & mask) != 0; 14396732ae5cSJean-Christophe PLAGNIOL-VILLARD } 14406732ae5cSJean-Christophe PLAGNIOL-VILLARD 14416732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_gpio_set(struct gpio_chip *chip, unsigned offset, 14426732ae5cSJean-Christophe PLAGNIOL-VILLARD int val) 14436732ae5cSJean-Christophe PLAGNIOL-VILLARD { 1444370ea611SLinus Walleij struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip); 14456732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 14466732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask = 1 << offset; 14476732ae5cSJean-Christophe PLAGNIOL-VILLARD 14486732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); 14496732ae5cSJean-Christophe PLAGNIOL-VILLARD } 14506732ae5cSJean-Christophe PLAGNIOL-VILLARD 14511893b2cfSAlexander Stein static void at91_gpio_set_multiple(struct gpio_chip *chip, 14521893b2cfSAlexander Stein unsigned long *mask, unsigned long *bits) 14531893b2cfSAlexander Stein { 1454370ea611SLinus Walleij struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip); 14551893b2cfSAlexander Stein void __iomem *pio = at91_gpio->regbase; 14561893b2cfSAlexander Stein 14571893b2cfSAlexander Stein #define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1)) 14581893b2cfSAlexander Stein /* Mask additionally to ngpio as not all GPIO controllers have 32 pins */ 14591893b2cfSAlexander Stein uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio); 14601893b2cfSAlexander Stein uint32_t clear_mask = (*mask & ~(*bits)) & BITS_MASK(chip->ngpio); 14611893b2cfSAlexander Stein 14621893b2cfSAlexander Stein writel_relaxed(set_mask, pio + PIO_SODR); 14631893b2cfSAlexander Stein writel_relaxed(clear_mask, pio + PIO_CODR); 14641893b2cfSAlexander Stein } 14651893b2cfSAlexander Stein 14666732ae5cSJean-Christophe PLAGNIOL-VILLARD static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 14676732ae5cSJean-Christophe PLAGNIOL-VILLARD int val) 14686732ae5cSJean-Christophe PLAGNIOL-VILLARD { 1469370ea611SLinus Walleij struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip); 14706732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 14716732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask = 1 << offset; 14726732ae5cSJean-Christophe PLAGNIOL-VILLARD 14736732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); 14746732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_OER); 14756732ae5cSJean-Christophe PLAGNIOL-VILLARD 14766732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 14776732ae5cSJean-Christophe PLAGNIOL-VILLARD } 14786732ae5cSJean-Christophe PLAGNIOL-VILLARD 14796732ae5cSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_DEBUG_FS 14806732ae5cSJean-Christophe PLAGNIOL-VILLARD static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 14816732ae5cSJean-Christophe PLAGNIOL-VILLARD { 14826732ae5cSJean-Christophe PLAGNIOL-VILLARD enum at91_mux mode; 14836732ae5cSJean-Christophe PLAGNIOL-VILLARD int i; 1484370ea611SLinus Walleij struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip); 14856732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 14866732ae5cSJean-Christophe PLAGNIOL-VILLARD 14876732ae5cSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < chip->ngpio; i++) { 148847f22716SAlexander Stein unsigned mask = pin_to_mask(i); 14896732ae5cSJean-Christophe PLAGNIOL-VILLARD const char *gpio_label; 14906732ae5cSJean-Christophe PLAGNIOL-VILLARD 14916732ae5cSJean-Christophe PLAGNIOL-VILLARD gpio_label = gpiochip_is_requested(chip, i); 14926732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!gpio_label) 14936732ae5cSJean-Christophe PLAGNIOL-VILLARD continue; 14946732ae5cSJean-Christophe PLAGNIOL-VILLARD mode = at91_gpio->ops->get_periph(pio, mask); 14956732ae5cSJean-Christophe PLAGNIOL-VILLARD seq_printf(s, "[%s] GPIO%s%d: ", 14966732ae5cSJean-Christophe PLAGNIOL-VILLARD gpio_label, chip->label, i); 14976732ae5cSJean-Christophe PLAGNIOL-VILLARD if (mode == AT91_MUX_GPIO) { 1498853b6bf0SMatthieu Crapet seq_printf(s, "[gpio] "); 1499853b6bf0SMatthieu Crapet seq_printf(s, "%s ", 1500853b6bf0SMatthieu Crapet readl_relaxed(pio + PIO_OSR) & mask ? 1501853b6bf0SMatthieu Crapet "output" : "input"); 1502853b6bf0SMatthieu Crapet seq_printf(s, "%s\n", 1503853b6bf0SMatthieu Crapet readl_relaxed(pio + PIO_PDSR) & mask ? 15046732ae5cSJean-Christophe PLAGNIOL-VILLARD "set" : "clear"); 15056732ae5cSJean-Christophe PLAGNIOL-VILLARD } else { 15066732ae5cSJean-Christophe PLAGNIOL-VILLARD seq_printf(s, "[periph %c]\n", 15076732ae5cSJean-Christophe PLAGNIOL-VILLARD mode + 'A' - 1); 15086732ae5cSJean-Christophe PLAGNIOL-VILLARD } 15096732ae5cSJean-Christophe PLAGNIOL-VILLARD } 15106732ae5cSJean-Christophe PLAGNIOL-VILLARD } 15116732ae5cSJean-Christophe PLAGNIOL-VILLARD #else 15126732ae5cSJean-Christophe PLAGNIOL-VILLARD #define at91_gpio_dbg_show NULL 15136732ae5cSJean-Christophe PLAGNIOL-VILLARD #endif 15146732ae5cSJean-Christophe PLAGNIOL-VILLARD 15156732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Several AIC controller irqs are dispatched through this GPIO handler. 15166732ae5cSJean-Christophe PLAGNIOL-VILLARD * To use any AT91_PIN_* as an externally triggered IRQ, first call 15176732ae5cSJean-Christophe PLAGNIOL-VILLARD * at91_set_gpio_input() then maybe enable its glitch filter. 15186732ae5cSJean-Christophe PLAGNIOL-VILLARD * Then just request_irq() with the pin ID; it works like any ARM IRQ 15196732ae5cSJean-Christophe PLAGNIOL-VILLARD * handler. 15206732ae5cSJean-Christophe PLAGNIOL-VILLARD * First implementation always triggers on rising and falling edges 15216732ae5cSJean-Christophe PLAGNIOL-VILLARD * whereas the newer PIO3 can be additionally configured to trigger on 15226732ae5cSJean-Christophe PLAGNIOL-VILLARD * level, edge with any polarity. 15236732ae5cSJean-Christophe PLAGNIOL-VILLARD * 15246732ae5cSJean-Christophe PLAGNIOL-VILLARD * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after 15256732ae5cSJean-Christophe PLAGNIOL-VILLARD * configuring them with at91_set_a_periph() or at91_set_b_periph(). 15266732ae5cSJean-Christophe PLAGNIOL-VILLARD * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering. 15276732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 15286732ae5cSJean-Christophe PLAGNIOL-VILLARD 15296732ae5cSJean-Christophe PLAGNIOL-VILLARD static void gpio_irq_mask(struct irq_data *d) 15306732ae5cSJean-Christophe PLAGNIOL-VILLARD { 15316732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 15326732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 15336732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask = 1 << d->hwirq; 15346732ae5cSJean-Christophe PLAGNIOL-VILLARD 15356732ae5cSJean-Christophe PLAGNIOL-VILLARD if (pio) 15366732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_IDR); 15376732ae5cSJean-Christophe PLAGNIOL-VILLARD } 15386732ae5cSJean-Christophe PLAGNIOL-VILLARD 15396732ae5cSJean-Christophe PLAGNIOL-VILLARD static void gpio_irq_unmask(struct irq_data *d) 15406732ae5cSJean-Christophe PLAGNIOL-VILLARD { 15416732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 15426732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 15436732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask = 1 << d->hwirq; 15446732ae5cSJean-Christophe PLAGNIOL-VILLARD 15456732ae5cSJean-Christophe PLAGNIOL-VILLARD if (pio) 15466732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_IER); 15476732ae5cSJean-Christophe PLAGNIOL-VILLARD } 15486732ae5cSJean-Christophe PLAGNIOL-VILLARD 15496732ae5cSJean-Christophe PLAGNIOL-VILLARD static int gpio_irq_type(struct irq_data *d, unsigned type) 15506732ae5cSJean-Christophe PLAGNIOL-VILLARD { 15516732ae5cSJean-Christophe PLAGNIOL-VILLARD switch (type) { 15526732ae5cSJean-Christophe PLAGNIOL-VILLARD case IRQ_TYPE_NONE: 15536732ae5cSJean-Christophe PLAGNIOL-VILLARD case IRQ_TYPE_EDGE_BOTH: 15546732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 15556732ae5cSJean-Christophe PLAGNIOL-VILLARD default: 15566732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 15576732ae5cSJean-Christophe PLAGNIOL-VILLARD } 15586732ae5cSJean-Christophe PLAGNIOL-VILLARD } 15596732ae5cSJean-Christophe PLAGNIOL-VILLARD 15606732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Alternate irq type for PIO3 support */ 15616732ae5cSJean-Christophe PLAGNIOL-VILLARD static int alt_gpio_irq_type(struct irq_data *d, unsigned type) 15626732ae5cSJean-Christophe PLAGNIOL-VILLARD { 15636732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 15646732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 15656732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned mask = 1 << d->hwirq; 15666732ae5cSJean-Christophe PLAGNIOL-VILLARD 15676732ae5cSJean-Christophe PLAGNIOL-VILLARD switch (type) { 15686732ae5cSJean-Christophe PLAGNIOL-VILLARD case IRQ_TYPE_EDGE_RISING: 1569c639845bSThomas Gleixner irq_set_handler_locked(d, handle_simple_irq); 15706732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_ESR); 15716732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_REHLSR); 15726732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 15736732ae5cSJean-Christophe PLAGNIOL-VILLARD case IRQ_TYPE_EDGE_FALLING: 1574c639845bSThomas Gleixner irq_set_handler_locked(d, handle_simple_irq); 15756732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_ESR); 15766732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_FELLSR); 15776732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 15786732ae5cSJean-Christophe PLAGNIOL-VILLARD case IRQ_TYPE_LEVEL_LOW: 1579c639845bSThomas Gleixner irq_set_handler_locked(d, handle_level_irq); 15806732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_LSR); 15816732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_FELLSR); 15826732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 15836732ae5cSJean-Christophe PLAGNIOL-VILLARD case IRQ_TYPE_LEVEL_HIGH: 1584c639845bSThomas Gleixner irq_set_handler_locked(d, handle_level_irq); 15856732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_LSR); 15866732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_REHLSR); 15876732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 15886732ae5cSJean-Christophe PLAGNIOL-VILLARD case IRQ_TYPE_EDGE_BOTH: 15896732ae5cSJean-Christophe PLAGNIOL-VILLARD /* 15906732ae5cSJean-Christophe PLAGNIOL-VILLARD * disable additional interrupt modes: 15916732ae5cSJean-Christophe PLAGNIOL-VILLARD * fall back to default behavior 15926732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 1593c639845bSThomas Gleixner irq_set_handler_locked(d, handle_simple_irq); 15946732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_AIMDR); 15956732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 15966732ae5cSJean-Christophe PLAGNIOL-VILLARD case IRQ_TYPE_NONE: 15976732ae5cSJean-Christophe PLAGNIOL-VILLARD default: 15981c5fb66aSLinus Walleij pr_warn("AT91: No type for GPIO irq offset %d\n", d->irq); 15996732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 16006732ae5cSJean-Christophe PLAGNIOL-VILLARD } 16016732ae5cSJean-Christophe PLAGNIOL-VILLARD 16026732ae5cSJean-Christophe PLAGNIOL-VILLARD /* enable additional interrupt modes */ 16036732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(mask, pio + PIO_AIMER); 16046732ae5cSJean-Christophe PLAGNIOL-VILLARD 16056732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 16066732ae5cSJean-Christophe PLAGNIOL-VILLARD } 16076732ae5cSJean-Christophe PLAGNIOL-VILLARD 160880cc3732SAlexander Stein static void gpio_irq_ack(struct irq_data *d) 160980cc3732SAlexander Stein { 161080cc3732SAlexander Stein /* the interrupt is already cleared before by reading ISR */ 161180cc3732SAlexander Stein } 161280cc3732SAlexander Stein 16136732ae5cSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_PM 1614647f8d94SLudovic Desroches 1615647f8d94SLudovic Desroches static u32 wakeups[MAX_GPIO_BANKS]; 1616647f8d94SLudovic Desroches static u32 backups[MAX_GPIO_BANKS]; 1617647f8d94SLudovic Desroches 16186732ae5cSJean-Christophe PLAGNIOL-VILLARD static int gpio_irq_set_wake(struct irq_data *d, unsigned state) 16196732ae5cSJean-Christophe PLAGNIOL-VILLARD { 16206732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 16216732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned bank = at91_gpio->pioc_idx; 1622647f8d94SLudovic Desroches unsigned mask = 1 << d->hwirq; 16236732ae5cSJean-Christophe PLAGNIOL-VILLARD 16246732ae5cSJean-Christophe PLAGNIOL-VILLARD if (unlikely(bank >= MAX_GPIO_BANKS)) 16256732ae5cSJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 16266732ae5cSJean-Christophe PLAGNIOL-VILLARD 1627647f8d94SLudovic Desroches if (state) 1628647f8d94SLudovic Desroches wakeups[bank] |= mask; 1629647f8d94SLudovic Desroches else 1630647f8d94SLudovic Desroches wakeups[bank] &= ~mask; 1631647f8d94SLudovic Desroches 16326732ae5cSJean-Christophe PLAGNIOL-VILLARD irq_set_irq_wake(at91_gpio->pioc_virq, state); 16336732ae5cSJean-Christophe PLAGNIOL-VILLARD 16346732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 16356732ae5cSJean-Christophe PLAGNIOL-VILLARD } 1636647f8d94SLudovic Desroches 1637647f8d94SLudovic Desroches void at91_pinctrl_gpio_suspend(void) 1638647f8d94SLudovic Desroches { 1639647f8d94SLudovic Desroches int i; 1640647f8d94SLudovic Desroches 1641647f8d94SLudovic Desroches for (i = 0; i < gpio_banks; i++) { 1642647f8d94SLudovic Desroches void __iomem *pio; 1643647f8d94SLudovic Desroches 1644647f8d94SLudovic Desroches if (!gpio_chips[i]) 1645647f8d94SLudovic Desroches continue; 1646647f8d94SLudovic Desroches 1647647f8d94SLudovic Desroches pio = gpio_chips[i]->regbase; 1648647f8d94SLudovic Desroches 1649d480239bSBen Dooks backups[i] = readl_relaxed(pio + PIO_IMR); 1650d480239bSBen Dooks writel_relaxed(backups[i], pio + PIO_IDR); 1651d480239bSBen Dooks writel_relaxed(wakeups[i], pio + PIO_IER); 1652647f8d94SLudovic Desroches 1653795f9953SBoris BREZILLON if (!wakeups[i]) 1654795f9953SBoris BREZILLON clk_disable_unprepare(gpio_chips[i]->clock); 1655795f9953SBoris BREZILLON else 1656647f8d94SLudovic Desroches printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 1657647f8d94SLudovic Desroches 'A'+i, wakeups[i]); 1658647f8d94SLudovic Desroches } 1659647f8d94SLudovic Desroches } 1660647f8d94SLudovic Desroches 1661647f8d94SLudovic Desroches void at91_pinctrl_gpio_resume(void) 1662647f8d94SLudovic Desroches { 1663647f8d94SLudovic Desroches int i; 1664647f8d94SLudovic Desroches 1665647f8d94SLudovic Desroches for (i = 0; i < gpio_banks; i++) { 1666647f8d94SLudovic Desroches void __iomem *pio; 1667647f8d94SLudovic Desroches 1668647f8d94SLudovic Desroches if (!gpio_chips[i]) 1669647f8d94SLudovic Desroches continue; 1670647f8d94SLudovic Desroches 1671647f8d94SLudovic Desroches pio = gpio_chips[i]->regbase; 1672647f8d94SLudovic Desroches 167337ef1d92SBoris BREZILLON if (!wakeups[i]) 167437ef1d92SBoris BREZILLON clk_prepare_enable(gpio_chips[i]->clock); 1675647f8d94SLudovic Desroches 1676d480239bSBen Dooks writel_relaxed(wakeups[i], pio + PIO_IDR); 1677d480239bSBen Dooks writel_relaxed(backups[i], pio + PIO_IER); 1678647f8d94SLudovic Desroches } 1679647f8d94SLudovic Desroches } 1680647f8d94SLudovic Desroches 16816732ae5cSJean-Christophe PLAGNIOL-VILLARD #else 16826732ae5cSJean-Christophe PLAGNIOL-VILLARD #define gpio_irq_set_wake NULL 1683647f8d94SLudovic Desroches #endif /* CONFIG_PM */ 16846732ae5cSJean-Christophe PLAGNIOL-VILLARD 1685bd0b9ac4SThomas Gleixner static void gpio_irq_handler(struct irq_desc *desc) 16866732ae5cSJean-Christophe PLAGNIOL-VILLARD { 16875663bb27SJiang Liu struct irq_chip *chip = irq_desc_get_chip(desc); 168880cc3732SAlexander Stein struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc); 1689370ea611SLinus Walleij struct at91_gpio_chip *at91_gpio = gpiochip_get_data(gpio_chip); 16906732ae5cSJean-Christophe PLAGNIOL-VILLARD void __iomem *pio = at91_gpio->regbase; 16916732ae5cSJean-Christophe PLAGNIOL-VILLARD unsigned long isr; 16926732ae5cSJean-Christophe PLAGNIOL-VILLARD int n; 16936732ae5cSJean-Christophe PLAGNIOL-VILLARD 16946732ae5cSJean-Christophe PLAGNIOL-VILLARD chained_irq_enter(chip, desc); 16956732ae5cSJean-Christophe PLAGNIOL-VILLARD for (;;) { 16966732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Reading ISR acks pending (edge triggered) GPIO interrupts. 1697c2eb9e7fSAlexandre Belloni * When there are none pending, we're finished unless we need 16986732ae5cSJean-Christophe PLAGNIOL-VILLARD * to process multiple banks (like ID_PIOCDE on sam9263). 16996732ae5cSJean-Christophe PLAGNIOL-VILLARD */ 17006732ae5cSJean-Christophe PLAGNIOL-VILLARD isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR); 17016732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!isr) { 17026732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!at91_gpio->next) 17036732ae5cSJean-Christophe PLAGNIOL-VILLARD break; 17046732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_gpio = at91_gpio->next; 17056732ae5cSJean-Christophe PLAGNIOL-VILLARD pio = at91_gpio->regbase; 1706cccb0c3eSAlexander Stein gpio_chip = &at91_gpio->chip; 17076732ae5cSJean-Christophe PLAGNIOL-VILLARD continue; 17086732ae5cSJean-Christophe PLAGNIOL-VILLARD } 17096732ae5cSJean-Christophe PLAGNIOL-VILLARD 171005daa16aSWei Yongjun for_each_set_bit(n, &isr, BITS_PER_LONG) { 171180cc3732SAlexander Stein generic_handle_irq(irq_find_mapping( 1712f0fbe7bcSThierry Reding gpio_chip->irq.domain, n)); 17136732ae5cSJean-Christophe PLAGNIOL-VILLARD } 17146732ae5cSJean-Christophe PLAGNIOL-VILLARD } 17156732ae5cSJean-Christophe PLAGNIOL-VILLARD chained_irq_exit(chip, desc); 17166732ae5cSJean-Christophe PLAGNIOL-VILLARD /* now it may re-trigger */ 17176732ae5cSJean-Christophe PLAGNIOL-VILLARD } 17186732ae5cSJean-Christophe PLAGNIOL-VILLARD 1719834e1678SPramod Gurav static int at91_gpio_of_irq_setup(struct platform_device *pdev, 17206732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_gpio) 17216732ae5cSJean-Christophe PLAGNIOL-VILLARD { 1722a0b957f3SJean-Christophe PLAGNIOL-VILLARD struct gpio_chip *gpiochip_prev = NULL; 1723cccb0c3eSAlexander Stein struct at91_gpio_chip *prev = NULL; 17246732ae5cSJean-Christophe PLAGNIOL-VILLARD struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq); 17250c3dfa17SLudovic Desroches struct irq_chip *gpio_irqchip; 1726a0b957f3SJean-Christophe PLAGNIOL-VILLARD int ret, i; 17276732ae5cSJean-Christophe PLAGNIOL-VILLARD 17280c3dfa17SLudovic Desroches gpio_irqchip = devm_kzalloc(&pdev->dev, sizeof(*gpio_irqchip), GFP_KERNEL); 17290c3dfa17SLudovic Desroches if (!gpio_irqchip) 17300c3dfa17SLudovic Desroches return -ENOMEM; 17310c3dfa17SLudovic Desroches 17326732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_gpio->pioc_hwirq = irqd_to_hwirq(d); 17336732ae5cSJean-Christophe PLAGNIOL-VILLARD 17340c3dfa17SLudovic Desroches gpio_irqchip->name = "GPIO"; 17350c3dfa17SLudovic Desroches gpio_irqchip->irq_ack = gpio_irq_ack; 17360c3dfa17SLudovic Desroches gpio_irqchip->irq_disable = gpio_irq_mask; 17370c3dfa17SLudovic Desroches gpio_irqchip->irq_mask = gpio_irq_mask; 17380c3dfa17SLudovic Desroches gpio_irqchip->irq_unmask = gpio_irq_unmask; 17390c3dfa17SLudovic Desroches gpio_irqchip->irq_set_wake = gpio_irq_set_wake, 17400c3dfa17SLudovic Desroches gpio_irqchip->irq_set_type = at91_gpio->ops->irq_type; 17416732ae5cSJean-Christophe PLAGNIOL-VILLARD 17426732ae5cSJean-Christophe PLAGNIOL-VILLARD /* Disable irqs of this PIO controller */ 17436732ae5cSJean-Christophe PLAGNIOL-VILLARD writel_relaxed(~0, at91_gpio->regbase + PIO_IDR); 17446732ae5cSJean-Christophe PLAGNIOL-VILLARD 174580cc3732SAlexander Stein /* 174680cc3732SAlexander Stein * Let the generic code handle this edge IRQ, the the chained 174780cc3732SAlexander Stein * handler will perform the actual work of handling the parent 174880cc3732SAlexander Stein * interrupt. 174980cc3732SAlexander Stein */ 175080cc3732SAlexander Stein ret = gpiochip_irqchip_add(&at91_gpio->chip, 17510c3dfa17SLudovic Desroches gpio_irqchip, 175280cc3732SAlexander Stein 0, 175380cc3732SAlexander Stein handle_edge_irq, 17545803348cSMarc Zyngier IRQ_TYPE_NONE); 1755834e1678SPramod Gurav if (ret) { 1756834e1678SPramod Gurav dev_err(&pdev->dev, "at91_gpio.%d: Couldn't add irqchip to gpiochip.\n", 17576732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_gpio->pioc_idx); 1758834e1678SPramod Gurav return ret; 1759834e1678SPramod Gurav } 17606732ae5cSJean-Christophe PLAGNIOL-VILLARD 1761cccb0c3eSAlexander Stein /* The top level handler handles one bank of GPIOs, except 1762cccb0c3eSAlexander Stein * on some SoC it can handle up to three... 1763cccb0c3eSAlexander Stein * We only set up the handler for the first of the list. 1764cccb0c3eSAlexander Stein */ 1765a0b957f3SJean-Christophe PLAGNIOL-VILLARD gpiochip_prev = irq_get_handler_data(at91_gpio->pioc_virq); 1766a0b957f3SJean-Christophe PLAGNIOL-VILLARD if (!gpiochip_prev) { 176780cc3732SAlexander Stein /* Then register the chain on the parent IRQ */ 176880cc3732SAlexander Stein gpiochip_set_chained_irqchip(&at91_gpio->chip, 17690c3dfa17SLudovic Desroches gpio_irqchip, 177080cc3732SAlexander Stein at91_gpio->pioc_virq, 177180cc3732SAlexander Stein gpio_irq_handler); 17726732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 17736732ae5cSJean-Christophe PLAGNIOL-VILLARD } 17746732ae5cSJean-Christophe PLAGNIOL-VILLARD 1775370ea611SLinus Walleij prev = gpiochip_get_data(gpiochip_prev); 1776a0b957f3SJean-Christophe PLAGNIOL-VILLARD 1777a0b957f3SJean-Christophe PLAGNIOL-VILLARD /* we can only have 2 banks before */ 1778a0b957f3SJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < 2; i++) { 1779a0b957f3SJean-Christophe PLAGNIOL-VILLARD if (prev->next) { 1780a0b957f3SJean-Christophe PLAGNIOL-VILLARD prev = prev->next; 1781a0b957f3SJean-Christophe PLAGNIOL-VILLARD } else { 1782a0b957f3SJean-Christophe PLAGNIOL-VILLARD prev->next = at91_gpio; 1783a0b957f3SJean-Christophe PLAGNIOL-VILLARD return 0; 1784a0b957f3SJean-Christophe PLAGNIOL-VILLARD } 1785a0b957f3SJean-Christophe PLAGNIOL-VILLARD } 1786a0b957f3SJean-Christophe PLAGNIOL-VILLARD 1787a0b957f3SJean-Christophe PLAGNIOL-VILLARD return -EINVAL; 1788a0b957f3SJean-Christophe PLAGNIOL-VILLARD } 1789a0b957f3SJean-Christophe PLAGNIOL-VILLARD 17906732ae5cSJean-Christophe PLAGNIOL-VILLARD /* This structure is replicated for each GPIO block allocated at probe time */ 1791234b6513SAlexander Stein static const struct gpio_chip at91_gpio_template = { 179298c85d58SJonas Gorski .request = gpiochip_generic_request, 179398c85d58SJonas Gorski .free = gpiochip_generic_free, 17948af584b8SRichard Genoud .get_direction = at91_gpio_get_direction, 17956732ae5cSJean-Christophe PLAGNIOL-VILLARD .direction_input = at91_gpio_direction_input, 17966732ae5cSJean-Christophe PLAGNIOL-VILLARD .get = at91_gpio_get, 17976732ae5cSJean-Christophe PLAGNIOL-VILLARD .direction_output = at91_gpio_direction_output, 17986732ae5cSJean-Christophe PLAGNIOL-VILLARD .set = at91_gpio_set, 17991893b2cfSAlexander Stein .set_multiple = at91_gpio_set_multiple, 18006732ae5cSJean-Christophe PLAGNIOL-VILLARD .dbg_show = at91_gpio_dbg_show, 18019fb1f39eSLinus Walleij .can_sleep = false, 18026732ae5cSJean-Christophe PLAGNIOL-VILLARD .ngpio = MAX_NB_GPIO_PER_BANK, 18036732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 18046732ae5cSJean-Christophe PLAGNIOL-VILLARD 1805baa9946eSFabian Frederick static const struct of_device_id at91_gpio_of_match[] = { 18066732ae5cSJean-Christophe PLAGNIOL-VILLARD { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, }, 18076732ae5cSJean-Christophe PLAGNIOL-VILLARD { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops }, 1808a2fcb1ceSClaudiu Beznea { .compatible = "microchip,sam9x60-gpio", .data = &sam9x60_ops }, 18096732ae5cSJean-Christophe PLAGNIOL-VILLARD { /* sentinel */ } 18106732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 18116732ae5cSJean-Christophe PLAGNIOL-VILLARD 1812150632b0SGreg Kroah-Hartman static int at91_gpio_probe(struct platform_device *pdev) 18136732ae5cSJean-Christophe PLAGNIOL-VILLARD { 18146732ae5cSJean-Christophe PLAGNIOL-VILLARD struct device_node *np = pdev->dev.of_node; 18156732ae5cSJean-Christophe PLAGNIOL-VILLARD struct resource *res; 18166732ae5cSJean-Christophe PLAGNIOL-VILLARD struct at91_gpio_chip *at91_chip = NULL; 18176732ae5cSJean-Christophe PLAGNIOL-VILLARD struct gpio_chip *chip; 18186732ae5cSJean-Christophe PLAGNIOL-VILLARD struct pinctrl_gpio_range *range; 18196732ae5cSJean-Christophe PLAGNIOL-VILLARD int ret = 0; 182032b01a36SJean-Christophe PLAGNIOL-VILLARD int irq, i; 18216732ae5cSJean-Christophe PLAGNIOL-VILLARD int alias_idx = of_alias_get_id(np, "gpio"); 18226732ae5cSJean-Christophe PLAGNIOL-VILLARD uint32_t ngpio; 182332b01a36SJean-Christophe PLAGNIOL-VILLARD char **names; 18246732ae5cSJean-Christophe PLAGNIOL-VILLARD 18256732ae5cSJean-Christophe PLAGNIOL-VILLARD BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips)); 18266732ae5cSJean-Christophe PLAGNIOL-VILLARD if (gpio_chips[alias_idx]) { 18276732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = -EBUSY; 18286732ae5cSJean-Christophe PLAGNIOL-VILLARD goto err; 18296732ae5cSJean-Christophe PLAGNIOL-VILLARD } 18306732ae5cSJean-Christophe PLAGNIOL-VILLARD 18316732ae5cSJean-Christophe PLAGNIOL-VILLARD irq = platform_get_irq(pdev, 0); 18326732ae5cSJean-Christophe PLAGNIOL-VILLARD if (irq < 0) { 18336732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = irq; 18346732ae5cSJean-Christophe PLAGNIOL-VILLARD goto err; 18356732ae5cSJean-Christophe PLAGNIOL-VILLARD } 18366732ae5cSJean-Christophe PLAGNIOL-VILLARD 18376732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL); 18386732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!at91_chip) { 18396732ae5cSJean-Christophe PLAGNIOL-VILLARD ret = -ENOMEM; 18406732ae5cSJean-Christophe PLAGNIOL-VILLARD goto err; 18416732ae5cSJean-Christophe PLAGNIOL-VILLARD } 18426732ae5cSJean-Christophe PLAGNIOL-VILLARD 1843f50b9e12SWolfram Sang res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 18449e0c1fb2SThierry Reding at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res); 18459e0c1fb2SThierry Reding if (IS_ERR(at91_chip->regbase)) { 18469e0c1fb2SThierry Reding ret = PTR_ERR(at91_chip->regbase); 18476732ae5cSJean-Christophe PLAGNIOL-VILLARD goto err; 18486732ae5cSJean-Christophe PLAGNIOL-VILLARD } 18496732ae5cSJean-Christophe PLAGNIOL-VILLARD 1850dffa9123SJean-Christophe PLAGNIOL-VILLARD at91_chip->ops = (struct at91_pinctrl_mux_ops *) 18516732ae5cSJean-Christophe PLAGNIOL-VILLARD of_match_device(at91_gpio_of_match, &pdev->dev)->data; 18526732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_chip->pioc_virq = irq; 18536732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_chip->pioc_idx = alias_idx; 18546732ae5cSJean-Christophe PLAGNIOL-VILLARD 185502b837ffSPramod Gurav at91_chip->clock = devm_clk_get(&pdev->dev, NULL); 18566732ae5cSJean-Christophe PLAGNIOL-VILLARD if (IS_ERR(at91_chip->clock)) { 18576732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(&pdev->dev, "failed to get clock, ignoring.\n"); 185870e41974SPramod Gurav ret = PTR_ERR(at91_chip->clock); 18596732ae5cSJean-Christophe PLAGNIOL-VILLARD goto err; 18606732ae5cSJean-Christophe PLAGNIOL-VILLARD } 18616732ae5cSJean-Christophe PLAGNIOL-VILLARD 18627d3a3fe6SAlexander Stein ret = clk_prepare_enable(at91_chip->clock); 186370e41974SPramod Gurav if (ret) { 18647d3a3fe6SAlexander Stein dev_err(&pdev->dev, "failed to prepare and enable clock, ignoring.\n"); 186570e41974SPramod Gurav goto clk_enable_err; 18666732ae5cSJean-Christophe PLAGNIOL-VILLARD } 18676732ae5cSJean-Christophe PLAGNIOL-VILLARD 18686732ae5cSJean-Christophe PLAGNIOL-VILLARD at91_chip->chip = at91_gpio_template; 18696732ae5cSJean-Christophe PLAGNIOL-VILLARD 18706732ae5cSJean-Christophe PLAGNIOL-VILLARD chip = &at91_chip->chip; 18716732ae5cSJean-Christophe PLAGNIOL-VILLARD chip->of_node = np; 18726732ae5cSJean-Christophe PLAGNIOL-VILLARD chip->label = dev_name(&pdev->dev); 187358383c78SLinus Walleij chip->parent = &pdev->dev; 18746732ae5cSJean-Christophe PLAGNIOL-VILLARD chip->owner = THIS_MODULE; 18756732ae5cSJean-Christophe PLAGNIOL-VILLARD chip->base = alias_idx * MAX_NB_GPIO_PER_BANK; 18766732ae5cSJean-Christophe PLAGNIOL-VILLARD 18776732ae5cSJean-Christophe PLAGNIOL-VILLARD if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) { 18786732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ngpio >= MAX_NB_GPIO_PER_BANK) 18796732ae5cSJean-Christophe PLAGNIOL-VILLARD pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n", 18806732ae5cSJean-Christophe PLAGNIOL-VILLARD alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK); 18816732ae5cSJean-Christophe PLAGNIOL-VILLARD else 18826732ae5cSJean-Christophe PLAGNIOL-VILLARD chip->ngpio = ngpio; 18836732ae5cSJean-Christophe PLAGNIOL-VILLARD } 18846732ae5cSJean-Christophe PLAGNIOL-VILLARD 1885a86854d0SKees Cook names = devm_kcalloc(&pdev->dev, chip->ngpio, sizeof(char *), 18863c93600dSSachin Kamat GFP_KERNEL); 188732b01a36SJean-Christophe PLAGNIOL-VILLARD 188832b01a36SJean-Christophe PLAGNIOL-VILLARD if (!names) { 188932b01a36SJean-Christophe PLAGNIOL-VILLARD ret = -ENOMEM; 189070e41974SPramod Gurav goto clk_enable_err; 189132b01a36SJean-Christophe PLAGNIOL-VILLARD } 189232b01a36SJean-Christophe PLAGNIOL-VILLARD 189332b01a36SJean-Christophe PLAGNIOL-VILLARD for (i = 0; i < chip->ngpio; i++) 189432b01a36SJean-Christophe PLAGNIOL-VILLARD names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i); 189532b01a36SJean-Christophe PLAGNIOL-VILLARD 189632b01a36SJean-Christophe PLAGNIOL-VILLARD chip->names = (const char *const *)names; 189732b01a36SJean-Christophe PLAGNIOL-VILLARD 18986732ae5cSJean-Christophe PLAGNIOL-VILLARD range = &at91_chip->range; 18996732ae5cSJean-Christophe PLAGNIOL-VILLARD range->name = chip->label; 19006732ae5cSJean-Christophe PLAGNIOL-VILLARD range->id = alias_idx; 19016732ae5cSJean-Christophe PLAGNIOL-VILLARD range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK; 19026732ae5cSJean-Christophe PLAGNIOL-VILLARD 19036732ae5cSJean-Christophe PLAGNIOL-VILLARD range->npins = chip->ngpio; 19046732ae5cSJean-Christophe PLAGNIOL-VILLARD range->gc = chip; 19056732ae5cSJean-Christophe PLAGNIOL-VILLARD 1906370ea611SLinus Walleij ret = gpiochip_add_data(chip, at91_chip); 19076732ae5cSJean-Christophe PLAGNIOL-VILLARD if (ret) 190870e41974SPramod Gurav goto gpiochip_add_err; 19096732ae5cSJean-Christophe PLAGNIOL-VILLARD 19106732ae5cSJean-Christophe PLAGNIOL-VILLARD gpio_chips[alias_idx] = at91_chip; 19116732ae5cSJean-Christophe PLAGNIOL-VILLARD gpio_banks = max(gpio_banks, alias_idx + 1); 19126732ae5cSJean-Christophe PLAGNIOL-VILLARD 1913834e1678SPramod Gurav ret = at91_gpio_of_irq_setup(pdev, at91_chip); 1914834e1678SPramod Gurav if (ret) 1915834e1678SPramod Gurav goto irq_setup_err; 19166732ae5cSJean-Christophe PLAGNIOL-VILLARD 19176732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase); 19186732ae5cSJean-Christophe PLAGNIOL-VILLARD 19196732ae5cSJean-Christophe PLAGNIOL-VILLARD return 0; 19206732ae5cSJean-Christophe PLAGNIOL-VILLARD 1921834e1678SPramod Gurav irq_setup_err: 1922834e1678SPramod Gurav gpiochip_remove(chip); 192370e41974SPramod Gurav gpiochip_add_err: 192470e41974SPramod Gurav clk_enable_err: 19257d3a3fe6SAlexander Stein clk_disable_unprepare(at91_chip->clock); 19266732ae5cSJean-Christophe PLAGNIOL-VILLARD err: 19276732ae5cSJean-Christophe PLAGNIOL-VILLARD dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx); 19286732ae5cSJean-Christophe PLAGNIOL-VILLARD 19296732ae5cSJean-Christophe PLAGNIOL-VILLARD return ret; 19306732ae5cSJean-Christophe PLAGNIOL-VILLARD } 19316732ae5cSJean-Christophe PLAGNIOL-VILLARD 19326732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct platform_driver at91_gpio_driver = { 19336732ae5cSJean-Christophe PLAGNIOL-VILLARD .driver = { 19346732ae5cSJean-Christophe PLAGNIOL-VILLARD .name = "gpio-at91", 1935606fca94SSachin Kamat .of_match_table = at91_gpio_of_match, 19366732ae5cSJean-Christophe PLAGNIOL-VILLARD }, 19376732ae5cSJean-Christophe PLAGNIOL-VILLARD .probe = at91_gpio_probe, 19386732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 19396732ae5cSJean-Christophe PLAGNIOL-VILLARD 19406732ae5cSJean-Christophe PLAGNIOL-VILLARD static struct platform_driver at91_pinctrl_driver = { 19416732ae5cSJean-Christophe PLAGNIOL-VILLARD .driver = { 19426732ae5cSJean-Christophe PLAGNIOL-VILLARD .name = "pinctrl-at91", 1943606fca94SSachin Kamat .of_match_table = at91_pinctrl_of_match, 19446732ae5cSJean-Christophe PLAGNIOL-VILLARD }, 19456732ae5cSJean-Christophe PLAGNIOL-VILLARD .probe = at91_pinctrl_probe, 19466732ae5cSJean-Christophe PLAGNIOL-VILLARD }; 19476732ae5cSJean-Christophe PLAGNIOL-VILLARD 1948bab7f5a4SThierry Reding static struct platform_driver * const drivers[] = { 1949bab7f5a4SThierry Reding &at91_gpio_driver, 1950bab7f5a4SThierry Reding &at91_pinctrl_driver, 1951bab7f5a4SThierry Reding }; 1952bab7f5a4SThierry Reding 19536732ae5cSJean-Christophe PLAGNIOL-VILLARD static int __init at91_pinctrl_init(void) 19546732ae5cSJean-Christophe PLAGNIOL-VILLARD { 1955bab7f5a4SThierry Reding return platform_register_drivers(drivers, ARRAY_SIZE(drivers)); 19566732ae5cSJean-Christophe PLAGNIOL-VILLARD } 19576732ae5cSJean-Christophe PLAGNIOL-VILLARD arch_initcall(at91_pinctrl_init); 1958