1 /* 2 * Driver for the Atmel PIO4 controller 3 * 4 * Copyright (C) 2015 Atmel, 5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 6 * 7 * This software is licensed under the terms of the GNU General Public 8 * License version 2, as published by the Free Software Foundation, and 9 * may be copied, distributed, and modified under those terms. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include <dt-bindings/pinctrl/at91.h> 18 #include <linux/clk.h> 19 #include <linux/gpio/driver.h> 20 /* FIXME: needed for gpio_to_irq(), get rid of this */ 21 #include <linux/gpio.h> 22 #include <linux/interrupt.h> 23 #include <linux/io.h> 24 #include <linux/init.h> 25 #include <linux/of.h> 26 #include <linux/platform_device.h> 27 #include <linux/pinctrl/pinconf.h> 28 #include <linux/pinctrl/pinconf-generic.h> 29 #include <linux/pinctrl/pinctrl.h> 30 #include <linux/pinctrl/pinmux.h> 31 #include <linux/slab.h> 32 #include "core.h" 33 #include "pinconf.h" 34 #include "pinctrl-utils.h" 35 36 /* 37 * Warning: 38 * In order to not introduce confusion between Atmel PIO groups and pinctrl 39 * framework groups, Atmel PIO groups will be called banks, line is kept to 40 * designed the pin id into this bank. 41 */ 42 43 #define ATMEL_PIO_MSKR 0x0000 44 #define ATMEL_PIO_CFGR 0x0004 45 #define ATMEL_PIO_CFGR_FUNC_MASK GENMASK(2, 0) 46 #define ATMEL_PIO_DIR_MASK BIT(8) 47 #define ATMEL_PIO_PUEN_MASK BIT(9) 48 #define ATMEL_PIO_PDEN_MASK BIT(10) 49 #define ATMEL_PIO_IFEN_MASK BIT(12) 50 #define ATMEL_PIO_IFSCEN_MASK BIT(13) 51 #define ATMEL_PIO_OPD_MASK BIT(14) 52 #define ATMEL_PIO_SCHMITT_MASK BIT(15) 53 #define ATMEL_PIO_DRVSTR_MASK GENMASK(17, 16) 54 #define ATMEL_PIO_DRVSTR_OFFSET 16 55 #define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24) 56 #define ATMEL_PIO_CFGR_EVTSEL_FALLING (0 << 24) 57 #define ATMEL_PIO_CFGR_EVTSEL_RISING (1 << 24) 58 #define ATMEL_PIO_CFGR_EVTSEL_BOTH (2 << 24) 59 #define ATMEL_PIO_CFGR_EVTSEL_LOW (3 << 24) 60 #define ATMEL_PIO_CFGR_EVTSEL_HIGH (4 << 24) 61 #define ATMEL_PIO_PDSR 0x0008 62 #define ATMEL_PIO_LOCKSR 0x000C 63 #define ATMEL_PIO_SODR 0x0010 64 #define ATMEL_PIO_CODR 0x0014 65 #define ATMEL_PIO_ODSR 0x0018 66 #define ATMEL_PIO_IER 0x0020 67 #define ATMEL_PIO_IDR 0x0024 68 #define ATMEL_PIO_IMR 0x0028 69 #define ATMEL_PIO_ISR 0x002C 70 #define ATMEL_PIO_IOFR 0x003C 71 72 #define ATMEL_PIO_NPINS_PER_BANK 32 73 #define ATMEL_PIO_BANK(pin_id) (pin_id / ATMEL_PIO_NPINS_PER_BANK) 74 #define ATMEL_PIO_LINE(pin_id) (pin_id % ATMEL_PIO_NPINS_PER_BANK) 75 #define ATMEL_PIO_BANK_OFFSET 0x40 76 77 #define ATMEL_GET_PIN_NO(pinfunc) ((pinfunc) & 0xff) 78 #define ATMEL_GET_PIN_FUNC(pinfunc) ((pinfunc >> 16) & 0xf) 79 #define ATMEL_GET_PIN_IOSET(pinfunc) ((pinfunc >> 20) & 0xf) 80 81 /* Custom pinconf parameters */ 82 #define ATMEL_PIN_CONFIG_DRIVE_STRENGTH (PIN_CONFIG_END + 1) 83 84 struct atmel_pioctrl_data { 85 unsigned nbanks; 86 }; 87 88 struct atmel_group { 89 const char *name; 90 u32 pin; 91 }; 92 93 struct atmel_pin { 94 unsigned pin_id; 95 unsigned mux; 96 unsigned ioset; 97 unsigned bank; 98 unsigned line; 99 const char *device; 100 }; 101 102 /** 103 * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio) 104 * @reg_base: base address of the controller. 105 * @clk: clock of the controller. 106 * @nbanks: number of PIO groups, it can vary depending on the SoC. 107 * @pinctrl_dev: pinctrl device registered. 108 * @groups: groups table to provide group name and pin in the group to pinctrl. 109 * @group_names: group names table to provide all the group/pin names to 110 * pinctrl or gpio. 111 * @pins: pins table used for both pinctrl and gpio. pin_id, bank and line 112 * fields are set at probe time. Other ones are set when parsing dt 113 * pinctrl. 114 * @npins: number of pins. 115 * @gpio_chip: gpio chip registered. 116 * @irq_domain: irq domain for the gpio controller. 117 * @irqs: table containing the hw irq number of the bank. The index of the 118 * table is the bank id. 119 * @dev: device entry for the Atmel PIO controller. 120 * @node: node of the Atmel PIO controller. 121 */ 122 struct atmel_pioctrl { 123 void __iomem *reg_base; 124 struct clk *clk; 125 unsigned nbanks; 126 struct pinctrl_dev *pinctrl_dev; 127 struct atmel_group *groups; 128 const char * const *group_names; 129 struct atmel_pin **pins; 130 unsigned npins; 131 struct gpio_chip *gpio_chip; 132 struct irq_domain *irq_domain; 133 int *irqs; 134 unsigned *pm_wakeup_sources; 135 struct { 136 u32 imr; 137 u32 odsr; 138 u32 cfgr[ATMEL_PIO_NPINS_PER_BANK]; 139 } *pm_suspend_backup; 140 struct device *dev; 141 struct device_node *node; 142 }; 143 144 static const char * const atmel_functions[] = { 145 "GPIO", "A", "B", "C", "D", "E", "F", "G" 146 }; 147 148 static const struct pinconf_generic_params atmel_custom_bindings[] = { 149 {"atmel,drive-strength", ATMEL_PIN_CONFIG_DRIVE_STRENGTH, 0}, 150 }; 151 152 /* --- GPIO --- */ 153 static unsigned int atmel_gpio_read(struct atmel_pioctrl *atmel_pioctrl, 154 unsigned int bank, unsigned int reg) 155 { 156 return readl_relaxed(atmel_pioctrl->reg_base 157 + ATMEL_PIO_BANK_OFFSET * bank + reg); 158 } 159 160 static void atmel_gpio_write(struct atmel_pioctrl *atmel_pioctrl, 161 unsigned int bank, unsigned int reg, 162 unsigned int val) 163 { 164 writel_relaxed(val, atmel_pioctrl->reg_base 165 + ATMEL_PIO_BANK_OFFSET * bank + reg); 166 } 167 168 static void atmel_gpio_irq_ack(struct irq_data *d) 169 { 170 /* 171 * Nothing to do, interrupt is cleared when reading the status 172 * register. 173 */ 174 } 175 176 static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned type) 177 { 178 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); 179 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; 180 unsigned reg; 181 182 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, 183 BIT(pin->line)); 184 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); 185 reg &= (~ATMEL_PIO_CFGR_EVTSEL_MASK); 186 187 switch (type) { 188 case IRQ_TYPE_EDGE_RISING: 189 irq_set_handler_locked(d, handle_edge_irq); 190 reg |= ATMEL_PIO_CFGR_EVTSEL_RISING; 191 break; 192 case IRQ_TYPE_EDGE_FALLING: 193 irq_set_handler_locked(d, handle_edge_irq); 194 reg |= ATMEL_PIO_CFGR_EVTSEL_FALLING; 195 break; 196 case IRQ_TYPE_EDGE_BOTH: 197 irq_set_handler_locked(d, handle_edge_irq); 198 reg |= ATMEL_PIO_CFGR_EVTSEL_BOTH; 199 break; 200 case IRQ_TYPE_LEVEL_LOW: 201 irq_set_handler_locked(d, handle_level_irq); 202 reg |= ATMEL_PIO_CFGR_EVTSEL_LOW; 203 break; 204 case IRQ_TYPE_LEVEL_HIGH: 205 irq_set_handler_locked(d, handle_level_irq); 206 reg |= ATMEL_PIO_CFGR_EVTSEL_HIGH; 207 break; 208 case IRQ_TYPE_NONE: 209 default: 210 return -EINVAL; 211 } 212 213 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); 214 215 return 0; 216 } 217 218 static void atmel_gpio_irq_mask(struct irq_data *d) 219 { 220 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); 221 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; 222 223 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR, 224 BIT(pin->line)); 225 } 226 227 static void atmel_gpio_irq_unmask(struct irq_data *d) 228 { 229 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); 230 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; 231 232 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IER, 233 BIT(pin->line)); 234 } 235 236 #ifdef CONFIG_PM_SLEEP 237 238 static int atmel_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 239 { 240 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); 241 int bank = ATMEL_PIO_BANK(d->hwirq); 242 int line = ATMEL_PIO_LINE(d->hwirq); 243 244 /* The gpio controller has one interrupt line per bank. */ 245 irq_set_irq_wake(atmel_pioctrl->irqs[bank], on); 246 247 if (on) 248 atmel_pioctrl->pm_wakeup_sources[bank] |= BIT(line); 249 else 250 atmel_pioctrl->pm_wakeup_sources[bank] &= ~(BIT(line)); 251 252 return 0; 253 } 254 #else 255 #define atmel_gpio_irq_set_wake NULL 256 #endif /* CONFIG_PM_SLEEP */ 257 258 static struct irq_chip atmel_gpio_irq_chip = { 259 .name = "GPIO", 260 .irq_ack = atmel_gpio_irq_ack, 261 .irq_mask = atmel_gpio_irq_mask, 262 .irq_unmask = atmel_gpio_irq_unmask, 263 .irq_set_type = atmel_gpio_irq_set_type, 264 .irq_set_wake = atmel_gpio_irq_set_wake, 265 }; 266 267 static void atmel_gpio_irq_handler(struct irq_desc *desc) 268 { 269 unsigned int irq = irq_desc_get_irq(desc); 270 struct atmel_pioctrl *atmel_pioctrl = irq_desc_get_handler_data(desc); 271 struct irq_chip *chip = irq_desc_get_chip(desc); 272 unsigned long isr; 273 int n, bank = -1; 274 275 /* Find from which bank is the irq received. */ 276 for (n = 0; n < atmel_pioctrl->nbanks; n++) { 277 if (atmel_pioctrl->irqs[n] == irq) { 278 bank = n; 279 break; 280 } 281 } 282 283 if (bank < 0) { 284 dev_err(atmel_pioctrl->dev, 285 "no bank associated to irq %u\n", irq); 286 return; 287 } 288 289 chained_irq_enter(chip, desc); 290 291 for (;;) { 292 isr = (unsigned long)atmel_gpio_read(atmel_pioctrl, bank, 293 ATMEL_PIO_ISR); 294 isr &= (unsigned long)atmel_gpio_read(atmel_pioctrl, bank, 295 ATMEL_PIO_IMR); 296 if (!isr) 297 break; 298 299 for_each_set_bit(n, &isr, BITS_PER_LONG) 300 generic_handle_irq(gpio_to_irq(bank * 301 ATMEL_PIO_NPINS_PER_BANK + n)); 302 } 303 304 chained_irq_exit(chip, desc); 305 } 306 307 static int atmel_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 308 { 309 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); 310 struct atmel_pin *pin = atmel_pioctrl->pins[offset]; 311 unsigned reg; 312 313 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, 314 BIT(pin->line)); 315 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); 316 reg &= ~ATMEL_PIO_DIR_MASK; 317 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); 318 319 return 0; 320 } 321 322 static int atmel_gpio_get(struct gpio_chip *chip, unsigned offset) 323 { 324 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); 325 struct atmel_pin *pin = atmel_pioctrl->pins[offset]; 326 unsigned reg; 327 328 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR); 329 330 return !!(reg & BIT(pin->line)); 331 } 332 333 static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 334 int value) 335 { 336 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); 337 struct atmel_pin *pin = atmel_pioctrl->pins[offset]; 338 unsigned reg; 339 340 atmel_gpio_write(atmel_pioctrl, pin->bank, 341 value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR, 342 BIT(pin->line)); 343 344 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, 345 BIT(pin->line)); 346 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); 347 reg |= ATMEL_PIO_DIR_MASK; 348 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); 349 350 return 0; 351 } 352 353 static void atmel_gpio_set(struct gpio_chip *chip, unsigned offset, int val) 354 { 355 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); 356 struct atmel_pin *pin = atmel_pioctrl->pins[offset]; 357 358 atmel_gpio_write(atmel_pioctrl, pin->bank, 359 val ? ATMEL_PIO_SODR : ATMEL_PIO_CODR, 360 BIT(pin->line)); 361 } 362 363 static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 364 { 365 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); 366 367 return irq_find_mapping(atmel_pioctrl->irq_domain, offset); 368 } 369 370 static struct gpio_chip atmel_gpio_chip = { 371 .direction_input = atmel_gpio_direction_input, 372 .get = atmel_gpio_get, 373 .direction_output = atmel_gpio_direction_output, 374 .set = atmel_gpio_set, 375 .to_irq = atmel_gpio_to_irq, 376 .base = 0, 377 }; 378 379 /* --- PINCTRL --- */ 380 static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev, 381 unsigned pin_id) 382 { 383 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 384 unsigned bank = atmel_pioctrl->pins[pin_id]->bank; 385 unsigned line = atmel_pioctrl->pins[pin_id]->line; 386 void __iomem *addr = atmel_pioctrl->reg_base 387 + bank * ATMEL_PIO_BANK_OFFSET; 388 389 writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR); 390 /* Have to set MSKR first, to access the right pin CFGR. */ 391 wmb(); 392 393 return readl_relaxed(addr + ATMEL_PIO_CFGR); 394 } 395 396 static void atmel_pin_config_write(struct pinctrl_dev *pctldev, 397 unsigned pin_id, u32 conf) 398 { 399 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 400 unsigned bank = atmel_pioctrl->pins[pin_id]->bank; 401 unsigned line = atmel_pioctrl->pins[pin_id]->line; 402 void __iomem *addr = atmel_pioctrl->reg_base 403 + bank * ATMEL_PIO_BANK_OFFSET; 404 405 writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR); 406 /* Have to set MSKR first, to access the right pin CFGR. */ 407 wmb(); 408 writel_relaxed(conf, addr + ATMEL_PIO_CFGR); 409 } 410 411 static int atmel_pctl_get_groups_count(struct pinctrl_dev *pctldev) 412 { 413 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 414 415 return atmel_pioctrl->npins; 416 } 417 418 static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev, 419 unsigned selector) 420 { 421 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 422 423 return atmel_pioctrl->groups[selector].name; 424 } 425 426 static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev, 427 unsigned selector, const unsigned **pins, 428 unsigned *num_pins) 429 { 430 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 431 432 *pins = (unsigned *)&atmel_pioctrl->groups[selector].pin; 433 *num_pins = 1; 434 435 return 0; 436 } 437 438 static struct atmel_group * 439 atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned pin) 440 { 441 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 442 int i; 443 444 for (i = 0; i < atmel_pioctrl->npins; i++) { 445 struct atmel_group *grp = atmel_pioctrl->groups + i; 446 447 if (grp->pin == pin) 448 return grp; 449 } 450 451 return NULL; 452 } 453 454 static int atmel_pctl_xlate_pinfunc(struct pinctrl_dev *pctldev, 455 struct device_node *np, 456 u32 pinfunc, const char **grp_name, 457 const char **func_name) 458 { 459 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 460 unsigned pin_id, func_id; 461 struct atmel_group *grp; 462 463 pin_id = ATMEL_GET_PIN_NO(pinfunc); 464 func_id = ATMEL_GET_PIN_FUNC(pinfunc); 465 466 if (func_id >= ARRAY_SIZE(atmel_functions)) 467 return -EINVAL; 468 469 *func_name = atmel_functions[func_id]; 470 471 grp = atmel_pctl_find_group_by_pin(pctldev, pin_id); 472 if (!grp) 473 return -EINVAL; 474 *grp_name = grp->name; 475 476 atmel_pioctrl->pins[pin_id]->mux = func_id; 477 atmel_pioctrl->pins[pin_id]->ioset = ATMEL_GET_PIN_IOSET(pinfunc); 478 /* Want the device name not the group one. */ 479 if (np->parent == atmel_pioctrl->node) 480 atmel_pioctrl->pins[pin_id]->device = np->name; 481 else 482 atmel_pioctrl->pins[pin_id]->device = np->parent->name; 483 484 return 0; 485 } 486 487 static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 488 struct device_node *np, 489 struct pinctrl_map **map, 490 unsigned *reserved_maps, 491 unsigned *num_maps) 492 { 493 unsigned num_pins, num_configs, reserve; 494 unsigned long *configs; 495 struct property *pins; 496 bool has_config; 497 u32 pinfunc; 498 int ret, i; 499 500 pins = of_find_property(np, "pinmux", NULL); 501 if (!pins) 502 return -EINVAL; 503 504 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, 505 &num_configs); 506 if (ret < 0) { 507 dev_err(pctldev->dev, "%pOF: could not parse node property\n", 508 np); 509 return ret; 510 } 511 512 if (num_configs) 513 has_config = true; 514 515 num_pins = pins->length / sizeof(u32); 516 if (!num_pins) { 517 dev_err(pctldev->dev, "no pins found in node %pOF\n", np); 518 ret = -EINVAL; 519 goto exit; 520 } 521 522 /* 523 * Reserve maps, at least there is a mux map and an optional conf 524 * map for each pin. 525 */ 526 reserve = 1; 527 if (has_config && num_pins >= 1) 528 reserve++; 529 reserve *= num_pins; 530 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps, 531 reserve); 532 if (ret < 0) 533 goto exit; 534 535 for (i = 0; i < num_pins; i++) { 536 const char *group, *func; 537 538 ret = of_property_read_u32_index(np, "pinmux", i, &pinfunc); 539 if (ret) 540 goto exit; 541 542 ret = atmel_pctl_xlate_pinfunc(pctldev, np, pinfunc, &group, 543 &func); 544 if (ret) 545 goto exit; 546 547 pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps, 548 group, func); 549 550 if (has_config) { 551 ret = pinctrl_utils_add_map_configs(pctldev, map, 552 reserved_maps, num_maps, group, 553 configs, num_configs, 554 PIN_MAP_TYPE_CONFIGS_GROUP); 555 if (ret < 0) 556 goto exit; 557 } 558 } 559 560 exit: 561 kfree(configs); 562 return ret; 563 } 564 565 static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, 566 struct device_node *np_config, 567 struct pinctrl_map **map, 568 unsigned *num_maps) 569 { 570 struct device_node *np; 571 unsigned reserved_maps; 572 int ret; 573 574 *map = NULL; 575 *num_maps = 0; 576 reserved_maps = 0; 577 578 /* 579 * If all the pins of a device have the same configuration (or no one), 580 * it is useless to add a subnode, so directly parse node referenced by 581 * phandle. 582 */ 583 ret = atmel_pctl_dt_subnode_to_map(pctldev, np_config, map, 584 &reserved_maps, num_maps); 585 if (ret) { 586 for_each_child_of_node(np_config, np) { 587 ret = atmel_pctl_dt_subnode_to_map(pctldev, np, map, 588 &reserved_maps, num_maps); 589 if (ret < 0) { 590 of_node_put(np); 591 break; 592 } 593 } 594 } 595 596 if (ret < 0) { 597 pinctrl_utils_free_map(pctldev, *map, *num_maps); 598 dev_err(pctldev->dev, "can't create maps for node %pOF\n", 599 np_config); 600 } 601 602 return ret; 603 } 604 605 static const struct pinctrl_ops atmel_pctlops = { 606 .get_groups_count = atmel_pctl_get_groups_count, 607 .get_group_name = atmel_pctl_get_group_name, 608 .get_group_pins = atmel_pctl_get_group_pins, 609 .dt_node_to_map = atmel_pctl_dt_node_to_map, 610 .dt_free_map = pinctrl_utils_free_map, 611 }; 612 613 static int atmel_pmx_get_functions_count(struct pinctrl_dev *pctldev) 614 { 615 return ARRAY_SIZE(atmel_functions); 616 } 617 618 static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev, 619 unsigned selector) 620 { 621 return atmel_functions[selector]; 622 } 623 624 static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev, 625 unsigned selector, 626 const char * const **groups, 627 unsigned * const num_groups) 628 { 629 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 630 631 *groups = atmel_pioctrl->group_names; 632 *num_groups = atmel_pioctrl->npins; 633 634 return 0; 635 } 636 637 static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev, 638 unsigned function, 639 unsigned group) 640 { 641 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 642 unsigned pin; 643 u32 conf; 644 645 dev_dbg(pctldev->dev, "enable function %s group %s\n", 646 atmel_functions[function], atmel_pioctrl->groups[group].name); 647 648 pin = atmel_pioctrl->groups[group].pin; 649 conf = atmel_pin_config_read(pctldev, pin); 650 conf &= (~ATMEL_PIO_CFGR_FUNC_MASK); 651 conf |= (function & ATMEL_PIO_CFGR_FUNC_MASK); 652 dev_dbg(pctldev->dev, "pin: %u, conf: 0x%08x\n", pin, conf); 653 atmel_pin_config_write(pctldev, pin, conf); 654 655 return 0; 656 } 657 658 static const struct pinmux_ops atmel_pmxops = { 659 .get_functions_count = atmel_pmx_get_functions_count, 660 .get_function_name = atmel_pmx_get_function_name, 661 .get_function_groups = atmel_pmx_get_function_groups, 662 .set_mux = atmel_pmx_set_mux, 663 }; 664 665 static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev, 666 unsigned group, 667 unsigned long *config) 668 { 669 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 670 unsigned param = pinconf_to_config_param(*config), arg = 0; 671 struct atmel_group *grp = atmel_pioctrl->groups + group; 672 unsigned pin_id = grp->pin; 673 u32 res; 674 675 res = atmel_pin_config_read(pctldev, pin_id); 676 677 switch (param) { 678 case PIN_CONFIG_BIAS_PULL_UP: 679 if (!(res & ATMEL_PIO_PUEN_MASK)) 680 return -EINVAL; 681 arg = 1; 682 break; 683 case PIN_CONFIG_BIAS_PULL_DOWN: 684 if ((res & ATMEL_PIO_PUEN_MASK) || 685 (!(res & ATMEL_PIO_PDEN_MASK))) 686 return -EINVAL; 687 arg = 1; 688 break; 689 case PIN_CONFIG_BIAS_DISABLE: 690 if ((res & ATMEL_PIO_PUEN_MASK) || 691 ((res & ATMEL_PIO_PDEN_MASK))) 692 return -EINVAL; 693 arg = 1; 694 break; 695 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 696 if (!(res & ATMEL_PIO_OPD_MASK)) 697 return -EINVAL; 698 arg = 1; 699 break; 700 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 701 if (!(res & ATMEL_PIO_SCHMITT_MASK)) 702 return -EINVAL; 703 arg = 1; 704 break; 705 case ATMEL_PIN_CONFIG_DRIVE_STRENGTH: 706 if (!(res & ATMEL_PIO_DRVSTR_MASK)) 707 return -EINVAL; 708 arg = (res & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET; 709 break; 710 default: 711 return -ENOTSUPP; 712 } 713 714 *config = pinconf_to_config_packed(param, arg); 715 return 0; 716 } 717 718 static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev, 719 unsigned group, 720 unsigned long *configs, 721 unsigned num_configs) 722 { 723 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 724 struct atmel_group *grp = atmel_pioctrl->groups + group; 725 unsigned bank, pin, pin_id = grp->pin; 726 u32 mask, conf = 0; 727 int i; 728 729 conf = atmel_pin_config_read(pctldev, pin_id); 730 731 for (i = 0; i < num_configs; i++) { 732 unsigned param = pinconf_to_config_param(configs[i]); 733 unsigned arg = pinconf_to_config_argument(configs[i]); 734 735 dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n", 736 __func__, pin_id, configs[i]); 737 738 switch (param) { 739 case PIN_CONFIG_BIAS_DISABLE: 740 conf &= (~ATMEL_PIO_PUEN_MASK); 741 conf &= (~ATMEL_PIO_PDEN_MASK); 742 break; 743 case PIN_CONFIG_BIAS_PULL_UP: 744 conf |= ATMEL_PIO_PUEN_MASK; 745 conf &= (~ATMEL_PIO_PDEN_MASK); 746 break; 747 case PIN_CONFIG_BIAS_PULL_DOWN: 748 conf |= ATMEL_PIO_PDEN_MASK; 749 conf &= (~ATMEL_PIO_PUEN_MASK); 750 break; 751 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 752 if (arg == 0) 753 conf &= (~ATMEL_PIO_OPD_MASK); 754 else 755 conf |= ATMEL_PIO_OPD_MASK; 756 break; 757 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 758 if (arg == 0) 759 conf |= ATMEL_PIO_SCHMITT_MASK; 760 else 761 conf &= (~ATMEL_PIO_SCHMITT_MASK); 762 break; 763 case PIN_CONFIG_INPUT_DEBOUNCE: 764 if (arg == 0) { 765 conf &= (~ATMEL_PIO_IFEN_MASK); 766 conf &= (~ATMEL_PIO_IFSCEN_MASK); 767 } else { 768 /* 769 * We don't care about the debounce value for several reasons: 770 * - can't have different debounce periods inside a same group, 771 * - the register to configure this period is a secure register. 772 * The debouncing filter can filter a pulse with a duration of less 773 * than 1/2 slow clock period. 774 */ 775 conf |= ATMEL_PIO_IFEN_MASK; 776 conf |= ATMEL_PIO_IFSCEN_MASK; 777 } 778 break; 779 case PIN_CONFIG_OUTPUT: 780 conf |= ATMEL_PIO_DIR_MASK; 781 bank = ATMEL_PIO_BANK(pin_id); 782 pin = ATMEL_PIO_LINE(pin_id); 783 mask = 1 << pin; 784 785 if (arg == 0) { 786 writel_relaxed(mask, atmel_pioctrl->reg_base + 787 bank * ATMEL_PIO_BANK_OFFSET + 788 ATMEL_PIO_CODR); 789 } else { 790 writel_relaxed(mask, atmel_pioctrl->reg_base + 791 bank * ATMEL_PIO_BANK_OFFSET + 792 ATMEL_PIO_SODR); 793 } 794 break; 795 case ATMEL_PIN_CONFIG_DRIVE_STRENGTH: 796 switch (arg) { 797 case ATMEL_PIO_DRVSTR_LO: 798 case ATMEL_PIO_DRVSTR_ME: 799 case ATMEL_PIO_DRVSTR_HI: 800 conf &= (~ATMEL_PIO_DRVSTR_MASK); 801 conf |= arg << ATMEL_PIO_DRVSTR_OFFSET; 802 break; 803 default: 804 dev_warn(pctldev->dev, "drive strength not updated (incorrect value)\n"); 805 } 806 break; 807 default: 808 dev_warn(pctldev->dev, 809 "unsupported configuration parameter: %u\n", 810 param); 811 continue; 812 } 813 } 814 815 dev_dbg(pctldev->dev, "%s: reg=0x%08x\n", __func__, conf); 816 atmel_pin_config_write(pctldev, pin_id, conf); 817 818 return 0; 819 } 820 821 static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev, 822 struct seq_file *s, unsigned pin_id) 823 { 824 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 825 u32 conf; 826 827 if (!atmel_pioctrl->pins[pin_id]->device) 828 return; 829 830 if (atmel_pioctrl->pins[pin_id]) 831 seq_printf(s, " (%s, ioset %u) ", 832 atmel_pioctrl->pins[pin_id]->device, 833 atmel_pioctrl->pins[pin_id]->ioset); 834 835 conf = atmel_pin_config_read(pctldev, pin_id); 836 if (conf & ATMEL_PIO_PUEN_MASK) 837 seq_printf(s, "%s ", "pull-up"); 838 if (conf & ATMEL_PIO_PDEN_MASK) 839 seq_printf(s, "%s ", "pull-down"); 840 if (conf & ATMEL_PIO_IFEN_MASK) 841 seq_printf(s, "%s ", "debounce"); 842 if (conf & ATMEL_PIO_OPD_MASK) 843 seq_printf(s, "%s ", "open-drain"); 844 if (conf & ATMEL_PIO_SCHMITT_MASK) 845 seq_printf(s, "%s ", "schmitt"); 846 if (conf & ATMEL_PIO_DRVSTR_MASK) { 847 switch ((conf & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET) { 848 case ATMEL_PIO_DRVSTR_ME: 849 seq_printf(s, "%s ", "medium-drive"); 850 break; 851 case ATMEL_PIO_DRVSTR_HI: 852 seq_printf(s, "%s ", "high-drive"); 853 break; 854 /* ATMEL_PIO_DRVSTR_LO and 0 which is the default value at reset */ 855 default: 856 seq_printf(s, "%s ", "low-drive"); 857 } 858 } 859 } 860 861 static const struct pinconf_ops atmel_confops = { 862 .pin_config_group_get = atmel_conf_pin_config_group_get, 863 .pin_config_group_set = atmel_conf_pin_config_group_set, 864 .pin_config_dbg_show = atmel_conf_pin_config_dbg_show, 865 }; 866 867 static struct pinctrl_desc atmel_pinctrl_desc = { 868 .name = "atmel_pinctrl", 869 .confops = &atmel_confops, 870 .pctlops = &atmel_pctlops, 871 .pmxops = &atmel_pmxops, 872 }; 873 874 static int __maybe_unused atmel_pctrl_suspend(struct device *dev) 875 { 876 struct platform_device *pdev = to_platform_device(dev); 877 struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev); 878 int i, j; 879 880 /* 881 * For each bank, save IMR to restore it later and disable all GPIO 882 * interrupts excepting the ones marked as wakeup sources. 883 */ 884 for (i = 0; i < atmel_pioctrl->nbanks; i++) { 885 atmel_pioctrl->pm_suspend_backup[i].imr = 886 atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_IMR); 887 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IDR, 888 ~atmel_pioctrl->pm_wakeup_sources[i]); 889 atmel_pioctrl->pm_suspend_backup[i].odsr = 890 atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_ODSR); 891 for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) { 892 atmel_gpio_write(atmel_pioctrl, i, 893 ATMEL_PIO_MSKR, BIT(j)); 894 atmel_pioctrl->pm_suspend_backup[i].cfgr[j] = 895 atmel_gpio_read(atmel_pioctrl, i, 896 ATMEL_PIO_CFGR); 897 } 898 } 899 900 return 0; 901 } 902 903 static int __maybe_unused atmel_pctrl_resume(struct device *dev) 904 { 905 struct platform_device *pdev = to_platform_device(dev); 906 struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev); 907 int i, j; 908 909 for (i = 0; i < atmel_pioctrl->nbanks; i++) { 910 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IER, 911 atmel_pioctrl->pm_suspend_backup[i].imr); 912 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_SODR, 913 atmel_pioctrl->pm_suspend_backup[i].odsr); 914 for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) { 915 atmel_gpio_write(atmel_pioctrl, i, 916 ATMEL_PIO_MSKR, BIT(j)); 917 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_CFGR, 918 atmel_pioctrl->pm_suspend_backup[i].cfgr[j]); 919 } 920 } 921 922 return 0; 923 } 924 925 static const struct dev_pm_ops atmel_pctrl_pm_ops = { 926 SET_SYSTEM_SLEEP_PM_OPS(atmel_pctrl_suspend, atmel_pctrl_resume) 927 }; 928 929 /* 930 * The number of banks can be different from a SoC to another one. 931 * We can have up to 16 banks. 932 */ 933 static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = { 934 .nbanks = 4, 935 }; 936 937 static const struct of_device_id atmel_pctrl_of_match[] = { 938 { 939 .compatible = "atmel,sama5d2-pinctrl", 940 .data = &atmel_sama5d2_pioctrl_data, 941 }, { 942 /* sentinel */ 943 } 944 }; 945 946 static int atmel_pinctrl_probe(struct platform_device *pdev) 947 { 948 struct device *dev = &pdev->dev; 949 struct pinctrl_pin_desc *pin_desc; 950 const char **group_names; 951 const struct of_device_id *match; 952 int i, ret; 953 struct resource *res; 954 struct atmel_pioctrl *atmel_pioctrl; 955 const struct atmel_pioctrl_data *atmel_pioctrl_data; 956 957 atmel_pioctrl = devm_kzalloc(dev, sizeof(*atmel_pioctrl), GFP_KERNEL); 958 if (!atmel_pioctrl) 959 return -ENOMEM; 960 atmel_pioctrl->dev = dev; 961 atmel_pioctrl->node = dev->of_node; 962 platform_set_drvdata(pdev, atmel_pioctrl); 963 964 match = of_match_node(atmel_pctrl_of_match, dev->of_node); 965 if (!match) { 966 dev_err(dev, "unknown compatible string\n"); 967 return -ENODEV; 968 } 969 atmel_pioctrl_data = match->data; 970 atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks; 971 atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK; 972 973 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 974 atmel_pioctrl->reg_base = devm_ioremap_resource(dev, res); 975 if (IS_ERR(atmel_pioctrl->reg_base)) 976 return -EINVAL; 977 978 atmel_pioctrl->clk = devm_clk_get(dev, NULL); 979 if (IS_ERR(atmel_pioctrl->clk)) { 980 dev_err(dev, "failed to get clock\n"); 981 return PTR_ERR(atmel_pioctrl->clk); 982 } 983 984 atmel_pioctrl->pins = devm_kcalloc(dev, 985 atmel_pioctrl->npins, 986 sizeof(*atmel_pioctrl->pins), 987 GFP_KERNEL); 988 if (!atmel_pioctrl->pins) 989 return -ENOMEM; 990 991 pin_desc = devm_kcalloc(dev, atmel_pioctrl->npins, sizeof(*pin_desc), 992 GFP_KERNEL); 993 if (!pin_desc) 994 return -ENOMEM; 995 atmel_pinctrl_desc.pins = pin_desc; 996 atmel_pinctrl_desc.npins = atmel_pioctrl->npins; 997 atmel_pinctrl_desc.num_custom_params = ARRAY_SIZE(atmel_custom_bindings); 998 atmel_pinctrl_desc.custom_params = atmel_custom_bindings; 999 1000 /* One pin is one group since a pin can achieve all functions. */ 1001 group_names = devm_kcalloc(dev, 1002 atmel_pioctrl->npins, sizeof(*group_names), 1003 GFP_KERNEL); 1004 if (!group_names) 1005 return -ENOMEM; 1006 atmel_pioctrl->group_names = group_names; 1007 1008 atmel_pioctrl->groups = devm_kcalloc(&pdev->dev, 1009 atmel_pioctrl->npins, sizeof(*atmel_pioctrl->groups), 1010 GFP_KERNEL); 1011 if (!atmel_pioctrl->groups) 1012 return -ENOMEM; 1013 for (i = 0 ; i < atmel_pioctrl->npins; i++) { 1014 struct atmel_group *group = atmel_pioctrl->groups + i; 1015 unsigned bank = ATMEL_PIO_BANK(i); 1016 unsigned line = ATMEL_PIO_LINE(i); 1017 1018 atmel_pioctrl->pins[i] = devm_kzalloc(dev, 1019 sizeof(**atmel_pioctrl->pins), GFP_KERNEL); 1020 if (!atmel_pioctrl->pins[i]) 1021 return -ENOMEM; 1022 1023 atmel_pioctrl->pins[i]->pin_id = i; 1024 atmel_pioctrl->pins[i]->bank = bank; 1025 atmel_pioctrl->pins[i]->line = line; 1026 1027 pin_desc[i].number = i; 1028 /* Pin naming convention: P(bank_name)(bank_pin_number). */ 1029 pin_desc[i].name = kasprintf(GFP_KERNEL, "P%c%d", 1030 bank + 'A', line); 1031 1032 group->name = group_names[i] = pin_desc[i].name; 1033 group->pin = pin_desc[i].number; 1034 1035 dev_dbg(dev, "pin_id=%u, bank=%u, line=%u", i, bank, line); 1036 } 1037 1038 atmel_pioctrl->gpio_chip = &atmel_gpio_chip; 1039 atmel_pioctrl->gpio_chip->of_node = dev->of_node; 1040 atmel_pioctrl->gpio_chip->ngpio = atmel_pioctrl->npins; 1041 atmel_pioctrl->gpio_chip->label = dev_name(dev); 1042 atmel_pioctrl->gpio_chip->parent = dev; 1043 atmel_pioctrl->gpio_chip->names = atmel_pioctrl->group_names; 1044 1045 atmel_pioctrl->pm_wakeup_sources = devm_kcalloc(dev, 1046 atmel_pioctrl->nbanks, 1047 sizeof(*atmel_pioctrl->pm_wakeup_sources), 1048 GFP_KERNEL); 1049 if (!atmel_pioctrl->pm_wakeup_sources) 1050 return -ENOMEM; 1051 1052 atmel_pioctrl->pm_suspend_backup = devm_kcalloc(dev, 1053 atmel_pioctrl->nbanks, 1054 sizeof(*atmel_pioctrl->pm_suspend_backup), 1055 GFP_KERNEL); 1056 if (!atmel_pioctrl->pm_suspend_backup) 1057 return -ENOMEM; 1058 1059 atmel_pioctrl->irqs = devm_kcalloc(dev, 1060 atmel_pioctrl->nbanks, 1061 sizeof(*atmel_pioctrl->irqs), 1062 GFP_KERNEL); 1063 if (!atmel_pioctrl->irqs) 1064 return -ENOMEM; 1065 1066 /* There is one controller but each bank has its own irq line. */ 1067 for (i = 0; i < atmel_pioctrl->nbanks; i++) { 1068 res = platform_get_resource(pdev, IORESOURCE_IRQ, i); 1069 if (!res) { 1070 dev_err(dev, "missing irq resource for group %c\n", 1071 'A' + i); 1072 return -EINVAL; 1073 } 1074 atmel_pioctrl->irqs[i] = res->start; 1075 irq_set_chained_handler(res->start, atmel_gpio_irq_handler); 1076 irq_set_handler_data(res->start, atmel_pioctrl); 1077 dev_dbg(dev, "bank %i: irq=%pr\n", i, res); 1078 } 1079 1080 atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node, 1081 atmel_pioctrl->gpio_chip->ngpio, 1082 &irq_domain_simple_ops, NULL); 1083 if (!atmel_pioctrl->irq_domain) { 1084 dev_err(dev, "can't add the irq domain\n"); 1085 return -ENODEV; 1086 } 1087 atmel_pioctrl->irq_domain->name = "atmel gpio"; 1088 1089 for (i = 0; i < atmel_pioctrl->npins; i++) { 1090 int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i); 1091 1092 irq_set_chip_and_handler(irq, &atmel_gpio_irq_chip, 1093 handle_simple_irq); 1094 irq_set_chip_data(irq, atmel_pioctrl); 1095 dev_dbg(dev, 1096 "atmel gpio irq domain: hwirq: %d, linux irq: %d\n", 1097 i, irq); 1098 } 1099 1100 ret = clk_prepare_enable(atmel_pioctrl->clk); 1101 if (ret) { 1102 dev_err(dev, "failed to prepare and enable clock\n"); 1103 goto clk_prepare_enable_error; 1104 } 1105 1106 atmel_pioctrl->pinctrl_dev = devm_pinctrl_register(&pdev->dev, 1107 &atmel_pinctrl_desc, 1108 atmel_pioctrl); 1109 if (IS_ERR(atmel_pioctrl->pinctrl_dev)) { 1110 ret = PTR_ERR(atmel_pioctrl->pinctrl_dev); 1111 dev_err(dev, "pinctrl registration failed\n"); 1112 goto clk_unprep; 1113 } 1114 1115 ret = gpiochip_add_data(atmel_pioctrl->gpio_chip, atmel_pioctrl); 1116 if (ret) { 1117 dev_err(dev, "failed to add gpiochip\n"); 1118 goto clk_unprep; 1119 } 1120 1121 ret = gpiochip_add_pin_range(atmel_pioctrl->gpio_chip, dev_name(dev), 1122 0, 0, atmel_pioctrl->gpio_chip->ngpio); 1123 if (ret) { 1124 dev_err(dev, "failed to add gpio pin range\n"); 1125 goto gpiochip_add_pin_range_error; 1126 } 1127 1128 dev_info(&pdev->dev, "atmel pinctrl initialized\n"); 1129 1130 return 0; 1131 1132 gpiochip_add_pin_range_error: 1133 gpiochip_remove(atmel_pioctrl->gpio_chip); 1134 1135 clk_unprep: 1136 clk_disable_unprepare(atmel_pioctrl->clk); 1137 1138 clk_prepare_enable_error: 1139 irq_domain_remove(atmel_pioctrl->irq_domain); 1140 1141 return ret; 1142 } 1143 1144 static struct platform_driver atmel_pinctrl_driver = { 1145 .driver = { 1146 .name = "pinctrl-at91-pio4", 1147 .of_match_table = atmel_pctrl_of_match, 1148 .pm = &atmel_pctrl_pm_ops, 1149 .suppress_bind_attrs = true, 1150 }, 1151 .probe = atmel_pinctrl_probe, 1152 }; 1153 builtin_platform_driver(atmel_pinctrl_driver); 1154