1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for the Atmel PIO4 controller 4 * 5 * Copyright (C) 2015 Atmel, 6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 7 */ 8 9 #include <dt-bindings/pinctrl/at91.h> 10 #include <linux/clk.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/init.h> 15 #include <linux/of.h> 16 #include <linux/platform_device.h> 17 #include <linux/pinctrl/pinconf.h> 18 #include <linux/pinctrl/pinconf-generic.h> 19 #include <linux/pinctrl/pinctrl.h> 20 #include <linux/pinctrl/pinmux.h> 21 #include <linux/slab.h> 22 #include "core.h" 23 #include "pinconf.h" 24 #include "pinctrl-utils.h" 25 26 /* 27 * Warning: 28 * In order to not introduce confusion between Atmel PIO groups and pinctrl 29 * framework groups, Atmel PIO groups will be called banks, line is kept to 30 * designed the pin id into this bank. 31 */ 32 33 #define ATMEL_PIO_MSKR 0x0000 34 #define ATMEL_PIO_CFGR 0x0004 35 #define ATMEL_PIO_CFGR_FUNC_MASK GENMASK(2, 0) 36 #define ATMEL_PIO_DIR_MASK BIT(8) 37 #define ATMEL_PIO_PUEN_MASK BIT(9) 38 #define ATMEL_PIO_PDEN_MASK BIT(10) 39 #define ATMEL_PIO_IFEN_MASK BIT(12) 40 #define ATMEL_PIO_IFSCEN_MASK BIT(13) 41 #define ATMEL_PIO_OPD_MASK BIT(14) 42 #define ATMEL_PIO_SCHMITT_MASK BIT(15) 43 #define ATMEL_PIO_DRVSTR_MASK GENMASK(17, 16) 44 #define ATMEL_PIO_DRVSTR_OFFSET 16 45 #define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24) 46 #define ATMEL_PIO_CFGR_EVTSEL_FALLING (0 << 24) 47 #define ATMEL_PIO_CFGR_EVTSEL_RISING (1 << 24) 48 #define ATMEL_PIO_CFGR_EVTSEL_BOTH (2 << 24) 49 #define ATMEL_PIO_CFGR_EVTSEL_LOW (3 << 24) 50 #define ATMEL_PIO_CFGR_EVTSEL_HIGH (4 << 24) 51 #define ATMEL_PIO_PDSR 0x0008 52 #define ATMEL_PIO_LOCKSR 0x000C 53 #define ATMEL_PIO_SODR 0x0010 54 #define ATMEL_PIO_CODR 0x0014 55 #define ATMEL_PIO_ODSR 0x0018 56 #define ATMEL_PIO_IER 0x0020 57 #define ATMEL_PIO_IDR 0x0024 58 #define ATMEL_PIO_IMR 0x0028 59 #define ATMEL_PIO_ISR 0x002C 60 #define ATMEL_PIO_IOFR 0x003C 61 62 #define ATMEL_PIO_NPINS_PER_BANK 32 63 #define ATMEL_PIO_BANK(pin_id) (pin_id / ATMEL_PIO_NPINS_PER_BANK) 64 #define ATMEL_PIO_LINE(pin_id) (pin_id % ATMEL_PIO_NPINS_PER_BANK) 65 #define ATMEL_PIO_BANK_OFFSET 0x40 66 67 #define ATMEL_GET_PIN_NO(pinfunc) ((pinfunc) & 0xff) 68 #define ATMEL_GET_PIN_FUNC(pinfunc) ((pinfunc >> 16) & 0xf) 69 #define ATMEL_GET_PIN_IOSET(pinfunc) ((pinfunc >> 20) & 0xf) 70 71 /* Custom pinconf parameters */ 72 #define ATMEL_PIN_CONFIG_DRIVE_STRENGTH (PIN_CONFIG_END + 1) 73 74 struct atmel_pioctrl_data { 75 unsigned nbanks; 76 }; 77 78 struct atmel_group { 79 const char *name; 80 u32 pin; 81 }; 82 83 struct atmel_pin { 84 unsigned pin_id; 85 unsigned mux; 86 unsigned ioset; 87 unsigned bank; 88 unsigned line; 89 const char *device; 90 }; 91 92 /** 93 * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio) 94 * @reg_base: base address of the controller. 95 * @clk: clock of the controller. 96 * @nbanks: number of PIO groups, it can vary depending on the SoC. 97 * @pinctrl_dev: pinctrl device registered. 98 * @groups: groups table to provide group name and pin in the group to pinctrl. 99 * @group_names: group names table to provide all the group/pin names to 100 * pinctrl or gpio. 101 * @pins: pins table used for both pinctrl and gpio. pin_id, bank and line 102 * fields are set at probe time. Other ones are set when parsing dt 103 * pinctrl. 104 * @npins: number of pins. 105 * @gpio_chip: gpio chip registered. 106 * @irq_domain: irq domain for the gpio controller. 107 * @irqs: table containing the hw irq number of the bank. The index of the 108 * table is the bank id. 109 * @dev: device entry for the Atmel PIO controller. 110 * @node: node of the Atmel PIO controller. 111 */ 112 struct atmel_pioctrl { 113 void __iomem *reg_base; 114 struct clk *clk; 115 unsigned nbanks; 116 struct pinctrl_dev *pinctrl_dev; 117 struct atmel_group *groups; 118 const char * const *group_names; 119 struct atmel_pin **pins; 120 unsigned npins; 121 struct gpio_chip *gpio_chip; 122 struct irq_domain *irq_domain; 123 int *irqs; 124 unsigned *pm_wakeup_sources; 125 struct { 126 u32 imr; 127 u32 odsr; 128 u32 cfgr[ATMEL_PIO_NPINS_PER_BANK]; 129 } *pm_suspend_backup; 130 struct device *dev; 131 struct device_node *node; 132 }; 133 134 static const char * const atmel_functions[] = { 135 "GPIO", "A", "B", "C", "D", "E", "F", "G" 136 }; 137 138 static const struct pinconf_generic_params atmel_custom_bindings[] = { 139 {"atmel,drive-strength", ATMEL_PIN_CONFIG_DRIVE_STRENGTH, 0}, 140 }; 141 142 /* --- GPIO --- */ 143 static unsigned int atmel_gpio_read(struct atmel_pioctrl *atmel_pioctrl, 144 unsigned int bank, unsigned int reg) 145 { 146 return readl_relaxed(atmel_pioctrl->reg_base 147 + ATMEL_PIO_BANK_OFFSET * bank + reg); 148 } 149 150 static void atmel_gpio_write(struct atmel_pioctrl *atmel_pioctrl, 151 unsigned int bank, unsigned int reg, 152 unsigned int val) 153 { 154 writel_relaxed(val, atmel_pioctrl->reg_base 155 + ATMEL_PIO_BANK_OFFSET * bank + reg); 156 } 157 158 static void atmel_gpio_irq_ack(struct irq_data *d) 159 { 160 /* 161 * Nothing to do, interrupt is cleared when reading the status 162 * register. 163 */ 164 } 165 166 static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned type) 167 { 168 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); 169 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; 170 unsigned reg; 171 172 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, 173 BIT(pin->line)); 174 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); 175 reg &= (~ATMEL_PIO_CFGR_EVTSEL_MASK); 176 177 switch (type) { 178 case IRQ_TYPE_EDGE_RISING: 179 irq_set_handler_locked(d, handle_edge_irq); 180 reg |= ATMEL_PIO_CFGR_EVTSEL_RISING; 181 break; 182 case IRQ_TYPE_EDGE_FALLING: 183 irq_set_handler_locked(d, handle_edge_irq); 184 reg |= ATMEL_PIO_CFGR_EVTSEL_FALLING; 185 break; 186 case IRQ_TYPE_EDGE_BOTH: 187 irq_set_handler_locked(d, handle_edge_irq); 188 reg |= ATMEL_PIO_CFGR_EVTSEL_BOTH; 189 break; 190 case IRQ_TYPE_LEVEL_LOW: 191 irq_set_handler_locked(d, handle_level_irq); 192 reg |= ATMEL_PIO_CFGR_EVTSEL_LOW; 193 break; 194 case IRQ_TYPE_LEVEL_HIGH: 195 irq_set_handler_locked(d, handle_level_irq); 196 reg |= ATMEL_PIO_CFGR_EVTSEL_HIGH; 197 break; 198 case IRQ_TYPE_NONE: 199 default: 200 return -EINVAL; 201 } 202 203 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); 204 205 return 0; 206 } 207 208 static void atmel_gpio_irq_mask(struct irq_data *d) 209 { 210 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); 211 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; 212 213 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR, 214 BIT(pin->line)); 215 } 216 217 static void atmel_gpio_irq_unmask(struct irq_data *d) 218 { 219 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); 220 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; 221 222 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IER, 223 BIT(pin->line)); 224 } 225 226 #ifdef CONFIG_PM_SLEEP 227 228 static int atmel_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 229 { 230 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); 231 int bank = ATMEL_PIO_BANK(d->hwirq); 232 int line = ATMEL_PIO_LINE(d->hwirq); 233 234 /* The gpio controller has one interrupt line per bank. */ 235 irq_set_irq_wake(atmel_pioctrl->irqs[bank], on); 236 237 if (on) 238 atmel_pioctrl->pm_wakeup_sources[bank] |= BIT(line); 239 else 240 atmel_pioctrl->pm_wakeup_sources[bank] &= ~(BIT(line)); 241 242 return 0; 243 } 244 #else 245 #define atmel_gpio_irq_set_wake NULL 246 #endif /* CONFIG_PM_SLEEP */ 247 248 static struct irq_chip atmel_gpio_irq_chip = { 249 .name = "GPIO", 250 .irq_ack = atmel_gpio_irq_ack, 251 .irq_mask = atmel_gpio_irq_mask, 252 .irq_unmask = atmel_gpio_irq_unmask, 253 .irq_set_type = atmel_gpio_irq_set_type, 254 .irq_set_wake = atmel_gpio_irq_set_wake, 255 }; 256 257 static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 258 { 259 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); 260 261 return irq_find_mapping(atmel_pioctrl->irq_domain, offset); 262 } 263 264 static void atmel_gpio_irq_handler(struct irq_desc *desc) 265 { 266 unsigned int irq = irq_desc_get_irq(desc); 267 struct atmel_pioctrl *atmel_pioctrl = irq_desc_get_handler_data(desc); 268 struct irq_chip *chip = irq_desc_get_chip(desc); 269 unsigned long isr; 270 int n, bank = -1; 271 272 /* Find from which bank is the irq received. */ 273 for (n = 0; n < atmel_pioctrl->nbanks; n++) { 274 if (atmel_pioctrl->irqs[n] == irq) { 275 bank = n; 276 break; 277 } 278 } 279 280 if (bank < 0) { 281 dev_err(atmel_pioctrl->dev, 282 "no bank associated to irq %u\n", irq); 283 return; 284 } 285 286 chained_irq_enter(chip, desc); 287 288 for (;;) { 289 isr = (unsigned long)atmel_gpio_read(atmel_pioctrl, bank, 290 ATMEL_PIO_ISR); 291 isr &= (unsigned long)atmel_gpio_read(atmel_pioctrl, bank, 292 ATMEL_PIO_IMR); 293 if (!isr) 294 break; 295 296 for_each_set_bit(n, &isr, BITS_PER_LONG) 297 generic_handle_irq(atmel_gpio_to_irq( 298 atmel_pioctrl->gpio_chip, 299 bank * ATMEL_PIO_NPINS_PER_BANK + n)); 300 } 301 302 chained_irq_exit(chip, desc); 303 } 304 305 static int atmel_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 306 { 307 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); 308 struct atmel_pin *pin = atmel_pioctrl->pins[offset]; 309 unsigned reg; 310 311 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, 312 BIT(pin->line)); 313 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); 314 reg &= ~ATMEL_PIO_DIR_MASK; 315 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); 316 317 return 0; 318 } 319 320 static int atmel_gpio_get(struct gpio_chip *chip, unsigned offset) 321 { 322 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); 323 struct atmel_pin *pin = atmel_pioctrl->pins[offset]; 324 unsigned reg; 325 326 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR); 327 328 return !!(reg & BIT(pin->line)); 329 } 330 331 static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 332 int value) 333 { 334 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); 335 struct atmel_pin *pin = atmel_pioctrl->pins[offset]; 336 unsigned reg; 337 338 atmel_gpio_write(atmel_pioctrl, pin->bank, 339 value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR, 340 BIT(pin->line)); 341 342 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, 343 BIT(pin->line)); 344 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); 345 reg |= ATMEL_PIO_DIR_MASK; 346 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); 347 348 return 0; 349 } 350 351 static void atmel_gpio_set(struct gpio_chip *chip, unsigned offset, int val) 352 { 353 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); 354 struct atmel_pin *pin = atmel_pioctrl->pins[offset]; 355 356 atmel_gpio_write(atmel_pioctrl, pin->bank, 357 val ? ATMEL_PIO_SODR : ATMEL_PIO_CODR, 358 BIT(pin->line)); 359 } 360 361 static struct gpio_chip atmel_gpio_chip = { 362 .direction_input = atmel_gpio_direction_input, 363 .get = atmel_gpio_get, 364 .direction_output = atmel_gpio_direction_output, 365 .set = atmel_gpio_set, 366 .to_irq = atmel_gpio_to_irq, 367 .base = 0, 368 }; 369 370 /* --- PINCTRL --- */ 371 static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev, 372 unsigned pin_id) 373 { 374 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 375 unsigned bank = atmel_pioctrl->pins[pin_id]->bank; 376 unsigned line = atmel_pioctrl->pins[pin_id]->line; 377 void __iomem *addr = atmel_pioctrl->reg_base 378 + bank * ATMEL_PIO_BANK_OFFSET; 379 380 writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR); 381 /* Have to set MSKR first, to access the right pin CFGR. */ 382 wmb(); 383 384 return readl_relaxed(addr + ATMEL_PIO_CFGR); 385 } 386 387 static void atmel_pin_config_write(struct pinctrl_dev *pctldev, 388 unsigned pin_id, u32 conf) 389 { 390 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 391 unsigned bank = atmel_pioctrl->pins[pin_id]->bank; 392 unsigned line = atmel_pioctrl->pins[pin_id]->line; 393 void __iomem *addr = atmel_pioctrl->reg_base 394 + bank * ATMEL_PIO_BANK_OFFSET; 395 396 writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR); 397 /* Have to set MSKR first, to access the right pin CFGR. */ 398 wmb(); 399 writel_relaxed(conf, addr + ATMEL_PIO_CFGR); 400 } 401 402 static int atmel_pctl_get_groups_count(struct pinctrl_dev *pctldev) 403 { 404 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 405 406 return atmel_pioctrl->npins; 407 } 408 409 static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev, 410 unsigned selector) 411 { 412 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 413 414 return atmel_pioctrl->groups[selector].name; 415 } 416 417 static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev, 418 unsigned selector, const unsigned **pins, 419 unsigned *num_pins) 420 { 421 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 422 423 *pins = (unsigned *)&atmel_pioctrl->groups[selector].pin; 424 *num_pins = 1; 425 426 return 0; 427 } 428 429 static struct atmel_group * 430 atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned pin) 431 { 432 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 433 int i; 434 435 for (i = 0; i < atmel_pioctrl->npins; i++) { 436 struct atmel_group *grp = atmel_pioctrl->groups + i; 437 438 if (grp->pin == pin) 439 return grp; 440 } 441 442 return NULL; 443 } 444 445 static int atmel_pctl_xlate_pinfunc(struct pinctrl_dev *pctldev, 446 struct device_node *np, 447 u32 pinfunc, const char **grp_name, 448 const char **func_name) 449 { 450 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 451 unsigned pin_id, func_id; 452 struct atmel_group *grp; 453 454 pin_id = ATMEL_GET_PIN_NO(pinfunc); 455 func_id = ATMEL_GET_PIN_FUNC(pinfunc); 456 457 if (func_id >= ARRAY_SIZE(atmel_functions)) 458 return -EINVAL; 459 460 *func_name = atmel_functions[func_id]; 461 462 grp = atmel_pctl_find_group_by_pin(pctldev, pin_id); 463 if (!grp) 464 return -EINVAL; 465 *grp_name = grp->name; 466 467 atmel_pioctrl->pins[pin_id]->mux = func_id; 468 atmel_pioctrl->pins[pin_id]->ioset = ATMEL_GET_PIN_IOSET(pinfunc); 469 /* Want the device name not the group one. */ 470 if (np->parent == atmel_pioctrl->node) 471 atmel_pioctrl->pins[pin_id]->device = np->name; 472 else 473 atmel_pioctrl->pins[pin_id]->device = np->parent->name; 474 475 return 0; 476 } 477 478 static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 479 struct device_node *np, 480 struct pinctrl_map **map, 481 unsigned *reserved_maps, 482 unsigned *num_maps) 483 { 484 unsigned num_pins, num_configs, reserve; 485 unsigned long *configs; 486 struct property *pins; 487 u32 pinfunc; 488 int ret, i; 489 490 pins = of_find_property(np, "pinmux", NULL); 491 if (!pins) 492 return -EINVAL; 493 494 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, 495 &num_configs); 496 if (ret < 0) { 497 dev_err(pctldev->dev, "%pOF: could not parse node property\n", 498 np); 499 return ret; 500 } 501 502 num_pins = pins->length / sizeof(u32); 503 if (!num_pins) { 504 dev_err(pctldev->dev, "no pins found in node %pOF\n", np); 505 ret = -EINVAL; 506 goto exit; 507 } 508 509 /* 510 * Reserve maps, at least there is a mux map and an optional conf 511 * map for each pin. 512 */ 513 reserve = 1; 514 if (num_configs) 515 reserve++; 516 reserve *= num_pins; 517 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps, 518 reserve); 519 if (ret < 0) 520 goto exit; 521 522 for (i = 0; i < num_pins; i++) { 523 const char *group, *func; 524 525 ret = of_property_read_u32_index(np, "pinmux", i, &pinfunc); 526 if (ret) 527 goto exit; 528 529 ret = atmel_pctl_xlate_pinfunc(pctldev, np, pinfunc, &group, 530 &func); 531 if (ret) 532 goto exit; 533 534 pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps, 535 group, func); 536 537 if (num_configs) { 538 ret = pinctrl_utils_add_map_configs(pctldev, map, 539 reserved_maps, num_maps, group, 540 configs, num_configs, 541 PIN_MAP_TYPE_CONFIGS_GROUP); 542 if (ret < 0) 543 goto exit; 544 } 545 } 546 547 exit: 548 kfree(configs); 549 return ret; 550 } 551 552 static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, 553 struct device_node *np_config, 554 struct pinctrl_map **map, 555 unsigned *num_maps) 556 { 557 struct device_node *np; 558 unsigned reserved_maps; 559 int ret; 560 561 *map = NULL; 562 *num_maps = 0; 563 reserved_maps = 0; 564 565 /* 566 * If all the pins of a device have the same configuration (or no one), 567 * it is useless to add a subnode, so directly parse node referenced by 568 * phandle. 569 */ 570 ret = atmel_pctl_dt_subnode_to_map(pctldev, np_config, map, 571 &reserved_maps, num_maps); 572 if (ret) { 573 for_each_child_of_node(np_config, np) { 574 ret = atmel_pctl_dt_subnode_to_map(pctldev, np, map, 575 &reserved_maps, num_maps); 576 if (ret < 0) { 577 of_node_put(np); 578 break; 579 } 580 } 581 } 582 583 if (ret < 0) { 584 pinctrl_utils_free_map(pctldev, *map, *num_maps); 585 dev_err(pctldev->dev, "can't create maps for node %pOF\n", 586 np_config); 587 } 588 589 return ret; 590 } 591 592 static const struct pinctrl_ops atmel_pctlops = { 593 .get_groups_count = atmel_pctl_get_groups_count, 594 .get_group_name = atmel_pctl_get_group_name, 595 .get_group_pins = atmel_pctl_get_group_pins, 596 .dt_node_to_map = atmel_pctl_dt_node_to_map, 597 .dt_free_map = pinctrl_utils_free_map, 598 }; 599 600 static int atmel_pmx_get_functions_count(struct pinctrl_dev *pctldev) 601 { 602 return ARRAY_SIZE(atmel_functions); 603 } 604 605 static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev, 606 unsigned selector) 607 { 608 return atmel_functions[selector]; 609 } 610 611 static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev, 612 unsigned selector, 613 const char * const **groups, 614 unsigned * const num_groups) 615 { 616 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 617 618 *groups = atmel_pioctrl->group_names; 619 *num_groups = atmel_pioctrl->npins; 620 621 return 0; 622 } 623 624 static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev, 625 unsigned function, 626 unsigned group) 627 { 628 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 629 unsigned pin; 630 u32 conf; 631 632 dev_dbg(pctldev->dev, "enable function %s group %s\n", 633 atmel_functions[function], atmel_pioctrl->groups[group].name); 634 635 pin = atmel_pioctrl->groups[group].pin; 636 conf = atmel_pin_config_read(pctldev, pin); 637 conf &= (~ATMEL_PIO_CFGR_FUNC_MASK); 638 conf |= (function & ATMEL_PIO_CFGR_FUNC_MASK); 639 dev_dbg(pctldev->dev, "pin: %u, conf: 0x%08x\n", pin, conf); 640 atmel_pin_config_write(pctldev, pin, conf); 641 642 return 0; 643 } 644 645 static const struct pinmux_ops atmel_pmxops = { 646 .get_functions_count = atmel_pmx_get_functions_count, 647 .get_function_name = atmel_pmx_get_function_name, 648 .get_function_groups = atmel_pmx_get_function_groups, 649 .set_mux = atmel_pmx_set_mux, 650 }; 651 652 static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev, 653 unsigned group, 654 unsigned long *config) 655 { 656 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 657 unsigned param = pinconf_to_config_param(*config), arg = 0; 658 struct atmel_group *grp = atmel_pioctrl->groups + group; 659 unsigned pin_id = grp->pin; 660 u32 res; 661 662 res = atmel_pin_config_read(pctldev, pin_id); 663 664 switch (param) { 665 case PIN_CONFIG_BIAS_PULL_UP: 666 if (!(res & ATMEL_PIO_PUEN_MASK)) 667 return -EINVAL; 668 arg = 1; 669 break; 670 case PIN_CONFIG_BIAS_PULL_DOWN: 671 if ((res & ATMEL_PIO_PUEN_MASK) || 672 (!(res & ATMEL_PIO_PDEN_MASK))) 673 return -EINVAL; 674 arg = 1; 675 break; 676 case PIN_CONFIG_BIAS_DISABLE: 677 if ((res & ATMEL_PIO_PUEN_MASK) || 678 ((res & ATMEL_PIO_PDEN_MASK))) 679 return -EINVAL; 680 arg = 1; 681 break; 682 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 683 if (!(res & ATMEL_PIO_OPD_MASK)) 684 return -EINVAL; 685 arg = 1; 686 break; 687 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 688 if (!(res & ATMEL_PIO_SCHMITT_MASK)) 689 return -EINVAL; 690 arg = 1; 691 break; 692 case ATMEL_PIN_CONFIG_DRIVE_STRENGTH: 693 if (!(res & ATMEL_PIO_DRVSTR_MASK)) 694 return -EINVAL; 695 arg = (res & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET; 696 break; 697 default: 698 return -ENOTSUPP; 699 } 700 701 *config = pinconf_to_config_packed(param, arg); 702 return 0; 703 } 704 705 static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev, 706 unsigned group, 707 unsigned long *configs, 708 unsigned num_configs) 709 { 710 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 711 struct atmel_group *grp = atmel_pioctrl->groups + group; 712 unsigned bank, pin, pin_id = grp->pin; 713 u32 mask, conf = 0; 714 int i; 715 716 conf = atmel_pin_config_read(pctldev, pin_id); 717 718 for (i = 0; i < num_configs; i++) { 719 unsigned param = pinconf_to_config_param(configs[i]); 720 unsigned arg = pinconf_to_config_argument(configs[i]); 721 722 dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n", 723 __func__, pin_id, configs[i]); 724 725 switch (param) { 726 case PIN_CONFIG_BIAS_DISABLE: 727 conf &= (~ATMEL_PIO_PUEN_MASK); 728 conf &= (~ATMEL_PIO_PDEN_MASK); 729 break; 730 case PIN_CONFIG_BIAS_PULL_UP: 731 conf |= ATMEL_PIO_PUEN_MASK; 732 conf &= (~ATMEL_PIO_PDEN_MASK); 733 break; 734 case PIN_CONFIG_BIAS_PULL_DOWN: 735 conf |= ATMEL_PIO_PDEN_MASK; 736 conf &= (~ATMEL_PIO_PUEN_MASK); 737 break; 738 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 739 if (arg == 0) 740 conf &= (~ATMEL_PIO_OPD_MASK); 741 else 742 conf |= ATMEL_PIO_OPD_MASK; 743 break; 744 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 745 if (arg == 0) 746 conf |= ATMEL_PIO_SCHMITT_MASK; 747 else 748 conf &= (~ATMEL_PIO_SCHMITT_MASK); 749 break; 750 case PIN_CONFIG_INPUT_DEBOUNCE: 751 if (arg == 0) { 752 conf &= (~ATMEL_PIO_IFEN_MASK); 753 conf &= (~ATMEL_PIO_IFSCEN_MASK); 754 } else { 755 /* 756 * We don't care about the debounce value for several reasons: 757 * - can't have different debounce periods inside a same group, 758 * - the register to configure this period is a secure register. 759 * The debouncing filter can filter a pulse with a duration of less 760 * than 1/2 slow clock period. 761 */ 762 conf |= ATMEL_PIO_IFEN_MASK; 763 conf |= ATMEL_PIO_IFSCEN_MASK; 764 } 765 break; 766 case PIN_CONFIG_OUTPUT: 767 conf |= ATMEL_PIO_DIR_MASK; 768 bank = ATMEL_PIO_BANK(pin_id); 769 pin = ATMEL_PIO_LINE(pin_id); 770 mask = 1 << pin; 771 772 if (arg == 0) { 773 writel_relaxed(mask, atmel_pioctrl->reg_base + 774 bank * ATMEL_PIO_BANK_OFFSET + 775 ATMEL_PIO_CODR); 776 } else { 777 writel_relaxed(mask, atmel_pioctrl->reg_base + 778 bank * ATMEL_PIO_BANK_OFFSET + 779 ATMEL_PIO_SODR); 780 } 781 break; 782 case ATMEL_PIN_CONFIG_DRIVE_STRENGTH: 783 switch (arg) { 784 case ATMEL_PIO_DRVSTR_LO: 785 case ATMEL_PIO_DRVSTR_ME: 786 case ATMEL_PIO_DRVSTR_HI: 787 conf &= (~ATMEL_PIO_DRVSTR_MASK); 788 conf |= arg << ATMEL_PIO_DRVSTR_OFFSET; 789 break; 790 default: 791 dev_warn(pctldev->dev, "drive strength not updated (incorrect value)\n"); 792 } 793 break; 794 default: 795 dev_warn(pctldev->dev, 796 "unsupported configuration parameter: %u\n", 797 param); 798 continue; 799 } 800 } 801 802 dev_dbg(pctldev->dev, "%s: reg=0x%08x\n", __func__, conf); 803 atmel_pin_config_write(pctldev, pin_id, conf); 804 805 return 0; 806 } 807 808 static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev, 809 struct seq_file *s, unsigned pin_id) 810 { 811 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 812 u32 conf; 813 814 if (!atmel_pioctrl->pins[pin_id]->device) 815 return; 816 817 if (atmel_pioctrl->pins[pin_id]) 818 seq_printf(s, " (%s, ioset %u) ", 819 atmel_pioctrl->pins[pin_id]->device, 820 atmel_pioctrl->pins[pin_id]->ioset); 821 822 conf = atmel_pin_config_read(pctldev, pin_id); 823 if (conf & ATMEL_PIO_PUEN_MASK) 824 seq_printf(s, "%s ", "pull-up"); 825 if (conf & ATMEL_PIO_PDEN_MASK) 826 seq_printf(s, "%s ", "pull-down"); 827 if (conf & ATMEL_PIO_IFEN_MASK) 828 seq_printf(s, "%s ", "debounce"); 829 if (conf & ATMEL_PIO_OPD_MASK) 830 seq_printf(s, "%s ", "open-drain"); 831 if (conf & ATMEL_PIO_SCHMITT_MASK) 832 seq_printf(s, "%s ", "schmitt"); 833 if (conf & ATMEL_PIO_DRVSTR_MASK) { 834 switch ((conf & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET) { 835 case ATMEL_PIO_DRVSTR_ME: 836 seq_printf(s, "%s ", "medium-drive"); 837 break; 838 case ATMEL_PIO_DRVSTR_HI: 839 seq_printf(s, "%s ", "high-drive"); 840 break; 841 /* ATMEL_PIO_DRVSTR_LO and 0 which is the default value at reset */ 842 default: 843 seq_printf(s, "%s ", "low-drive"); 844 } 845 } 846 } 847 848 static const struct pinconf_ops atmel_confops = { 849 .pin_config_group_get = atmel_conf_pin_config_group_get, 850 .pin_config_group_set = atmel_conf_pin_config_group_set, 851 .pin_config_dbg_show = atmel_conf_pin_config_dbg_show, 852 }; 853 854 static struct pinctrl_desc atmel_pinctrl_desc = { 855 .name = "atmel_pinctrl", 856 .confops = &atmel_confops, 857 .pctlops = &atmel_pctlops, 858 .pmxops = &atmel_pmxops, 859 }; 860 861 static int __maybe_unused atmel_pctrl_suspend(struct device *dev) 862 { 863 struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev); 864 int i, j; 865 866 /* 867 * For each bank, save IMR to restore it later and disable all GPIO 868 * interrupts excepting the ones marked as wakeup sources. 869 */ 870 for (i = 0; i < atmel_pioctrl->nbanks; i++) { 871 atmel_pioctrl->pm_suspend_backup[i].imr = 872 atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_IMR); 873 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IDR, 874 ~atmel_pioctrl->pm_wakeup_sources[i]); 875 atmel_pioctrl->pm_suspend_backup[i].odsr = 876 atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_ODSR); 877 for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) { 878 atmel_gpio_write(atmel_pioctrl, i, 879 ATMEL_PIO_MSKR, BIT(j)); 880 atmel_pioctrl->pm_suspend_backup[i].cfgr[j] = 881 atmel_gpio_read(atmel_pioctrl, i, 882 ATMEL_PIO_CFGR); 883 } 884 } 885 886 return 0; 887 } 888 889 static int __maybe_unused atmel_pctrl_resume(struct device *dev) 890 { 891 struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev); 892 int i, j; 893 894 for (i = 0; i < atmel_pioctrl->nbanks; i++) { 895 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IER, 896 atmel_pioctrl->pm_suspend_backup[i].imr); 897 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_SODR, 898 atmel_pioctrl->pm_suspend_backup[i].odsr); 899 for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) { 900 atmel_gpio_write(atmel_pioctrl, i, 901 ATMEL_PIO_MSKR, BIT(j)); 902 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_CFGR, 903 atmel_pioctrl->pm_suspend_backup[i].cfgr[j]); 904 } 905 } 906 907 return 0; 908 } 909 910 static const struct dev_pm_ops atmel_pctrl_pm_ops = { 911 SET_SYSTEM_SLEEP_PM_OPS(atmel_pctrl_suspend, atmel_pctrl_resume) 912 }; 913 914 /* 915 * The number of banks can be different from a SoC to another one. 916 * We can have up to 16 banks. 917 */ 918 static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = { 919 .nbanks = 4, 920 }; 921 922 static const struct of_device_id atmel_pctrl_of_match[] = { 923 { 924 .compatible = "atmel,sama5d2-pinctrl", 925 .data = &atmel_sama5d2_pioctrl_data, 926 }, { 927 /* sentinel */ 928 } 929 }; 930 931 static int atmel_pinctrl_probe(struct platform_device *pdev) 932 { 933 struct device *dev = &pdev->dev; 934 struct pinctrl_pin_desc *pin_desc; 935 const char **group_names; 936 const struct of_device_id *match; 937 int i, ret; 938 struct resource *res; 939 struct atmel_pioctrl *atmel_pioctrl; 940 const struct atmel_pioctrl_data *atmel_pioctrl_data; 941 942 atmel_pioctrl = devm_kzalloc(dev, sizeof(*atmel_pioctrl), GFP_KERNEL); 943 if (!atmel_pioctrl) 944 return -ENOMEM; 945 atmel_pioctrl->dev = dev; 946 atmel_pioctrl->node = dev->of_node; 947 platform_set_drvdata(pdev, atmel_pioctrl); 948 949 match = of_match_node(atmel_pctrl_of_match, dev->of_node); 950 if (!match) { 951 dev_err(dev, "unknown compatible string\n"); 952 return -ENODEV; 953 } 954 atmel_pioctrl_data = match->data; 955 atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks; 956 atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK; 957 958 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 959 atmel_pioctrl->reg_base = devm_ioremap_resource(dev, res); 960 if (IS_ERR(atmel_pioctrl->reg_base)) 961 return -EINVAL; 962 963 atmel_pioctrl->clk = devm_clk_get(dev, NULL); 964 if (IS_ERR(atmel_pioctrl->clk)) { 965 dev_err(dev, "failed to get clock\n"); 966 return PTR_ERR(atmel_pioctrl->clk); 967 } 968 969 atmel_pioctrl->pins = devm_kcalloc(dev, 970 atmel_pioctrl->npins, 971 sizeof(*atmel_pioctrl->pins), 972 GFP_KERNEL); 973 if (!atmel_pioctrl->pins) 974 return -ENOMEM; 975 976 pin_desc = devm_kcalloc(dev, atmel_pioctrl->npins, sizeof(*pin_desc), 977 GFP_KERNEL); 978 if (!pin_desc) 979 return -ENOMEM; 980 atmel_pinctrl_desc.pins = pin_desc; 981 atmel_pinctrl_desc.npins = atmel_pioctrl->npins; 982 atmel_pinctrl_desc.num_custom_params = ARRAY_SIZE(atmel_custom_bindings); 983 atmel_pinctrl_desc.custom_params = atmel_custom_bindings; 984 985 /* One pin is one group since a pin can achieve all functions. */ 986 group_names = devm_kcalloc(dev, 987 atmel_pioctrl->npins, sizeof(*group_names), 988 GFP_KERNEL); 989 if (!group_names) 990 return -ENOMEM; 991 atmel_pioctrl->group_names = group_names; 992 993 atmel_pioctrl->groups = devm_kcalloc(&pdev->dev, 994 atmel_pioctrl->npins, sizeof(*atmel_pioctrl->groups), 995 GFP_KERNEL); 996 if (!atmel_pioctrl->groups) 997 return -ENOMEM; 998 for (i = 0 ; i < atmel_pioctrl->npins; i++) { 999 struct atmel_group *group = atmel_pioctrl->groups + i; 1000 unsigned bank = ATMEL_PIO_BANK(i); 1001 unsigned line = ATMEL_PIO_LINE(i); 1002 1003 atmel_pioctrl->pins[i] = devm_kzalloc(dev, 1004 sizeof(**atmel_pioctrl->pins), GFP_KERNEL); 1005 if (!atmel_pioctrl->pins[i]) 1006 return -ENOMEM; 1007 1008 atmel_pioctrl->pins[i]->pin_id = i; 1009 atmel_pioctrl->pins[i]->bank = bank; 1010 atmel_pioctrl->pins[i]->line = line; 1011 1012 pin_desc[i].number = i; 1013 /* Pin naming convention: P(bank_name)(bank_pin_number). */ 1014 pin_desc[i].name = kasprintf(GFP_KERNEL, "P%c%d", 1015 bank + 'A', line); 1016 1017 group->name = group_names[i] = pin_desc[i].name; 1018 group->pin = pin_desc[i].number; 1019 1020 dev_dbg(dev, "pin_id=%u, bank=%u, line=%u", i, bank, line); 1021 } 1022 1023 atmel_pioctrl->gpio_chip = &atmel_gpio_chip; 1024 atmel_pioctrl->gpio_chip->of_node = dev->of_node; 1025 atmel_pioctrl->gpio_chip->ngpio = atmel_pioctrl->npins; 1026 atmel_pioctrl->gpio_chip->label = dev_name(dev); 1027 atmel_pioctrl->gpio_chip->parent = dev; 1028 atmel_pioctrl->gpio_chip->names = atmel_pioctrl->group_names; 1029 1030 atmel_pioctrl->pm_wakeup_sources = devm_kcalloc(dev, 1031 atmel_pioctrl->nbanks, 1032 sizeof(*atmel_pioctrl->pm_wakeup_sources), 1033 GFP_KERNEL); 1034 if (!atmel_pioctrl->pm_wakeup_sources) 1035 return -ENOMEM; 1036 1037 atmel_pioctrl->pm_suspend_backup = devm_kcalloc(dev, 1038 atmel_pioctrl->nbanks, 1039 sizeof(*atmel_pioctrl->pm_suspend_backup), 1040 GFP_KERNEL); 1041 if (!atmel_pioctrl->pm_suspend_backup) 1042 return -ENOMEM; 1043 1044 atmel_pioctrl->irqs = devm_kcalloc(dev, 1045 atmel_pioctrl->nbanks, 1046 sizeof(*atmel_pioctrl->irqs), 1047 GFP_KERNEL); 1048 if (!atmel_pioctrl->irqs) 1049 return -ENOMEM; 1050 1051 /* There is one controller but each bank has its own irq line. */ 1052 for (i = 0; i < atmel_pioctrl->nbanks; i++) { 1053 res = platform_get_resource(pdev, IORESOURCE_IRQ, i); 1054 if (!res) { 1055 dev_err(dev, "missing irq resource for group %c\n", 1056 'A' + i); 1057 return -EINVAL; 1058 } 1059 atmel_pioctrl->irqs[i] = res->start; 1060 irq_set_chained_handler(res->start, atmel_gpio_irq_handler); 1061 irq_set_handler_data(res->start, atmel_pioctrl); 1062 dev_dbg(dev, "bank %i: irq=%pr\n", i, res); 1063 } 1064 1065 atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node, 1066 atmel_pioctrl->gpio_chip->ngpio, 1067 &irq_domain_simple_ops, NULL); 1068 if (!atmel_pioctrl->irq_domain) { 1069 dev_err(dev, "can't add the irq domain\n"); 1070 return -ENODEV; 1071 } 1072 atmel_pioctrl->irq_domain->name = "atmel gpio"; 1073 1074 for (i = 0; i < atmel_pioctrl->npins; i++) { 1075 int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i); 1076 1077 irq_set_chip_and_handler(irq, &atmel_gpio_irq_chip, 1078 handle_simple_irq); 1079 irq_set_chip_data(irq, atmel_pioctrl); 1080 dev_dbg(dev, 1081 "atmel gpio irq domain: hwirq: %d, linux irq: %d\n", 1082 i, irq); 1083 } 1084 1085 ret = clk_prepare_enable(atmel_pioctrl->clk); 1086 if (ret) { 1087 dev_err(dev, "failed to prepare and enable clock\n"); 1088 goto clk_prepare_enable_error; 1089 } 1090 1091 atmel_pioctrl->pinctrl_dev = devm_pinctrl_register(&pdev->dev, 1092 &atmel_pinctrl_desc, 1093 atmel_pioctrl); 1094 if (IS_ERR(atmel_pioctrl->pinctrl_dev)) { 1095 ret = PTR_ERR(atmel_pioctrl->pinctrl_dev); 1096 dev_err(dev, "pinctrl registration failed\n"); 1097 goto clk_unprep; 1098 } 1099 1100 ret = gpiochip_add_data(atmel_pioctrl->gpio_chip, atmel_pioctrl); 1101 if (ret) { 1102 dev_err(dev, "failed to add gpiochip\n"); 1103 goto clk_unprep; 1104 } 1105 1106 ret = gpiochip_add_pin_range(atmel_pioctrl->gpio_chip, dev_name(dev), 1107 0, 0, atmel_pioctrl->gpio_chip->ngpio); 1108 if (ret) { 1109 dev_err(dev, "failed to add gpio pin range\n"); 1110 goto gpiochip_add_pin_range_error; 1111 } 1112 1113 dev_info(&pdev->dev, "atmel pinctrl initialized\n"); 1114 1115 return 0; 1116 1117 gpiochip_add_pin_range_error: 1118 gpiochip_remove(atmel_pioctrl->gpio_chip); 1119 1120 clk_unprep: 1121 clk_disable_unprepare(atmel_pioctrl->clk); 1122 1123 clk_prepare_enable_error: 1124 irq_domain_remove(atmel_pioctrl->irq_domain); 1125 1126 return ret; 1127 } 1128 1129 static struct platform_driver atmel_pinctrl_driver = { 1130 .driver = { 1131 .name = "pinctrl-at91-pio4", 1132 .of_match_table = atmel_pctrl_of_match, 1133 .pm = &atmel_pctrl_pm_ops, 1134 .suppress_bind_attrs = true, 1135 }, 1136 .probe = atmel_pinctrl_probe, 1137 }; 1138 builtin_platform_driver(atmel_pinctrl_driver); 1139