1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for the Atmel PIO4 controller 4 * 5 * Copyright (C) 2015 Atmel, 6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 7 */ 8 9 #include <dt-bindings/pinctrl/at91.h> 10 #include <linux/clk.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/init.h> 15 #include <linux/of.h> 16 #include <linux/platform_device.h> 17 #include <linux/pinctrl/pinconf.h> 18 #include <linux/pinctrl/pinconf-generic.h> 19 #include <linux/pinctrl/pinctrl.h> 20 #include <linux/pinctrl/pinmux.h> 21 #include <linux/slab.h> 22 #include "core.h" 23 #include "pinconf.h" 24 #include "pinctrl-utils.h" 25 26 /* 27 * Warning: 28 * In order to not introduce confusion between Atmel PIO groups and pinctrl 29 * framework groups, Atmel PIO groups will be called banks, line is kept to 30 * designed the pin id into this bank. 31 */ 32 33 #define ATMEL_PIO_MSKR 0x0000 34 #define ATMEL_PIO_CFGR 0x0004 35 #define ATMEL_PIO_CFGR_FUNC_MASK GENMASK(2, 0) 36 #define ATMEL_PIO_DIR_MASK BIT(8) 37 #define ATMEL_PIO_PUEN_MASK BIT(9) 38 #define ATMEL_PIO_PDEN_MASK BIT(10) 39 #define ATMEL_PIO_SR_MASK BIT(11) 40 #define ATMEL_PIO_IFEN_MASK BIT(12) 41 #define ATMEL_PIO_IFSCEN_MASK BIT(13) 42 #define ATMEL_PIO_OPD_MASK BIT(14) 43 #define ATMEL_PIO_SCHMITT_MASK BIT(15) 44 #define ATMEL_PIO_DRVSTR_MASK GENMASK(17, 16) 45 #define ATMEL_PIO_DRVSTR_OFFSET 16 46 #define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24) 47 #define ATMEL_PIO_CFGR_EVTSEL_FALLING (0 << 24) 48 #define ATMEL_PIO_CFGR_EVTSEL_RISING (1 << 24) 49 #define ATMEL_PIO_CFGR_EVTSEL_BOTH (2 << 24) 50 #define ATMEL_PIO_CFGR_EVTSEL_LOW (3 << 24) 51 #define ATMEL_PIO_CFGR_EVTSEL_HIGH (4 << 24) 52 #define ATMEL_PIO_PDSR 0x0008 53 #define ATMEL_PIO_LOCKSR 0x000C 54 #define ATMEL_PIO_SODR 0x0010 55 #define ATMEL_PIO_CODR 0x0014 56 #define ATMEL_PIO_ODSR 0x0018 57 #define ATMEL_PIO_IER 0x0020 58 #define ATMEL_PIO_IDR 0x0024 59 #define ATMEL_PIO_IMR 0x0028 60 #define ATMEL_PIO_ISR 0x002C 61 #define ATMEL_PIO_IOFR 0x003C 62 63 #define ATMEL_PIO_NPINS_PER_BANK 32 64 #define ATMEL_PIO_BANK(pin_id) (pin_id / ATMEL_PIO_NPINS_PER_BANK) 65 #define ATMEL_PIO_LINE(pin_id) (pin_id % ATMEL_PIO_NPINS_PER_BANK) 66 #define ATMEL_PIO_BANK_OFFSET 0x40 67 68 #define ATMEL_GET_PIN_NO(pinfunc) ((pinfunc) & 0xff) 69 #define ATMEL_GET_PIN_FUNC(pinfunc) ((pinfunc >> 16) & 0xf) 70 #define ATMEL_GET_PIN_IOSET(pinfunc) ((pinfunc >> 20) & 0xf) 71 72 /* Custom pinconf parameters */ 73 #define ATMEL_PIN_CONFIG_DRIVE_STRENGTH (PIN_CONFIG_END + 1) 74 75 /** 76 * struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct 77 * @nbanks: number of PIO banks 78 * @last_bank_count: number of lines in the last bank (can be less than 79 * the rest of the banks). 80 * @slew_rate_support: slew rate support 81 */ 82 struct atmel_pioctrl_data { 83 unsigned int nbanks; 84 unsigned int last_bank_count; 85 unsigned int slew_rate_support; 86 }; 87 88 struct atmel_group { 89 const char *name; 90 u32 pin; 91 }; 92 93 struct atmel_pin { 94 unsigned int pin_id; 95 unsigned int mux; 96 unsigned int ioset; 97 unsigned int bank; 98 unsigned int line; 99 const char *device; 100 }; 101 102 /** 103 * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio) 104 * @reg_base: base address of the controller. 105 * @clk: clock of the controller. 106 * @nbanks: number of PIO groups, it can vary depending on the SoC. 107 * @pinctrl_dev: pinctrl device registered. 108 * @groups: groups table to provide group name and pin in the group to pinctrl. 109 * @group_names: group names table to provide all the group/pin names to 110 * pinctrl or gpio. 111 * @pins: pins table used for both pinctrl and gpio. pin_id, bank and line 112 * fields are set at probe time. Other ones are set when parsing dt 113 * pinctrl. 114 * @npins: number of pins. 115 * @gpio_chip: gpio chip registered. 116 * @irq_domain: irq domain for the gpio controller. 117 * @irqs: table containing the hw irq number of the bank. The index of the 118 * table is the bank id. 119 * @pm_wakeup_sources: bitmap of wakeup sources (lines) 120 * @pm_suspend_backup: backup/restore register values on suspend/resume 121 * @dev: device entry for the Atmel PIO controller. 122 * @node: node of the Atmel PIO controller. 123 * @slew_rate_support: slew rate support 124 */ 125 struct atmel_pioctrl { 126 void __iomem *reg_base; 127 struct clk *clk; 128 unsigned int nbanks; 129 struct pinctrl_dev *pinctrl_dev; 130 struct atmel_group *groups; 131 const char * const *group_names; 132 struct atmel_pin **pins; 133 unsigned int npins; 134 struct gpio_chip *gpio_chip; 135 struct irq_domain *irq_domain; 136 int *irqs; 137 unsigned int *pm_wakeup_sources; 138 struct { 139 u32 imr; 140 u32 odsr; 141 u32 cfgr[ATMEL_PIO_NPINS_PER_BANK]; 142 } *pm_suspend_backup; 143 struct device *dev; 144 struct device_node *node; 145 unsigned int slew_rate_support; 146 }; 147 148 static const char * const atmel_functions[] = { 149 "GPIO", "A", "B", "C", "D", "E", "F", "G" 150 }; 151 152 static const struct pinconf_generic_params atmel_custom_bindings[] = { 153 {"atmel,drive-strength", ATMEL_PIN_CONFIG_DRIVE_STRENGTH, 0}, 154 }; 155 156 /* --- GPIO --- */ 157 static unsigned int atmel_gpio_read(struct atmel_pioctrl *atmel_pioctrl, 158 unsigned int bank, unsigned int reg) 159 { 160 return readl_relaxed(atmel_pioctrl->reg_base 161 + ATMEL_PIO_BANK_OFFSET * bank + reg); 162 } 163 164 static void atmel_gpio_write(struct atmel_pioctrl *atmel_pioctrl, 165 unsigned int bank, unsigned int reg, 166 unsigned int val) 167 { 168 writel_relaxed(val, atmel_pioctrl->reg_base 169 + ATMEL_PIO_BANK_OFFSET * bank + reg); 170 } 171 172 static void atmel_gpio_irq_ack(struct irq_data *d) 173 { 174 /* 175 * Nothing to do, interrupt is cleared when reading the status 176 * register. 177 */ 178 } 179 180 static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned int type) 181 { 182 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); 183 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; 184 unsigned int reg; 185 186 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, 187 BIT(pin->line)); 188 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); 189 reg &= (~ATMEL_PIO_CFGR_EVTSEL_MASK); 190 191 switch (type) { 192 case IRQ_TYPE_EDGE_RISING: 193 irq_set_handler_locked(d, handle_edge_irq); 194 reg |= ATMEL_PIO_CFGR_EVTSEL_RISING; 195 break; 196 case IRQ_TYPE_EDGE_FALLING: 197 irq_set_handler_locked(d, handle_edge_irq); 198 reg |= ATMEL_PIO_CFGR_EVTSEL_FALLING; 199 break; 200 case IRQ_TYPE_EDGE_BOTH: 201 irq_set_handler_locked(d, handle_edge_irq); 202 reg |= ATMEL_PIO_CFGR_EVTSEL_BOTH; 203 break; 204 case IRQ_TYPE_LEVEL_LOW: 205 irq_set_handler_locked(d, handle_level_irq); 206 reg |= ATMEL_PIO_CFGR_EVTSEL_LOW; 207 break; 208 case IRQ_TYPE_LEVEL_HIGH: 209 irq_set_handler_locked(d, handle_level_irq); 210 reg |= ATMEL_PIO_CFGR_EVTSEL_HIGH; 211 break; 212 case IRQ_TYPE_NONE: 213 default: 214 return -EINVAL; 215 } 216 217 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); 218 219 return 0; 220 } 221 222 static void atmel_gpio_irq_mask(struct irq_data *d) 223 { 224 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); 225 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; 226 227 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR, 228 BIT(pin->line)); 229 } 230 231 static void atmel_gpio_irq_unmask(struct irq_data *d) 232 { 233 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); 234 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; 235 236 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IER, 237 BIT(pin->line)); 238 } 239 240 #ifdef CONFIG_PM_SLEEP 241 242 static int atmel_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 243 { 244 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); 245 int bank = ATMEL_PIO_BANK(d->hwirq); 246 int line = ATMEL_PIO_LINE(d->hwirq); 247 248 /* The gpio controller has one interrupt line per bank. */ 249 irq_set_irq_wake(atmel_pioctrl->irqs[bank], on); 250 251 if (on) 252 atmel_pioctrl->pm_wakeup_sources[bank] |= BIT(line); 253 else 254 atmel_pioctrl->pm_wakeup_sources[bank] &= ~(BIT(line)); 255 256 return 0; 257 } 258 #else 259 #define atmel_gpio_irq_set_wake NULL 260 #endif /* CONFIG_PM_SLEEP */ 261 262 static struct irq_chip atmel_gpio_irq_chip = { 263 .name = "GPIO", 264 .irq_ack = atmel_gpio_irq_ack, 265 .irq_mask = atmel_gpio_irq_mask, 266 .irq_unmask = atmel_gpio_irq_unmask, 267 .irq_set_type = atmel_gpio_irq_set_type, 268 .irq_set_wake = atmel_gpio_irq_set_wake, 269 }; 270 271 static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) 272 { 273 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); 274 275 return irq_find_mapping(atmel_pioctrl->irq_domain, offset); 276 } 277 278 static void atmel_gpio_irq_handler(struct irq_desc *desc) 279 { 280 unsigned int irq = irq_desc_get_irq(desc); 281 struct atmel_pioctrl *atmel_pioctrl = irq_desc_get_handler_data(desc); 282 struct irq_chip *chip = irq_desc_get_chip(desc); 283 unsigned long isr; 284 int n, bank = -1; 285 286 /* Find from which bank is the irq received. */ 287 for (n = 0; n < atmel_pioctrl->nbanks; n++) { 288 if (atmel_pioctrl->irqs[n] == irq) { 289 bank = n; 290 break; 291 } 292 } 293 294 if (bank < 0) { 295 dev_err(atmel_pioctrl->dev, 296 "no bank associated to irq %u\n", irq); 297 return; 298 } 299 300 chained_irq_enter(chip, desc); 301 302 for (;;) { 303 isr = (unsigned long)atmel_gpio_read(atmel_pioctrl, bank, 304 ATMEL_PIO_ISR); 305 isr &= (unsigned long)atmel_gpio_read(atmel_pioctrl, bank, 306 ATMEL_PIO_IMR); 307 if (!isr) 308 break; 309 310 for_each_set_bit(n, &isr, BITS_PER_LONG) 311 generic_handle_irq(atmel_gpio_to_irq( 312 atmel_pioctrl->gpio_chip, 313 bank * ATMEL_PIO_NPINS_PER_BANK + n)); 314 } 315 316 chained_irq_exit(chip, desc); 317 } 318 319 static int atmel_gpio_direction_input(struct gpio_chip *chip, 320 unsigned int offset) 321 { 322 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); 323 struct atmel_pin *pin = atmel_pioctrl->pins[offset]; 324 unsigned int reg; 325 326 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, 327 BIT(pin->line)); 328 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); 329 reg &= ~ATMEL_PIO_DIR_MASK; 330 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); 331 332 return 0; 333 } 334 335 static int atmel_gpio_get(struct gpio_chip *chip, unsigned int offset) 336 { 337 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); 338 struct atmel_pin *pin = atmel_pioctrl->pins[offset]; 339 unsigned int reg; 340 341 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR); 342 343 return !!(reg & BIT(pin->line)); 344 } 345 346 static int atmel_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, 347 unsigned long *bits) 348 { 349 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); 350 unsigned int bank; 351 352 bitmap_zero(bits, atmel_pioctrl->npins); 353 354 for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) { 355 unsigned int word = bank; 356 unsigned int offset = 0; 357 unsigned int reg; 358 359 #if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG 360 word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK); 361 offset = bank * ATMEL_PIO_NPINS_PER_BANK % BITS_PER_LONG; 362 #endif 363 if (!mask[word]) 364 continue; 365 366 reg = atmel_gpio_read(atmel_pioctrl, bank, ATMEL_PIO_PDSR); 367 bits[word] |= mask[word] & (reg << offset); 368 } 369 370 return 0; 371 } 372 373 static int atmel_gpio_direction_output(struct gpio_chip *chip, 374 unsigned int offset, 375 int value) 376 { 377 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); 378 struct atmel_pin *pin = atmel_pioctrl->pins[offset]; 379 unsigned int reg; 380 381 atmel_gpio_write(atmel_pioctrl, pin->bank, 382 value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR, 383 BIT(pin->line)); 384 385 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, 386 BIT(pin->line)); 387 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); 388 reg |= ATMEL_PIO_DIR_MASK; 389 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); 390 391 return 0; 392 } 393 394 static void atmel_gpio_set(struct gpio_chip *chip, unsigned int offset, int val) 395 { 396 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); 397 struct atmel_pin *pin = atmel_pioctrl->pins[offset]; 398 399 atmel_gpio_write(atmel_pioctrl, pin->bank, 400 val ? ATMEL_PIO_SODR : ATMEL_PIO_CODR, 401 BIT(pin->line)); 402 } 403 404 static void atmel_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask, 405 unsigned long *bits) 406 { 407 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); 408 unsigned int bank; 409 410 for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) { 411 unsigned int bitmask; 412 unsigned int word = bank; 413 414 /* 415 * On a 64-bit platform, BITS_PER_LONG is 64 so it is necessary to iterate over 416 * two 32bit words to handle the whole bitmask 417 */ 418 #if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG 419 word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK); 420 #endif 421 if (!mask[word]) 422 continue; 423 424 bitmask = mask[word] & bits[word]; 425 atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_SODR, bitmask); 426 427 bitmask = mask[word] & ~bits[word]; 428 atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_CODR, bitmask); 429 430 #if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG 431 mask[word] >>= ATMEL_PIO_NPINS_PER_BANK; 432 bits[word] >>= ATMEL_PIO_NPINS_PER_BANK; 433 #endif 434 } 435 } 436 437 static struct gpio_chip atmel_gpio_chip = { 438 .direction_input = atmel_gpio_direction_input, 439 .get = atmel_gpio_get, 440 .get_multiple = atmel_gpio_get_multiple, 441 .direction_output = atmel_gpio_direction_output, 442 .set = atmel_gpio_set, 443 .set_multiple = atmel_gpio_set_multiple, 444 .to_irq = atmel_gpio_to_irq, 445 .base = 0, 446 }; 447 448 /* --- PINCTRL --- */ 449 static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev, 450 unsigned int pin_id) 451 { 452 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 453 unsigned int bank = atmel_pioctrl->pins[pin_id]->bank; 454 unsigned int line = atmel_pioctrl->pins[pin_id]->line; 455 void __iomem *addr = atmel_pioctrl->reg_base 456 + bank * ATMEL_PIO_BANK_OFFSET; 457 458 writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR); 459 /* Have to set MSKR first, to access the right pin CFGR. */ 460 wmb(); 461 462 return readl_relaxed(addr + ATMEL_PIO_CFGR); 463 } 464 465 static void atmel_pin_config_write(struct pinctrl_dev *pctldev, 466 unsigned int pin_id, u32 conf) 467 { 468 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 469 unsigned int bank = atmel_pioctrl->pins[pin_id]->bank; 470 unsigned int line = atmel_pioctrl->pins[pin_id]->line; 471 void __iomem *addr = atmel_pioctrl->reg_base 472 + bank * ATMEL_PIO_BANK_OFFSET; 473 474 writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR); 475 /* Have to set MSKR first, to access the right pin CFGR. */ 476 wmb(); 477 writel_relaxed(conf, addr + ATMEL_PIO_CFGR); 478 } 479 480 static int atmel_pctl_get_groups_count(struct pinctrl_dev *pctldev) 481 { 482 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 483 484 return atmel_pioctrl->npins; 485 } 486 487 static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev, 488 unsigned int selector) 489 { 490 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 491 492 return atmel_pioctrl->groups[selector].name; 493 } 494 495 static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev, 496 unsigned int selector, 497 const unsigned int **pins, 498 unsigned int *num_pins) 499 { 500 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 501 502 *pins = (unsigned int *)&atmel_pioctrl->groups[selector].pin; 503 *num_pins = 1; 504 505 return 0; 506 } 507 508 static struct atmel_group * 509 atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned int pin) 510 { 511 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 512 int i; 513 514 for (i = 0; i < atmel_pioctrl->npins; i++) { 515 struct atmel_group *grp = atmel_pioctrl->groups + i; 516 517 if (grp->pin == pin) 518 return grp; 519 } 520 521 return NULL; 522 } 523 524 static int atmel_pctl_xlate_pinfunc(struct pinctrl_dev *pctldev, 525 struct device_node *np, 526 u32 pinfunc, const char **grp_name, 527 const char **func_name) 528 { 529 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 530 unsigned int pin_id, func_id; 531 struct atmel_group *grp; 532 533 pin_id = ATMEL_GET_PIN_NO(pinfunc); 534 func_id = ATMEL_GET_PIN_FUNC(pinfunc); 535 536 if (func_id >= ARRAY_SIZE(atmel_functions)) 537 return -EINVAL; 538 539 *func_name = atmel_functions[func_id]; 540 541 grp = atmel_pctl_find_group_by_pin(pctldev, pin_id); 542 if (!grp) 543 return -EINVAL; 544 *grp_name = grp->name; 545 546 atmel_pioctrl->pins[pin_id]->mux = func_id; 547 atmel_pioctrl->pins[pin_id]->ioset = ATMEL_GET_PIN_IOSET(pinfunc); 548 /* Want the device name not the group one. */ 549 if (np->parent == atmel_pioctrl->node) 550 atmel_pioctrl->pins[pin_id]->device = np->name; 551 else 552 atmel_pioctrl->pins[pin_id]->device = np->parent->name; 553 554 return 0; 555 } 556 557 static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 558 struct device_node *np, 559 struct pinctrl_map **map, 560 unsigned int *reserved_maps, 561 unsigned int *num_maps) 562 { 563 unsigned int num_pins, num_configs, reserve; 564 unsigned long *configs; 565 struct property *pins; 566 u32 pinfunc; 567 int ret, i; 568 569 pins = of_find_property(np, "pinmux", NULL); 570 if (!pins) 571 return -EINVAL; 572 573 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, 574 &num_configs); 575 if (ret < 0) { 576 dev_err(pctldev->dev, "%pOF: could not parse node property\n", 577 np); 578 return ret; 579 } 580 581 num_pins = pins->length / sizeof(u32); 582 if (!num_pins) { 583 dev_err(pctldev->dev, "no pins found in node %pOF\n", np); 584 ret = -EINVAL; 585 goto exit; 586 } 587 588 /* 589 * Reserve maps, at least there is a mux map and an optional conf 590 * map for each pin. 591 */ 592 reserve = 1; 593 if (num_configs) 594 reserve++; 595 reserve *= num_pins; 596 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps, 597 reserve); 598 if (ret < 0) 599 goto exit; 600 601 for (i = 0; i < num_pins; i++) { 602 const char *group, *func; 603 604 ret = of_property_read_u32_index(np, "pinmux", i, &pinfunc); 605 if (ret) 606 goto exit; 607 608 ret = atmel_pctl_xlate_pinfunc(pctldev, np, pinfunc, &group, 609 &func); 610 if (ret) 611 goto exit; 612 613 pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps, 614 group, func); 615 616 if (num_configs) { 617 ret = pinctrl_utils_add_map_configs(pctldev, map, 618 reserved_maps, num_maps, group, 619 configs, num_configs, 620 PIN_MAP_TYPE_CONFIGS_GROUP); 621 if (ret < 0) 622 goto exit; 623 } 624 } 625 626 exit: 627 kfree(configs); 628 return ret; 629 } 630 631 static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, 632 struct device_node *np_config, 633 struct pinctrl_map **map, 634 unsigned int *num_maps) 635 { 636 struct device_node *np; 637 unsigned int reserved_maps; 638 int ret; 639 640 *map = NULL; 641 *num_maps = 0; 642 reserved_maps = 0; 643 644 /* 645 * If all the pins of a device have the same configuration (or no one), 646 * it is useless to add a subnode, so directly parse node referenced by 647 * phandle. 648 */ 649 ret = atmel_pctl_dt_subnode_to_map(pctldev, np_config, map, 650 &reserved_maps, num_maps); 651 if (ret) { 652 for_each_child_of_node(np_config, np) { 653 ret = atmel_pctl_dt_subnode_to_map(pctldev, np, map, 654 &reserved_maps, num_maps); 655 if (ret < 0) { 656 of_node_put(np); 657 break; 658 } 659 } 660 } 661 662 if (ret < 0) { 663 pinctrl_utils_free_map(pctldev, *map, *num_maps); 664 dev_err(pctldev->dev, "can't create maps for node %pOF\n", 665 np_config); 666 } 667 668 return ret; 669 } 670 671 static const struct pinctrl_ops atmel_pctlops = { 672 .get_groups_count = atmel_pctl_get_groups_count, 673 .get_group_name = atmel_pctl_get_group_name, 674 .get_group_pins = atmel_pctl_get_group_pins, 675 .dt_node_to_map = atmel_pctl_dt_node_to_map, 676 .dt_free_map = pinctrl_utils_free_map, 677 }; 678 679 static int atmel_pmx_get_functions_count(struct pinctrl_dev *pctldev) 680 { 681 return ARRAY_SIZE(atmel_functions); 682 } 683 684 static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev, 685 unsigned int selector) 686 { 687 return atmel_functions[selector]; 688 } 689 690 static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev, 691 unsigned int selector, 692 const char * const **groups, 693 unsigned * const num_groups) 694 { 695 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 696 697 *groups = atmel_pioctrl->group_names; 698 *num_groups = atmel_pioctrl->npins; 699 700 return 0; 701 } 702 703 static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev, 704 unsigned int function, 705 unsigned int group) 706 { 707 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 708 unsigned int pin; 709 u32 conf; 710 711 dev_dbg(pctldev->dev, "enable function %s group %s\n", 712 atmel_functions[function], atmel_pioctrl->groups[group].name); 713 714 pin = atmel_pioctrl->groups[group].pin; 715 conf = atmel_pin_config_read(pctldev, pin); 716 conf &= (~ATMEL_PIO_CFGR_FUNC_MASK); 717 conf |= (function & ATMEL_PIO_CFGR_FUNC_MASK); 718 dev_dbg(pctldev->dev, "pin: %u, conf: 0x%08x\n", pin, conf); 719 atmel_pin_config_write(pctldev, pin, conf); 720 721 return 0; 722 } 723 724 static const struct pinmux_ops atmel_pmxops = { 725 .get_functions_count = atmel_pmx_get_functions_count, 726 .get_function_name = atmel_pmx_get_function_name, 727 .get_function_groups = atmel_pmx_get_function_groups, 728 .set_mux = atmel_pmx_set_mux, 729 }; 730 731 static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev, 732 unsigned int group, 733 unsigned long *config) 734 { 735 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 736 unsigned int param = pinconf_to_config_param(*config), arg = 0; 737 struct atmel_group *grp = atmel_pioctrl->groups + group; 738 unsigned int pin_id = grp->pin; 739 u32 res; 740 741 res = atmel_pin_config_read(pctldev, pin_id); 742 743 switch (param) { 744 case PIN_CONFIG_BIAS_PULL_UP: 745 if (!(res & ATMEL_PIO_PUEN_MASK)) 746 return -EINVAL; 747 arg = 1; 748 break; 749 case PIN_CONFIG_BIAS_PULL_DOWN: 750 if ((res & ATMEL_PIO_PUEN_MASK) || 751 (!(res & ATMEL_PIO_PDEN_MASK))) 752 return -EINVAL; 753 arg = 1; 754 break; 755 case PIN_CONFIG_BIAS_DISABLE: 756 if ((res & ATMEL_PIO_PUEN_MASK) || 757 ((res & ATMEL_PIO_PDEN_MASK))) 758 return -EINVAL; 759 arg = 1; 760 break; 761 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 762 if (!(res & ATMEL_PIO_OPD_MASK)) 763 return -EINVAL; 764 arg = 1; 765 break; 766 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 767 if (!(res & ATMEL_PIO_SCHMITT_MASK)) 768 return -EINVAL; 769 arg = 1; 770 break; 771 case PIN_CONFIG_SLEW_RATE: 772 if (!atmel_pioctrl->slew_rate_support) 773 return -EOPNOTSUPP; 774 if (!(res & ATMEL_PIO_SR_MASK)) 775 return -EINVAL; 776 arg = 1; 777 break; 778 case ATMEL_PIN_CONFIG_DRIVE_STRENGTH: 779 if (!(res & ATMEL_PIO_DRVSTR_MASK)) 780 return -EINVAL; 781 arg = (res & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET; 782 break; 783 default: 784 return -ENOTSUPP; 785 } 786 787 *config = pinconf_to_config_packed(param, arg); 788 return 0; 789 } 790 791 static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev, 792 unsigned int group, 793 unsigned long *configs, 794 unsigned int num_configs) 795 { 796 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 797 struct atmel_group *grp = atmel_pioctrl->groups + group; 798 unsigned int bank, pin, pin_id = grp->pin; 799 u32 mask, conf = 0; 800 int i; 801 802 conf = atmel_pin_config_read(pctldev, pin_id); 803 804 /* Keep slew rate enabled by default. */ 805 if (atmel_pioctrl->slew_rate_support) 806 conf |= ATMEL_PIO_SR_MASK; 807 808 for (i = 0; i < num_configs; i++) { 809 unsigned int param = pinconf_to_config_param(configs[i]); 810 unsigned int arg = pinconf_to_config_argument(configs[i]); 811 812 dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n", 813 __func__, pin_id, configs[i]); 814 815 switch (param) { 816 case PIN_CONFIG_BIAS_DISABLE: 817 conf &= (~ATMEL_PIO_PUEN_MASK); 818 conf &= (~ATMEL_PIO_PDEN_MASK); 819 break; 820 case PIN_CONFIG_BIAS_PULL_UP: 821 conf |= ATMEL_PIO_PUEN_MASK; 822 conf &= (~ATMEL_PIO_PDEN_MASK); 823 break; 824 case PIN_CONFIG_BIAS_PULL_DOWN: 825 conf |= ATMEL_PIO_PDEN_MASK; 826 conf &= (~ATMEL_PIO_PUEN_MASK); 827 break; 828 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 829 if (arg == 0) 830 conf &= (~ATMEL_PIO_OPD_MASK); 831 else 832 conf |= ATMEL_PIO_OPD_MASK; 833 break; 834 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 835 if (arg == 0) 836 conf |= ATMEL_PIO_SCHMITT_MASK; 837 else 838 conf &= (~ATMEL_PIO_SCHMITT_MASK); 839 break; 840 case PIN_CONFIG_INPUT_DEBOUNCE: 841 if (arg == 0) { 842 conf &= (~ATMEL_PIO_IFEN_MASK); 843 conf &= (~ATMEL_PIO_IFSCEN_MASK); 844 } else { 845 /* 846 * We don't care about the debounce value for several reasons: 847 * - can't have different debounce periods inside a same group, 848 * - the register to configure this period is a secure register. 849 * The debouncing filter can filter a pulse with a duration of less 850 * than 1/2 slow clock period. 851 */ 852 conf |= ATMEL_PIO_IFEN_MASK; 853 conf |= ATMEL_PIO_IFSCEN_MASK; 854 } 855 break; 856 case PIN_CONFIG_OUTPUT: 857 conf |= ATMEL_PIO_DIR_MASK; 858 bank = ATMEL_PIO_BANK(pin_id); 859 pin = ATMEL_PIO_LINE(pin_id); 860 mask = 1 << pin; 861 862 if (arg == 0) { 863 writel_relaxed(mask, atmel_pioctrl->reg_base + 864 bank * ATMEL_PIO_BANK_OFFSET + 865 ATMEL_PIO_CODR); 866 } else { 867 writel_relaxed(mask, atmel_pioctrl->reg_base + 868 bank * ATMEL_PIO_BANK_OFFSET + 869 ATMEL_PIO_SODR); 870 } 871 break; 872 case PIN_CONFIG_SLEW_RATE: 873 if (!atmel_pioctrl->slew_rate_support) 874 break; 875 /* And remove it if explicitly requested. */ 876 if (arg == 0) 877 conf &= ~ATMEL_PIO_SR_MASK; 878 break; 879 case ATMEL_PIN_CONFIG_DRIVE_STRENGTH: 880 switch (arg) { 881 case ATMEL_PIO_DRVSTR_LO: 882 case ATMEL_PIO_DRVSTR_ME: 883 case ATMEL_PIO_DRVSTR_HI: 884 conf &= (~ATMEL_PIO_DRVSTR_MASK); 885 conf |= arg << ATMEL_PIO_DRVSTR_OFFSET; 886 break; 887 default: 888 dev_warn(pctldev->dev, "drive strength not updated (incorrect value)\n"); 889 } 890 break; 891 default: 892 dev_warn(pctldev->dev, 893 "unsupported configuration parameter: %u\n", 894 param); 895 continue; 896 } 897 } 898 899 dev_dbg(pctldev->dev, "%s: reg=0x%08x\n", __func__, conf); 900 atmel_pin_config_write(pctldev, pin_id, conf); 901 902 return 0; 903 } 904 905 static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev, 906 struct seq_file *s, 907 unsigned int pin_id) 908 { 909 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); 910 u32 conf; 911 912 if (!atmel_pioctrl->pins[pin_id]->device) 913 return; 914 915 if (atmel_pioctrl->pins[pin_id]) 916 seq_printf(s, " (%s, ioset %u) ", 917 atmel_pioctrl->pins[pin_id]->device, 918 atmel_pioctrl->pins[pin_id]->ioset); 919 920 conf = atmel_pin_config_read(pctldev, pin_id); 921 if (conf & ATMEL_PIO_PUEN_MASK) 922 seq_printf(s, "%s ", "pull-up"); 923 if (conf & ATMEL_PIO_PDEN_MASK) 924 seq_printf(s, "%s ", "pull-down"); 925 if (conf & ATMEL_PIO_IFEN_MASK) 926 seq_printf(s, "%s ", "debounce"); 927 if (conf & ATMEL_PIO_OPD_MASK) 928 seq_printf(s, "%s ", "open-drain"); 929 if (conf & ATMEL_PIO_SCHMITT_MASK) 930 seq_printf(s, "%s ", "schmitt"); 931 if (atmel_pioctrl->slew_rate_support && (conf & ATMEL_PIO_SR_MASK)) 932 seq_printf(s, "%s ", "slew-rate"); 933 if (conf & ATMEL_PIO_DRVSTR_MASK) { 934 switch ((conf & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET) { 935 case ATMEL_PIO_DRVSTR_ME: 936 seq_printf(s, "%s ", "medium-drive"); 937 break; 938 case ATMEL_PIO_DRVSTR_HI: 939 seq_printf(s, "%s ", "high-drive"); 940 break; 941 /* ATMEL_PIO_DRVSTR_LO and 0 which is the default value at reset */ 942 default: 943 seq_printf(s, "%s ", "low-drive"); 944 } 945 } 946 } 947 948 static const struct pinconf_ops atmel_confops = { 949 .pin_config_group_get = atmel_conf_pin_config_group_get, 950 .pin_config_group_set = atmel_conf_pin_config_group_set, 951 .pin_config_dbg_show = atmel_conf_pin_config_dbg_show, 952 }; 953 954 static struct pinctrl_desc atmel_pinctrl_desc = { 955 .name = "atmel_pinctrl", 956 .confops = &atmel_confops, 957 .pctlops = &atmel_pctlops, 958 .pmxops = &atmel_pmxops, 959 }; 960 961 static int __maybe_unused atmel_pctrl_suspend(struct device *dev) 962 { 963 struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev); 964 int i, j; 965 966 /* 967 * For each bank, save IMR to restore it later and disable all GPIO 968 * interrupts excepting the ones marked as wakeup sources. 969 */ 970 for (i = 0; i < atmel_pioctrl->nbanks; i++) { 971 atmel_pioctrl->pm_suspend_backup[i].imr = 972 atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_IMR); 973 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IDR, 974 ~atmel_pioctrl->pm_wakeup_sources[i]); 975 atmel_pioctrl->pm_suspend_backup[i].odsr = 976 atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_ODSR); 977 for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) { 978 atmel_gpio_write(atmel_pioctrl, i, 979 ATMEL_PIO_MSKR, BIT(j)); 980 atmel_pioctrl->pm_suspend_backup[i].cfgr[j] = 981 atmel_gpio_read(atmel_pioctrl, i, 982 ATMEL_PIO_CFGR); 983 } 984 } 985 986 return 0; 987 } 988 989 static int __maybe_unused atmel_pctrl_resume(struct device *dev) 990 { 991 struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev); 992 int i, j; 993 994 for (i = 0; i < atmel_pioctrl->nbanks; i++) { 995 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IER, 996 atmel_pioctrl->pm_suspend_backup[i].imr); 997 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_SODR, 998 atmel_pioctrl->pm_suspend_backup[i].odsr); 999 for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) { 1000 atmel_gpio_write(atmel_pioctrl, i, 1001 ATMEL_PIO_MSKR, BIT(j)); 1002 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_CFGR, 1003 atmel_pioctrl->pm_suspend_backup[i].cfgr[j]); 1004 } 1005 } 1006 1007 return 0; 1008 } 1009 1010 static const struct dev_pm_ops atmel_pctrl_pm_ops = { 1011 SET_SYSTEM_SLEEP_PM_OPS(atmel_pctrl_suspend, atmel_pctrl_resume) 1012 }; 1013 1014 /* 1015 * The number of banks can be different from a SoC to another one. 1016 * We can have up to 16 banks. 1017 */ 1018 static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = { 1019 .nbanks = 4, 1020 .last_bank_count = ATMEL_PIO_NPINS_PER_BANK, 1021 }; 1022 1023 static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = { 1024 .nbanks = 5, 1025 .last_bank_count = 8, /* sama7g5 has only PE0 to PE7 */ 1026 .slew_rate_support = 1, 1027 }; 1028 1029 static const struct of_device_id atmel_pctrl_of_match[] = { 1030 { 1031 .compatible = "atmel,sama5d2-pinctrl", 1032 .data = &atmel_sama5d2_pioctrl_data, 1033 }, { 1034 .compatible = "microchip,sama7g5-pinctrl", 1035 .data = µchip_sama7g5_pioctrl_data, 1036 }, { 1037 /* sentinel */ 1038 } 1039 }; 1040 1041 static int atmel_pinctrl_probe(struct platform_device *pdev) 1042 { 1043 struct device *dev = &pdev->dev; 1044 struct pinctrl_pin_desc *pin_desc; 1045 const char **group_names; 1046 const struct of_device_id *match; 1047 int i, ret; 1048 struct atmel_pioctrl *atmel_pioctrl; 1049 const struct atmel_pioctrl_data *atmel_pioctrl_data; 1050 1051 atmel_pioctrl = devm_kzalloc(dev, sizeof(*atmel_pioctrl), GFP_KERNEL); 1052 if (!atmel_pioctrl) 1053 return -ENOMEM; 1054 atmel_pioctrl->dev = dev; 1055 atmel_pioctrl->node = dev->of_node; 1056 platform_set_drvdata(pdev, atmel_pioctrl); 1057 1058 match = of_match_node(atmel_pctrl_of_match, dev->of_node); 1059 if (!match) { 1060 dev_err(dev, "unknown compatible string\n"); 1061 return -ENODEV; 1062 } 1063 atmel_pioctrl_data = match->data; 1064 atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks; 1065 atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK; 1066 /* if last bank has limited number of pins, adjust accordingly */ 1067 if (atmel_pioctrl_data->last_bank_count != ATMEL_PIO_NPINS_PER_BANK) { 1068 atmel_pioctrl->npins -= ATMEL_PIO_NPINS_PER_BANK; 1069 atmel_pioctrl->npins += atmel_pioctrl_data->last_bank_count; 1070 } 1071 atmel_pioctrl->slew_rate_support = atmel_pioctrl_data->slew_rate_support; 1072 1073 atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0); 1074 if (IS_ERR(atmel_pioctrl->reg_base)) 1075 return PTR_ERR(atmel_pioctrl->reg_base); 1076 1077 atmel_pioctrl->clk = devm_clk_get(dev, NULL); 1078 if (IS_ERR(atmel_pioctrl->clk)) { 1079 dev_err(dev, "failed to get clock\n"); 1080 return PTR_ERR(atmel_pioctrl->clk); 1081 } 1082 1083 atmel_pioctrl->pins = devm_kcalloc(dev, 1084 atmel_pioctrl->npins, 1085 sizeof(*atmel_pioctrl->pins), 1086 GFP_KERNEL); 1087 if (!atmel_pioctrl->pins) 1088 return -ENOMEM; 1089 1090 pin_desc = devm_kcalloc(dev, atmel_pioctrl->npins, sizeof(*pin_desc), 1091 GFP_KERNEL); 1092 if (!pin_desc) 1093 return -ENOMEM; 1094 atmel_pinctrl_desc.pins = pin_desc; 1095 atmel_pinctrl_desc.npins = atmel_pioctrl->npins; 1096 atmel_pinctrl_desc.num_custom_params = ARRAY_SIZE(atmel_custom_bindings); 1097 atmel_pinctrl_desc.custom_params = atmel_custom_bindings; 1098 1099 /* One pin is one group since a pin can achieve all functions. */ 1100 group_names = devm_kcalloc(dev, 1101 atmel_pioctrl->npins, sizeof(*group_names), 1102 GFP_KERNEL); 1103 if (!group_names) 1104 return -ENOMEM; 1105 atmel_pioctrl->group_names = group_names; 1106 1107 atmel_pioctrl->groups = devm_kcalloc(&pdev->dev, 1108 atmel_pioctrl->npins, sizeof(*atmel_pioctrl->groups), 1109 GFP_KERNEL); 1110 if (!atmel_pioctrl->groups) 1111 return -ENOMEM; 1112 for (i = 0 ; i < atmel_pioctrl->npins; i++) { 1113 struct atmel_group *group = atmel_pioctrl->groups + i; 1114 unsigned int bank = ATMEL_PIO_BANK(i); 1115 unsigned int line = ATMEL_PIO_LINE(i); 1116 1117 atmel_pioctrl->pins[i] = devm_kzalloc(dev, 1118 sizeof(**atmel_pioctrl->pins), GFP_KERNEL); 1119 if (!atmel_pioctrl->pins[i]) 1120 return -ENOMEM; 1121 1122 atmel_pioctrl->pins[i]->pin_id = i; 1123 atmel_pioctrl->pins[i]->bank = bank; 1124 atmel_pioctrl->pins[i]->line = line; 1125 1126 pin_desc[i].number = i; 1127 /* Pin naming convention: P(bank_name)(bank_pin_number). */ 1128 pin_desc[i].name = kasprintf(GFP_KERNEL, "P%c%d", 1129 bank + 'A', line); 1130 1131 group->name = group_names[i] = pin_desc[i].name; 1132 group->pin = pin_desc[i].number; 1133 1134 dev_dbg(dev, "pin_id=%u, bank=%u, line=%u", i, bank, line); 1135 } 1136 1137 atmel_pioctrl->gpio_chip = &atmel_gpio_chip; 1138 atmel_pioctrl->gpio_chip->ngpio = atmel_pioctrl->npins; 1139 atmel_pioctrl->gpio_chip->label = dev_name(dev); 1140 atmel_pioctrl->gpio_chip->parent = dev; 1141 atmel_pioctrl->gpio_chip->names = atmel_pioctrl->group_names; 1142 1143 atmel_pioctrl->pm_wakeup_sources = devm_kcalloc(dev, 1144 atmel_pioctrl->nbanks, 1145 sizeof(*atmel_pioctrl->pm_wakeup_sources), 1146 GFP_KERNEL); 1147 if (!atmel_pioctrl->pm_wakeup_sources) 1148 return -ENOMEM; 1149 1150 atmel_pioctrl->pm_suspend_backup = devm_kcalloc(dev, 1151 atmel_pioctrl->nbanks, 1152 sizeof(*atmel_pioctrl->pm_suspend_backup), 1153 GFP_KERNEL); 1154 if (!atmel_pioctrl->pm_suspend_backup) 1155 return -ENOMEM; 1156 1157 atmel_pioctrl->irqs = devm_kcalloc(dev, 1158 atmel_pioctrl->nbanks, 1159 sizeof(*atmel_pioctrl->irqs), 1160 GFP_KERNEL); 1161 if (!atmel_pioctrl->irqs) 1162 return -ENOMEM; 1163 1164 /* There is one controller but each bank has its own irq line. */ 1165 for (i = 0; i < atmel_pioctrl->nbanks; i++) { 1166 ret = platform_get_irq(pdev, i); 1167 if (ret < 0) { 1168 dev_dbg(dev, "missing irq resource for group %c\n", 1169 'A' + i); 1170 return ret; 1171 } 1172 atmel_pioctrl->irqs[i] = ret; 1173 irq_set_chained_handler_and_data(ret, atmel_gpio_irq_handler, atmel_pioctrl); 1174 dev_dbg(dev, "bank %i: irq=%d\n", i, ret); 1175 } 1176 1177 atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node, 1178 atmel_pioctrl->gpio_chip->ngpio, 1179 &irq_domain_simple_ops, NULL); 1180 if (!atmel_pioctrl->irq_domain) { 1181 dev_err(dev, "can't add the irq domain\n"); 1182 return -ENODEV; 1183 } 1184 atmel_pioctrl->irq_domain->name = "atmel gpio"; 1185 1186 for (i = 0; i < atmel_pioctrl->npins; i++) { 1187 int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i); 1188 1189 irq_set_chip_and_handler(irq, &atmel_gpio_irq_chip, 1190 handle_simple_irq); 1191 irq_set_chip_data(irq, atmel_pioctrl); 1192 dev_dbg(dev, 1193 "atmel gpio irq domain: hwirq: %d, linux irq: %d\n", 1194 i, irq); 1195 } 1196 1197 ret = clk_prepare_enable(atmel_pioctrl->clk); 1198 if (ret) { 1199 dev_err(dev, "failed to prepare and enable clock\n"); 1200 goto clk_prepare_enable_error; 1201 } 1202 1203 atmel_pioctrl->pinctrl_dev = devm_pinctrl_register(&pdev->dev, 1204 &atmel_pinctrl_desc, 1205 atmel_pioctrl); 1206 if (IS_ERR(atmel_pioctrl->pinctrl_dev)) { 1207 ret = PTR_ERR(atmel_pioctrl->pinctrl_dev); 1208 dev_err(dev, "pinctrl registration failed\n"); 1209 goto clk_unprep; 1210 } 1211 1212 ret = gpiochip_add_data(atmel_pioctrl->gpio_chip, atmel_pioctrl); 1213 if (ret) { 1214 dev_err(dev, "failed to add gpiochip\n"); 1215 goto clk_unprep; 1216 } 1217 1218 ret = gpiochip_add_pin_range(atmel_pioctrl->gpio_chip, dev_name(dev), 1219 0, 0, atmel_pioctrl->gpio_chip->ngpio); 1220 if (ret) { 1221 dev_err(dev, "failed to add gpio pin range\n"); 1222 goto gpiochip_add_pin_range_error; 1223 } 1224 1225 dev_info(&pdev->dev, "atmel pinctrl initialized\n"); 1226 1227 return 0; 1228 1229 gpiochip_add_pin_range_error: 1230 gpiochip_remove(atmel_pioctrl->gpio_chip); 1231 1232 clk_unprep: 1233 clk_disable_unprepare(atmel_pioctrl->clk); 1234 1235 clk_prepare_enable_error: 1236 irq_domain_remove(atmel_pioctrl->irq_domain); 1237 1238 return ret; 1239 } 1240 1241 static struct platform_driver atmel_pinctrl_driver = { 1242 .driver = { 1243 .name = "pinctrl-at91-pio4", 1244 .of_match_table = atmel_pctrl_of_match, 1245 .pm = &atmel_pctrl_pm_ops, 1246 .suppress_bind_attrs = true, 1247 }, 1248 .probe = atmel_pinctrl_probe, 1249 }; 1250 builtin_platform_driver(atmel_pinctrl_driver); 1251