1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Driver for the Atmel PIO4 controller
4  *
5  * Copyright (C) 2015 Atmel,
6  *               2015 Ludovic Desroches <ludovic.desroches@atmel.com>
7  */
8 
9 #include <dt-bindings/pinctrl/at91.h>
10 #include <linux/clk.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/init.h>
15 #include <linux/of.h>
16 #include <linux/platform_device.h>
17 #include <linux/pinctrl/pinconf.h>
18 #include <linux/pinctrl/pinconf-generic.h>
19 #include <linux/pinctrl/pinctrl.h>
20 #include <linux/pinctrl/pinmux.h>
21 #include <linux/slab.h>
22 #include "core.h"
23 #include "pinconf.h"
24 #include "pinctrl-utils.h"
25 
26 /*
27  * Warning:
28  * In order to not introduce confusion between Atmel PIO groups and pinctrl
29  * framework groups, Atmel PIO groups will be called banks, line is kept to
30  * designed the pin id into this bank.
31  */
32 
33 #define ATMEL_PIO_MSKR		0x0000
34 #define ATMEL_PIO_CFGR		0x0004
35 #define		ATMEL_PIO_CFGR_FUNC_MASK	GENMASK(2, 0)
36 #define		ATMEL_PIO_DIR_MASK		BIT(8)
37 #define		ATMEL_PIO_PUEN_MASK		BIT(9)
38 #define		ATMEL_PIO_PDEN_MASK		BIT(10)
39 #define		ATMEL_PIO_SR_MASK		BIT(11)
40 #define		ATMEL_PIO_IFEN_MASK		BIT(12)
41 #define		ATMEL_PIO_IFSCEN_MASK		BIT(13)
42 #define		ATMEL_PIO_OPD_MASK		BIT(14)
43 #define		ATMEL_PIO_SCHMITT_MASK		BIT(15)
44 #define		ATMEL_PIO_DRVSTR_MASK		GENMASK(17, 16)
45 #define		ATMEL_PIO_DRVSTR_OFFSET		16
46 #define		ATMEL_PIO_CFGR_EVTSEL_MASK	GENMASK(26, 24)
47 #define		ATMEL_PIO_CFGR_EVTSEL_FALLING	(0 << 24)
48 #define		ATMEL_PIO_CFGR_EVTSEL_RISING	(1 << 24)
49 #define		ATMEL_PIO_CFGR_EVTSEL_BOTH	(2 << 24)
50 #define		ATMEL_PIO_CFGR_EVTSEL_LOW	(3 << 24)
51 #define		ATMEL_PIO_CFGR_EVTSEL_HIGH	(4 << 24)
52 #define ATMEL_PIO_PDSR		0x0008
53 #define ATMEL_PIO_LOCKSR	0x000C
54 #define ATMEL_PIO_SODR		0x0010
55 #define ATMEL_PIO_CODR		0x0014
56 #define ATMEL_PIO_ODSR		0x0018
57 #define ATMEL_PIO_IER		0x0020
58 #define ATMEL_PIO_IDR		0x0024
59 #define ATMEL_PIO_IMR		0x0028
60 #define ATMEL_PIO_ISR		0x002C
61 #define ATMEL_PIO_IOFR		0x003C
62 
63 #define ATMEL_PIO_NPINS_PER_BANK	32
64 #define ATMEL_PIO_BANK(pin_id)		(pin_id / ATMEL_PIO_NPINS_PER_BANK)
65 #define ATMEL_PIO_LINE(pin_id)		(pin_id % ATMEL_PIO_NPINS_PER_BANK)
66 #define ATMEL_PIO_BANK_OFFSET		0x40
67 
68 #define ATMEL_GET_PIN_NO(pinfunc)	((pinfunc) & 0xff)
69 #define ATMEL_GET_PIN_FUNC(pinfunc)	((pinfunc >> 16) & 0xf)
70 #define ATMEL_GET_PIN_IOSET(pinfunc)	((pinfunc >> 20) & 0xf)
71 
72 /* Custom pinconf parameters */
73 #define ATMEL_PIN_CONFIG_DRIVE_STRENGTH	(PIN_CONFIG_END + 1)
74 
75 /**
76  * struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct
77  * @nbanks: number of PIO banks
78  * @last_bank_count: number of lines in the last bank (can be less than
79  *	the rest of the banks).
80  * @slew_rate_support: slew rate support
81  */
82 struct atmel_pioctrl_data {
83 	unsigned int nbanks;
84 	unsigned int last_bank_count;
85 	unsigned int slew_rate_support;
86 };
87 
88 struct atmel_group {
89 	const char *name;
90 	u32 pin;
91 };
92 
93 struct atmel_pin {
94 	unsigned int pin_id;
95 	unsigned int mux;
96 	unsigned int ioset;
97 	unsigned int bank;
98 	unsigned int line;
99 	const char *device;
100 };
101 
102 /**
103  * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio)
104  * @reg_base: base address of the controller.
105  * @clk: clock of the controller.
106  * @nbanks: number of PIO groups, it can vary depending on the SoC.
107  * @pinctrl_dev: pinctrl device registered.
108  * @groups: groups table to provide group name and pin in the group to pinctrl.
109  * @group_names: group names table to provide all the group/pin names to
110  *     pinctrl or gpio.
111  * @pins: pins table used for both pinctrl and gpio. pin_id, bank and line
112  *     fields are set at probe time. Other ones are set when parsing dt
113  *     pinctrl.
114  * @npins: number of pins.
115  * @gpio_chip: gpio chip registered.
116  * @irq_domain: irq domain for the gpio controller.
117  * @irqs: table containing the hw irq number of the bank. The index of the
118  *     table is the bank id.
119  * @pm_wakeup_sources: bitmap of wakeup sources (lines)
120  * @pm_suspend_backup: backup/restore register values on suspend/resume
121  * @dev: device entry for the Atmel PIO controller.
122  * @node: node of the Atmel PIO controller.
123  * @slew_rate_support: slew rate support
124  */
125 struct atmel_pioctrl {
126 	void __iomem		*reg_base;
127 	struct clk		*clk;
128 	unsigned int		nbanks;
129 	struct pinctrl_dev	*pinctrl_dev;
130 	struct atmel_group	*groups;
131 	const char * const	*group_names;
132 	struct atmel_pin	**pins;
133 	unsigned int		npins;
134 	struct gpio_chip	*gpio_chip;
135 	struct irq_domain	*irq_domain;
136 	int			*irqs;
137 	unsigned int		*pm_wakeup_sources;
138 	struct {
139 		u32		imr;
140 		u32		odsr;
141 		u32		cfgr[ATMEL_PIO_NPINS_PER_BANK];
142 	} *pm_suspend_backup;
143 	struct device		*dev;
144 	struct device_node	*node;
145 	unsigned int		slew_rate_support;
146 };
147 
148 static const char * const atmel_functions[] = {
149 	"GPIO", "A", "B", "C", "D", "E", "F", "G"
150 };
151 
152 static const struct pinconf_generic_params atmel_custom_bindings[] = {
153 	{"atmel,drive-strength", ATMEL_PIN_CONFIG_DRIVE_STRENGTH, 0},
154 };
155 
156 /* --- GPIO --- */
157 static unsigned int atmel_gpio_read(struct atmel_pioctrl *atmel_pioctrl,
158 				    unsigned int bank, unsigned int reg)
159 {
160 	return readl_relaxed(atmel_pioctrl->reg_base
161 			     + ATMEL_PIO_BANK_OFFSET * bank + reg);
162 }
163 
164 static void atmel_gpio_write(struct atmel_pioctrl *atmel_pioctrl,
165 			     unsigned int bank, unsigned int reg,
166 			     unsigned int val)
167 {
168 	writel_relaxed(val, atmel_pioctrl->reg_base
169 		       + ATMEL_PIO_BANK_OFFSET * bank + reg);
170 }
171 
172 static void atmel_gpio_irq_ack(struct irq_data *d)
173 {
174 	/*
175 	 * Nothing to do, interrupt is cleared when reading the status
176 	 * register.
177 	 */
178 }
179 
180 static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned int type)
181 {
182 	struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
183 	struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
184 	unsigned int reg;
185 
186 	atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
187 			 BIT(pin->line));
188 	reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
189 	reg &= (~ATMEL_PIO_CFGR_EVTSEL_MASK);
190 
191 	switch (type) {
192 	case IRQ_TYPE_EDGE_RISING:
193 		irq_set_handler_locked(d, handle_edge_irq);
194 		reg |= ATMEL_PIO_CFGR_EVTSEL_RISING;
195 		break;
196 	case IRQ_TYPE_EDGE_FALLING:
197 		irq_set_handler_locked(d, handle_edge_irq);
198 		reg |= ATMEL_PIO_CFGR_EVTSEL_FALLING;
199 		break;
200 	case IRQ_TYPE_EDGE_BOTH:
201 		irq_set_handler_locked(d, handle_edge_irq);
202 		reg |= ATMEL_PIO_CFGR_EVTSEL_BOTH;
203 		break;
204 	case IRQ_TYPE_LEVEL_LOW:
205 		irq_set_handler_locked(d, handle_level_irq);
206 		reg |= ATMEL_PIO_CFGR_EVTSEL_LOW;
207 		break;
208 	case IRQ_TYPE_LEVEL_HIGH:
209 		irq_set_handler_locked(d, handle_level_irq);
210 		reg |= ATMEL_PIO_CFGR_EVTSEL_HIGH;
211 		break;
212 	case IRQ_TYPE_NONE:
213 	default:
214 		return -EINVAL;
215 	}
216 
217 	atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
218 
219 	return 0;
220 }
221 
222 static void atmel_gpio_irq_mask(struct irq_data *d)
223 {
224 	struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
225 	struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
226 
227 	atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR,
228 			 BIT(pin->line));
229 }
230 
231 static void atmel_gpio_irq_unmask(struct irq_data *d)
232 {
233 	struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
234 	struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
235 
236 	atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IER,
237 			 BIT(pin->line));
238 }
239 
240 static int atmel_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
241 {
242 	struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
243 	int bank = ATMEL_PIO_BANK(d->hwirq);
244 	int line = ATMEL_PIO_LINE(d->hwirq);
245 
246 	/* The gpio controller has one interrupt line per bank. */
247 	irq_set_irq_wake(atmel_pioctrl->irqs[bank], on);
248 
249 	if (on)
250 		atmel_pioctrl->pm_wakeup_sources[bank] |= BIT(line);
251 	else
252 		atmel_pioctrl->pm_wakeup_sources[bank] &= ~(BIT(line));
253 
254 	return 0;
255 }
256 
257 static struct irq_chip atmel_gpio_irq_chip = {
258 	.name		= "GPIO",
259 	.irq_ack	= atmel_gpio_irq_ack,
260 	.irq_mask	= atmel_gpio_irq_mask,
261 	.irq_unmask	= atmel_gpio_irq_unmask,
262 	.irq_set_type	= atmel_gpio_irq_set_type,
263 	.irq_set_wake	= pm_sleep_ptr(atmel_gpio_irq_set_wake),
264 };
265 
266 static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
267 {
268 	struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
269 
270 	return irq_find_mapping(atmel_pioctrl->irq_domain, offset);
271 }
272 
273 static void atmel_gpio_irq_handler(struct irq_desc *desc)
274 {
275 	unsigned int irq = irq_desc_get_irq(desc);
276 	struct atmel_pioctrl *atmel_pioctrl = irq_desc_get_handler_data(desc);
277 	struct irq_chip *chip = irq_desc_get_chip(desc);
278 	unsigned long isr;
279 	int n, bank = -1;
280 
281 	/* Find from which bank is the irq received. */
282 	for (n = 0; n < atmel_pioctrl->nbanks; n++) {
283 		if (atmel_pioctrl->irqs[n] == irq) {
284 			bank = n;
285 			break;
286 		}
287 	}
288 
289 	if (bank < 0) {
290 		dev_err(atmel_pioctrl->dev,
291 			"no bank associated to irq %u\n", irq);
292 		return;
293 	}
294 
295 	chained_irq_enter(chip, desc);
296 
297 	for (;;) {
298 		isr = (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
299 						     ATMEL_PIO_ISR);
300 		isr &= (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
301 						      ATMEL_PIO_IMR);
302 		if (!isr)
303 			break;
304 
305 		for_each_set_bit(n, &isr, BITS_PER_LONG)
306 			generic_handle_irq(atmel_gpio_to_irq(
307 					atmel_pioctrl->gpio_chip,
308 					bank * ATMEL_PIO_NPINS_PER_BANK + n));
309 	}
310 
311 	chained_irq_exit(chip, desc);
312 }
313 
314 static int atmel_gpio_direction_input(struct gpio_chip *chip,
315 				      unsigned int offset)
316 {
317 	struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
318 	struct atmel_pin *pin = atmel_pioctrl->pins[offset];
319 	unsigned int reg;
320 
321 	atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
322 			 BIT(pin->line));
323 	reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
324 	reg &= ~ATMEL_PIO_DIR_MASK;
325 	atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
326 
327 	return 0;
328 }
329 
330 static int atmel_gpio_get(struct gpio_chip *chip, unsigned int offset)
331 {
332 	struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
333 	struct atmel_pin *pin = atmel_pioctrl->pins[offset];
334 	unsigned int reg;
335 
336 	reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR);
337 
338 	return !!(reg & BIT(pin->line));
339 }
340 
341 static int atmel_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
342 				   unsigned long *bits)
343 {
344 	struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
345 	unsigned int bank;
346 
347 	bitmap_zero(bits, atmel_pioctrl->npins);
348 
349 	for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) {
350 		unsigned int word = bank;
351 		unsigned int offset = 0;
352 		unsigned int reg;
353 
354 #if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG
355 		word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK);
356 		offset = bank * ATMEL_PIO_NPINS_PER_BANK % BITS_PER_LONG;
357 #endif
358 		if (!mask[word])
359 			continue;
360 
361 		reg = atmel_gpio_read(atmel_pioctrl, bank, ATMEL_PIO_PDSR);
362 		bits[word] |= mask[word] & (reg << offset);
363 	}
364 
365 	return 0;
366 }
367 
368 static int atmel_gpio_direction_output(struct gpio_chip *chip,
369 				       unsigned int offset,
370 				       int value)
371 {
372 	struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
373 	struct atmel_pin *pin = atmel_pioctrl->pins[offset];
374 	unsigned int reg;
375 
376 	atmel_gpio_write(atmel_pioctrl, pin->bank,
377 			 value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
378 			 BIT(pin->line));
379 
380 	atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
381 			 BIT(pin->line));
382 	reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
383 	reg |= ATMEL_PIO_DIR_MASK;
384 	atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
385 
386 	return 0;
387 }
388 
389 static void atmel_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
390 {
391 	struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
392 	struct atmel_pin *pin = atmel_pioctrl->pins[offset];
393 
394 	atmel_gpio_write(atmel_pioctrl, pin->bank,
395 			 val ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
396 			 BIT(pin->line));
397 }
398 
399 static void atmel_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
400 				    unsigned long *bits)
401 {
402 	struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
403 	unsigned int bank;
404 
405 	for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) {
406 		unsigned int bitmask;
407 		unsigned int word = bank;
408 
409 /*
410  * On a 64-bit platform, BITS_PER_LONG is 64 so it is necessary to iterate over
411  * two 32bit words to handle the whole  bitmask
412  */
413 #if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG
414 		word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK);
415 #endif
416 		if (!mask[word])
417 			continue;
418 
419 		bitmask = mask[word] & bits[word];
420 		atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_SODR, bitmask);
421 
422 		bitmask = mask[word] & ~bits[word];
423 		atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_CODR, bitmask);
424 
425 #if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG
426 		mask[word] >>= ATMEL_PIO_NPINS_PER_BANK;
427 		bits[word] >>= ATMEL_PIO_NPINS_PER_BANK;
428 #endif
429 	}
430 }
431 
432 static struct gpio_chip atmel_gpio_chip = {
433 	.direction_input        = atmel_gpio_direction_input,
434 	.get                    = atmel_gpio_get,
435 	.get_multiple           = atmel_gpio_get_multiple,
436 	.direction_output       = atmel_gpio_direction_output,
437 	.set                    = atmel_gpio_set,
438 	.set_multiple           = atmel_gpio_set_multiple,
439 	.to_irq                 = atmel_gpio_to_irq,
440 	.base                   = 0,
441 };
442 
443 /* --- PINCTRL --- */
444 static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev,
445 					  unsigned int pin_id)
446 {
447 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
448 	unsigned int bank = atmel_pioctrl->pins[pin_id]->bank;
449 	unsigned int line = atmel_pioctrl->pins[pin_id]->line;
450 	void __iomem *addr = atmel_pioctrl->reg_base
451 			     + bank * ATMEL_PIO_BANK_OFFSET;
452 
453 	writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
454 	/* Have to set MSKR first, to access the right pin CFGR. */
455 	wmb();
456 
457 	return readl_relaxed(addr + ATMEL_PIO_CFGR);
458 }
459 
460 static void atmel_pin_config_write(struct pinctrl_dev *pctldev,
461 				   unsigned int pin_id, u32 conf)
462 {
463 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
464 	unsigned int bank = atmel_pioctrl->pins[pin_id]->bank;
465 	unsigned int line = atmel_pioctrl->pins[pin_id]->line;
466 	void __iomem *addr = atmel_pioctrl->reg_base
467 			     + bank * ATMEL_PIO_BANK_OFFSET;
468 
469 	writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
470 	/* Have to set MSKR first, to access the right pin CFGR. */
471 	wmb();
472 	writel_relaxed(conf, addr + ATMEL_PIO_CFGR);
473 }
474 
475 static int atmel_pctl_get_groups_count(struct pinctrl_dev *pctldev)
476 {
477 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
478 
479 	return atmel_pioctrl->npins;
480 }
481 
482 static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev,
483 					     unsigned int selector)
484 {
485 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
486 
487 	return atmel_pioctrl->groups[selector].name;
488 }
489 
490 static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev,
491 				     unsigned int selector,
492 				     const unsigned int **pins,
493 				     unsigned int *num_pins)
494 {
495 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
496 
497 	*pins = (unsigned int *)&atmel_pioctrl->groups[selector].pin;
498 	*num_pins = 1;
499 
500 	return 0;
501 }
502 
503 static struct atmel_group *
504 atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned int pin)
505 {
506 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
507 	int i;
508 
509 	for (i = 0; i < atmel_pioctrl->npins; i++) {
510 		struct atmel_group *grp = atmel_pioctrl->groups + i;
511 
512 		if (grp->pin == pin)
513 			return grp;
514 	}
515 
516 	return NULL;
517 }
518 
519 static int atmel_pctl_xlate_pinfunc(struct pinctrl_dev *pctldev,
520 				    struct device_node *np,
521 				    u32 pinfunc, const char **grp_name,
522 				    const char **func_name)
523 {
524 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
525 	unsigned int pin_id, func_id;
526 	struct atmel_group *grp;
527 
528 	pin_id = ATMEL_GET_PIN_NO(pinfunc);
529 	func_id = ATMEL_GET_PIN_FUNC(pinfunc);
530 
531 	if (func_id >= ARRAY_SIZE(atmel_functions))
532 		return -EINVAL;
533 
534 	*func_name = atmel_functions[func_id];
535 
536 	grp = atmel_pctl_find_group_by_pin(pctldev, pin_id);
537 	if (!grp)
538 		return -EINVAL;
539 	*grp_name = grp->name;
540 
541 	atmel_pioctrl->pins[pin_id]->mux = func_id;
542 	atmel_pioctrl->pins[pin_id]->ioset = ATMEL_GET_PIN_IOSET(pinfunc);
543 	/* Want the device name not the group one. */
544 	if (np->parent == atmel_pioctrl->node)
545 		atmel_pioctrl->pins[pin_id]->device = np->name;
546 	else
547 		atmel_pioctrl->pins[pin_id]->device = np->parent->name;
548 
549 	return 0;
550 }
551 
552 static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
553 					struct device_node *np,
554 					struct pinctrl_map **map,
555 					unsigned int *reserved_maps,
556 					unsigned int *num_maps)
557 {
558 	unsigned int num_pins, num_configs, reserve;
559 	unsigned long *configs;
560 	struct property	*pins;
561 	u32 pinfunc;
562 	int ret, i;
563 
564 	pins = of_find_property(np, "pinmux", NULL);
565 	if (!pins)
566 		return -EINVAL;
567 
568 	ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
569 					      &num_configs);
570 	if (ret < 0) {
571 		dev_err(pctldev->dev, "%pOF: could not parse node property\n",
572 			np);
573 		return ret;
574 	}
575 
576 	num_pins = pins->length / sizeof(u32);
577 	if (!num_pins) {
578 		dev_err(pctldev->dev, "no pins found in node %pOF\n", np);
579 		ret = -EINVAL;
580 		goto exit;
581 	}
582 
583 	/*
584 	 * Reserve maps, at least there is a mux map and an optional conf
585 	 * map for each pin.
586 	 */
587 	reserve = 1;
588 	if (num_configs)
589 		reserve++;
590 	reserve *= num_pins;
591 	ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
592 					reserve);
593 	if (ret < 0)
594 		goto exit;
595 
596 	for (i = 0; i < num_pins; i++) {
597 		const char *group, *func;
598 
599 		ret = of_property_read_u32_index(np, "pinmux", i, &pinfunc);
600 		if (ret)
601 			goto exit;
602 
603 		ret = atmel_pctl_xlate_pinfunc(pctldev, np, pinfunc, &group,
604 					       &func);
605 		if (ret)
606 			goto exit;
607 
608 		pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps,
609 					  group, func);
610 
611 		if (num_configs) {
612 			ret = pinctrl_utils_add_map_configs(pctldev, map,
613 					reserved_maps, num_maps, group,
614 					configs, num_configs,
615 					PIN_MAP_TYPE_CONFIGS_GROUP);
616 			if (ret < 0)
617 				goto exit;
618 		}
619 	}
620 
621 exit:
622 	kfree(configs);
623 	return ret;
624 }
625 
626 static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
627 				     struct device_node *np_config,
628 				     struct pinctrl_map **map,
629 				     unsigned int *num_maps)
630 {
631 	struct device_node *np;
632 	unsigned int reserved_maps;
633 	int ret;
634 
635 	*map = NULL;
636 	*num_maps = 0;
637 	reserved_maps = 0;
638 
639 	/*
640 	 * If all the pins of a device have the same configuration (or no one),
641 	 * it is useless to add a subnode, so directly parse node referenced by
642 	 * phandle.
643 	 */
644 	ret = atmel_pctl_dt_subnode_to_map(pctldev, np_config, map,
645 					   &reserved_maps, num_maps);
646 	if (ret) {
647 		for_each_child_of_node(np_config, np) {
648 			ret = atmel_pctl_dt_subnode_to_map(pctldev, np, map,
649 						    &reserved_maps, num_maps);
650 			if (ret < 0) {
651 				of_node_put(np);
652 				break;
653 			}
654 		}
655 	}
656 
657 	if (ret < 0) {
658 		pinctrl_utils_free_map(pctldev, *map, *num_maps);
659 		dev_err(pctldev->dev, "can't create maps for node %pOF\n",
660 			np_config);
661 	}
662 
663 	return ret;
664 }
665 
666 static const struct pinctrl_ops atmel_pctlops = {
667 	.get_groups_count	= atmel_pctl_get_groups_count,
668 	.get_group_name		= atmel_pctl_get_group_name,
669 	.get_group_pins		= atmel_pctl_get_group_pins,
670 	.dt_node_to_map		= atmel_pctl_dt_node_to_map,
671 	.dt_free_map		= pinctrl_utils_free_map,
672 };
673 
674 static int atmel_pmx_get_functions_count(struct pinctrl_dev *pctldev)
675 {
676 	return ARRAY_SIZE(atmel_functions);
677 }
678 
679 static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev,
680 					       unsigned int selector)
681 {
682 	return atmel_functions[selector];
683 }
684 
685 static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev,
686 					 unsigned int selector,
687 					 const char * const **groups,
688 					 unsigned * const num_groups)
689 {
690 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
691 
692 	*groups = atmel_pioctrl->group_names;
693 	*num_groups = atmel_pioctrl->npins;
694 
695 	return 0;
696 }
697 
698 static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev,
699 			     unsigned int function,
700 			     unsigned int group)
701 {
702 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
703 	unsigned int pin;
704 	u32 conf;
705 
706 	dev_dbg(pctldev->dev, "enable function %s group %s\n",
707 		atmel_functions[function], atmel_pioctrl->groups[group].name);
708 
709 	pin = atmel_pioctrl->groups[group].pin;
710 	conf = atmel_pin_config_read(pctldev, pin);
711 	conf &= (~ATMEL_PIO_CFGR_FUNC_MASK);
712 	conf |= (function & ATMEL_PIO_CFGR_FUNC_MASK);
713 	dev_dbg(pctldev->dev, "pin: %u, conf: 0x%08x\n", pin, conf);
714 	atmel_pin_config_write(pctldev, pin, conf);
715 
716 	return 0;
717 }
718 
719 static const struct pinmux_ops atmel_pmxops = {
720 	.get_functions_count	= atmel_pmx_get_functions_count,
721 	.get_function_name	= atmel_pmx_get_function_name,
722 	.get_function_groups	= atmel_pmx_get_function_groups,
723 	.set_mux		= atmel_pmx_set_mux,
724 };
725 
726 static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev,
727 					   unsigned int group,
728 					   unsigned long *config)
729 {
730 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
731 	unsigned int param = pinconf_to_config_param(*config), arg = 0;
732 	struct atmel_group *grp = atmel_pioctrl->groups + group;
733 	unsigned int pin_id = grp->pin;
734 	u32 res;
735 
736 	res = atmel_pin_config_read(pctldev, pin_id);
737 
738 	switch (param) {
739 	case PIN_CONFIG_BIAS_PULL_UP:
740 		if (!(res & ATMEL_PIO_PUEN_MASK))
741 			return -EINVAL;
742 		arg = 1;
743 		break;
744 	case PIN_CONFIG_BIAS_PULL_DOWN:
745 		if ((res & ATMEL_PIO_PUEN_MASK) ||
746 		    (!(res & ATMEL_PIO_PDEN_MASK)))
747 			return -EINVAL;
748 		arg = 1;
749 		break;
750 	case PIN_CONFIG_BIAS_DISABLE:
751 		if ((res & ATMEL_PIO_PUEN_MASK) ||
752 		    ((res & ATMEL_PIO_PDEN_MASK)))
753 			return -EINVAL;
754 		arg = 1;
755 		break;
756 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
757 		if (!(res & ATMEL_PIO_OPD_MASK))
758 			return -EINVAL;
759 		arg = 1;
760 		break;
761 	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
762 		if (!(res & ATMEL_PIO_SCHMITT_MASK))
763 			return -EINVAL;
764 		arg = 1;
765 		break;
766 	case PIN_CONFIG_SLEW_RATE:
767 		if (!atmel_pioctrl->slew_rate_support)
768 			return -EOPNOTSUPP;
769 		if (!(res & ATMEL_PIO_SR_MASK))
770 			return -EINVAL;
771 		arg = 1;
772 		break;
773 	case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
774 		if (!(res & ATMEL_PIO_DRVSTR_MASK))
775 			return -EINVAL;
776 		arg = (res & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET;
777 		break;
778 	default:
779 		return -ENOTSUPP;
780 	}
781 
782 	*config = pinconf_to_config_packed(param, arg);
783 	return 0;
784 }
785 
786 static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
787 					   unsigned int group,
788 					   unsigned long *configs,
789 					   unsigned int num_configs)
790 {
791 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
792 	struct atmel_group *grp = atmel_pioctrl->groups + group;
793 	unsigned int bank, pin, pin_id = grp->pin;
794 	u32 mask, conf = 0;
795 	int i;
796 
797 	conf = atmel_pin_config_read(pctldev, pin_id);
798 
799 	/* Keep slew rate enabled by default. */
800 	if (atmel_pioctrl->slew_rate_support)
801 		conf |= ATMEL_PIO_SR_MASK;
802 
803 	for (i = 0; i < num_configs; i++) {
804 		unsigned int param = pinconf_to_config_param(configs[i]);
805 		unsigned int arg = pinconf_to_config_argument(configs[i]);
806 
807 		dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n",
808 			__func__, pin_id, configs[i]);
809 
810 		switch (param) {
811 		case PIN_CONFIG_BIAS_DISABLE:
812 			conf &= (~ATMEL_PIO_PUEN_MASK);
813 			conf &= (~ATMEL_PIO_PDEN_MASK);
814 			break;
815 		case PIN_CONFIG_BIAS_PULL_UP:
816 			conf |= ATMEL_PIO_PUEN_MASK;
817 			conf &= (~ATMEL_PIO_PDEN_MASK);
818 			break;
819 		case PIN_CONFIG_BIAS_PULL_DOWN:
820 			conf |= ATMEL_PIO_PDEN_MASK;
821 			conf &= (~ATMEL_PIO_PUEN_MASK);
822 			break;
823 		case PIN_CONFIG_DRIVE_OPEN_DRAIN:
824 			if (arg == 0)
825 				conf &= (~ATMEL_PIO_OPD_MASK);
826 			else
827 				conf |= ATMEL_PIO_OPD_MASK;
828 			break;
829 		case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
830 			if (arg == 0)
831 				conf |= ATMEL_PIO_SCHMITT_MASK;
832 			else
833 				conf &= (~ATMEL_PIO_SCHMITT_MASK);
834 			break;
835 		case PIN_CONFIG_INPUT_DEBOUNCE:
836 			if (arg == 0) {
837 				conf &= (~ATMEL_PIO_IFEN_MASK);
838 				conf &= (~ATMEL_PIO_IFSCEN_MASK);
839 			} else {
840 				/*
841 				 * We don't care about the debounce value for several reasons:
842 				 * - can't have different debounce periods inside a same group,
843 				 * - the register to configure this period is a secure register.
844 				 * The debouncing filter can filter a pulse with a duration of less
845 				 * than 1/2 slow clock period.
846 				 */
847 				conf |= ATMEL_PIO_IFEN_MASK;
848 				conf |= ATMEL_PIO_IFSCEN_MASK;
849 			}
850 			break;
851 		case PIN_CONFIG_OUTPUT:
852 			conf |= ATMEL_PIO_DIR_MASK;
853 			bank = ATMEL_PIO_BANK(pin_id);
854 			pin = ATMEL_PIO_LINE(pin_id);
855 			mask = 1 << pin;
856 
857 			if (arg == 0) {
858 				writel_relaxed(mask, atmel_pioctrl->reg_base +
859 					bank * ATMEL_PIO_BANK_OFFSET +
860 					ATMEL_PIO_CODR);
861 			} else {
862 				writel_relaxed(mask, atmel_pioctrl->reg_base +
863 					bank * ATMEL_PIO_BANK_OFFSET +
864 					ATMEL_PIO_SODR);
865 			}
866 			break;
867 		case PIN_CONFIG_SLEW_RATE:
868 			if (!atmel_pioctrl->slew_rate_support)
869 				break;
870 			/* And remove it if explicitly requested. */
871 			if (arg == 0)
872 				conf &= ~ATMEL_PIO_SR_MASK;
873 			break;
874 		case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
875 			switch (arg) {
876 			case ATMEL_PIO_DRVSTR_LO:
877 			case ATMEL_PIO_DRVSTR_ME:
878 			case ATMEL_PIO_DRVSTR_HI:
879 				conf &= (~ATMEL_PIO_DRVSTR_MASK);
880 				conf |= arg << ATMEL_PIO_DRVSTR_OFFSET;
881 				break;
882 			default:
883 				dev_warn(pctldev->dev, "drive strength not updated (incorrect value)\n");
884 			}
885 			break;
886 		default:
887 			dev_warn(pctldev->dev,
888 				 "unsupported configuration parameter: %u\n",
889 				 param);
890 			continue;
891 		}
892 	}
893 
894 	dev_dbg(pctldev->dev, "%s: reg=0x%08x\n", __func__, conf);
895 	atmel_pin_config_write(pctldev, pin_id, conf);
896 
897 	return 0;
898 }
899 
900 static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev,
901 					   struct seq_file *s,
902 					   unsigned int pin_id)
903 {
904 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
905 	u32 conf;
906 
907 	if (!atmel_pioctrl->pins[pin_id]->device)
908 		return;
909 
910 	if (atmel_pioctrl->pins[pin_id])
911 		seq_printf(s, " (%s, ioset %u) ",
912 			   atmel_pioctrl->pins[pin_id]->device,
913 			   atmel_pioctrl->pins[pin_id]->ioset);
914 
915 	conf = atmel_pin_config_read(pctldev, pin_id);
916 	if (conf & ATMEL_PIO_PUEN_MASK)
917 		seq_printf(s, "%s ", "pull-up");
918 	if (conf & ATMEL_PIO_PDEN_MASK)
919 		seq_printf(s, "%s ", "pull-down");
920 	if (conf & ATMEL_PIO_IFEN_MASK)
921 		seq_printf(s, "%s ", "debounce");
922 	if (conf & ATMEL_PIO_OPD_MASK)
923 		seq_printf(s, "%s ", "open-drain");
924 	if (conf & ATMEL_PIO_SCHMITT_MASK)
925 		seq_printf(s, "%s ", "schmitt");
926 	if (atmel_pioctrl->slew_rate_support && (conf & ATMEL_PIO_SR_MASK))
927 		seq_printf(s, "%s ", "slew-rate");
928 	if (conf & ATMEL_PIO_DRVSTR_MASK) {
929 		switch ((conf & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET) {
930 		case ATMEL_PIO_DRVSTR_ME:
931 			seq_printf(s, "%s ", "medium-drive");
932 			break;
933 		case ATMEL_PIO_DRVSTR_HI:
934 			seq_printf(s, "%s ", "high-drive");
935 			break;
936 		/* ATMEL_PIO_DRVSTR_LO and 0 which is the default value at reset */
937 		default:
938 			seq_printf(s, "%s ", "low-drive");
939 		}
940 	}
941 }
942 
943 static const struct pinconf_ops atmel_confops = {
944 	.pin_config_group_get	= atmel_conf_pin_config_group_get,
945 	.pin_config_group_set	= atmel_conf_pin_config_group_set,
946 	.pin_config_dbg_show	= atmel_conf_pin_config_dbg_show,
947 };
948 
949 static struct pinctrl_desc atmel_pinctrl_desc = {
950 	.name		= "atmel_pinctrl",
951 	.confops	= &atmel_confops,
952 	.pctlops	= &atmel_pctlops,
953 	.pmxops		= &atmel_pmxops,
954 };
955 
956 static int __maybe_unused atmel_pctrl_suspend(struct device *dev)
957 {
958 	struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev);
959 	int i, j;
960 
961 	/*
962 	 * For each bank, save IMR to restore it later and disable all GPIO
963 	 * interrupts excepting the ones marked as wakeup sources.
964 	 */
965 	for (i = 0; i < atmel_pioctrl->nbanks; i++) {
966 		atmel_pioctrl->pm_suspend_backup[i].imr =
967 			atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_IMR);
968 		atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IDR,
969 				 ~atmel_pioctrl->pm_wakeup_sources[i]);
970 		atmel_pioctrl->pm_suspend_backup[i].odsr =
971 			atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_ODSR);
972 		for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) {
973 			atmel_gpio_write(atmel_pioctrl, i,
974 					 ATMEL_PIO_MSKR, BIT(j));
975 			atmel_pioctrl->pm_suspend_backup[i].cfgr[j] =
976 				atmel_gpio_read(atmel_pioctrl, i,
977 						ATMEL_PIO_CFGR);
978 		}
979 	}
980 
981 	return 0;
982 }
983 
984 static int __maybe_unused atmel_pctrl_resume(struct device *dev)
985 {
986 	struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev);
987 	int i, j;
988 
989 	for (i = 0; i < atmel_pioctrl->nbanks; i++) {
990 		atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IER,
991 				 atmel_pioctrl->pm_suspend_backup[i].imr);
992 		atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_SODR,
993 				 atmel_pioctrl->pm_suspend_backup[i].odsr);
994 		for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) {
995 			atmel_gpio_write(atmel_pioctrl, i,
996 					 ATMEL_PIO_MSKR, BIT(j));
997 			atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_CFGR,
998 					 atmel_pioctrl->pm_suspend_backup[i].cfgr[j]);
999 		}
1000 	}
1001 
1002 	return 0;
1003 }
1004 
1005 static const struct dev_pm_ops atmel_pctrl_pm_ops = {
1006 	SET_SYSTEM_SLEEP_PM_OPS(atmel_pctrl_suspend, atmel_pctrl_resume)
1007 };
1008 
1009 /*
1010  * The number of banks can be different from a SoC to another one.
1011  * We can have up to 16 banks.
1012  */
1013 static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
1014 	.nbanks			= 4,
1015 	.last_bank_count	= ATMEL_PIO_NPINS_PER_BANK,
1016 };
1017 
1018 static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = {
1019 	.nbanks			= 5,
1020 	.last_bank_count	= 8, /* sama7g5 has only PE0 to PE7 */
1021 	.slew_rate_support	= 1,
1022 };
1023 
1024 static const struct of_device_id atmel_pctrl_of_match[] = {
1025 	{
1026 		.compatible = "atmel,sama5d2-pinctrl",
1027 		.data = &atmel_sama5d2_pioctrl_data,
1028 	}, {
1029 		.compatible = "microchip,sama7g5-pinctrl",
1030 		.data = &microchip_sama7g5_pioctrl_data,
1031 	}, {
1032 		/* sentinel */
1033 	}
1034 };
1035 
1036 static int atmel_pinctrl_probe(struct platform_device *pdev)
1037 {
1038 	struct device *dev = &pdev->dev;
1039 	struct pinctrl_pin_desc	*pin_desc;
1040 	const char **group_names;
1041 	const struct of_device_id *match;
1042 	int i, ret;
1043 	struct atmel_pioctrl *atmel_pioctrl;
1044 	const struct atmel_pioctrl_data *atmel_pioctrl_data;
1045 
1046 	atmel_pioctrl = devm_kzalloc(dev, sizeof(*atmel_pioctrl), GFP_KERNEL);
1047 	if (!atmel_pioctrl)
1048 		return -ENOMEM;
1049 	atmel_pioctrl->dev = dev;
1050 	atmel_pioctrl->node = dev->of_node;
1051 	platform_set_drvdata(pdev, atmel_pioctrl);
1052 
1053 	match = of_match_node(atmel_pctrl_of_match, dev->of_node);
1054 	if (!match) {
1055 		dev_err(dev, "unknown compatible string\n");
1056 		return -ENODEV;
1057 	}
1058 	atmel_pioctrl_data = match->data;
1059 	atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks;
1060 	atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK;
1061 	/* if last bank has limited number of pins, adjust accordingly */
1062 	if (atmel_pioctrl_data->last_bank_count != ATMEL_PIO_NPINS_PER_BANK) {
1063 		atmel_pioctrl->npins -= ATMEL_PIO_NPINS_PER_BANK;
1064 		atmel_pioctrl->npins += atmel_pioctrl_data->last_bank_count;
1065 	}
1066 	atmel_pioctrl->slew_rate_support = atmel_pioctrl_data->slew_rate_support;
1067 
1068 	atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0);
1069 	if (IS_ERR(atmel_pioctrl->reg_base))
1070 		return PTR_ERR(atmel_pioctrl->reg_base);
1071 
1072 	atmel_pioctrl->clk = devm_clk_get(dev, NULL);
1073 	if (IS_ERR(atmel_pioctrl->clk)) {
1074 		dev_err(dev, "failed to get clock\n");
1075 		return PTR_ERR(atmel_pioctrl->clk);
1076 	}
1077 
1078 	atmel_pioctrl->pins = devm_kcalloc(dev,
1079 					   atmel_pioctrl->npins,
1080 					   sizeof(*atmel_pioctrl->pins),
1081 					   GFP_KERNEL);
1082 	if (!atmel_pioctrl->pins)
1083 		return -ENOMEM;
1084 
1085 	pin_desc = devm_kcalloc(dev, atmel_pioctrl->npins, sizeof(*pin_desc),
1086 				GFP_KERNEL);
1087 	if (!pin_desc)
1088 		return -ENOMEM;
1089 	atmel_pinctrl_desc.pins = pin_desc;
1090 	atmel_pinctrl_desc.npins = atmel_pioctrl->npins;
1091 	atmel_pinctrl_desc.num_custom_params = ARRAY_SIZE(atmel_custom_bindings);
1092 	atmel_pinctrl_desc.custom_params = atmel_custom_bindings;
1093 
1094 	/* One pin is one group since a pin can achieve all functions. */
1095 	group_names = devm_kcalloc(dev,
1096 				   atmel_pioctrl->npins, sizeof(*group_names),
1097 				   GFP_KERNEL);
1098 	if (!group_names)
1099 		return -ENOMEM;
1100 	atmel_pioctrl->group_names = group_names;
1101 
1102 	atmel_pioctrl->groups = devm_kcalloc(&pdev->dev,
1103 			atmel_pioctrl->npins, sizeof(*atmel_pioctrl->groups),
1104 			GFP_KERNEL);
1105 	if (!atmel_pioctrl->groups)
1106 		return -ENOMEM;
1107 	for (i = 0 ; i < atmel_pioctrl->npins; i++) {
1108 		struct atmel_group *group = atmel_pioctrl->groups + i;
1109 		unsigned int bank = ATMEL_PIO_BANK(i);
1110 		unsigned int line = ATMEL_PIO_LINE(i);
1111 
1112 		atmel_pioctrl->pins[i] = devm_kzalloc(dev,
1113 				sizeof(**atmel_pioctrl->pins), GFP_KERNEL);
1114 		if (!atmel_pioctrl->pins[i])
1115 			return -ENOMEM;
1116 
1117 		atmel_pioctrl->pins[i]->pin_id = i;
1118 		atmel_pioctrl->pins[i]->bank = bank;
1119 		atmel_pioctrl->pins[i]->line = line;
1120 
1121 		pin_desc[i].number = i;
1122 		/* Pin naming convention: P(bank_name)(bank_pin_number). */
1123 		pin_desc[i].name = kasprintf(GFP_KERNEL, "P%c%d",
1124 					     bank + 'A', line);
1125 
1126 		group->name = group_names[i] = pin_desc[i].name;
1127 		group->pin = pin_desc[i].number;
1128 
1129 		dev_dbg(dev, "pin_id=%u, bank=%u, line=%u", i, bank, line);
1130 	}
1131 
1132 	atmel_pioctrl->gpio_chip = &atmel_gpio_chip;
1133 	atmel_pioctrl->gpio_chip->ngpio = atmel_pioctrl->npins;
1134 	atmel_pioctrl->gpio_chip->label = dev_name(dev);
1135 	atmel_pioctrl->gpio_chip->parent = dev;
1136 	atmel_pioctrl->gpio_chip->names = atmel_pioctrl->group_names;
1137 
1138 	atmel_pioctrl->pm_wakeup_sources = devm_kcalloc(dev,
1139 			atmel_pioctrl->nbanks,
1140 			sizeof(*atmel_pioctrl->pm_wakeup_sources),
1141 			GFP_KERNEL);
1142 	if (!atmel_pioctrl->pm_wakeup_sources)
1143 		return -ENOMEM;
1144 
1145 	atmel_pioctrl->pm_suspend_backup = devm_kcalloc(dev,
1146 			atmel_pioctrl->nbanks,
1147 			sizeof(*atmel_pioctrl->pm_suspend_backup),
1148 			GFP_KERNEL);
1149 	if (!atmel_pioctrl->pm_suspend_backup)
1150 		return -ENOMEM;
1151 
1152 	atmel_pioctrl->irqs = devm_kcalloc(dev,
1153 					   atmel_pioctrl->nbanks,
1154 					   sizeof(*atmel_pioctrl->irqs),
1155 					   GFP_KERNEL);
1156 	if (!atmel_pioctrl->irqs)
1157 		return -ENOMEM;
1158 
1159 	/* There is one controller but each bank has its own irq line. */
1160 	for (i = 0; i < atmel_pioctrl->nbanks; i++) {
1161 		ret = platform_get_irq(pdev, i);
1162 		if (ret < 0) {
1163 			dev_dbg(dev, "missing irq resource for group %c\n",
1164 				'A' + i);
1165 			return ret;
1166 		}
1167 		atmel_pioctrl->irqs[i] = ret;
1168 		irq_set_chained_handler_and_data(ret, atmel_gpio_irq_handler, atmel_pioctrl);
1169 		dev_dbg(dev, "bank %i: irq=%d\n", i, ret);
1170 	}
1171 
1172 	atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node,
1173 			atmel_pioctrl->gpio_chip->ngpio,
1174 			&irq_domain_simple_ops, NULL);
1175 	if (!atmel_pioctrl->irq_domain) {
1176 		dev_err(dev, "can't add the irq domain\n");
1177 		return -ENODEV;
1178 	}
1179 	atmel_pioctrl->irq_domain->name = "atmel gpio";
1180 
1181 	for (i = 0; i < atmel_pioctrl->npins; i++) {
1182 		int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i);
1183 
1184 		irq_set_chip_and_handler(irq, &atmel_gpio_irq_chip,
1185 					 handle_simple_irq);
1186 		irq_set_chip_data(irq, atmel_pioctrl);
1187 		dev_dbg(dev,
1188 			"atmel gpio irq domain: hwirq: %d, linux irq: %d\n",
1189 			i, irq);
1190 	}
1191 
1192 	ret = clk_prepare_enable(atmel_pioctrl->clk);
1193 	if (ret) {
1194 		dev_err(dev, "failed to prepare and enable clock\n");
1195 		goto clk_prepare_enable_error;
1196 	}
1197 
1198 	atmel_pioctrl->pinctrl_dev = devm_pinctrl_register(&pdev->dev,
1199 							   &atmel_pinctrl_desc,
1200 							   atmel_pioctrl);
1201 	if (IS_ERR(atmel_pioctrl->pinctrl_dev)) {
1202 		ret = PTR_ERR(atmel_pioctrl->pinctrl_dev);
1203 		dev_err(dev, "pinctrl registration failed\n");
1204 		goto clk_unprep;
1205 	}
1206 
1207 	ret = gpiochip_add_data(atmel_pioctrl->gpio_chip, atmel_pioctrl);
1208 	if (ret) {
1209 		dev_err(dev, "failed to add gpiochip\n");
1210 		goto clk_unprep;
1211 	}
1212 
1213 	ret = gpiochip_add_pin_range(atmel_pioctrl->gpio_chip, dev_name(dev),
1214 				     0, 0, atmel_pioctrl->gpio_chip->ngpio);
1215 	if (ret) {
1216 		dev_err(dev, "failed to add gpio pin range\n");
1217 		goto gpiochip_add_pin_range_error;
1218 	}
1219 
1220 	dev_info(&pdev->dev, "atmel pinctrl initialized\n");
1221 
1222 	return 0;
1223 
1224 gpiochip_add_pin_range_error:
1225 	gpiochip_remove(atmel_pioctrl->gpio_chip);
1226 
1227 clk_unprep:
1228 	clk_disable_unprepare(atmel_pioctrl->clk);
1229 
1230 clk_prepare_enable_error:
1231 	irq_domain_remove(atmel_pioctrl->irq_domain);
1232 
1233 	return ret;
1234 }
1235 
1236 static struct platform_driver atmel_pinctrl_driver = {
1237 	.driver = {
1238 		.name = "pinctrl-at91-pio4",
1239 		.of_match_table = atmel_pctrl_of_match,
1240 		.pm = &atmel_pctrl_pm_ops,
1241 		.suppress_bind_attrs = true,
1242 	},
1243 	.probe = atmel_pinctrl_probe,
1244 };
1245 builtin_platform_driver(atmel_pinctrl_driver);
1246