1 /*
2  * Driver for the Atmel PIO4 controller
3  *
4  * Copyright (C) 2015 Atmel,
5  *               2015 Ludovic Desroches <ludovic.desroches@atmel.com>
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  */
16 
17 #include <dt-bindings/pinctrl/at91.h>
18 #include <linux/clk.h>
19 #include <linux/gpio/driver.h>
20 #include <linux/interrupt.h>
21 #include <linux/io.h>
22 #include <linux/init.h>
23 #include <linux/of.h>
24 #include <linux/platform_device.h>
25 #include <linux/pinctrl/pinconf.h>
26 #include <linux/pinctrl/pinconf-generic.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinmux.h>
29 #include <linux/slab.h>
30 #include "core.h"
31 #include "pinconf.h"
32 #include "pinctrl-utils.h"
33 
34 /*
35  * Warning:
36  * In order to not introduce confusion between Atmel PIO groups and pinctrl
37  * framework groups, Atmel PIO groups will be called banks, line is kept to
38  * designed the pin id into this bank.
39  */
40 
41 #define ATMEL_PIO_MSKR		0x0000
42 #define ATMEL_PIO_CFGR		0x0004
43 #define		ATMEL_PIO_CFGR_FUNC_MASK	GENMASK(2, 0)
44 #define		ATMEL_PIO_DIR_MASK		BIT(8)
45 #define		ATMEL_PIO_PUEN_MASK		BIT(9)
46 #define		ATMEL_PIO_PDEN_MASK		BIT(10)
47 #define		ATMEL_PIO_IFEN_MASK		BIT(12)
48 #define		ATMEL_PIO_IFSCEN_MASK		BIT(13)
49 #define		ATMEL_PIO_OPD_MASK		BIT(14)
50 #define		ATMEL_PIO_SCHMITT_MASK		BIT(15)
51 #define		ATMEL_PIO_DRVSTR_MASK		GENMASK(17, 16)
52 #define		ATMEL_PIO_DRVSTR_OFFSET		16
53 #define		ATMEL_PIO_CFGR_EVTSEL_MASK	GENMASK(26, 24)
54 #define		ATMEL_PIO_CFGR_EVTSEL_FALLING	(0 << 24)
55 #define		ATMEL_PIO_CFGR_EVTSEL_RISING	(1 << 24)
56 #define		ATMEL_PIO_CFGR_EVTSEL_BOTH	(2 << 24)
57 #define		ATMEL_PIO_CFGR_EVTSEL_LOW	(3 << 24)
58 #define		ATMEL_PIO_CFGR_EVTSEL_HIGH	(4 << 24)
59 #define ATMEL_PIO_PDSR		0x0008
60 #define ATMEL_PIO_LOCKSR	0x000C
61 #define ATMEL_PIO_SODR		0x0010
62 #define ATMEL_PIO_CODR		0x0014
63 #define ATMEL_PIO_ODSR		0x0018
64 #define ATMEL_PIO_IER		0x0020
65 #define ATMEL_PIO_IDR		0x0024
66 #define ATMEL_PIO_IMR		0x0028
67 #define ATMEL_PIO_ISR		0x002C
68 #define ATMEL_PIO_IOFR		0x003C
69 
70 #define ATMEL_PIO_NPINS_PER_BANK	32
71 #define ATMEL_PIO_BANK(pin_id)		(pin_id / ATMEL_PIO_NPINS_PER_BANK)
72 #define ATMEL_PIO_LINE(pin_id)		(pin_id % ATMEL_PIO_NPINS_PER_BANK)
73 #define ATMEL_PIO_BANK_OFFSET		0x40
74 
75 #define ATMEL_GET_PIN_NO(pinfunc)	((pinfunc) & 0xff)
76 #define ATMEL_GET_PIN_FUNC(pinfunc)	((pinfunc >> 16) & 0xf)
77 #define ATMEL_GET_PIN_IOSET(pinfunc)	((pinfunc >> 20) & 0xf)
78 
79 /* Custom pinconf parameters */
80 #define ATMEL_PIN_CONFIG_DRIVE_STRENGTH	(PIN_CONFIG_END + 1)
81 
82 struct atmel_pioctrl_data {
83 	unsigned nbanks;
84 };
85 
86 struct atmel_group {
87 	const char *name;
88 	u32 pin;
89 };
90 
91 struct atmel_pin {
92 	unsigned pin_id;
93 	unsigned mux;
94 	unsigned ioset;
95 	unsigned bank;
96 	unsigned line;
97 	const char *device;
98 };
99 
100 /**
101  * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio)
102  * @reg_base: base address of the controller.
103  * @clk: clock of the controller.
104  * @nbanks: number of PIO groups, it can vary depending on the SoC.
105  * @pinctrl_dev: pinctrl device registered.
106  * @groups: groups table to provide group name and pin in the group to pinctrl.
107  * @group_names: group names table to provide all the group/pin names to
108  *     pinctrl or gpio.
109  * @pins: pins table used for both pinctrl and gpio. pin_id, bank and line
110  *     fields are set at probe time. Other ones are set when parsing dt
111  *     pinctrl.
112  * @npins: number of pins.
113  * @gpio_chip: gpio chip registered.
114  * @irq_domain: irq domain for the gpio controller.
115  * @irqs: table containing the hw irq number of the bank. The index of the
116  *     table is the bank id.
117  * @dev: device entry for the Atmel PIO controller.
118  * @node: node of the Atmel PIO controller.
119  */
120 struct atmel_pioctrl {
121 	void __iomem		*reg_base;
122 	struct clk		*clk;
123 	unsigned		nbanks;
124 	struct pinctrl_dev	*pinctrl_dev;
125 	struct atmel_group	*groups;
126 	const char * const	*group_names;
127 	struct atmel_pin	**pins;
128 	unsigned		npins;
129 	struct gpio_chip	*gpio_chip;
130 	struct irq_domain	*irq_domain;
131 	int			*irqs;
132 	unsigned		*pm_wakeup_sources;
133 	struct {
134 		u32		imr;
135 		u32		odsr;
136 		u32		cfgr[ATMEL_PIO_NPINS_PER_BANK];
137 	} *pm_suspend_backup;
138 	struct device		*dev;
139 	struct device_node	*node;
140 };
141 
142 static const char * const atmel_functions[] = {
143 	"GPIO", "A", "B", "C", "D", "E", "F", "G"
144 };
145 
146 static const struct pinconf_generic_params atmel_custom_bindings[] = {
147 	{"atmel,drive-strength", ATMEL_PIN_CONFIG_DRIVE_STRENGTH, 0},
148 };
149 
150 /* --- GPIO --- */
151 static unsigned int atmel_gpio_read(struct atmel_pioctrl *atmel_pioctrl,
152 				    unsigned int bank, unsigned int reg)
153 {
154 	return readl_relaxed(atmel_pioctrl->reg_base
155 			     + ATMEL_PIO_BANK_OFFSET * bank + reg);
156 }
157 
158 static void atmel_gpio_write(struct atmel_pioctrl *atmel_pioctrl,
159 			     unsigned int bank, unsigned int reg,
160 			     unsigned int val)
161 {
162 	writel_relaxed(val, atmel_pioctrl->reg_base
163 		       + ATMEL_PIO_BANK_OFFSET * bank + reg);
164 }
165 
166 static void atmel_gpio_irq_ack(struct irq_data *d)
167 {
168 	/*
169 	 * Nothing to do, interrupt is cleared when reading the status
170 	 * register.
171 	 */
172 }
173 
174 static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned type)
175 {
176 	struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
177 	struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
178 	unsigned reg;
179 
180 	atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
181 			 BIT(pin->line));
182 	reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
183 	reg &= (~ATMEL_PIO_CFGR_EVTSEL_MASK);
184 
185 	switch (type) {
186 	case IRQ_TYPE_EDGE_RISING:
187 		irq_set_handler_locked(d, handle_edge_irq);
188 		reg |= ATMEL_PIO_CFGR_EVTSEL_RISING;
189 		break;
190 	case IRQ_TYPE_EDGE_FALLING:
191 		irq_set_handler_locked(d, handle_edge_irq);
192 		reg |= ATMEL_PIO_CFGR_EVTSEL_FALLING;
193 		break;
194 	case IRQ_TYPE_EDGE_BOTH:
195 		irq_set_handler_locked(d, handle_edge_irq);
196 		reg |= ATMEL_PIO_CFGR_EVTSEL_BOTH;
197 		break;
198 	case IRQ_TYPE_LEVEL_LOW:
199 		irq_set_handler_locked(d, handle_level_irq);
200 		reg |= ATMEL_PIO_CFGR_EVTSEL_LOW;
201 		break;
202 	case IRQ_TYPE_LEVEL_HIGH:
203 		irq_set_handler_locked(d, handle_level_irq);
204 		reg |= ATMEL_PIO_CFGR_EVTSEL_HIGH;
205 		break;
206 	case IRQ_TYPE_NONE:
207 	default:
208 		return -EINVAL;
209 	}
210 
211 	atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
212 
213 	return 0;
214 }
215 
216 static void atmel_gpio_irq_mask(struct irq_data *d)
217 {
218 	struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
219 	struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
220 
221 	atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR,
222 			 BIT(pin->line));
223 }
224 
225 static void atmel_gpio_irq_unmask(struct irq_data *d)
226 {
227 	struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
228 	struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
229 
230 	atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IER,
231 			 BIT(pin->line));
232 }
233 
234 #ifdef CONFIG_PM_SLEEP
235 
236 static int atmel_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
237 {
238 	struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
239 	int bank = ATMEL_PIO_BANK(d->hwirq);
240 	int line = ATMEL_PIO_LINE(d->hwirq);
241 
242 	/* The gpio controller has one interrupt line per bank. */
243 	irq_set_irq_wake(atmel_pioctrl->irqs[bank], on);
244 
245 	if (on)
246 		atmel_pioctrl->pm_wakeup_sources[bank] |= BIT(line);
247 	else
248 		atmel_pioctrl->pm_wakeup_sources[bank] &= ~(BIT(line));
249 
250 	return 0;
251 }
252 #else
253 #define atmel_gpio_irq_set_wake NULL
254 #endif /* CONFIG_PM_SLEEP */
255 
256 static struct irq_chip atmel_gpio_irq_chip = {
257 	.name		= "GPIO",
258 	.irq_ack	= atmel_gpio_irq_ack,
259 	.irq_mask	= atmel_gpio_irq_mask,
260 	.irq_unmask	= atmel_gpio_irq_unmask,
261 	.irq_set_type	= atmel_gpio_irq_set_type,
262 	.irq_set_wake	= atmel_gpio_irq_set_wake,
263 };
264 
265 static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
266 {
267 	struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
268 
269 	return irq_find_mapping(atmel_pioctrl->irq_domain, offset);
270 }
271 
272 static void atmel_gpio_irq_handler(struct irq_desc *desc)
273 {
274 	unsigned int irq = irq_desc_get_irq(desc);
275 	struct atmel_pioctrl *atmel_pioctrl = irq_desc_get_handler_data(desc);
276 	struct irq_chip *chip = irq_desc_get_chip(desc);
277 	unsigned long isr;
278 	int n, bank = -1;
279 
280 	/* Find from which bank is the irq received. */
281 	for (n = 0; n < atmel_pioctrl->nbanks; n++) {
282 		if (atmel_pioctrl->irqs[n] == irq) {
283 			bank = n;
284 			break;
285 		}
286 	}
287 
288 	if (bank < 0) {
289 		dev_err(atmel_pioctrl->dev,
290 			"no bank associated to irq %u\n", irq);
291 		return;
292 	}
293 
294 	chained_irq_enter(chip, desc);
295 
296 	for (;;) {
297 		isr = (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
298 						     ATMEL_PIO_ISR);
299 		isr &= (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
300 						      ATMEL_PIO_IMR);
301 		if (!isr)
302 			break;
303 
304 		for_each_set_bit(n, &isr, BITS_PER_LONG)
305 			generic_handle_irq(atmel_gpio_to_irq(
306 					atmel_pioctrl->gpio_chip,
307 					bank * ATMEL_PIO_NPINS_PER_BANK + n));
308 	}
309 
310 	chained_irq_exit(chip, desc);
311 }
312 
313 static int atmel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
314 {
315 	struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
316 	struct atmel_pin *pin = atmel_pioctrl->pins[offset];
317 	unsigned reg;
318 
319 	atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
320 			 BIT(pin->line));
321 	reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
322 	reg &= ~ATMEL_PIO_DIR_MASK;
323 	atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
324 
325 	return 0;
326 }
327 
328 static int atmel_gpio_get(struct gpio_chip *chip, unsigned offset)
329 {
330 	struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
331 	struct atmel_pin *pin = atmel_pioctrl->pins[offset];
332 	unsigned reg;
333 
334 	reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR);
335 
336 	return !!(reg & BIT(pin->line));
337 }
338 
339 static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
340 				       int value)
341 {
342 	struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
343 	struct atmel_pin *pin = atmel_pioctrl->pins[offset];
344 	unsigned reg;
345 
346 	atmel_gpio_write(atmel_pioctrl, pin->bank,
347 			 value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
348 			 BIT(pin->line));
349 
350 	atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
351 			 BIT(pin->line));
352 	reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
353 	reg |= ATMEL_PIO_DIR_MASK;
354 	atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
355 
356 	return 0;
357 }
358 
359 static void atmel_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
360 {
361 	struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
362 	struct atmel_pin *pin = atmel_pioctrl->pins[offset];
363 
364 	atmel_gpio_write(atmel_pioctrl, pin->bank,
365 			 val ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
366 			 BIT(pin->line));
367 }
368 
369 static struct gpio_chip atmel_gpio_chip = {
370 	.direction_input        = atmel_gpio_direction_input,
371 	.get                    = atmel_gpio_get,
372 	.direction_output       = atmel_gpio_direction_output,
373 	.set                    = atmel_gpio_set,
374 	.to_irq                 = atmel_gpio_to_irq,
375 	.base                   = 0,
376 };
377 
378 /* --- PINCTRL --- */
379 static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev,
380 					  unsigned pin_id)
381 {
382 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
383 	unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
384 	unsigned line = atmel_pioctrl->pins[pin_id]->line;
385 	void __iomem *addr = atmel_pioctrl->reg_base
386 			     + bank * ATMEL_PIO_BANK_OFFSET;
387 
388 	writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
389 	/* Have to set MSKR first, to access the right pin CFGR. */
390 	wmb();
391 
392 	return readl_relaxed(addr + ATMEL_PIO_CFGR);
393 }
394 
395 static void atmel_pin_config_write(struct pinctrl_dev *pctldev,
396 				   unsigned pin_id, u32 conf)
397 {
398 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
399 	unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
400 	unsigned line = atmel_pioctrl->pins[pin_id]->line;
401 	void __iomem *addr = atmel_pioctrl->reg_base
402 			     + bank * ATMEL_PIO_BANK_OFFSET;
403 
404 	writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
405 	/* Have to set MSKR first, to access the right pin CFGR. */
406 	wmb();
407 	writel_relaxed(conf, addr + ATMEL_PIO_CFGR);
408 }
409 
410 static int atmel_pctl_get_groups_count(struct pinctrl_dev *pctldev)
411 {
412 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
413 
414 	return atmel_pioctrl->npins;
415 }
416 
417 static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev,
418 					     unsigned selector)
419 {
420 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
421 
422 	return atmel_pioctrl->groups[selector].name;
423 }
424 
425 static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev,
426 				     unsigned selector, const unsigned **pins,
427 				     unsigned *num_pins)
428 {
429 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
430 
431 	*pins = (unsigned *)&atmel_pioctrl->groups[selector].pin;
432 	*num_pins = 1;
433 
434 	return 0;
435 }
436 
437 static struct atmel_group *
438 atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned pin)
439 {
440 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
441 	int i;
442 
443 	for (i = 0; i < atmel_pioctrl->npins; i++) {
444 		struct atmel_group *grp = atmel_pioctrl->groups + i;
445 
446 		if (grp->pin == pin)
447 			return grp;
448 	}
449 
450 	return NULL;
451 }
452 
453 static int atmel_pctl_xlate_pinfunc(struct pinctrl_dev *pctldev,
454 				    struct device_node *np,
455 				    u32 pinfunc, const char **grp_name,
456 				    const char **func_name)
457 {
458 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
459 	unsigned pin_id, func_id;
460 	struct atmel_group *grp;
461 
462 	pin_id = ATMEL_GET_PIN_NO(pinfunc);
463 	func_id = ATMEL_GET_PIN_FUNC(pinfunc);
464 
465 	if (func_id >= ARRAY_SIZE(atmel_functions))
466 		return -EINVAL;
467 
468 	*func_name = atmel_functions[func_id];
469 
470 	grp = atmel_pctl_find_group_by_pin(pctldev, pin_id);
471 	if (!grp)
472 		return -EINVAL;
473 	*grp_name = grp->name;
474 
475 	atmel_pioctrl->pins[pin_id]->mux = func_id;
476 	atmel_pioctrl->pins[pin_id]->ioset = ATMEL_GET_PIN_IOSET(pinfunc);
477 	/* Want the device name not the group one. */
478 	if (np->parent == atmel_pioctrl->node)
479 		atmel_pioctrl->pins[pin_id]->device = np->name;
480 	else
481 		atmel_pioctrl->pins[pin_id]->device = np->parent->name;
482 
483 	return 0;
484 }
485 
486 static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
487 					struct device_node *np,
488 					struct pinctrl_map **map,
489 					unsigned *reserved_maps,
490 					unsigned *num_maps)
491 {
492 	unsigned num_pins, num_configs, reserve;
493 	unsigned long *configs;
494 	struct property	*pins;
495 	u32 pinfunc;
496 	int ret, i;
497 
498 	pins = of_find_property(np, "pinmux", NULL);
499 	if (!pins)
500 		return -EINVAL;
501 
502 	ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
503 					      &num_configs);
504 	if (ret < 0) {
505 		dev_err(pctldev->dev, "%pOF: could not parse node property\n",
506 			np);
507 		return ret;
508 	}
509 
510 	num_pins = pins->length / sizeof(u32);
511 	if (!num_pins) {
512 		dev_err(pctldev->dev, "no pins found in node %pOF\n", np);
513 		ret = -EINVAL;
514 		goto exit;
515 	}
516 
517 	/*
518 	 * Reserve maps, at least there is a mux map and an optional conf
519 	 * map for each pin.
520 	 */
521 	reserve = 1;
522 	if (num_configs)
523 		reserve++;
524 	reserve *= num_pins;
525 	ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
526 					reserve);
527 	if (ret < 0)
528 		goto exit;
529 
530 	for (i = 0; i < num_pins; i++) {
531 		const char *group, *func;
532 
533 		ret = of_property_read_u32_index(np, "pinmux", i, &pinfunc);
534 		if (ret)
535 			goto exit;
536 
537 		ret = atmel_pctl_xlate_pinfunc(pctldev, np, pinfunc, &group,
538 					       &func);
539 		if (ret)
540 			goto exit;
541 
542 		pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps,
543 					  group, func);
544 
545 		if (num_configs) {
546 			ret = pinctrl_utils_add_map_configs(pctldev, map,
547 					reserved_maps, num_maps, group,
548 					configs, num_configs,
549 					PIN_MAP_TYPE_CONFIGS_GROUP);
550 			if (ret < 0)
551 				goto exit;
552 		}
553 	}
554 
555 exit:
556 	kfree(configs);
557 	return ret;
558 }
559 
560 static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
561 				     struct device_node *np_config,
562 				     struct pinctrl_map **map,
563 				     unsigned *num_maps)
564 {
565 	struct device_node *np;
566 	unsigned reserved_maps;
567 	int ret;
568 
569 	*map = NULL;
570 	*num_maps = 0;
571 	reserved_maps = 0;
572 
573 	/*
574 	 * If all the pins of a device have the same configuration (or no one),
575 	 * it is useless to add a subnode, so directly parse node referenced by
576 	 * phandle.
577 	 */
578 	ret = atmel_pctl_dt_subnode_to_map(pctldev, np_config, map,
579 					   &reserved_maps, num_maps);
580 	if (ret) {
581 		for_each_child_of_node(np_config, np) {
582 			ret = atmel_pctl_dt_subnode_to_map(pctldev, np, map,
583 						    &reserved_maps, num_maps);
584 			if (ret < 0) {
585 				of_node_put(np);
586 				break;
587 			}
588 		}
589 	}
590 
591 	if (ret < 0) {
592 		pinctrl_utils_free_map(pctldev, *map, *num_maps);
593 		dev_err(pctldev->dev, "can't create maps for node %pOF\n",
594 			np_config);
595 	}
596 
597 	return ret;
598 }
599 
600 static const struct pinctrl_ops atmel_pctlops = {
601 	.get_groups_count	= atmel_pctl_get_groups_count,
602 	.get_group_name		= atmel_pctl_get_group_name,
603 	.get_group_pins		= atmel_pctl_get_group_pins,
604 	.dt_node_to_map		= atmel_pctl_dt_node_to_map,
605 	.dt_free_map		= pinctrl_utils_free_map,
606 };
607 
608 static int atmel_pmx_get_functions_count(struct pinctrl_dev *pctldev)
609 {
610 	return ARRAY_SIZE(atmel_functions);
611 }
612 
613 static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev,
614 					       unsigned selector)
615 {
616 	return atmel_functions[selector];
617 }
618 
619 static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev,
620 					 unsigned selector,
621 					 const char * const **groups,
622 					 unsigned * const num_groups)
623 {
624 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
625 
626 	*groups = atmel_pioctrl->group_names;
627 	*num_groups = atmel_pioctrl->npins;
628 
629 	return 0;
630 }
631 
632 static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev,
633 			     unsigned function,
634 			     unsigned group)
635 {
636 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
637 	unsigned pin;
638 	u32 conf;
639 
640 	dev_dbg(pctldev->dev, "enable function %s group %s\n",
641 		atmel_functions[function], atmel_pioctrl->groups[group].name);
642 
643 	pin = atmel_pioctrl->groups[group].pin;
644 	conf = atmel_pin_config_read(pctldev, pin);
645 	conf &= (~ATMEL_PIO_CFGR_FUNC_MASK);
646 	conf |= (function & ATMEL_PIO_CFGR_FUNC_MASK);
647 	dev_dbg(pctldev->dev, "pin: %u, conf: 0x%08x\n", pin, conf);
648 	atmel_pin_config_write(pctldev, pin, conf);
649 
650 	return 0;
651 }
652 
653 static const struct pinmux_ops atmel_pmxops = {
654 	.get_functions_count	= atmel_pmx_get_functions_count,
655 	.get_function_name	= atmel_pmx_get_function_name,
656 	.get_function_groups	= atmel_pmx_get_function_groups,
657 	.set_mux		= atmel_pmx_set_mux,
658 };
659 
660 static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev,
661 					   unsigned group,
662 					   unsigned long *config)
663 {
664 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
665 	unsigned param = pinconf_to_config_param(*config), arg = 0;
666 	struct atmel_group *grp = atmel_pioctrl->groups + group;
667 	unsigned pin_id = grp->pin;
668 	u32 res;
669 
670 	res = atmel_pin_config_read(pctldev, pin_id);
671 
672 	switch (param) {
673 	case PIN_CONFIG_BIAS_PULL_UP:
674 		if (!(res & ATMEL_PIO_PUEN_MASK))
675 			return -EINVAL;
676 		arg = 1;
677 		break;
678 	case PIN_CONFIG_BIAS_PULL_DOWN:
679 		if ((res & ATMEL_PIO_PUEN_MASK) ||
680 		    (!(res & ATMEL_PIO_PDEN_MASK)))
681 			return -EINVAL;
682 		arg = 1;
683 		break;
684 	case PIN_CONFIG_BIAS_DISABLE:
685 		if ((res & ATMEL_PIO_PUEN_MASK) ||
686 		    ((res & ATMEL_PIO_PDEN_MASK)))
687 			return -EINVAL;
688 		arg = 1;
689 		break;
690 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
691 		if (!(res & ATMEL_PIO_OPD_MASK))
692 			return -EINVAL;
693 		arg = 1;
694 		break;
695 	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
696 		if (!(res & ATMEL_PIO_SCHMITT_MASK))
697 			return -EINVAL;
698 		arg = 1;
699 		break;
700 	case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
701 		if (!(res & ATMEL_PIO_DRVSTR_MASK))
702 			return -EINVAL;
703 		arg = (res & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET;
704 		break;
705 	default:
706 		return -ENOTSUPP;
707 	}
708 
709 	*config = pinconf_to_config_packed(param, arg);
710 	return 0;
711 }
712 
713 static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
714 					   unsigned group,
715 					   unsigned long *configs,
716 					   unsigned num_configs)
717 {
718 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
719 	struct atmel_group *grp = atmel_pioctrl->groups + group;
720 	unsigned bank, pin, pin_id = grp->pin;
721 	u32 mask, conf = 0;
722 	int i;
723 
724 	conf = atmel_pin_config_read(pctldev, pin_id);
725 
726 	for (i = 0; i < num_configs; i++) {
727 		unsigned param = pinconf_to_config_param(configs[i]);
728 		unsigned arg = pinconf_to_config_argument(configs[i]);
729 
730 		dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n",
731 			__func__, pin_id, configs[i]);
732 
733 		switch (param) {
734 		case PIN_CONFIG_BIAS_DISABLE:
735 			conf &= (~ATMEL_PIO_PUEN_MASK);
736 			conf &= (~ATMEL_PIO_PDEN_MASK);
737 			break;
738 		case PIN_CONFIG_BIAS_PULL_UP:
739 			conf |= ATMEL_PIO_PUEN_MASK;
740 			conf &= (~ATMEL_PIO_PDEN_MASK);
741 			break;
742 		case PIN_CONFIG_BIAS_PULL_DOWN:
743 			conf |= ATMEL_PIO_PDEN_MASK;
744 			conf &= (~ATMEL_PIO_PUEN_MASK);
745 			break;
746 		case PIN_CONFIG_DRIVE_OPEN_DRAIN:
747 			if (arg == 0)
748 				conf &= (~ATMEL_PIO_OPD_MASK);
749 			else
750 				conf |= ATMEL_PIO_OPD_MASK;
751 			break;
752 		case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
753 			if (arg == 0)
754 				conf |= ATMEL_PIO_SCHMITT_MASK;
755 			else
756 				conf &= (~ATMEL_PIO_SCHMITT_MASK);
757 			break;
758 		case PIN_CONFIG_INPUT_DEBOUNCE:
759 			if (arg == 0) {
760 				conf &= (~ATMEL_PIO_IFEN_MASK);
761 				conf &= (~ATMEL_PIO_IFSCEN_MASK);
762 			} else {
763 				/*
764 				 * We don't care about the debounce value for several reasons:
765 				 * - can't have different debounce periods inside a same group,
766 				 * - the register to configure this period is a secure register.
767 				 * The debouncing filter can filter a pulse with a duration of less
768 				 * than 1/2 slow clock period.
769 				 */
770 				conf |= ATMEL_PIO_IFEN_MASK;
771 				conf |= ATMEL_PIO_IFSCEN_MASK;
772 			}
773 			break;
774 		case PIN_CONFIG_OUTPUT:
775 			conf |= ATMEL_PIO_DIR_MASK;
776 			bank = ATMEL_PIO_BANK(pin_id);
777 			pin = ATMEL_PIO_LINE(pin_id);
778 			mask = 1 << pin;
779 
780 			if (arg == 0) {
781 				writel_relaxed(mask, atmel_pioctrl->reg_base +
782 					bank * ATMEL_PIO_BANK_OFFSET +
783 					ATMEL_PIO_CODR);
784 			} else {
785 				writel_relaxed(mask, atmel_pioctrl->reg_base +
786 					bank * ATMEL_PIO_BANK_OFFSET +
787 					ATMEL_PIO_SODR);
788 			}
789 			break;
790 		case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
791 			switch (arg) {
792 			case ATMEL_PIO_DRVSTR_LO:
793 			case ATMEL_PIO_DRVSTR_ME:
794 			case ATMEL_PIO_DRVSTR_HI:
795 				conf &= (~ATMEL_PIO_DRVSTR_MASK);
796 				conf |= arg << ATMEL_PIO_DRVSTR_OFFSET;
797 				break;
798 			default:
799 				dev_warn(pctldev->dev, "drive strength not updated (incorrect value)\n");
800 			}
801 			break;
802 		default:
803 			dev_warn(pctldev->dev,
804 				 "unsupported configuration parameter: %u\n",
805 				 param);
806 			continue;
807 		}
808 	}
809 
810 	dev_dbg(pctldev->dev, "%s: reg=0x%08x\n", __func__, conf);
811 	atmel_pin_config_write(pctldev, pin_id, conf);
812 
813 	return 0;
814 }
815 
816 static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev,
817 					   struct seq_file *s, unsigned pin_id)
818 {
819 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
820 	u32 conf;
821 
822 	if (!atmel_pioctrl->pins[pin_id]->device)
823 		return;
824 
825 	if (atmel_pioctrl->pins[pin_id])
826 		seq_printf(s, " (%s, ioset %u) ",
827 			   atmel_pioctrl->pins[pin_id]->device,
828 			   atmel_pioctrl->pins[pin_id]->ioset);
829 
830 	conf = atmel_pin_config_read(pctldev, pin_id);
831 	if (conf & ATMEL_PIO_PUEN_MASK)
832 		seq_printf(s, "%s ", "pull-up");
833 	if (conf & ATMEL_PIO_PDEN_MASK)
834 		seq_printf(s, "%s ", "pull-down");
835 	if (conf & ATMEL_PIO_IFEN_MASK)
836 		seq_printf(s, "%s ", "debounce");
837 	if (conf & ATMEL_PIO_OPD_MASK)
838 		seq_printf(s, "%s ", "open-drain");
839 	if (conf & ATMEL_PIO_SCHMITT_MASK)
840 		seq_printf(s, "%s ", "schmitt");
841 	if (conf & ATMEL_PIO_DRVSTR_MASK) {
842 		switch ((conf & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET) {
843 		case ATMEL_PIO_DRVSTR_ME:
844 			seq_printf(s, "%s ", "medium-drive");
845 			break;
846 		case ATMEL_PIO_DRVSTR_HI:
847 			seq_printf(s, "%s ", "high-drive");
848 			break;
849 		/* ATMEL_PIO_DRVSTR_LO and 0 which is the default value at reset */
850 		default:
851 			seq_printf(s, "%s ", "low-drive");
852 		}
853 	}
854 }
855 
856 static const struct pinconf_ops atmel_confops = {
857 	.pin_config_group_get	= atmel_conf_pin_config_group_get,
858 	.pin_config_group_set	= atmel_conf_pin_config_group_set,
859 	.pin_config_dbg_show	= atmel_conf_pin_config_dbg_show,
860 };
861 
862 static struct pinctrl_desc atmel_pinctrl_desc = {
863 	.name		= "atmel_pinctrl",
864 	.confops	= &atmel_confops,
865 	.pctlops	= &atmel_pctlops,
866 	.pmxops		= &atmel_pmxops,
867 };
868 
869 static int __maybe_unused atmel_pctrl_suspend(struct device *dev)
870 {
871 	struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev);
872 	int i, j;
873 
874 	/*
875 	 * For each bank, save IMR to restore it later and disable all GPIO
876 	 * interrupts excepting the ones marked as wakeup sources.
877 	 */
878 	for (i = 0; i < atmel_pioctrl->nbanks; i++) {
879 		atmel_pioctrl->pm_suspend_backup[i].imr =
880 			atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_IMR);
881 		atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IDR,
882 				 ~atmel_pioctrl->pm_wakeup_sources[i]);
883 		atmel_pioctrl->pm_suspend_backup[i].odsr =
884 			atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_ODSR);
885 		for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) {
886 			atmel_gpio_write(atmel_pioctrl, i,
887 					 ATMEL_PIO_MSKR, BIT(j));
888 			atmel_pioctrl->pm_suspend_backup[i].cfgr[j] =
889 				atmel_gpio_read(atmel_pioctrl, i,
890 						ATMEL_PIO_CFGR);
891 		}
892 	}
893 
894 	return 0;
895 }
896 
897 static int __maybe_unused atmel_pctrl_resume(struct device *dev)
898 {
899 	struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev);
900 	int i, j;
901 
902 	for (i = 0; i < atmel_pioctrl->nbanks; i++) {
903 		atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IER,
904 				 atmel_pioctrl->pm_suspend_backup[i].imr);
905 		atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_SODR,
906 				 atmel_pioctrl->pm_suspend_backup[i].odsr);
907 		for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) {
908 			atmel_gpio_write(atmel_pioctrl, i,
909 					 ATMEL_PIO_MSKR, BIT(j));
910 			atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_CFGR,
911 					 atmel_pioctrl->pm_suspend_backup[i].cfgr[j]);
912 		}
913 	}
914 
915 	return 0;
916 }
917 
918 static const struct dev_pm_ops atmel_pctrl_pm_ops = {
919 	SET_SYSTEM_SLEEP_PM_OPS(atmel_pctrl_suspend, atmel_pctrl_resume)
920 };
921 
922 /*
923  * The number of banks can be different from a SoC to another one.
924  * We can have up to 16 banks.
925  */
926 static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
927 	.nbanks		= 4,
928 };
929 
930 static const struct of_device_id atmel_pctrl_of_match[] = {
931 	{
932 		.compatible = "atmel,sama5d2-pinctrl",
933 		.data = &atmel_sama5d2_pioctrl_data,
934 	}, {
935 		/* sentinel */
936 	}
937 };
938 
939 static int atmel_pinctrl_probe(struct platform_device *pdev)
940 {
941 	struct device *dev = &pdev->dev;
942 	struct pinctrl_pin_desc	*pin_desc;
943 	const char **group_names;
944 	const struct of_device_id *match;
945 	int i, ret;
946 	struct resource	*res;
947 	struct atmel_pioctrl *atmel_pioctrl;
948 	const struct atmel_pioctrl_data *atmel_pioctrl_data;
949 
950 	atmel_pioctrl = devm_kzalloc(dev, sizeof(*atmel_pioctrl), GFP_KERNEL);
951 	if (!atmel_pioctrl)
952 		return -ENOMEM;
953 	atmel_pioctrl->dev = dev;
954 	atmel_pioctrl->node = dev->of_node;
955 	platform_set_drvdata(pdev, atmel_pioctrl);
956 
957 	match = of_match_node(atmel_pctrl_of_match, dev->of_node);
958 	if (!match) {
959 		dev_err(dev, "unknown compatible string\n");
960 		return -ENODEV;
961 	}
962 	atmel_pioctrl_data = match->data;
963 	atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks;
964 	atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK;
965 
966 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
967 	atmel_pioctrl->reg_base = devm_ioremap_resource(dev, res);
968 	if (IS_ERR(atmel_pioctrl->reg_base))
969 		return -EINVAL;
970 
971 	atmel_pioctrl->clk = devm_clk_get(dev, NULL);
972 	if (IS_ERR(atmel_pioctrl->clk)) {
973 		dev_err(dev, "failed to get clock\n");
974 		return PTR_ERR(atmel_pioctrl->clk);
975 	}
976 
977 	atmel_pioctrl->pins = devm_kcalloc(dev,
978 					   atmel_pioctrl->npins,
979 					   sizeof(*atmel_pioctrl->pins),
980 					   GFP_KERNEL);
981 	if (!atmel_pioctrl->pins)
982 		return -ENOMEM;
983 
984 	pin_desc = devm_kcalloc(dev, atmel_pioctrl->npins, sizeof(*pin_desc),
985 				GFP_KERNEL);
986 	if (!pin_desc)
987 		return -ENOMEM;
988 	atmel_pinctrl_desc.pins = pin_desc;
989 	atmel_pinctrl_desc.npins = atmel_pioctrl->npins;
990 	atmel_pinctrl_desc.num_custom_params = ARRAY_SIZE(atmel_custom_bindings);
991 	atmel_pinctrl_desc.custom_params = atmel_custom_bindings;
992 
993 	/* One pin is one group since a pin can achieve all functions. */
994 	group_names = devm_kcalloc(dev,
995 				   atmel_pioctrl->npins, sizeof(*group_names),
996 				   GFP_KERNEL);
997 	if (!group_names)
998 		return -ENOMEM;
999 	atmel_pioctrl->group_names = group_names;
1000 
1001 	atmel_pioctrl->groups = devm_kcalloc(&pdev->dev,
1002 			atmel_pioctrl->npins, sizeof(*atmel_pioctrl->groups),
1003 			GFP_KERNEL);
1004 	if (!atmel_pioctrl->groups)
1005 		return -ENOMEM;
1006 	for (i = 0 ; i < atmel_pioctrl->npins; i++) {
1007 		struct atmel_group *group = atmel_pioctrl->groups + i;
1008 		unsigned bank = ATMEL_PIO_BANK(i);
1009 		unsigned line = ATMEL_PIO_LINE(i);
1010 
1011 		atmel_pioctrl->pins[i] = devm_kzalloc(dev,
1012 				sizeof(**atmel_pioctrl->pins), GFP_KERNEL);
1013 		if (!atmel_pioctrl->pins[i])
1014 			return -ENOMEM;
1015 
1016 		atmel_pioctrl->pins[i]->pin_id = i;
1017 		atmel_pioctrl->pins[i]->bank = bank;
1018 		atmel_pioctrl->pins[i]->line = line;
1019 
1020 		pin_desc[i].number = i;
1021 		/* Pin naming convention: P(bank_name)(bank_pin_number). */
1022 		pin_desc[i].name = kasprintf(GFP_KERNEL, "P%c%d",
1023 					     bank + 'A', line);
1024 
1025 		group->name = group_names[i] = pin_desc[i].name;
1026 		group->pin = pin_desc[i].number;
1027 
1028 		dev_dbg(dev, "pin_id=%u, bank=%u, line=%u", i, bank, line);
1029 	}
1030 
1031 	atmel_pioctrl->gpio_chip = &atmel_gpio_chip;
1032 	atmel_pioctrl->gpio_chip->of_node = dev->of_node;
1033 	atmel_pioctrl->gpio_chip->ngpio = atmel_pioctrl->npins;
1034 	atmel_pioctrl->gpio_chip->label = dev_name(dev);
1035 	atmel_pioctrl->gpio_chip->parent = dev;
1036 	atmel_pioctrl->gpio_chip->names = atmel_pioctrl->group_names;
1037 
1038 	atmel_pioctrl->pm_wakeup_sources = devm_kcalloc(dev,
1039 			atmel_pioctrl->nbanks,
1040 			sizeof(*atmel_pioctrl->pm_wakeup_sources),
1041 			GFP_KERNEL);
1042 	if (!atmel_pioctrl->pm_wakeup_sources)
1043 		return -ENOMEM;
1044 
1045 	atmel_pioctrl->pm_suspend_backup = devm_kcalloc(dev,
1046 			atmel_pioctrl->nbanks,
1047 			sizeof(*atmel_pioctrl->pm_suspend_backup),
1048 			GFP_KERNEL);
1049 	if (!atmel_pioctrl->pm_suspend_backup)
1050 		return -ENOMEM;
1051 
1052 	atmel_pioctrl->irqs = devm_kcalloc(dev,
1053 					   atmel_pioctrl->nbanks,
1054 					   sizeof(*atmel_pioctrl->irqs),
1055 					   GFP_KERNEL);
1056 	if (!atmel_pioctrl->irqs)
1057 		return -ENOMEM;
1058 
1059 	/* There is one controller but each bank has its own irq line. */
1060 	for (i = 0; i < atmel_pioctrl->nbanks; i++) {
1061 		res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
1062 		if (!res) {
1063 			dev_err(dev, "missing irq resource for group %c\n",
1064 				'A' + i);
1065 			return -EINVAL;
1066 		}
1067 		atmel_pioctrl->irqs[i] = res->start;
1068 		irq_set_chained_handler(res->start, atmel_gpio_irq_handler);
1069 		irq_set_handler_data(res->start, atmel_pioctrl);
1070 		dev_dbg(dev, "bank %i: irq=%pr\n", i, res);
1071 	}
1072 
1073 	atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node,
1074 			atmel_pioctrl->gpio_chip->ngpio,
1075 			&irq_domain_simple_ops, NULL);
1076 	if (!atmel_pioctrl->irq_domain) {
1077 		dev_err(dev, "can't add the irq domain\n");
1078 		return -ENODEV;
1079 	}
1080 	atmel_pioctrl->irq_domain->name = "atmel gpio";
1081 
1082 	for (i = 0; i < atmel_pioctrl->npins; i++) {
1083 		int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i);
1084 
1085 		irq_set_chip_and_handler(irq, &atmel_gpio_irq_chip,
1086 					 handle_simple_irq);
1087 		irq_set_chip_data(irq, atmel_pioctrl);
1088 		dev_dbg(dev,
1089 			"atmel gpio irq domain: hwirq: %d, linux irq: %d\n",
1090 			i, irq);
1091 	}
1092 
1093 	ret = clk_prepare_enable(atmel_pioctrl->clk);
1094 	if (ret) {
1095 		dev_err(dev, "failed to prepare and enable clock\n");
1096 		goto clk_prepare_enable_error;
1097 	}
1098 
1099 	atmel_pioctrl->pinctrl_dev = devm_pinctrl_register(&pdev->dev,
1100 							   &atmel_pinctrl_desc,
1101 							   atmel_pioctrl);
1102 	if (IS_ERR(atmel_pioctrl->pinctrl_dev)) {
1103 		ret = PTR_ERR(atmel_pioctrl->pinctrl_dev);
1104 		dev_err(dev, "pinctrl registration failed\n");
1105 		goto clk_unprep;
1106 	}
1107 
1108 	ret = gpiochip_add_data(atmel_pioctrl->gpio_chip, atmel_pioctrl);
1109 	if (ret) {
1110 		dev_err(dev, "failed to add gpiochip\n");
1111 		goto clk_unprep;
1112 	}
1113 
1114 	ret = gpiochip_add_pin_range(atmel_pioctrl->gpio_chip, dev_name(dev),
1115 				     0, 0, atmel_pioctrl->gpio_chip->ngpio);
1116 	if (ret) {
1117 		dev_err(dev, "failed to add gpio pin range\n");
1118 		goto gpiochip_add_pin_range_error;
1119 	}
1120 
1121 	dev_info(&pdev->dev, "atmel pinctrl initialized\n");
1122 
1123 	return 0;
1124 
1125 gpiochip_add_pin_range_error:
1126 	gpiochip_remove(atmel_pioctrl->gpio_chip);
1127 
1128 clk_unprep:
1129 	clk_disable_unprepare(atmel_pioctrl->clk);
1130 
1131 clk_prepare_enable_error:
1132 	irq_domain_remove(atmel_pioctrl->irq_domain);
1133 
1134 	return ret;
1135 }
1136 
1137 static struct platform_driver atmel_pinctrl_driver = {
1138 	.driver = {
1139 		.name = "pinctrl-at91-pio4",
1140 		.of_match_table = atmel_pctrl_of_match,
1141 		.pm = &atmel_pctrl_pm_ops,
1142 		.suppress_bind_attrs = true,
1143 	},
1144 	.probe = atmel_pinctrl_probe,
1145 };
1146 builtin_platform_driver(atmel_pinctrl_driver);
1147