1 /* 2 * ams AS3722 pin control and GPIO driver. 3 * 4 * Copyright (c) 2013, NVIDIA Corporation. 5 * 6 * Author: Laxman Dewangan <ldewangan@nvidia.com> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation version 2. 11 * 12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind, 13 * whether express or implied; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 20 * 02111-1307, USA 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/gpio.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/mfd/as3722.h> 28 #include <linux/of.h> 29 #include <linux/of_device.h> 30 #include <linux/platform_device.h> 31 #include <linux/pinctrl/consumer.h> 32 #include <linux/pinctrl/machine.h> 33 #include <linux/pinctrl/pinctrl.h> 34 #include <linux/pinctrl/pinconf-generic.h> 35 #include <linux/pinctrl/pinconf.h> 36 #include <linux/pinctrl/pinmux.h> 37 #include <linux/pm.h> 38 #include <linux/slab.h> 39 40 #include "core.h" 41 #include "pinconf.h" 42 #include "pinctrl-utils.h" 43 44 #define AS3722_PIN_GPIO0 0 45 #define AS3722_PIN_GPIO1 1 46 #define AS3722_PIN_GPIO2 2 47 #define AS3722_PIN_GPIO3 3 48 #define AS3722_PIN_GPIO4 4 49 #define AS3722_PIN_GPIO5 5 50 #define AS3722_PIN_GPIO6 6 51 #define AS3722_PIN_GPIO7 7 52 #define AS3722_PIN_NUM (AS3722_PIN_GPIO7 + 1) 53 54 #define AS3722_GPIO_MODE_PULL_UP BIT(PIN_CONFIG_BIAS_PULL_UP) 55 #define AS3722_GPIO_MODE_PULL_DOWN BIT(PIN_CONFIG_BIAS_PULL_DOWN) 56 #define AS3722_GPIO_MODE_HIGH_IMPED BIT(PIN_CONFIG_BIAS_HIGH_IMPEDANCE) 57 #define AS3722_GPIO_MODE_OPEN_DRAIN BIT(PIN_CONFIG_DRIVE_OPEN_DRAIN) 58 59 struct as3722_pin_function { 60 const char *name; 61 const char * const *groups; 62 unsigned ngroups; 63 int mux_option; 64 }; 65 66 struct as3722_gpio_pin_control { 67 unsigned mode_prop; 68 int io_function; 69 }; 70 71 struct as3722_pingroup { 72 const char *name; 73 const unsigned pins[1]; 74 unsigned npins; 75 }; 76 77 struct as3722_pctrl_info { 78 struct device *dev; 79 struct pinctrl_dev *pctl; 80 struct as3722 *as3722; 81 struct gpio_chip gpio_chip; 82 int pins_current_opt[AS3722_PIN_NUM]; 83 const struct as3722_pin_function *functions; 84 unsigned num_functions; 85 const struct as3722_pingroup *pin_groups; 86 int num_pin_groups; 87 const struct pinctrl_pin_desc *pins; 88 unsigned num_pins; 89 struct as3722_gpio_pin_control gpio_control[AS3722_PIN_NUM]; 90 }; 91 92 static const struct pinctrl_pin_desc as3722_pins_desc[] = { 93 PINCTRL_PIN(AS3722_PIN_GPIO0, "gpio0"), 94 PINCTRL_PIN(AS3722_PIN_GPIO1, "gpio1"), 95 PINCTRL_PIN(AS3722_PIN_GPIO2, "gpio2"), 96 PINCTRL_PIN(AS3722_PIN_GPIO3, "gpio3"), 97 PINCTRL_PIN(AS3722_PIN_GPIO4, "gpio4"), 98 PINCTRL_PIN(AS3722_PIN_GPIO5, "gpio5"), 99 PINCTRL_PIN(AS3722_PIN_GPIO6, "gpio6"), 100 PINCTRL_PIN(AS3722_PIN_GPIO7, "gpio7"), 101 }; 102 103 static const char * const gpio_groups[] = { 104 "gpio0", 105 "gpio1", 106 "gpio2", 107 "gpio3", 108 "gpio4", 109 "gpio5", 110 "gpio6", 111 "gpio7", 112 }; 113 114 enum as3722_pinmux_option { 115 AS3722_PINMUX_GPIO = 0, 116 AS3722_PINMUX_INTERRUPT_OUT = 1, 117 AS3722_PINMUX_VSUB_VBAT_UNDEB_LOW_OUT = 2, 118 AS3722_PINMUX_GPIO_INTERRUPT = 3, 119 AS3722_PINMUX_PWM_INPUT = 4, 120 AS3722_PINMUX_VOLTAGE_IN_STBY = 5, 121 AS3722_PINMUX_OC_PG_SD0 = 6, 122 AS3722_PINMUX_PG_OUT = 7, 123 AS3722_PINMUX_CLK32K_OUT = 8, 124 AS3722_PINMUX_WATCHDOG_INPUT = 9, 125 AS3722_PINMUX_SOFT_RESET_IN = 11, 126 AS3722_PINMUX_PWM_OUTPUT = 12, 127 AS3722_PINMUX_VSUB_VBAT_LOW_DEB_OUT = 13, 128 AS3722_PINMUX_OC_PG_SD6 = 14, 129 }; 130 131 #define FUNCTION_GROUP(fname, mux) \ 132 { \ 133 .name = #fname, \ 134 .groups = gpio_groups, \ 135 .ngroups = ARRAY_SIZE(gpio_groups), \ 136 .mux_option = AS3722_PINMUX_##mux, \ 137 } 138 139 static const struct as3722_pin_function as3722_pin_function[] = { 140 FUNCTION_GROUP(gpio, GPIO), 141 FUNCTION_GROUP(interrupt-out, INTERRUPT_OUT), 142 FUNCTION_GROUP(gpio-in-interrupt, GPIO_INTERRUPT), 143 FUNCTION_GROUP(vsup-vbat-low-undebounce-out, VSUB_VBAT_UNDEB_LOW_OUT), 144 FUNCTION_GROUP(vsup-vbat-low-debounce-out, VSUB_VBAT_LOW_DEB_OUT), 145 FUNCTION_GROUP(voltage-in-standby, VOLTAGE_IN_STBY), 146 FUNCTION_GROUP(oc-pg-sd0, OC_PG_SD0), 147 FUNCTION_GROUP(oc-pg-sd6, OC_PG_SD6), 148 FUNCTION_GROUP(powergood-out, PG_OUT), 149 FUNCTION_GROUP(pwm-in, PWM_INPUT), 150 FUNCTION_GROUP(pwm-out, PWM_OUTPUT), 151 FUNCTION_GROUP(clk32k-out, CLK32K_OUT), 152 FUNCTION_GROUP(watchdog-in, WATCHDOG_INPUT), 153 FUNCTION_GROUP(soft-reset-in, SOFT_RESET_IN), 154 }; 155 156 #define AS3722_PINGROUP(pg_name, pin_id) \ 157 { \ 158 .name = #pg_name, \ 159 .pins = {AS3722_PIN_##pin_id}, \ 160 .npins = 1, \ 161 } 162 163 static const struct as3722_pingroup as3722_pingroups[] = { 164 AS3722_PINGROUP(gpio0, GPIO0), 165 AS3722_PINGROUP(gpio1, GPIO1), 166 AS3722_PINGROUP(gpio2, GPIO2), 167 AS3722_PINGROUP(gpio3, GPIO3), 168 AS3722_PINGROUP(gpio4, GPIO4), 169 AS3722_PINGROUP(gpio5, GPIO5), 170 AS3722_PINGROUP(gpio6, GPIO6), 171 AS3722_PINGROUP(gpio7, GPIO7), 172 }; 173 174 static int as3722_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 175 { 176 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); 177 178 return as_pci->num_pin_groups; 179 } 180 181 static const char *as3722_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 182 unsigned group) 183 { 184 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); 185 186 return as_pci->pin_groups[group].name; 187 } 188 189 static int as3722_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, 190 unsigned group, const unsigned **pins, unsigned *num_pins) 191 { 192 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); 193 194 *pins = as_pci->pin_groups[group].pins; 195 *num_pins = as_pci->pin_groups[group].npins; 196 return 0; 197 } 198 199 static const struct pinctrl_ops as3722_pinctrl_ops = { 200 .get_groups_count = as3722_pinctrl_get_groups_count, 201 .get_group_name = as3722_pinctrl_get_group_name, 202 .get_group_pins = as3722_pinctrl_get_group_pins, 203 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 204 .dt_free_map = pinctrl_utils_free_map, 205 }; 206 207 static int as3722_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) 208 { 209 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); 210 211 return as_pci->num_functions; 212 } 213 214 static const char *as3722_pinctrl_get_func_name(struct pinctrl_dev *pctldev, 215 unsigned function) 216 { 217 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); 218 219 return as_pci->functions[function].name; 220 } 221 222 static int as3722_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, 223 unsigned function, const char * const **groups, 224 unsigned * const num_groups) 225 { 226 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); 227 228 *groups = as_pci->functions[function].groups; 229 *num_groups = as_pci->functions[function].ngroups; 230 return 0; 231 } 232 233 static int as3722_pinctrl_set(struct pinctrl_dev *pctldev, unsigned function, 234 unsigned group) 235 { 236 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); 237 int gpio_cntr_reg = AS3722_GPIOn_CONTROL_REG(group); 238 u8 val = AS3722_GPIO_IOSF_VAL(as_pci->functions[function].mux_option); 239 int ret; 240 241 dev_dbg(as_pci->dev, "%s(): GPIO %u pin to function %u and val %u\n", 242 __func__, group, function, val); 243 244 ret = as3722_update_bits(as_pci->as3722, gpio_cntr_reg, 245 AS3722_GPIO_IOSF_MASK, val); 246 if (ret < 0) { 247 dev_err(as_pci->dev, "GPIO%d_CTRL_REG update failed %d\n", 248 group, ret); 249 return ret; 250 } 251 as_pci->gpio_control[group].io_function = function; 252 253 switch (val) { 254 case AS3722_GPIO_IOSF_SD0_OUT: 255 case AS3722_GPIO_IOSF_PWR_GOOD_OUT: 256 case AS3722_GPIO_IOSF_Q32K_OUT: 257 case AS3722_GPIO_IOSF_PWM_OUT: 258 case AS3722_GPIO_IOSF_SD6_LOW_VOLT_LOW: 259 ret = as3722_update_bits(as_pci->as3722, gpio_cntr_reg, 260 AS3722_GPIO_MODE_MASK, AS3722_GPIO_MODE_OUTPUT_VDDH); 261 if (ret < 0) { 262 dev_err(as_pci->dev, "GPIO%d_CTRL update failed %d\n", 263 group, ret); 264 return ret; 265 } 266 as_pci->gpio_control[group].mode_prop = 267 AS3722_GPIO_MODE_OUTPUT_VDDH; 268 break; 269 default: 270 break; 271 } 272 return ret; 273 } 274 275 static int as3722_pinctrl_gpio_get_mode(unsigned gpio_mode_prop, bool input) 276 { 277 if (gpio_mode_prop & AS3722_GPIO_MODE_HIGH_IMPED) 278 return -EINVAL; 279 280 if (gpio_mode_prop & AS3722_GPIO_MODE_OPEN_DRAIN) { 281 if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_UP) 282 return AS3722_GPIO_MODE_IO_OPEN_DRAIN_PULL_UP; 283 return AS3722_GPIO_MODE_IO_OPEN_DRAIN; 284 } 285 if (input) { 286 if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_UP) 287 return AS3722_GPIO_MODE_INPUT_PULL_UP; 288 else if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_DOWN) 289 return AS3722_GPIO_MODE_INPUT_PULL_DOWN; 290 return AS3722_GPIO_MODE_INPUT; 291 } 292 if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_DOWN) 293 return AS3722_GPIO_MODE_OUTPUT_VDDL; 294 return AS3722_GPIO_MODE_OUTPUT_VDDH; 295 } 296 297 static int as3722_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev, 298 struct pinctrl_gpio_range *range, unsigned offset) 299 { 300 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); 301 302 if (as_pci->gpio_control[offset].io_function) 303 return -EBUSY; 304 return 0; 305 } 306 307 static int as3722_pinctrl_gpio_set_direction(struct pinctrl_dev *pctldev, 308 struct pinctrl_gpio_range *range, unsigned offset, bool input) 309 { 310 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); 311 struct as3722 *as3722 = as_pci->as3722; 312 int mode; 313 314 mode = as3722_pinctrl_gpio_get_mode( 315 as_pci->gpio_control[offset].mode_prop, input); 316 if (mode < 0) { 317 dev_err(as_pci->dev, "%s direction for GPIO %d not supported\n", 318 (input) ? "Input" : "Output", offset); 319 return mode; 320 } 321 322 return as3722_update_bits(as3722, AS3722_GPIOn_CONTROL_REG(offset), 323 AS3722_GPIO_MODE_MASK, mode); 324 } 325 326 static const struct pinmux_ops as3722_pinmux_ops = { 327 .get_functions_count = as3722_pinctrl_get_funcs_count, 328 .get_function_name = as3722_pinctrl_get_func_name, 329 .get_function_groups = as3722_pinctrl_get_func_groups, 330 .set_mux = as3722_pinctrl_set, 331 .gpio_request_enable = as3722_pinctrl_gpio_request_enable, 332 .gpio_set_direction = as3722_pinctrl_gpio_set_direction, 333 }; 334 335 static int as3722_pinconf_get(struct pinctrl_dev *pctldev, 336 unsigned pin, unsigned long *config) 337 { 338 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); 339 enum pin_config_param param = pinconf_to_config_param(*config); 340 int arg = 0; 341 u16 prop; 342 343 switch (param) { 344 case PIN_CONFIG_BIAS_DISABLE: 345 prop = AS3722_GPIO_MODE_PULL_UP | 346 AS3722_GPIO_MODE_PULL_DOWN; 347 if (!(as_pci->gpio_control[pin].mode_prop & prop)) 348 arg = 1; 349 prop = 0; 350 break; 351 352 case PIN_CONFIG_BIAS_PULL_UP: 353 prop = AS3722_GPIO_MODE_PULL_UP; 354 break; 355 356 case PIN_CONFIG_BIAS_PULL_DOWN: 357 prop = AS3722_GPIO_MODE_PULL_DOWN; 358 break; 359 360 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 361 prop = AS3722_GPIO_MODE_OPEN_DRAIN; 362 break; 363 364 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 365 prop = AS3722_GPIO_MODE_HIGH_IMPED; 366 break; 367 368 default: 369 dev_err(as_pci->dev, "Properties not supported\n"); 370 return -ENOTSUPP; 371 } 372 373 if (as_pci->gpio_control[pin].mode_prop & prop) 374 arg = 1; 375 376 *config = pinconf_to_config_packed(param, (u16)arg); 377 return 0; 378 } 379 380 static int as3722_pinconf_set(struct pinctrl_dev *pctldev, 381 unsigned pin, unsigned long *configs, 382 unsigned num_configs) 383 { 384 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); 385 enum pin_config_param param; 386 int mode_prop; 387 int i; 388 389 for (i = 0; i < num_configs; i++) { 390 param = pinconf_to_config_param(configs[i]); 391 mode_prop = as_pci->gpio_control[pin].mode_prop; 392 393 switch (param) { 394 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 395 break; 396 397 case PIN_CONFIG_BIAS_DISABLE: 398 mode_prop &= ~(AS3722_GPIO_MODE_PULL_UP | 399 AS3722_GPIO_MODE_PULL_DOWN); 400 break; 401 case PIN_CONFIG_BIAS_PULL_UP: 402 mode_prop |= AS3722_GPIO_MODE_PULL_UP; 403 break; 404 405 case PIN_CONFIG_BIAS_PULL_DOWN: 406 mode_prop |= AS3722_GPIO_MODE_PULL_DOWN; 407 break; 408 409 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 410 mode_prop |= AS3722_GPIO_MODE_HIGH_IMPED; 411 break; 412 413 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 414 mode_prop |= AS3722_GPIO_MODE_OPEN_DRAIN; 415 break; 416 417 default: 418 dev_err(as_pci->dev, "Properties not supported\n"); 419 return -ENOTSUPP; 420 } 421 422 as_pci->gpio_control[pin].mode_prop = mode_prop; 423 } 424 return 0; 425 } 426 427 static const struct pinconf_ops as3722_pinconf_ops = { 428 .pin_config_get = as3722_pinconf_get, 429 .pin_config_set = as3722_pinconf_set, 430 }; 431 432 static struct pinctrl_desc as3722_pinctrl_desc = { 433 .pctlops = &as3722_pinctrl_ops, 434 .pmxops = &as3722_pinmux_ops, 435 .confops = &as3722_pinconf_ops, 436 .owner = THIS_MODULE, 437 }; 438 439 static int as3722_gpio_get(struct gpio_chip *chip, unsigned offset) 440 { 441 struct as3722_pctrl_info *as_pci = gpiochip_get_data(chip); 442 struct as3722 *as3722 = as_pci->as3722; 443 int ret; 444 u32 reg; 445 u32 control; 446 u32 val; 447 int mode; 448 int invert_enable; 449 450 ret = as3722_read(as3722, AS3722_GPIOn_CONTROL_REG(offset), &control); 451 if (ret < 0) { 452 dev_err(as_pci->dev, 453 "GPIO_CONTROL%d_REG read failed: %d\n", offset, ret); 454 return ret; 455 } 456 457 invert_enable = !!(control & AS3722_GPIO_INV); 458 mode = control & AS3722_GPIO_MODE_MASK; 459 switch (mode) { 460 case AS3722_GPIO_MODE_INPUT: 461 case AS3722_GPIO_MODE_INPUT_PULL_UP: 462 case AS3722_GPIO_MODE_INPUT_PULL_DOWN: 463 case AS3722_GPIO_MODE_IO_OPEN_DRAIN: 464 case AS3722_GPIO_MODE_IO_OPEN_DRAIN_PULL_UP: 465 reg = AS3722_GPIO_SIGNAL_IN_REG; 466 break; 467 case AS3722_GPIO_MODE_OUTPUT_VDDH: 468 case AS3722_GPIO_MODE_OUTPUT_VDDL: 469 reg = AS3722_GPIO_SIGNAL_OUT_REG; 470 break; 471 default: 472 return -EINVAL; 473 } 474 475 ret = as3722_read(as3722, reg, &val); 476 if (ret < 0) { 477 dev_err(as_pci->dev, 478 "GPIO_SIGNAL_IN_REG read failed: %d\n", ret); 479 return ret; 480 } 481 482 val = !!(val & AS3722_GPIOn_SIGNAL(offset)); 483 return (invert_enable) ? !val : val; 484 } 485 486 static void as3722_gpio_set(struct gpio_chip *chip, unsigned offset, 487 int value) 488 { 489 struct as3722_pctrl_info *as_pci = gpiochip_get_data(chip); 490 struct as3722 *as3722 = as_pci->as3722; 491 int en_invert; 492 u32 val; 493 int ret; 494 495 ret = as3722_read(as3722, AS3722_GPIOn_CONTROL_REG(offset), &val); 496 if (ret < 0) { 497 dev_err(as_pci->dev, 498 "GPIO_CONTROL%d_REG read failed: %d\n", offset, ret); 499 return; 500 } 501 en_invert = !!(val & AS3722_GPIO_INV); 502 503 if (value) 504 val = (en_invert) ? 0 : AS3722_GPIOn_SIGNAL(offset); 505 else 506 val = (en_invert) ? AS3722_GPIOn_SIGNAL(offset) : 0; 507 508 ret = as3722_update_bits(as3722, AS3722_GPIO_SIGNAL_OUT_REG, 509 AS3722_GPIOn_SIGNAL(offset), val); 510 if (ret < 0) 511 dev_err(as_pci->dev, 512 "GPIO_SIGNAL_OUT_REG update failed: %d\n", ret); 513 } 514 515 static int as3722_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 516 { 517 return pinctrl_gpio_direction_input(chip->base + offset); 518 } 519 520 static int as3722_gpio_direction_output(struct gpio_chip *chip, 521 unsigned offset, int value) 522 { 523 as3722_gpio_set(chip, offset, value); 524 return pinctrl_gpio_direction_output(chip->base + offset); 525 } 526 527 static int as3722_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 528 { 529 struct as3722_pctrl_info *as_pci = gpiochip_get_data(chip); 530 531 return as3722_irq_get_virq(as_pci->as3722, offset); 532 } 533 534 static const struct gpio_chip as3722_gpio_chip = { 535 .label = "as3722-gpio", 536 .owner = THIS_MODULE, 537 .request = gpiochip_generic_request, 538 .free = gpiochip_generic_free, 539 .get = as3722_gpio_get, 540 .set = as3722_gpio_set, 541 .direction_input = as3722_gpio_direction_input, 542 .direction_output = as3722_gpio_direction_output, 543 .to_irq = as3722_gpio_to_irq, 544 .can_sleep = true, 545 .ngpio = AS3722_PIN_NUM, 546 .base = -1, 547 }; 548 549 static int as3722_pinctrl_probe(struct platform_device *pdev) 550 { 551 struct as3722_pctrl_info *as_pci; 552 int ret; 553 554 as_pci = devm_kzalloc(&pdev->dev, sizeof(*as_pci), GFP_KERNEL); 555 if (!as_pci) 556 return -ENOMEM; 557 558 as_pci->dev = &pdev->dev; 559 as_pci->dev->of_node = pdev->dev.parent->of_node; 560 as_pci->as3722 = dev_get_drvdata(pdev->dev.parent); 561 platform_set_drvdata(pdev, as_pci); 562 563 as_pci->pins = as3722_pins_desc; 564 as_pci->num_pins = ARRAY_SIZE(as3722_pins_desc); 565 as_pci->functions = as3722_pin_function; 566 as_pci->num_functions = ARRAY_SIZE(as3722_pin_function); 567 as_pci->pin_groups = as3722_pingroups; 568 as_pci->num_pin_groups = ARRAY_SIZE(as3722_pingroups); 569 as3722_pinctrl_desc.name = dev_name(&pdev->dev); 570 as3722_pinctrl_desc.pins = as3722_pins_desc; 571 as3722_pinctrl_desc.npins = ARRAY_SIZE(as3722_pins_desc); 572 as_pci->pctl = devm_pinctrl_register(&pdev->dev, &as3722_pinctrl_desc, 573 as_pci); 574 if (IS_ERR(as_pci->pctl)) { 575 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 576 return PTR_ERR(as_pci->pctl); 577 } 578 579 as_pci->gpio_chip = as3722_gpio_chip; 580 as_pci->gpio_chip.parent = &pdev->dev; 581 as_pci->gpio_chip.of_node = pdev->dev.parent->of_node; 582 ret = gpiochip_add_data(&as_pci->gpio_chip, as_pci); 583 if (ret < 0) { 584 dev_err(&pdev->dev, "Couldn't register gpiochip, %d\n", ret); 585 return ret; 586 } 587 588 ret = gpiochip_add_pin_range(&as_pci->gpio_chip, dev_name(&pdev->dev), 589 0, 0, AS3722_PIN_NUM); 590 if (ret < 0) { 591 dev_err(&pdev->dev, "Couldn't add pin range, %d\n", ret); 592 goto fail_range_add; 593 } 594 595 return 0; 596 597 fail_range_add: 598 gpiochip_remove(&as_pci->gpio_chip); 599 return ret; 600 } 601 602 static int as3722_pinctrl_remove(struct platform_device *pdev) 603 { 604 struct as3722_pctrl_info *as_pci = platform_get_drvdata(pdev); 605 606 gpiochip_remove(&as_pci->gpio_chip); 607 return 0; 608 } 609 610 static const struct of_device_id as3722_pinctrl_of_match[] = { 611 { .compatible = "ams,as3722-pinctrl", }, 612 { }, 613 }; 614 MODULE_DEVICE_TABLE(of, as3722_pinctrl_of_match); 615 616 static struct platform_driver as3722_pinctrl_driver = { 617 .driver = { 618 .name = "as3722-pinctrl", 619 .of_match_table = as3722_pinctrl_of_match, 620 }, 621 .probe = as3722_pinctrl_probe, 622 .remove = as3722_pinctrl_remove, 623 }; 624 module_platform_driver(as3722_pinctrl_driver); 625 626 MODULE_ALIAS("platform:as3722-pinctrl"); 627 MODULE_DESCRIPTION("AS3722 pin control and GPIO driver"); 628 MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>"); 629 MODULE_LICENSE("GPL v2"); 630