1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Apple SoC pinctrl+GPIO+external IRQ driver 4 * 5 * Copyright (C) The Asahi Linux Contributors 6 * Copyright (C) 2020 Corellium LLC 7 * 8 * Based on: pinctrl-pistachio.c 9 * Copyright (C) 2014 Imagination Technologies Ltd. 10 * Copyright (C) 2014 Google, Inc. 11 */ 12 13 #include <dt-bindings/pinctrl/apple.h> 14 #include <linux/bits.h> 15 #include <linux/gpio/driver.h> 16 #include <linux/interrupt.h> 17 #include <linux/irq.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_irq.h> 21 #include <linux/pinctrl/pinctrl.h> 22 #include <linux/pinctrl/pinmux.h> 23 #include <linux/platform_device.h> 24 #include <linux/regmap.h> 25 26 #include "pinctrl-utils.h" 27 #include "core.h" 28 #include "pinmux.h" 29 30 struct apple_gpio_pinctrl { 31 struct device *dev; 32 struct pinctrl_dev *pctldev; 33 34 void __iomem *base; 35 struct regmap *map; 36 37 struct pinctrl_desc pinctrl_desc; 38 struct gpio_chip gpio_chip; 39 u8 irqgrps[]; 40 }; 41 42 #define REG_GPIO(x) (4 * (x)) 43 #define REG_GPIOx_DATA BIT(0) 44 #define REG_GPIOx_MODE GENMASK(3, 1) 45 #define REG_GPIOx_OUT 1 46 #define REG_GPIOx_IN_IRQ_HI 2 47 #define REG_GPIOx_IN_IRQ_LO 3 48 #define REG_GPIOx_IN_IRQ_UP 4 49 #define REG_GPIOx_IN_IRQ_DN 5 50 #define REG_GPIOx_IN_IRQ_ANY 6 51 #define REG_GPIOx_IN_IRQ_OFF 7 52 #define REG_GPIOx_PERIPH GENMASK(6, 5) 53 #define REG_GPIOx_PULL GENMASK(8, 7) 54 #define REG_GPIOx_PULL_OFF 0 55 #define REG_GPIOx_PULL_DOWN 1 56 #define REG_GPIOx_PULL_UP_STRONG 2 57 #define REG_GPIOx_PULL_UP 3 58 #define REG_GPIOx_INPUT_ENABLE BIT(9) 59 #define REG_GPIOx_DRIVE_STRENGTH0 GENMASK(11, 10) 60 #define REG_GPIOx_SCHMITT BIT(15) 61 #define REG_GPIOx_GRP GENMASK(18, 16) 62 #define REG_GPIOx_LOCK BIT(21) 63 #define REG_GPIOx_DRIVE_STRENGTH1 GENMASK(23, 22) 64 #define REG_IRQ(g, x) (0x800 + 0x40 * (g) + 4 * ((x) >> 5)) 65 66 struct regmap_config regmap_config = { 67 .reg_bits = 32, 68 .val_bits = 32, 69 .reg_stride = 4, 70 .cache_type = REGCACHE_FLAT, 71 .max_register = 512 * sizeof(u32), 72 .num_reg_defaults_raw = 512, 73 .use_relaxed_mmio = true, 74 }; 75 76 /* No locking needed to mask/unmask IRQs as the interrupt mode is per pin-register. */ 77 static void apple_gpio_set_reg(struct apple_gpio_pinctrl *pctl, 78 unsigned int pin, u32 mask, u32 value) 79 { 80 regmap_update_bits(pctl->map, REG_GPIO(pin), mask, value); 81 } 82 83 static u32 apple_gpio_get_reg(struct apple_gpio_pinctrl *pctl, 84 unsigned int pin) 85 { 86 int ret; 87 u32 val; 88 89 ret = regmap_read(pctl->map, REG_GPIO(pin), &val); 90 if (ret) 91 return 0; 92 93 return val; 94 } 95 96 /* Pin controller functions */ 97 98 static int apple_gpio_dt_node_to_map(struct pinctrl_dev *pctldev, 99 struct device_node *node, 100 struct pinctrl_map **map, 101 unsigned *num_maps) 102 { 103 unsigned reserved_maps; 104 struct apple_gpio_pinctrl *pctl; 105 u32 pinfunc, pin, func; 106 int num_pins, i, ret; 107 const char *group_name; 108 const char *function_name; 109 110 *map = NULL; 111 *num_maps = 0; 112 reserved_maps = 0; 113 114 pctl = pinctrl_dev_get_drvdata(pctldev); 115 116 ret = of_property_count_u32_elems(node, "pinmux"); 117 if (ret <= 0) { 118 dev_err(pctl->dev, 119 "missing or empty pinmux property in node %pOFn.\n", 120 node); 121 return ret ? ret : -EINVAL; 122 } 123 124 num_pins = ret; 125 126 ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps, num_maps, num_pins); 127 if (ret) 128 return ret; 129 130 for (i = 0; i < num_pins; i++) { 131 ret = of_property_read_u32_index(node, "pinmux", i, &pinfunc); 132 if (ret) 133 goto free_map; 134 135 pin = APPLE_PIN(pinfunc); 136 func = APPLE_FUNC(pinfunc); 137 138 if (func >= pinmux_generic_get_function_count(pctldev)) { 139 ret = -EINVAL; 140 goto free_map; 141 } 142 143 group_name = pinctrl_generic_get_group_name(pctldev, pin); 144 function_name = pinmux_generic_get_function_name(pctl->pctldev, func); 145 ret = pinctrl_utils_add_map_mux(pctl->pctldev, map, 146 &reserved_maps, num_maps, 147 group_name, function_name); 148 if (ret) 149 goto free_map; 150 } 151 152 free_map: 153 if (ret < 0) 154 pinctrl_utils_free_map(pctldev, *map, *num_maps); 155 156 return ret; 157 } 158 159 static const struct pinctrl_ops apple_gpio_pinctrl_ops = { 160 .get_groups_count = pinctrl_generic_get_group_count, 161 .get_group_name = pinctrl_generic_get_group_name, 162 .get_group_pins = pinctrl_generic_get_group_pins, 163 .dt_node_to_map = apple_gpio_dt_node_to_map, 164 .dt_free_map = pinctrl_utils_free_map, 165 }; 166 167 /* Pin multiplexer functions */ 168 169 static int apple_gpio_pinmux_set(struct pinctrl_dev *pctldev, unsigned func, 170 unsigned group) 171 { 172 struct apple_gpio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 173 174 apple_gpio_set_reg( 175 pctl, group, REG_GPIOx_PERIPH | REG_GPIOx_INPUT_ENABLE, 176 FIELD_PREP(REG_GPIOx_PERIPH, func) | REG_GPIOx_INPUT_ENABLE); 177 178 return 0; 179 } 180 181 static const struct pinmux_ops apple_gpio_pinmux_ops = { 182 .get_functions_count = pinmux_generic_get_function_count, 183 .get_function_name = pinmux_generic_get_function_name, 184 .get_function_groups = pinmux_generic_get_function_groups, 185 .set_mux = apple_gpio_pinmux_set, 186 .strict = true, 187 }; 188 189 /* GPIO chip functions */ 190 191 static int apple_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 192 { 193 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip); 194 unsigned int reg = apple_gpio_get_reg(pctl, offset); 195 196 if (FIELD_GET(REG_GPIOx_MODE, reg) == REG_GPIOx_OUT) 197 return GPIO_LINE_DIRECTION_OUT; 198 return GPIO_LINE_DIRECTION_IN; 199 } 200 201 static int apple_gpio_get(struct gpio_chip *chip, unsigned offset) 202 { 203 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip); 204 unsigned int reg = apple_gpio_get_reg(pctl, offset); 205 206 /* 207 * If this is an input GPIO, read the actual value (not the 208 * cached regmap value) 209 */ 210 if (FIELD_GET(REG_GPIOx_MODE, reg) != REG_GPIOx_OUT) 211 reg = readl_relaxed(pctl->base + REG_GPIO(offset)); 212 213 return !!(reg & REG_GPIOx_DATA); 214 } 215 216 static void apple_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 217 { 218 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip); 219 220 apple_gpio_set_reg(pctl, offset, REG_GPIOx_DATA, value ? REG_GPIOx_DATA : 0); 221 } 222 223 static int apple_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 224 { 225 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip); 226 227 apple_gpio_set_reg(pctl, offset, 228 REG_GPIOx_PERIPH | REG_GPIOx_MODE | REG_GPIOx_DATA | 229 REG_GPIOx_INPUT_ENABLE, 230 FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_IN_IRQ_OFF) | 231 REG_GPIOx_INPUT_ENABLE); 232 return 0; 233 } 234 235 static int apple_gpio_direction_output(struct gpio_chip *chip, 236 unsigned int offset, int value) 237 { 238 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip); 239 240 apple_gpio_set_reg(pctl, offset, 241 REG_GPIOx_PERIPH | REG_GPIOx_MODE | REG_GPIOx_DATA, 242 FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_OUT) | 243 (value ? REG_GPIOx_DATA : 0)); 244 return 0; 245 } 246 247 /* IRQ chip functions */ 248 249 static void apple_gpio_irq_ack(struct irq_data *data) 250 { 251 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(irq_data_get_irq_chip_data(data)); 252 unsigned int irqgrp = FIELD_GET(REG_GPIOx_GRP, apple_gpio_get_reg(pctl, data->hwirq)); 253 254 writel(BIT(data->hwirq % 32), pctl->base + REG_IRQ(irqgrp, data->hwirq)); 255 } 256 257 static unsigned int apple_gpio_irq_type(unsigned int type) 258 { 259 switch (type & IRQ_TYPE_SENSE_MASK) { 260 case IRQ_TYPE_EDGE_RISING: 261 return REG_GPIOx_IN_IRQ_UP; 262 case IRQ_TYPE_EDGE_FALLING: 263 return REG_GPIOx_IN_IRQ_DN; 264 case IRQ_TYPE_EDGE_BOTH: 265 return REG_GPIOx_IN_IRQ_ANY; 266 case IRQ_TYPE_LEVEL_HIGH: 267 return REG_GPIOx_IN_IRQ_HI; 268 case IRQ_TYPE_LEVEL_LOW: 269 return REG_GPIOx_IN_IRQ_LO; 270 default: 271 return REG_GPIOx_IN_IRQ_OFF; 272 } 273 } 274 275 static void apple_gpio_irq_mask(struct irq_data *data) 276 { 277 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 278 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(gc); 279 280 apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE, 281 FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_IN_IRQ_OFF)); 282 gpiochip_disable_irq(gc, data->hwirq); 283 } 284 285 static void apple_gpio_irq_unmask(struct irq_data *data) 286 { 287 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 288 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(gc); 289 unsigned int irqtype = apple_gpio_irq_type(irqd_get_trigger_type(data)); 290 291 gpiochip_enable_irq(gc, data->hwirq); 292 apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE, 293 FIELD_PREP(REG_GPIOx_MODE, irqtype)); 294 } 295 296 static unsigned int apple_gpio_irq_startup(struct irq_data *data) 297 { 298 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 299 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip); 300 301 apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_GRP, 302 FIELD_PREP(REG_GPIOx_GRP, 0)); 303 304 apple_gpio_direction_input(chip, data->hwirq); 305 apple_gpio_irq_unmask(data); 306 307 return 0; 308 } 309 310 static int apple_gpio_irq_set_type(struct irq_data *data, unsigned int type) 311 { 312 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(irq_data_get_irq_chip_data(data)); 313 unsigned int irqtype = apple_gpio_irq_type(type); 314 315 if (irqtype == REG_GPIOx_IN_IRQ_OFF) 316 return -EINVAL; 317 318 apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE, 319 FIELD_PREP(REG_GPIOx_MODE, irqtype)); 320 321 if (type & IRQ_TYPE_LEVEL_MASK) 322 irq_set_handler_locked(data, handle_level_irq); 323 else 324 irq_set_handler_locked(data, handle_edge_irq); 325 return 0; 326 } 327 328 static void apple_gpio_irq_handler(struct irq_desc *desc) 329 { 330 struct irq_chip *chip = irq_desc_get_chip(desc); 331 u8 *grpp = irq_desc_get_handler_data(desc); 332 struct apple_gpio_pinctrl *pctl; 333 unsigned int pinh, pinl; 334 unsigned long pending; 335 struct gpio_chip *gc; 336 337 pctl = container_of(grpp - *grpp, typeof(*pctl), irqgrps[0]); 338 gc = &pctl->gpio_chip; 339 340 chained_irq_enter(chip, desc); 341 for (pinh = 0; pinh < gc->ngpio; pinh += 32) { 342 pending = readl_relaxed(pctl->base + REG_IRQ(*grpp, pinh)); 343 for_each_set_bit(pinl, &pending, 32) 344 generic_handle_domain_irq(gc->irq.domain, pinh + pinl); 345 } 346 chained_irq_exit(chip, desc); 347 } 348 349 static const struct irq_chip apple_gpio_irqchip = { 350 .name = "Apple-GPIO", 351 .irq_startup = apple_gpio_irq_startup, 352 .irq_ack = apple_gpio_irq_ack, 353 .irq_mask = apple_gpio_irq_mask, 354 .irq_unmask = apple_gpio_irq_unmask, 355 .irq_set_type = apple_gpio_irq_set_type, 356 .flags = IRQCHIP_IMMUTABLE, 357 GPIOCHIP_IRQ_RESOURCE_HELPERS, 358 }; 359 360 /* Probe & register */ 361 362 static int apple_gpio_register(struct apple_gpio_pinctrl *pctl) 363 { 364 struct gpio_irq_chip *girq = &pctl->gpio_chip.irq; 365 void **irq_data = NULL; 366 int ret; 367 368 pctl->gpio_chip.label = dev_name(pctl->dev); 369 pctl->gpio_chip.request = gpiochip_generic_request; 370 pctl->gpio_chip.free = gpiochip_generic_free; 371 pctl->gpio_chip.get_direction = apple_gpio_get_direction; 372 pctl->gpio_chip.direction_input = apple_gpio_direction_input; 373 pctl->gpio_chip.direction_output = apple_gpio_direction_output; 374 pctl->gpio_chip.get = apple_gpio_get; 375 pctl->gpio_chip.set = apple_gpio_set; 376 pctl->gpio_chip.base = -1; 377 pctl->gpio_chip.ngpio = pctl->pinctrl_desc.npins; 378 pctl->gpio_chip.parent = pctl->dev; 379 380 if (girq->num_parents) { 381 int i; 382 383 gpio_irq_chip_set_chip(girq, &apple_gpio_irqchip); 384 girq->parent_handler = apple_gpio_irq_handler; 385 386 girq->parents = kmalloc_array(girq->num_parents, 387 sizeof(*girq->parents), 388 GFP_KERNEL); 389 irq_data = kmalloc_array(girq->num_parents, sizeof(*irq_data), 390 GFP_KERNEL); 391 if (!girq->parents || !irq_data) { 392 ret = -ENOMEM; 393 goto out_free_irq_data; 394 } 395 396 for (i = 0; i < girq->num_parents; i++) { 397 ret = platform_get_irq(to_platform_device(pctl->dev), i); 398 if (ret < 0) 399 goto out_free_irq_data; 400 401 girq->parents[i] = ret; 402 pctl->irqgrps[i] = i; 403 irq_data[i] = &pctl->irqgrps[i]; 404 } 405 406 girq->parent_handler_data_array = irq_data; 407 girq->per_parent_data = true; 408 girq->default_type = IRQ_TYPE_NONE; 409 girq->handler = handle_level_irq; 410 } 411 412 ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl); 413 414 out_free_irq_data: 415 kfree(girq->parents); 416 kfree(irq_data); 417 418 return ret; 419 } 420 421 static int apple_gpio_pinctrl_probe(struct platform_device *pdev) 422 { 423 struct apple_gpio_pinctrl *pctl; 424 struct pinctrl_pin_desc *pins; 425 unsigned int npins; 426 const char **pin_names; 427 unsigned int *pin_nums; 428 static const char* pinmux_functions[] = { 429 "gpio", "periph1", "periph2", "periph3" 430 }; 431 unsigned int i, nirqs = 0; 432 int res; 433 434 if (of_property_read_bool(pdev->dev.of_node, "interrupt-controller")) { 435 res = platform_irq_count(pdev); 436 if (res > 0) 437 nirqs = res; 438 } 439 440 pctl = devm_kzalloc(&pdev->dev, struct_size(pctl, irqgrps, nirqs), 441 GFP_KERNEL); 442 if (!pctl) 443 return -ENOMEM; 444 pctl->dev = &pdev->dev; 445 pctl->gpio_chip.irq.num_parents = nirqs; 446 dev_set_drvdata(&pdev->dev, pctl); 447 448 if (of_property_read_u32(pdev->dev.of_node, "apple,npins", &npins)) 449 return dev_err_probe(&pdev->dev, -EINVAL, 450 "apple,npins property not found\n"); 451 452 pins = devm_kmalloc_array(&pdev->dev, npins, sizeof(pins[0]), 453 GFP_KERNEL); 454 pin_names = devm_kmalloc_array(&pdev->dev, npins, sizeof(pin_names[0]), 455 GFP_KERNEL); 456 pin_nums = devm_kmalloc_array(&pdev->dev, npins, sizeof(pin_nums[0]), 457 GFP_KERNEL); 458 if (!pins || !pin_names || !pin_nums) 459 return -ENOMEM; 460 461 pctl->base = devm_platform_ioremap_resource(pdev, 0); 462 if (IS_ERR(pctl->base)) 463 return PTR_ERR(pctl->base); 464 465 pctl->map = devm_regmap_init_mmio(&pdev->dev, pctl->base, ®map_config); 466 if (IS_ERR(pctl->map)) 467 return dev_err_probe(&pdev->dev, PTR_ERR(pctl->map), 468 "Failed to create regmap\n"); 469 470 for (i = 0; i < npins; i++) { 471 pins[i].number = i; 472 pins[i].name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "PIN%u", i); 473 pins[i].drv_data = pctl; 474 pin_names[i] = pins[i].name; 475 pin_nums[i] = i; 476 } 477 478 pctl->pinctrl_desc.name = dev_name(pctl->dev); 479 pctl->pinctrl_desc.pins = pins; 480 pctl->pinctrl_desc.npins = npins; 481 pctl->pinctrl_desc.pctlops = &apple_gpio_pinctrl_ops; 482 pctl->pinctrl_desc.pmxops = &apple_gpio_pinmux_ops; 483 484 pctl->pctldev = devm_pinctrl_register(&pdev->dev, &pctl->pinctrl_desc, pctl); 485 if (IS_ERR(pctl->pctldev)) 486 return dev_err_probe(&pdev->dev, PTR_ERR(pctl->pctldev), 487 "Failed to register pinctrl device.\n"); 488 489 for (i = 0; i < npins; i++) { 490 res = pinctrl_generic_add_group(pctl->pctldev, pins[i].name, 491 pin_nums + i, 1, pctl); 492 if (res < 0) 493 return dev_err_probe(pctl->dev, res, 494 "Failed to register group"); 495 } 496 497 for (i = 0; i < ARRAY_SIZE(pinmux_functions); ++i) { 498 res = pinmux_generic_add_function(pctl->pctldev, pinmux_functions[i], 499 pin_names, npins, pctl); 500 if (res < 0) 501 return dev_err_probe(pctl->dev, res, 502 "Failed to register function."); 503 } 504 505 return apple_gpio_register(pctl); 506 } 507 508 static const struct of_device_id apple_gpio_pinctrl_of_match[] = { 509 { .compatible = "apple,pinctrl", }, 510 { } 511 }; 512 513 static struct platform_driver apple_gpio_pinctrl_driver = { 514 .driver = { 515 .name = "apple-gpio-pinctrl", 516 .of_match_table = apple_gpio_pinctrl_of_match, 517 .suppress_bind_attrs = true, 518 }, 519 .probe = apple_gpio_pinctrl_probe, 520 }; 521 module_platform_driver(apple_gpio_pinctrl_driver); 522 523 MODULE_DESCRIPTION("Apple pinctrl/GPIO driver"); 524 MODULE_AUTHOR("Stan Skowronek <stan@corellium.com>"); 525 MODULE_AUTHOR("Joey Gouly <joey.gouly@arm.com>"); 526 MODULE_LICENSE("GPL v2"); 527