1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Apple SoC pinctrl+GPIO+external IRQ driver 4 * 5 * Copyright (C) The Asahi Linux Contributors 6 * Copyright (C) 2020 Corellium LLC 7 * 8 * Based on: pinctrl-pistachio.c 9 * Copyright (C) 2014 Imagination Technologies Ltd. 10 * Copyright (C) 2014 Google, Inc. 11 */ 12 13 #include <dt-bindings/pinctrl/apple.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/interrupt.h> 16 #include <linux/irq.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_irq.h> 20 #include <linux/pinctrl/pinctrl.h> 21 #include <linux/pinctrl/pinmux.h> 22 #include <linux/platform_device.h> 23 #include <linux/regmap.h> 24 25 #include "pinctrl-utils.h" 26 #include "core.h" 27 #include "pinmux.h" 28 29 struct apple_gpio_pinctrl { 30 struct device *dev; 31 struct pinctrl_dev *pctldev; 32 33 void __iomem *base; 34 struct regmap *map; 35 36 struct pinctrl_desc pinctrl_desc; 37 struct gpio_chip gpio_chip; 38 struct irq_chip irq_chip; 39 u8 irqgrps[0]; 40 }; 41 42 #define REG_GPIO(x) (4 * (x)) 43 #define REG_GPIOx_DATA BIT(0) 44 #define REG_GPIOx_MODE GENMASK(3, 1) 45 #define REG_GPIOx_OUT 1 46 #define REG_GPIOx_IN_IRQ_HI 2 47 #define REG_GPIOx_IN_IRQ_LO 3 48 #define REG_GPIOx_IN_IRQ_UP 4 49 #define REG_GPIOx_IN_IRQ_DN 5 50 #define REG_GPIOx_IN_IRQ_ANY 6 51 #define REG_GPIOx_IN_IRQ_OFF 7 52 #define REG_GPIOx_PERIPH GENMASK(6, 5) 53 #define REG_GPIOx_PULL GENMASK(8, 7) 54 #define REG_GPIOx_PULL_OFF 0 55 #define REG_GPIOx_PULL_DOWN 1 56 #define REG_GPIOx_PULL_UP_STRONG 2 57 #define REG_GPIOx_PULL_UP 3 58 #define REG_GPIOx_INPUT_ENABLE BIT(9) 59 #define REG_GPIOx_DRIVE_STRENGTH0 GENMASK(11, 10) 60 #define REG_GPIOx_SCHMITT BIT(15) 61 #define REG_GPIOx_GRP GENMASK(18, 16) 62 #define REG_GPIOx_LOCK BIT(21) 63 #define REG_GPIOx_DRIVE_STRENGTH1 GENMASK(23, 22) 64 #define REG_IRQ(g, x) (0x800 + 0x40 * (g) + 4 * ((x) >> 5)) 65 66 struct regmap_config regmap_config = { 67 .reg_bits = 32, 68 .val_bits = 32, 69 .reg_stride = 4, 70 .cache_type = REGCACHE_FLAT, 71 .max_register = 512 * sizeof(u32), 72 .num_reg_defaults_raw = 512, 73 .use_relaxed_mmio = true 74 }; 75 76 // No locking needed to mask/unmask IRQs as the interrupt mode is per pin-register. 77 static void apple_gpio_set_reg(struct apple_gpio_pinctrl *pctl, 78 unsigned int pin, u32 mask, u32 value) 79 { 80 regmap_update_bits(pctl->map, REG_GPIO(pin), mask, value); 81 } 82 83 static uint32_t apple_gpio_get_reg(struct apple_gpio_pinctrl *pctl, 84 unsigned int pin) 85 { 86 unsigned int val = 0; 87 88 regmap_read(pctl->map, REG_GPIO(pin), &val); 89 return val; 90 } 91 92 /* Pin controller functions */ 93 94 static int apple_gpio_dt_node_to_map(struct pinctrl_dev *pctldev, 95 struct device_node *node, 96 struct pinctrl_map **map, 97 unsigned *num_maps) 98 { 99 unsigned reserved_maps; 100 struct apple_gpio_pinctrl *pctl; 101 u32 pinfunc, pin, func; 102 int num_pins, i, ret; 103 const char *group_name; 104 const char *function_name; 105 106 *map = NULL; 107 *num_maps = 0; 108 reserved_maps = 0; 109 110 pctl = pinctrl_dev_get_drvdata(pctldev); 111 112 ret = of_property_count_u32_elems(node, "pinmux"); 113 if (ret <= 0) { 114 dev_err(pctl->dev, 115 "missing or empty pinmux property in node %pOFn.\n", 116 node); 117 return ret; 118 } 119 120 num_pins = ret; 121 122 ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps, num_maps, 123 num_pins); 124 if (ret) 125 return ret; 126 127 for (i = 0; i < num_pins; i++) { 128 ret = of_property_read_u32_index(node, "pinmux", i, &pinfunc); 129 if (ret) 130 goto free_map; 131 132 pin = APPLE_PIN(pinfunc); 133 func = APPLE_FUNC(pinfunc); 134 135 if (func >= pinmux_generic_get_function_count(pctldev)) { 136 ret = -EINVAL; 137 goto free_map; 138 } 139 140 group_name = pinctrl_generic_get_group_name(pctldev, pin); 141 function_name = 142 pinmux_generic_get_function_name(pctl->pctldev, func); 143 ret = pinctrl_utils_add_map_mux(pctl->pctldev, map, 144 &reserved_maps, num_maps, 145 group_name, function_name); 146 if (ret) 147 goto free_map; 148 } 149 150 free_map: 151 if (ret < 0) 152 pinctrl_utils_free_map(pctldev, *map, *num_maps); 153 154 return ret; 155 } 156 157 static const struct pinctrl_ops apple_gpio_pinctrl_ops = { 158 .get_groups_count = pinctrl_generic_get_group_count, 159 .get_group_name = pinctrl_generic_get_group_name, 160 .get_group_pins = pinctrl_generic_get_group_pins, 161 .dt_node_to_map = apple_gpio_dt_node_to_map, 162 .dt_free_map = pinctrl_utils_free_map, 163 }; 164 165 /* Pin multiplexer functions */ 166 167 static int apple_gpio_pinmux_set(struct pinctrl_dev *pctldev, unsigned func, 168 unsigned group) 169 { 170 struct apple_gpio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 171 172 apple_gpio_set_reg( 173 pctl, group, REG_GPIOx_PERIPH | REG_GPIOx_INPUT_ENABLE, 174 FIELD_PREP(REG_GPIOx_PERIPH, func) | REG_GPIOx_INPUT_ENABLE); 175 176 return 0; 177 } 178 179 static const struct pinmux_ops apple_gpio_pinmux_ops = { 180 .get_functions_count = pinmux_generic_get_function_count, 181 .get_function_name = pinmux_generic_get_function_name, 182 .get_function_groups = pinmux_generic_get_function_groups, 183 .set_mux = apple_gpio_pinmux_set, 184 .strict = true, 185 }; 186 187 /* GPIO chip functions */ 188 189 static int apple_gpio_get_direction(struct gpio_chip *chip, 190 unsigned int offset) 191 { 192 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip); 193 unsigned int reg = apple_gpio_get_reg(pctl, offset); 194 195 return (FIELD_GET(REG_GPIOx_MODE, reg) == REG_GPIOx_OUT) ? 196 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 197 } 198 199 static int apple_gpio_get(struct gpio_chip *chip, unsigned offset) 200 { 201 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip); 202 unsigned int reg = apple_gpio_get_reg(pctl, offset); 203 204 /* 205 * If this is an input GPIO, read the actual value (not the 206 * cached regmap value) 207 */ 208 if (FIELD_GET(REG_GPIOx_MODE, reg) != REG_GPIOx_OUT) 209 reg = readl_relaxed(pctl->base + REG_GPIO(offset)); 210 211 return !!(reg & REG_GPIOx_DATA); 212 } 213 214 static void apple_gpio_set(struct gpio_chip *chip, unsigned int offset, 215 int value) 216 { 217 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip); 218 219 apple_gpio_set_reg(pctl, offset, REG_GPIOx_DATA, 220 value ? REG_GPIOx_DATA : 0); 221 } 222 223 static int apple_gpio_direction_input(struct gpio_chip *chip, 224 unsigned int offset) 225 { 226 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip); 227 228 apple_gpio_set_reg(pctl, offset, 229 REG_GPIOx_PERIPH | REG_GPIOx_MODE | REG_GPIOx_DATA | 230 REG_GPIOx_INPUT_ENABLE, 231 FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_IN_IRQ_OFF) | 232 REG_GPIOx_INPUT_ENABLE); 233 return 0; 234 } 235 236 static int apple_gpio_direction_output(struct gpio_chip *chip, 237 unsigned int offset, int value) 238 { 239 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip); 240 241 apple_gpio_set_reg(pctl, offset, 242 REG_GPIOx_PERIPH | REG_GPIOx_MODE | REG_GPIOx_DATA, 243 FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_OUT) | 244 (value ? REG_GPIOx_DATA : 0)); 245 return 0; 246 } 247 248 /* IRQ chip functions */ 249 250 static void apple_gpio_irq_ack(struct irq_data *data) 251 { 252 struct apple_gpio_pinctrl *pctl = 253 gpiochip_get_data(irq_data_get_irq_chip_data(data)); 254 unsigned int irqgrp = 255 FIELD_GET(REG_GPIOx_GRP, apple_gpio_get_reg(pctl, data->hwirq)); 256 257 writel(BIT(data->hwirq & 31), 258 pctl->base + REG_IRQ(irqgrp, data->hwirq)); 259 } 260 261 static int apple_gpio_irq_type(unsigned int type) 262 { 263 switch (type & IRQ_TYPE_SENSE_MASK) { 264 case IRQ_TYPE_EDGE_RISING: 265 return REG_GPIOx_IN_IRQ_UP; 266 case IRQ_TYPE_EDGE_FALLING: 267 return REG_GPIOx_IN_IRQ_DN; 268 case IRQ_TYPE_EDGE_BOTH: 269 return REG_GPIOx_IN_IRQ_ANY; 270 case IRQ_TYPE_LEVEL_HIGH: 271 return REG_GPIOx_IN_IRQ_HI; 272 case IRQ_TYPE_LEVEL_LOW: 273 return REG_GPIOx_IN_IRQ_LO; 274 default: 275 return -EINVAL; 276 } 277 } 278 279 static void apple_gpio_irq_mask(struct irq_data *data) 280 { 281 struct apple_gpio_pinctrl *pctl = 282 gpiochip_get_data(irq_data_get_irq_chip_data(data)); 283 apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE, 284 FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_IN_IRQ_OFF)); 285 } 286 287 static void apple_gpio_irq_unmask(struct irq_data *data) 288 { 289 struct apple_gpio_pinctrl *pctl = 290 gpiochip_get_data(irq_data_get_irq_chip_data(data)); 291 int irqtype = apple_gpio_irq_type(irqd_get_trigger_type(data)); 292 293 apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE, 294 FIELD_PREP(REG_GPIOx_MODE, irqtype)); 295 } 296 297 static unsigned int apple_gpio_irq_startup(struct irq_data *data) 298 { 299 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 300 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip); 301 302 apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_GRP, 303 FIELD_PREP(REG_GPIOx_GRP, 0)); 304 305 apple_gpio_direction_input(chip, data->hwirq); 306 apple_gpio_irq_unmask(data); 307 308 return 0; 309 } 310 311 static int apple_gpio_irq_set_type(struct irq_data *data, 312 unsigned int type) 313 { 314 struct apple_gpio_pinctrl *pctl = 315 gpiochip_get_data(irq_data_get_irq_chip_data(data)); 316 int irqtype = apple_gpio_irq_type(type); 317 318 if (irqtype < 0) 319 return irqtype; 320 321 apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE, 322 FIELD_PREP(REG_GPIOx_MODE, irqtype)); 323 324 if (type & IRQ_TYPE_LEVEL_MASK) 325 irq_set_handler_locked(data, handle_level_irq); 326 else 327 irq_set_handler_locked(data, handle_edge_irq); 328 return 0; 329 } 330 331 static void apple_gpio_irq_handler(struct irq_desc *desc) 332 { 333 struct irq_chip *chip = irq_desc_get_chip(desc); 334 u8 *grpp = irq_desc_get_handler_data(desc); 335 struct apple_gpio_pinctrl *pctl; 336 unsigned int pinh, pinl; 337 unsigned long pending; 338 struct gpio_chip *gc; 339 340 pctl = container_of(grpp - *grpp, typeof(*pctl), irqgrps[0]); 341 gc = &pctl->gpio_chip; 342 343 chained_irq_enter(chip, desc); 344 for (pinh = 0; pinh < gc->ngpio; pinh += 32) { 345 pending = readl_relaxed(pctl->base + REG_IRQ(*grpp, pinh)); 346 for_each_set_bit(pinl, &pending, 32) 347 generic_handle_domain_irq(gc->irq.domain, pinh + pinl); 348 } 349 chained_irq_exit(chip, desc); 350 } 351 352 static struct irq_chip apple_gpio_irqchip = { 353 .name = "Apple-GPIO", 354 .irq_startup = apple_gpio_irq_startup, 355 .irq_ack = apple_gpio_irq_ack, 356 .irq_mask = apple_gpio_irq_mask, 357 .irq_unmask = apple_gpio_irq_unmask, 358 .irq_set_type = apple_gpio_irq_set_type, 359 }; 360 361 /* Probe & register */ 362 363 static int apple_gpio_register(struct apple_gpio_pinctrl *pctl) 364 { 365 struct gpio_irq_chip *girq = &pctl->gpio_chip.irq; 366 void **irq_data = NULL; 367 int ret; 368 369 if (!of_property_read_bool(pctl->dev->of_node, "gpio-controller")) 370 return dev_err_probe(pctl->dev, -ENODEV, 371 "No gpio-controller property\n"); 372 373 pctl->irq_chip = apple_gpio_irqchip; 374 375 pctl->gpio_chip.label = dev_name(pctl->dev); 376 pctl->gpio_chip.request = gpiochip_generic_request; 377 pctl->gpio_chip.free = gpiochip_generic_free; 378 pctl->gpio_chip.get_direction = apple_gpio_get_direction; 379 pctl->gpio_chip.direction_input = apple_gpio_direction_input; 380 pctl->gpio_chip.direction_output = apple_gpio_direction_output; 381 pctl->gpio_chip.get = apple_gpio_get; 382 pctl->gpio_chip.set = apple_gpio_set; 383 pctl->gpio_chip.base = -1; 384 pctl->gpio_chip.ngpio = pctl->pinctrl_desc.npins; 385 pctl->gpio_chip.parent = pctl->dev; 386 pctl->gpio_chip.of_node = pctl->dev->of_node; 387 388 if (girq->num_parents) { 389 int i; 390 391 girq->chip = &pctl->irq_chip; 392 girq->parent_handler = apple_gpio_irq_handler; 393 394 girq->parents = kmalloc_array(girq->num_parents, 395 sizeof(*girq->parents), 396 GFP_KERNEL); 397 irq_data = kmalloc_array(girq->num_parents, sizeof(*irq_data), 398 GFP_KERNEL); 399 if (!girq->parents || !irq_data) { 400 ret = -ENOMEM; 401 goto out; 402 } 403 404 for (i = 0; i < girq->num_parents; i++) { 405 ret = platform_get_irq(to_platform_device(pctl->dev), 406 i); 407 if (ret < 0) 408 goto out; 409 410 girq->parents[i] = ret; 411 pctl->irqgrps[i] = i; 412 irq_data[i] = &pctl->irqgrps[i]; 413 } 414 415 girq->parent_handler_data_array = irq_data; 416 girq->per_parent_data = true; 417 girq->default_type = IRQ_TYPE_NONE; 418 girq->handler = handle_level_irq; 419 } 420 421 ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl); 422 out: 423 kfree(girq->parents); 424 kfree(irq_data); 425 426 return ret; 427 } 428 429 static int apple_gpio_pinctrl_probe(struct platform_device *pdev) 430 { 431 struct apple_gpio_pinctrl *pctl; 432 struct pinctrl_pin_desc *pins; 433 unsigned int npins; 434 const char **pin_names; 435 unsigned int *pin_nums; 436 static const char* pinmux_functions[] = { 437 "gpio", "periph1", "periph2", "periph3" 438 }; 439 unsigned int i, nirqs = 0; 440 int res; 441 442 if (of_property_read_bool(pdev->dev.of_node, "interrupt-controller")) { 443 res = platform_irq_count(pdev); 444 if (res > 0) 445 nirqs = res; 446 } 447 448 pctl = devm_kzalloc(&pdev->dev, struct_size(pctl, irqgrps, nirqs), 449 GFP_KERNEL); 450 if (!pctl) 451 return -ENOMEM; 452 pctl->dev = &pdev->dev; 453 pctl->gpio_chip.irq.num_parents = nirqs; 454 dev_set_drvdata(&pdev->dev, pctl); 455 456 if (of_property_read_u32(pdev->dev.of_node, "apple,npins", &npins)) 457 return dev_err_probe(&pdev->dev, -EINVAL, 458 "apple,npins property not found\n"); 459 460 pins = devm_kmalloc_array(&pdev->dev, npins, sizeof(pins[0]), 461 GFP_KERNEL); 462 pin_names = devm_kmalloc_array(&pdev->dev, npins, sizeof(pin_names[0]), 463 GFP_KERNEL); 464 pin_nums = devm_kmalloc_array(&pdev->dev, npins, sizeof(pin_nums[0]), 465 GFP_KERNEL); 466 if (!pins || !pin_names || !pin_nums) 467 return -ENOMEM; 468 469 pctl->base = devm_platform_ioremap_resource(pdev, 0); 470 if (IS_ERR(pctl->base)) 471 return PTR_ERR(pctl->base); 472 473 pctl->map = devm_regmap_init_mmio(&pdev->dev, pctl->base, ®map_config); 474 if (IS_ERR(pctl->map)) 475 return dev_err_probe(&pdev->dev, PTR_ERR(pctl->map), 476 "Failed to create regmap\n"); 477 478 for (i = 0; i < npins; i++) { 479 pins[i].number = i; 480 pins[i].name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "PIN%u", i); 481 pins[i].drv_data = pctl; 482 pin_names[i] = pins[i].name; 483 pin_nums[i] = i; 484 } 485 486 pctl->pinctrl_desc.name = dev_name(pctl->dev); 487 pctl->pinctrl_desc.pins = pins; 488 pctl->pinctrl_desc.npins = npins; 489 pctl->pinctrl_desc.pctlops = &apple_gpio_pinctrl_ops; 490 pctl->pinctrl_desc.pmxops = &apple_gpio_pinmux_ops; 491 492 pctl->pctldev = devm_pinctrl_register(&pdev->dev, &pctl->pinctrl_desc, pctl); 493 if (IS_ERR(pctl->pctldev)) 494 return dev_err_probe(&pdev->dev, PTR_ERR(pctl->pctldev), 495 "Failed to register pinctrl device.\n"); 496 497 for (i = 0; i < npins; i++) { 498 res = pinctrl_generic_add_group(pctl->pctldev, pins[i].name, 499 pin_nums + i, 1, pctl); 500 if (res < 0) 501 return dev_err_probe(pctl->dev, res, 502 "Failed to register group"); 503 } 504 505 for (i = 0; i < ARRAY_SIZE(pinmux_functions); ++i) { 506 res = pinmux_generic_add_function(pctl->pctldev, pinmux_functions[i], 507 pin_names, npins, pctl); 508 if (res < 0) 509 return dev_err_probe(pctl->dev, res, 510 "Failed to register function."); 511 } 512 513 return apple_gpio_register(pctl); 514 } 515 516 static const struct of_device_id apple_gpio_pinctrl_of_match[] = { 517 { .compatible = "apple,pinctrl", }, 518 { } 519 }; 520 521 static struct platform_driver apple_gpio_pinctrl_driver = { 522 .driver = { 523 .name = "apple-gpio-pinctrl", 524 .of_match_table = apple_gpio_pinctrl_of_match, 525 .suppress_bind_attrs = true, 526 }, 527 .probe = apple_gpio_pinctrl_probe, 528 }; 529 module_platform_driver(apple_gpio_pinctrl_driver); 530 531 MODULE_DESCRIPTION("Apple pinctrl/GPIO driver"); 532 MODULE_AUTHOR("Stan Skowronek <stan@corellium.com>"); 533 MODULE_AUTHOR("Joey Gouly <joey.gouly@arm.com>"); 534 MODULE_LICENSE("GPL v2"); 535