1 /* 2 * GPIO driver for AMD 3 * 4 * Copyright (c) 2014,2015 Ken Xue <Ken.Xue@amd.com> 5 * Jeff Wu <Jeff.Wu@amd.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2, as published by the Free Software Foundation. 10 * 11 */ 12 13 #ifndef _PINCTRL_AMD_H 14 #define _PINCTRL_AMD_H 15 16 #define AMD_GPIO_PINS_PER_BANK 64 17 18 #define AMD_GPIO_PINS_BANK0 63 19 #define AMD_GPIO_PINS_BANK1 64 20 #define AMD_GPIO_PINS_BANK2 56 21 #define AMD_GPIO_PINS_BANK3 32 22 23 #define WAKE_INT_MASTER_REG 0xfc 24 #define EOI_MASK (1 << 29) 25 26 #define WAKE_INT_STATUS_REG0 0x2f8 27 #define WAKE_INT_STATUS_REG1 0x2fc 28 29 #define DB_TMR_OUT_OFF 0 30 #define DB_TMR_OUT_UNIT_OFF 4 31 #define DB_CNTRL_OFF 5 32 #define DB_TMR_LARGE_OFF 7 33 #define LEVEL_TRIG_OFF 8 34 #define ACTIVE_LEVEL_OFF 9 35 #define INTERRUPT_ENABLE_OFF 11 36 #define INTERRUPT_MASK_OFF 12 37 #define WAKE_CNTRL_OFF_S0I3 13 38 #define WAKE_CNTRL_OFF_S3 14 39 #define WAKE_CNTRL_OFF_S4 15 40 #define PIN_STS_OFF 16 41 #define DRV_STRENGTH_SEL_OFF 17 42 #define PULL_UP_SEL_OFF 19 43 #define PULL_UP_ENABLE_OFF 20 44 #define PULL_DOWN_ENABLE_OFF 21 45 #define OUTPUT_VALUE_OFF 22 46 #define OUTPUT_ENABLE_OFF 23 47 #define SW_CNTRL_IN_OFF 24 48 #define SW_CNTRL_EN_OFF 25 49 #define INTERRUPT_STS_OFF 28 50 #define WAKE_STS_OFF 29 51 52 #define DB_TMR_OUT_MASK 0xFUL 53 #define DB_CNTRl_MASK 0x3UL 54 #define ACTIVE_LEVEL_MASK 0x3UL 55 #define DRV_STRENGTH_SEL_MASK 0x3UL 56 57 #define ACTIVE_LEVEL_HIGH 0x0UL 58 #define ACTIVE_LEVEL_LOW 0x1UL 59 #define ACTIVE_LEVEL_BOTH 0x2UL 60 61 #define DB_TYPE_NO_DEBOUNCE 0x0UL 62 #define DB_TYPE_PRESERVE_LOW_GLITCH 0x1UL 63 #define DB_TYPE_PRESERVE_HIGH_GLITCH 0x2UL 64 #define DB_TYPE_REMOVE_GLITCH 0x3UL 65 66 #define EDGE_TRAGGER 0x0UL 67 #define LEVEL_TRIGGER 0x1UL 68 69 #define ACTIVE_HIGH 0x0UL 70 #define ACTIVE_LOW 0x1UL 71 #define BOTH_EADGE 0x2UL 72 73 #define ENABLE_INTERRUPT 0x1UL 74 #define DISABLE_INTERRUPT 0x0UL 75 76 #define ENABLE_INTERRUPT_MASK 0x0UL 77 #define DISABLE_INTERRUPT_MASK 0x1UL 78 79 #define CLR_INTR_STAT 0x1UL 80 81 struct amd_pingroup { 82 const char *name; 83 const unsigned *pins; 84 unsigned npins; 85 }; 86 87 struct amd_function { 88 const char *name; 89 const char * const *groups; 90 unsigned ngroups; 91 }; 92 93 struct amd_gpio { 94 raw_spinlock_t lock; 95 void __iomem *base; 96 97 const struct amd_pingroup *groups; 98 u32 ngroups; 99 struct pinctrl_dev *pctrl; 100 struct gpio_chip gc; 101 unsigned int hwbank_num; 102 struct resource *res; 103 struct platform_device *pdev; 104 u32 *saved_regs; 105 }; 106 107 /* KERNCZ configuration*/ 108 static const struct pinctrl_pin_desc kerncz_pins[] = { 109 PINCTRL_PIN(0, "GPIO_0"), 110 PINCTRL_PIN(1, "GPIO_1"), 111 PINCTRL_PIN(2, "GPIO_2"), 112 PINCTRL_PIN(3, "GPIO_3"), 113 PINCTRL_PIN(4, "GPIO_4"), 114 PINCTRL_PIN(5, "GPIO_5"), 115 PINCTRL_PIN(6, "GPIO_6"), 116 PINCTRL_PIN(7, "GPIO_7"), 117 PINCTRL_PIN(8, "GPIO_8"), 118 PINCTRL_PIN(9, "GPIO_9"), 119 PINCTRL_PIN(10, "GPIO_10"), 120 PINCTRL_PIN(11, "GPIO_11"), 121 PINCTRL_PIN(12, "GPIO_12"), 122 PINCTRL_PIN(13, "GPIO_13"), 123 PINCTRL_PIN(14, "GPIO_14"), 124 PINCTRL_PIN(15, "GPIO_15"), 125 PINCTRL_PIN(16, "GPIO_16"), 126 PINCTRL_PIN(17, "GPIO_17"), 127 PINCTRL_PIN(18, "GPIO_18"), 128 PINCTRL_PIN(19, "GPIO_19"), 129 PINCTRL_PIN(20, "GPIO_20"), 130 PINCTRL_PIN(23, "GPIO_23"), 131 PINCTRL_PIN(24, "GPIO_24"), 132 PINCTRL_PIN(25, "GPIO_25"), 133 PINCTRL_PIN(26, "GPIO_26"), 134 PINCTRL_PIN(39, "GPIO_39"), 135 PINCTRL_PIN(40, "GPIO_40"), 136 PINCTRL_PIN(43, "GPIO_42"), 137 PINCTRL_PIN(46, "GPIO_46"), 138 PINCTRL_PIN(47, "GPIO_47"), 139 PINCTRL_PIN(48, "GPIO_48"), 140 PINCTRL_PIN(49, "GPIO_49"), 141 PINCTRL_PIN(50, "GPIO_50"), 142 PINCTRL_PIN(51, "GPIO_51"), 143 PINCTRL_PIN(52, "GPIO_52"), 144 PINCTRL_PIN(53, "GPIO_53"), 145 PINCTRL_PIN(54, "GPIO_54"), 146 PINCTRL_PIN(55, "GPIO_55"), 147 PINCTRL_PIN(56, "GPIO_56"), 148 PINCTRL_PIN(57, "GPIO_57"), 149 PINCTRL_PIN(58, "GPIO_58"), 150 PINCTRL_PIN(59, "GPIO_59"), 151 PINCTRL_PIN(60, "GPIO_60"), 152 PINCTRL_PIN(61, "GPIO_61"), 153 PINCTRL_PIN(62, "GPIO_62"), 154 PINCTRL_PIN(64, "GPIO_64"), 155 PINCTRL_PIN(65, "GPIO_65"), 156 PINCTRL_PIN(66, "GPIO_66"), 157 PINCTRL_PIN(68, "GPIO_68"), 158 PINCTRL_PIN(69, "GPIO_69"), 159 PINCTRL_PIN(70, "GPIO_70"), 160 PINCTRL_PIN(71, "GPIO_71"), 161 PINCTRL_PIN(72, "GPIO_72"), 162 PINCTRL_PIN(74, "GPIO_74"), 163 PINCTRL_PIN(75, "GPIO_75"), 164 PINCTRL_PIN(76, "GPIO_76"), 165 PINCTRL_PIN(84, "GPIO_84"), 166 PINCTRL_PIN(85, "GPIO_85"), 167 PINCTRL_PIN(86, "GPIO_86"), 168 PINCTRL_PIN(87, "GPIO_87"), 169 PINCTRL_PIN(88, "GPIO_88"), 170 PINCTRL_PIN(89, "GPIO_89"), 171 PINCTRL_PIN(90, "GPIO_90"), 172 PINCTRL_PIN(91, "GPIO_91"), 173 PINCTRL_PIN(92, "GPIO_92"), 174 PINCTRL_PIN(93, "GPIO_93"), 175 PINCTRL_PIN(95, "GPIO_95"), 176 PINCTRL_PIN(96, "GPIO_96"), 177 PINCTRL_PIN(97, "GPIO_97"), 178 PINCTRL_PIN(98, "GPIO_98"), 179 PINCTRL_PIN(99, "GPIO_99"), 180 PINCTRL_PIN(100, "GPIO_100"), 181 PINCTRL_PIN(101, "GPIO_101"), 182 PINCTRL_PIN(102, "GPIO_102"), 183 PINCTRL_PIN(113, "GPIO_113"), 184 PINCTRL_PIN(114, "GPIO_114"), 185 PINCTRL_PIN(115, "GPIO_115"), 186 PINCTRL_PIN(116, "GPIO_116"), 187 PINCTRL_PIN(117, "GPIO_117"), 188 PINCTRL_PIN(118, "GPIO_118"), 189 PINCTRL_PIN(119, "GPIO_119"), 190 PINCTRL_PIN(120, "GPIO_120"), 191 PINCTRL_PIN(121, "GPIO_121"), 192 PINCTRL_PIN(122, "GPIO_122"), 193 PINCTRL_PIN(126, "GPIO_126"), 194 PINCTRL_PIN(129, "GPIO_129"), 195 PINCTRL_PIN(130, "GPIO_130"), 196 PINCTRL_PIN(131, "GPIO_131"), 197 PINCTRL_PIN(132, "GPIO_132"), 198 PINCTRL_PIN(133, "GPIO_133"), 199 PINCTRL_PIN(135, "GPIO_135"), 200 PINCTRL_PIN(136, "GPIO_136"), 201 PINCTRL_PIN(137, "GPIO_137"), 202 PINCTRL_PIN(138, "GPIO_138"), 203 PINCTRL_PIN(139, "GPIO_139"), 204 PINCTRL_PIN(140, "GPIO_140"), 205 PINCTRL_PIN(141, "GPIO_141"), 206 PINCTRL_PIN(142, "GPIO_142"), 207 PINCTRL_PIN(143, "GPIO_143"), 208 PINCTRL_PIN(144, "GPIO_144"), 209 PINCTRL_PIN(145, "GPIO_145"), 210 PINCTRL_PIN(146, "GPIO_146"), 211 PINCTRL_PIN(147, "GPIO_147"), 212 PINCTRL_PIN(148, "GPIO_148"), 213 PINCTRL_PIN(166, "GPIO_166"), 214 PINCTRL_PIN(167, "GPIO_167"), 215 PINCTRL_PIN(168, "GPIO_168"), 216 PINCTRL_PIN(169, "GPIO_169"), 217 PINCTRL_PIN(170, "GPIO_170"), 218 PINCTRL_PIN(171, "GPIO_171"), 219 PINCTRL_PIN(172, "GPIO_172"), 220 PINCTRL_PIN(173, "GPIO_173"), 221 PINCTRL_PIN(174, "GPIO_174"), 222 PINCTRL_PIN(175, "GPIO_175"), 223 PINCTRL_PIN(176, "GPIO_176"), 224 PINCTRL_PIN(177, "GPIO_177"), 225 }; 226 227 static const unsigned i2c0_pins[] = {145, 146}; 228 static const unsigned i2c1_pins[] = {147, 148}; 229 static const unsigned i2c2_pins[] = {113, 114}; 230 static const unsigned i2c3_pins[] = {19, 20}; 231 232 static const unsigned uart0_pins[] = {135, 136, 137, 138, 139}; 233 static const unsigned uart1_pins[] = {140, 141, 142, 143, 144}; 234 235 static const struct amd_pingroup kerncz_groups[] = { 236 { 237 .name = "i2c0", 238 .pins = i2c0_pins, 239 .npins = 2, 240 }, 241 { 242 .name = "i2c1", 243 .pins = i2c1_pins, 244 .npins = 2, 245 }, 246 { 247 .name = "i2c2", 248 .pins = i2c2_pins, 249 .npins = 2, 250 }, 251 { 252 .name = "i2c3", 253 .pins = i2c3_pins, 254 .npins = 2, 255 }, 256 { 257 .name = "uart0", 258 .pins = uart0_pins, 259 .npins = 9, 260 }, 261 { 262 .name = "uart1", 263 .pins = uart1_pins, 264 .npins = 5, 265 }, 266 }; 267 268 #endif 269