1*fd84aaa8SChester Lin // SPDX-License-Identifier: GPL-2.0-or-later 2*fd84aaa8SChester Lin /* 3*fd84aaa8SChester Lin * NXP S32G pinctrl driver 4*fd84aaa8SChester Lin * 5*fd84aaa8SChester Lin * Copyright 2015-2016 Freescale Semiconductor, Inc. 6*fd84aaa8SChester Lin * Copyright 2017-2018, 2020-2022 NXP 7*fd84aaa8SChester Lin * Copyright (C) 2022 SUSE LLC 8*fd84aaa8SChester Lin */ 9*fd84aaa8SChester Lin 10*fd84aaa8SChester Lin #include <linux/err.h> 11*fd84aaa8SChester Lin #include <linux/init.h> 12*fd84aaa8SChester Lin #include <linux/io.h> 13*fd84aaa8SChester Lin #include <linux/module.h> 14*fd84aaa8SChester Lin #include <linux/of.h> 15*fd84aaa8SChester Lin #include <linux/of_device.h> 16*fd84aaa8SChester Lin #include <linux/pinctrl/pinctrl.h> 17*fd84aaa8SChester Lin 18*fd84aaa8SChester Lin #include "pinctrl-s32.h" 19*fd84aaa8SChester Lin 20*fd84aaa8SChester Lin enum s32_pins { 21*fd84aaa8SChester Lin S32G_MSCR_PA_00 = 0, 22*fd84aaa8SChester Lin S32G_MSCR_PA_01 = 1, 23*fd84aaa8SChester Lin S32G_MSCR_PA_02 = 2, 24*fd84aaa8SChester Lin S32G_MSCR_PA_03 = 3, 25*fd84aaa8SChester Lin S32G_MSCR_PA_04 = 4, 26*fd84aaa8SChester Lin S32G_MSCR_PA_05 = 5, 27*fd84aaa8SChester Lin S32G_MSCR_PA_06 = 6, 28*fd84aaa8SChester Lin S32G_MSCR_PA_07 = 7, 29*fd84aaa8SChester Lin S32G_MSCR_PA_08 = 8, 30*fd84aaa8SChester Lin S32G_MSCR_PA_09 = 9, 31*fd84aaa8SChester Lin S32G_MSCR_PA_10 = 10, 32*fd84aaa8SChester Lin S32G_MSCR_PA_11 = 11, 33*fd84aaa8SChester Lin S32G_MSCR_PA_12 = 12, 34*fd84aaa8SChester Lin S32G_MSCR_PA_13 = 13, 35*fd84aaa8SChester Lin S32G_MSCR_PA_14 = 14, 36*fd84aaa8SChester Lin S32G_MSCR_PA_15 = 15, 37*fd84aaa8SChester Lin S32G_MSCR_PB_00 = 16, 38*fd84aaa8SChester Lin S32G_MSCR_PB_01 = 17, 39*fd84aaa8SChester Lin S32G_MSCR_PB_02 = 18, 40*fd84aaa8SChester Lin S32G_MSCR_PB_03 = 19, 41*fd84aaa8SChester Lin S32G_MSCR_PB_04 = 20, 42*fd84aaa8SChester Lin S32G_MSCR_PB_05 = 21, 43*fd84aaa8SChester Lin S32G_MSCR_PB_06 = 22, 44*fd84aaa8SChester Lin S32G_MSCR_PB_07 = 23, 45*fd84aaa8SChester Lin S32G_MSCR_PB_08 = 24, 46*fd84aaa8SChester Lin S32G_MSCR_PB_09 = 25, 47*fd84aaa8SChester Lin S32G_MSCR_PB_10 = 26, 48*fd84aaa8SChester Lin S32G_MSCR_PB_11 = 27, 49*fd84aaa8SChester Lin S32G_MSCR_PB_12 = 28, 50*fd84aaa8SChester Lin S32G_MSCR_PB_13 = 29, 51*fd84aaa8SChester Lin S32G_MSCR_PB_14 = 30, 52*fd84aaa8SChester Lin S32G_MSCR_PB_15 = 31, 53*fd84aaa8SChester Lin S32G_MSCR_PC_00 = 32, 54*fd84aaa8SChester Lin S32G_MSCR_PC_01 = 33, 55*fd84aaa8SChester Lin S32G_MSCR_PC_02 = 34, 56*fd84aaa8SChester Lin S32G_MSCR_PC_03 = 35, 57*fd84aaa8SChester Lin S32G_MSCR_PC_04 = 36, 58*fd84aaa8SChester Lin S32G_MSCR_PC_05 = 37, 59*fd84aaa8SChester Lin S32G_MSCR_PC_06 = 38, 60*fd84aaa8SChester Lin S32G_MSCR_PC_07 = 39, 61*fd84aaa8SChester Lin S32G_MSCR_PC_08 = 40, 62*fd84aaa8SChester Lin S32G_MSCR_PC_09 = 41, 63*fd84aaa8SChester Lin S32G_MSCR_PC_10 = 42, 64*fd84aaa8SChester Lin S32G_MSCR_PC_11 = 43, 65*fd84aaa8SChester Lin S32G_MSCR_PC_12 = 44, 66*fd84aaa8SChester Lin S32G_MSCR_PC_13 = 45, 67*fd84aaa8SChester Lin S32G_MSCR_PC_14 = 46, 68*fd84aaa8SChester Lin S32G_MSCR_PC_15 = 47, 69*fd84aaa8SChester Lin S32G_MSCR_PD_00 = 48, 70*fd84aaa8SChester Lin S32G_MSCR_PD_01 = 49, 71*fd84aaa8SChester Lin S32G_MSCR_PD_02 = 50, 72*fd84aaa8SChester Lin S32G_MSCR_PD_03 = 51, 73*fd84aaa8SChester Lin S32G_MSCR_PD_04 = 52, 74*fd84aaa8SChester Lin S32G_MSCR_PD_05 = 53, 75*fd84aaa8SChester Lin S32G_MSCR_PD_06 = 54, 76*fd84aaa8SChester Lin S32G_MSCR_PD_07 = 55, 77*fd84aaa8SChester Lin S32G_MSCR_PD_08 = 56, 78*fd84aaa8SChester Lin S32G_MSCR_PD_09 = 57, 79*fd84aaa8SChester Lin S32G_MSCR_PD_10 = 58, 80*fd84aaa8SChester Lin S32G_MSCR_PD_11 = 59, 81*fd84aaa8SChester Lin S32G_MSCR_PD_12 = 60, 82*fd84aaa8SChester Lin S32G_MSCR_PD_13 = 61, 83*fd84aaa8SChester Lin S32G_MSCR_PD_14 = 62, 84*fd84aaa8SChester Lin S32G_MSCR_PD_15 = 63, 85*fd84aaa8SChester Lin S32G_MSCR_PE_00 = 64, 86*fd84aaa8SChester Lin S32G_MSCR_PE_01 = 65, 87*fd84aaa8SChester Lin S32G_MSCR_PE_02 = 66, 88*fd84aaa8SChester Lin S32G_MSCR_PE_03 = 67, 89*fd84aaa8SChester Lin S32G_MSCR_PE_04 = 68, 90*fd84aaa8SChester Lin S32G_MSCR_PE_05 = 69, 91*fd84aaa8SChester Lin S32G_MSCR_PE_06 = 70, 92*fd84aaa8SChester Lin S32G_MSCR_PE_07 = 71, 93*fd84aaa8SChester Lin S32G_MSCR_PE_08 = 72, 94*fd84aaa8SChester Lin S32G_MSCR_PE_09 = 73, 95*fd84aaa8SChester Lin S32G_MSCR_PE_10 = 74, 96*fd84aaa8SChester Lin S32G_MSCR_PE_11 = 75, 97*fd84aaa8SChester Lin S32G_MSCR_PE_12 = 76, 98*fd84aaa8SChester Lin S32G_MSCR_PE_13 = 77, 99*fd84aaa8SChester Lin S32G_MSCR_PE_14 = 78, 100*fd84aaa8SChester Lin S32G_MSCR_PE_15 = 79, 101*fd84aaa8SChester Lin S32G_MSCR_PF_00 = 80, 102*fd84aaa8SChester Lin S32G_MSCR_PF_01 = 81, 103*fd84aaa8SChester Lin S32G_MSCR_PF_02 = 82, 104*fd84aaa8SChester Lin S32G_MSCR_PF_03 = 83, 105*fd84aaa8SChester Lin S32G_MSCR_PF_04 = 84, 106*fd84aaa8SChester Lin S32G_MSCR_PF_05 = 85, 107*fd84aaa8SChester Lin S32G_MSCR_PF_06 = 86, 108*fd84aaa8SChester Lin S32G_MSCR_PF_07 = 87, 109*fd84aaa8SChester Lin S32G_MSCR_PF_08 = 88, 110*fd84aaa8SChester Lin S32G_MSCR_PF_09 = 89, 111*fd84aaa8SChester Lin S32G_MSCR_PF_10 = 90, 112*fd84aaa8SChester Lin S32G_MSCR_PF_11 = 91, 113*fd84aaa8SChester Lin S32G_MSCR_PF_12 = 92, 114*fd84aaa8SChester Lin S32G_MSCR_PF_13 = 93, 115*fd84aaa8SChester Lin S32G_MSCR_PF_14 = 94, 116*fd84aaa8SChester Lin S32G_MSCR_PF_15 = 95, 117*fd84aaa8SChester Lin S32G_MSCR_PG_00 = 96, 118*fd84aaa8SChester Lin S32G_MSCR_PG_01 = 97, 119*fd84aaa8SChester Lin S32G_MSCR_PG_02 = 98, 120*fd84aaa8SChester Lin S32G_MSCR_PG_03 = 99, 121*fd84aaa8SChester Lin S32G_MSCR_PG_04 = 100, 122*fd84aaa8SChester Lin S32G_MSCR_PG_05 = 101, 123*fd84aaa8SChester Lin S32G_MSCR_PH_00 = 112, 124*fd84aaa8SChester Lin S32G_MSCR_PH_01 = 113, 125*fd84aaa8SChester Lin S32G_MSCR_PH_02 = 114, 126*fd84aaa8SChester Lin S32G_MSCR_PH_03 = 115, 127*fd84aaa8SChester Lin S32G_MSCR_PH_04 = 116, 128*fd84aaa8SChester Lin S32G_MSCR_PH_05 = 117, 129*fd84aaa8SChester Lin S32G_MSCR_PH_06 = 118, 130*fd84aaa8SChester Lin S32G_MSCR_PH_07 = 119, 131*fd84aaa8SChester Lin S32G_MSCR_PH_08 = 120, 132*fd84aaa8SChester Lin S32G_MSCR_PH_09 = 121, 133*fd84aaa8SChester Lin S32G_MSCR_PH_10 = 122, 134*fd84aaa8SChester Lin S32G_MSCR_PJ_00 = 144, 135*fd84aaa8SChester Lin S32G_MSCR_PJ_01 = 145, 136*fd84aaa8SChester Lin S32G_MSCR_PJ_02 = 146, 137*fd84aaa8SChester Lin S32G_MSCR_PJ_03 = 147, 138*fd84aaa8SChester Lin S32G_MSCR_PJ_04 = 148, 139*fd84aaa8SChester Lin S32G_MSCR_PJ_05 = 149, 140*fd84aaa8SChester Lin S32G_MSCR_PJ_06 = 150, 141*fd84aaa8SChester Lin S32G_MSCR_PJ_07 = 151, 142*fd84aaa8SChester Lin S32G_MSCR_PJ_08 = 152, 143*fd84aaa8SChester Lin S32G_MSCR_PJ_09 = 153, 144*fd84aaa8SChester Lin S32G_MSCR_PJ_10 = 154, 145*fd84aaa8SChester Lin S32G_MSCR_PJ_11 = 155, 146*fd84aaa8SChester Lin S32G_MSCR_PJ_12 = 156, 147*fd84aaa8SChester Lin S32G_MSCR_PJ_13 = 157, 148*fd84aaa8SChester Lin S32G_MSCR_PJ_14 = 158, 149*fd84aaa8SChester Lin S32G_MSCR_PJ_15 = 159, 150*fd84aaa8SChester Lin S32G_MSCR_PK_00 = 160, 151*fd84aaa8SChester Lin S32G_MSCR_PK_01 = 161, 152*fd84aaa8SChester Lin S32G_MSCR_PK_02 = 162, 153*fd84aaa8SChester Lin S32G_MSCR_PK_03 = 163, 154*fd84aaa8SChester Lin S32G_MSCR_PK_04 = 164, 155*fd84aaa8SChester Lin S32G_MSCR_PK_05 = 165, 156*fd84aaa8SChester Lin S32G_MSCR_PK_06 = 166, 157*fd84aaa8SChester Lin S32G_MSCR_PK_07 = 167, 158*fd84aaa8SChester Lin S32G_MSCR_PK_08 = 168, 159*fd84aaa8SChester Lin S32G_MSCR_PK_09 = 169, 160*fd84aaa8SChester Lin S32G_MSCR_PK_10 = 170, 161*fd84aaa8SChester Lin S32G_MSCR_PK_11 = 171, 162*fd84aaa8SChester Lin S32G_MSCR_PK_12 = 172, 163*fd84aaa8SChester Lin S32G_MSCR_PK_13 = 173, 164*fd84aaa8SChester Lin S32G_MSCR_PK_14 = 174, 165*fd84aaa8SChester Lin S32G_MSCR_PK_15 = 175, 166*fd84aaa8SChester Lin S32G_MSCR_PL_00 = 176, 167*fd84aaa8SChester Lin S32G_MSCR_PL_01 = 177, 168*fd84aaa8SChester Lin S32G_MSCR_PL_02 = 178, 169*fd84aaa8SChester Lin S32G_MSCR_PL_03 = 179, 170*fd84aaa8SChester Lin S32G_MSCR_PL_04 = 180, 171*fd84aaa8SChester Lin S32G_MSCR_PL_05 = 181, 172*fd84aaa8SChester Lin S32G_MSCR_PL_06 = 182, 173*fd84aaa8SChester Lin S32G_MSCR_PL_07 = 183, 174*fd84aaa8SChester Lin S32G_MSCR_PL_08 = 184, 175*fd84aaa8SChester Lin S32G_MSCR_PL_09 = 185, 176*fd84aaa8SChester Lin S32G_MSCR_PL_10 = 186, 177*fd84aaa8SChester Lin S32G_MSCR_PL_11 = 187, 178*fd84aaa8SChester Lin S32G_MSCR_PL_12 = 188, 179*fd84aaa8SChester Lin S32G_MSCR_PL_13 = 189, 180*fd84aaa8SChester Lin S32G_MSCR_PL_14 = 190, 181*fd84aaa8SChester Lin 182*fd84aaa8SChester Lin S32G_IMCR_QSPI_A_DATA0 = 540, 183*fd84aaa8SChester Lin S32G_IMCR_QSPI_A_DATA1 = 541, 184*fd84aaa8SChester Lin S32G_IMCR_QSPI_A_DATA2 = 542, 185*fd84aaa8SChester Lin S32G_IMCR_QSPI_A_DATA3 = 543, 186*fd84aaa8SChester Lin S32G_IMCR_QSPI_A_DATA4 = 544, 187*fd84aaa8SChester Lin S32G_IMCR_QSPI_A_DATA5 = 545, 188*fd84aaa8SChester Lin S32G_IMCR_QSPI_A_DATA6 = 546, 189*fd84aaa8SChester Lin S32G_IMCR_QSPI_A_DATA7 = 547, 190*fd84aaa8SChester Lin S32G_IMCR_QSPI_DQS_A = 548, 191*fd84aaa8SChester Lin S32G_IMCR_QSPI_B_DATA0 = 552, 192*fd84aaa8SChester Lin S32G_IMCR_QSPI_B_DATA1 = 554, 193*fd84aaa8SChester Lin S32G_IMCR_QSPI_B_DATA2 = 551, 194*fd84aaa8SChester Lin S32G_IMCR_QSPI_B_DATA3 = 553, 195*fd84aaa8SChester Lin S32G_IMCR_QSPI_B_DATA4 = 557, 196*fd84aaa8SChester Lin S32G_IMCR_QSPI_B_DATA5 = 550, 197*fd84aaa8SChester Lin S32G_IMCR_QSPI_B_DATA6 = 556, 198*fd84aaa8SChester Lin S32G_IMCR_QSPI_B_DATA7 = 555, 199*fd84aaa8SChester Lin S32G_IMCR_QSPI_DQS_B = 558, 200*fd84aaa8SChester Lin S32G_IMCR_BOOT_BOOTMOD0 = 560, 201*fd84aaa8SChester Lin S32G_IMCR_BOOT_BOOTMOD1 = 561, 202*fd84aaa8SChester Lin S32G_IMCR_I2C0_SCL = 566, 203*fd84aaa8SChester Lin S32G_IMCR_I2C0_SDA = 565, 204*fd84aaa8SChester Lin S32G_IMCR_LIN0_RX = 512, 205*fd84aaa8SChester Lin S32G_IMCR_USDHC_CMD = 515, 206*fd84aaa8SChester Lin S32G_IMCR_USDHC_DAT0 = 516, 207*fd84aaa8SChester Lin S32G_IMCR_USDHC_DAT1 = 517, 208*fd84aaa8SChester Lin S32G_IMCR_USDHC_DAT2 = 520, 209*fd84aaa8SChester Lin S32G_IMCR_USDHC_DAT3 = 521, 210*fd84aaa8SChester Lin S32G_IMCR_USDHC_DAT4 = 522, 211*fd84aaa8SChester Lin S32G_IMCR_USDHC_DAT5 = 523, 212*fd84aaa8SChester Lin S32G_IMCR_USDHC_DAT6 = 519, 213*fd84aaa8SChester Lin S32G_IMCR_USDHC_DAT7 = 518, 214*fd84aaa8SChester Lin S32G_IMCR_USDHC_DQS = 524, 215*fd84aaa8SChester Lin S32G_IMCR_CAN0_RXD = 513, 216*fd84aaa8SChester Lin S32G_IMCR_CAN1_RXD = 631, 217*fd84aaa8SChester Lin S32G_IMCR_CAN2_RXD = 632, 218*fd84aaa8SChester Lin S32G_IMCR_CAN3_RXD = 633, 219*fd84aaa8SChester Lin /* GMAC0 */ 220*fd84aaa8SChester Lin S32G_IMCR_Ethernet_MDIO = 527, 221*fd84aaa8SChester Lin S32G_IMCR_Ethernet_CRS = 526, 222*fd84aaa8SChester Lin S32G_IMCR_Ethernet_COL = 525, 223*fd84aaa8SChester Lin S32G_IMCR_Ethernet_RX_D0 = 531, 224*fd84aaa8SChester Lin S32G_IMCR_Ethernet_RX_D1 = 532, 225*fd84aaa8SChester Lin S32G_IMCR_Ethernet_RX_D2 = 533, 226*fd84aaa8SChester Lin S32G_IMCR_Ethernet_RX_D3 = 534, 227*fd84aaa8SChester Lin S32G_IMCR_Ethernet_RX_ER = 528, 228*fd84aaa8SChester Lin S32G_IMCR_Ethernet_RX_CLK = 529, 229*fd84aaa8SChester Lin S32G_IMCR_Ethernet_RX_DV = 530, 230*fd84aaa8SChester Lin S32G_IMCR_Ethernet_TX_CLK = 538, 231*fd84aaa8SChester Lin S32G_IMCR_Ethernet_REF_CLK = 535, 232*fd84aaa8SChester Lin /* PFE EMAC 0 MII */ 233*fd84aaa8SChester Lin /* PFE EMAC 1 MII */ 234*fd84aaa8SChester Lin S32G_IMCR_PFE_EMAC_1_MDIO = 857, 235*fd84aaa8SChester Lin S32G_IMCR_PFE_EMAC_1_CRS = 856, 236*fd84aaa8SChester Lin S32G_IMCR_PFE_EMAC_1_COL = 855, 237*fd84aaa8SChester Lin S32G_IMCR_PFE_EMAC_1_RX_D0 = 861, 238*fd84aaa8SChester Lin S32G_IMCR_PFE_EMAC_1_RX_D1 = 862, 239*fd84aaa8SChester Lin S32G_IMCR_PFE_EMAC_1_RX_D2 = 863, 240*fd84aaa8SChester Lin S32G_IMCR_PFE_EMAC_1_RX_D3 = 864, 241*fd84aaa8SChester Lin S32G_IMCR_PFE_EMAC_1_RX_ER = 860, 242*fd84aaa8SChester Lin S32G_IMCR_PFE_EMAC_1_RX_CLK = 859, 243*fd84aaa8SChester Lin S32G_IMCR_PFE_EMAC_1_RX_DV = 865, 244*fd84aaa8SChester Lin S32G_IMCR_PFE_EMAC_1_TX_CLK = 866, 245*fd84aaa8SChester Lin S32G_IMCR_PFE_EMAC_1_REF_CLK = 858, 246*fd84aaa8SChester Lin /* PFE EMAC 2 MII */ 247*fd84aaa8SChester Lin S32G_IMCR_PFE_EMAC_2_MDIO = 877, 248*fd84aaa8SChester Lin S32G_IMCR_PFE_EMAC_2_CRS = 876, 249*fd84aaa8SChester Lin S32G_IMCR_PFE_EMAC_2_COL = 875, 250*fd84aaa8SChester Lin S32G_IMCR_PFE_EMAC_2_RX_D0 = 881, 251*fd84aaa8SChester Lin S32G_IMCR_PFE_EMAC_2_RX_D1 = 882, 252*fd84aaa8SChester Lin S32G_IMCR_PFE_EMAC_2_RX_D2 = 883, 253*fd84aaa8SChester Lin S32G_IMCR_PFE_EMAC_2_RX_D3 = 884, 254*fd84aaa8SChester Lin S32G_IMCR_PFE_EMAC_2_RX_ER = 880, 255*fd84aaa8SChester Lin S32G_IMCR_PFE_EMAC_2_RX_CLK = 879, 256*fd84aaa8SChester Lin S32G_IMCR_PFE_EMAC_2_RX_DV = 885, 257*fd84aaa8SChester Lin S32G_IMCR_PFE_EMAC_2_TX_CLK = 886, 258*fd84aaa8SChester Lin S32G_IMCR_PFE_EMAC_2_REF_CLK = 878, 259*fd84aaa8SChester Lin 260*fd84aaa8SChester Lin S32G_IMCR_FlexRay0_A_RX = 785, 261*fd84aaa8SChester Lin S32G_IMCR_FlexRay0_B_RX = 786, 262*fd84aaa8SChester Lin S32G_IMCR_FlexTimer0_CH0 = 655, 263*fd84aaa8SChester Lin S32G_IMCR_FlexTimer1_CH0 = 665, 264*fd84aaa8SChester Lin S32G_IMCR_FlexTimer0_CH1 = 656, 265*fd84aaa8SChester Lin S32G_IMCR_FlexTimer1_CH1 = 666, 266*fd84aaa8SChester Lin S32G_IMCR_FlexTimer0_CH2 = 657, 267*fd84aaa8SChester Lin S32G_IMCR_FlexTimer1_CH2 = 667, 268*fd84aaa8SChester Lin S32G_IMCR_FlexTimer0_CH3 = 658, 269*fd84aaa8SChester Lin S32G_IMCR_FlexTimer1_CH3 = 668, 270*fd84aaa8SChester Lin S32G_IMCR_FlexTimer0_CH4 = 659, 271*fd84aaa8SChester Lin S32G_IMCR_FlexTimer1_CH4 = 669, 272*fd84aaa8SChester Lin S32G_IMCR_FlexTimer0_CH5 = 660, 273*fd84aaa8SChester Lin S32G_IMCR_FlexTimer1_CH5 = 670, 274*fd84aaa8SChester Lin S32G_IMCR_FlexTimer0_EXTCLK = 661, 275*fd84aaa8SChester Lin S32G_IMCR_FlexTimer1_EXTCLK = 671, 276*fd84aaa8SChester Lin S32G_IMCR_I2C1_SCL = 717, 277*fd84aaa8SChester Lin S32G_IMCR_I2C1_SDA = 718, 278*fd84aaa8SChester Lin S32G_IMCR_I2C2_SCL = 719, 279*fd84aaa8SChester Lin S32G_IMCR_I2C2_SDA = 720, 280*fd84aaa8SChester Lin S32G_IMCR_I2C3_SCL = 721, 281*fd84aaa8SChester Lin S32G_IMCR_I2C3_SDA = 722, 282*fd84aaa8SChester Lin S32G_IMCR_I2C4_SCL = 723, 283*fd84aaa8SChester Lin S32G_IMCR_I2C4_SDA = 724, 284*fd84aaa8SChester Lin S32G_IMCR_LIN1_RX = 736, 285*fd84aaa8SChester Lin S32G_IMCR_LIN2_RX = 737, 286*fd84aaa8SChester Lin S32G_IMCR_DSPI0_PCS0 = 980, 287*fd84aaa8SChester Lin S32G_IMCR_DSPI0_SCK = 981, 288*fd84aaa8SChester Lin S32G_IMCR_DSPI0_SIN = 982, 289*fd84aaa8SChester Lin S32G_IMCR_DSPI1_PCS0 = 985, 290*fd84aaa8SChester Lin S32G_IMCR_DSPI1_SCK = 986, 291*fd84aaa8SChester Lin S32G_IMCR_DSPI1_SIN = 987, 292*fd84aaa8SChester Lin S32G_IMCR_DSPI2_PCS0 = 990, 293*fd84aaa8SChester Lin S32G_IMCR_DSPI2_SCK = 991, 294*fd84aaa8SChester Lin S32G_IMCR_DSPI2_SIN = 992, 295*fd84aaa8SChester Lin S32G_IMCR_DSPI3_PCS0 = 995, 296*fd84aaa8SChester Lin S32G_IMCR_DSPI3_SCK = 996, 297*fd84aaa8SChester Lin S32G_IMCR_DSPI3_SIN = 997, 298*fd84aaa8SChester Lin S32G_IMCR_DSPI4_PCS0 = 1000, 299*fd84aaa8SChester Lin S32G_IMCR_DSPI4_SCK = 1001, 300*fd84aaa8SChester Lin S32G_IMCR_DSPI4_SIN = 1002, 301*fd84aaa8SChester Lin S32G_IMCR_DSPI5_PCS0 = 1005, 302*fd84aaa8SChester Lin S32G_IMCR_DSPI5_SCK = 1006, 303*fd84aaa8SChester Lin S32G_IMCR_DSPI5_SIN = 1007, 304*fd84aaa8SChester Lin S32G_IMCR_LLCE_CAN0_RXD = 745, 305*fd84aaa8SChester Lin S32G_IMCR_LLCE_CAN1_RXD = 746, 306*fd84aaa8SChester Lin S32G_IMCR_LLCE_CAN2_RXD = 747, 307*fd84aaa8SChester Lin S32G_IMCR_LLCE_CAN3_RXD = 748, 308*fd84aaa8SChester Lin S32G_IMCR_LLCE_CAN4_RXD = 749, 309*fd84aaa8SChester Lin S32G_IMCR_LLCE_CAN5_RXD = 750, 310*fd84aaa8SChester Lin S32G_IMCR_LLCE_CAN6_RXD = 751, 311*fd84aaa8SChester Lin S32G_IMCR_LLCE_CAN7_RXD = 752, 312*fd84aaa8SChester Lin S32G_IMCR_LLCE_CAN8_RXD = 753, 313*fd84aaa8SChester Lin S32G_IMCR_LLCE_CAN9_RXD = 754, 314*fd84aaa8SChester Lin S32G_IMCR_LLCE_CAN10_RXD = 755, 315*fd84aaa8SChester Lin S32G_IMCR_LLCE_CAN11_RXD = 756, 316*fd84aaa8SChester Lin S32G_IMCR_LLCE_CAN12_RXD = 757, 317*fd84aaa8SChester Lin S32G_IMCR_LLCE_CAN13_RXD = 758, 318*fd84aaa8SChester Lin S32G_IMCR_LLCE_CAN14_RXD = 759, 319*fd84aaa8SChester Lin S32G_IMCR_LLCE_CAN15_RXD = 760, 320*fd84aaa8SChester Lin S32G_IMCR_USB_CLK = 895, 321*fd84aaa8SChester Lin S32G_IMCR_USB_DATA0 = 896, 322*fd84aaa8SChester Lin S32G_IMCR_USB_DATA1 = 897, 323*fd84aaa8SChester Lin S32G_IMCR_USB_DATA2 = 898, 324*fd84aaa8SChester Lin S32G_IMCR_USB_DATA3 = 899, 325*fd84aaa8SChester Lin S32G_IMCR_USB_DATA4 = 900, 326*fd84aaa8SChester Lin S32G_IMCR_USB_DATA5 = 901, 327*fd84aaa8SChester Lin S32G_IMCR_USB_DATA6 = 902, 328*fd84aaa8SChester Lin S32G_IMCR_USB_DATA7 = 903, 329*fd84aaa8SChester Lin S32G_IMCR_USB_DIR = 904, 330*fd84aaa8SChester Lin S32G_IMCR_USB_NXT = 905, 331*fd84aaa8SChester Lin 332*fd84aaa8SChester Lin S32G_IMCR_SIUL_EIRQ0 = 910, 333*fd84aaa8SChester Lin S32G_IMCR_SIUL_EIRQ1 = 911, 334*fd84aaa8SChester Lin S32G_IMCR_SIUL_EIRQ2 = 912, 335*fd84aaa8SChester Lin S32G_IMCR_SIUL_EIRQ3 = 913, 336*fd84aaa8SChester Lin S32G_IMCR_SIUL_EIRQ4 = 914, 337*fd84aaa8SChester Lin S32G_IMCR_SIUL_EIRQ5 = 915, 338*fd84aaa8SChester Lin S32G_IMCR_SIUL_EIRQ6 = 916, 339*fd84aaa8SChester Lin S32G_IMCR_SIUL_EIRQ7 = 917, 340*fd84aaa8SChester Lin S32G_IMCR_SIUL_EIRQ8 = 918, 341*fd84aaa8SChester Lin S32G_IMCR_SIUL_EIRQ9 = 919, 342*fd84aaa8SChester Lin S32G_IMCR_SIUL_EIRQ10 = 920, 343*fd84aaa8SChester Lin S32G_IMCR_SIUL_EIRQ11 = 921, 344*fd84aaa8SChester Lin S32G_IMCR_SIUL_EIRQ12 = 922, 345*fd84aaa8SChester Lin S32G_IMCR_SIUL_EIRQ13 = 923, 346*fd84aaa8SChester Lin S32G_IMCR_SIUL_EIRQ14 = 924, 347*fd84aaa8SChester Lin S32G_IMCR_SIUL_EIRQ15 = 925, 348*fd84aaa8SChester Lin S32G_IMCR_SIUL_EIRQ16 = 926, 349*fd84aaa8SChester Lin S32G_IMCR_SIUL_EIRQ17 = 927, 350*fd84aaa8SChester Lin S32G_IMCR_SIUL_EIRQ18 = 928, 351*fd84aaa8SChester Lin S32G_IMCR_SIUL_EIRQ19 = 929, 352*fd84aaa8SChester Lin S32G_IMCR_SIUL_EIRQ20 = 930, 353*fd84aaa8SChester Lin S32G_IMCR_SIUL_EIRQ21 = 931, 354*fd84aaa8SChester Lin S32G_IMCR_SIUL_EIRQ22 = 932, 355*fd84aaa8SChester Lin S32G_IMCR_SIUL_EIRQ23 = 933, 356*fd84aaa8SChester Lin S32G_IMCR_SIUL_EIRQ24 = 934, 357*fd84aaa8SChester Lin S32G_IMCR_SIUL_EIRQ25 = 935, 358*fd84aaa8SChester Lin S32G_IMCR_SIUL_EIRQ26 = 936, 359*fd84aaa8SChester Lin S32G_IMCR_SIUL_EIRQ27 = 937, 360*fd84aaa8SChester Lin S32G_IMCR_SIUL_EIRQ28 = 938, 361*fd84aaa8SChester Lin S32G_IMCR_SIUL_EIRQ29 = 939, 362*fd84aaa8SChester Lin S32G_IMCR_SIUL_EIRQ30 = 940, 363*fd84aaa8SChester Lin S32G_IMCR_SIUL_EIRQ31 = 941, 364*fd84aaa8SChester Lin }; 365*fd84aaa8SChester Lin 366*fd84aaa8SChester Lin /* Pad names for the pinmux subsystem */ 367*fd84aaa8SChester Lin static const struct pinctrl_pin_desc s32_pinctrl_pads_siul2[] = { 368*fd84aaa8SChester Lin 369*fd84aaa8SChester Lin /* SIUL2_0 pins. */ 370*fd84aaa8SChester Lin 371*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PA_00), 372*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PA_01), 373*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PA_02), 374*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PA_03), 375*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PA_04), 376*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PA_05), 377*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PA_06), 378*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PA_07), 379*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PA_08), 380*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PA_09), 381*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PA_10), 382*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PA_11), 383*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PA_12), 384*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PA_13), 385*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PA_14), 386*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PA_15), 387*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PB_00), 388*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PB_01), 389*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PB_02), 390*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PB_03), 391*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PB_04), 392*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PB_05), 393*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PB_06), 394*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PB_07), 395*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PB_08), 396*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PB_09), 397*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PB_10), 398*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PB_11), 399*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PB_12), 400*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PB_13), 401*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PB_14), 402*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PB_15), 403*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PC_00), 404*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PC_01), 405*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PC_02), 406*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PC_03), 407*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PC_04), 408*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PC_05), 409*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PC_06), 410*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PC_07), 411*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PC_08), 412*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PC_09), 413*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PC_10), 414*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PC_11), 415*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PC_12), 416*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PC_13), 417*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PC_14), 418*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PC_15), 419*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PD_00), 420*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PD_01), 421*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PD_02), 422*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PD_03), 423*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PD_04), 424*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PD_05), 425*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PD_06), 426*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PD_07), 427*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PD_08), 428*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PD_09), 429*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PD_10), 430*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PD_11), 431*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PD_12), 432*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PD_13), 433*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PD_14), 434*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PD_15), 435*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PE_00), 436*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PE_01), 437*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PE_02), 438*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PE_03), 439*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PE_04), 440*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PE_05), 441*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PE_06), 442*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PE_07), 443*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PE_08), 444*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PE_09), 445*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PE_10), 446*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PE_11), 447*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PE_12), 448*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PE_13), 449*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PE_14), 450*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PE_15), 451*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PF_00), 452*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PF_01), 453*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PF_02), 454*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PF_03), 455*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PF_04), 456*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PF_05), 457*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PF_06), 458*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PF_07), 459*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PF_08), 460*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PF_09), 461*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PF_10), 462*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PF_11), 463*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PF_12), 464*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PF_13), 465*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PF_14), 466*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PF_15), 467*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PG_00), 468*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PG_01), 469*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PG_02), 470*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PG_03), 471*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PG_04), 472*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PG_05), 473*fd84aaa8SChester Lin 474*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_QSPI_A_DATA0), 475*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_QSPI_A_DATA1), 476*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_QSPI_A_DATA2), 477*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_QSPI_A_DATA3), 478*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_QSPI_A_DATA4), 479*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_QSPI_A_DATA5), 480*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_QSPI_A_DATA6), 481*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_QSPI_A_DATA7), 482*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_QSPI_DQS_A), 483*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_QSPI_B_DATA0), 484*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_QSPI_B_DATA1), 485*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_QSPI_B_DATA2), 486*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_QSPI_B_DATA3), 487*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_QSPI_B_DATA4), 488*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_QSPI_B_DATA5), 489*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_QSPI_B_DATA6), 490*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_QSPI_B_DATA7), 491*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_QSPI_DQS_B), 492*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_I2C0_SCL), 493*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_I2C0_SDA), 494*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_LIN0_RX), 495*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_USDHC_CMD), 496*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_USDHC_DAT0), 497*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_USDHC_DAT1), 498*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_USDHC_DAT2), 499*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_USDHC_DAT3), 500*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_USDHC_DAT4), 501*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_USDHC_DAT5), 502*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_USDHC_DAT6), 503*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_USDHC_DAT7), 504*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_USDHC_DQS), 505*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_CAN0_RXD), 506*fd84aaa8SChester Lin /* GMAC0 */ 507*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_Ethernet_MDIO), 508*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_Ethernet_CRS), 509*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_Ethernet_COL), 510*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_Ethernet_RX_D0), 511*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_Ethernet_RX_D1), 512*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_Ethernet_RX_D2), 513*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_Ethernet_RX_D3), 514*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_Ethernet_RX_ER), 515*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_Ethernet_RX_CLK), 516*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_Ethernet_RX_DV), 517*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_Ethernet_TX_CLK), 518*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_Ethernet_REF_CLK), 519*fd84aaa8SChester Lin 520*fd84aaa8SChester Lin /* SIUL2_1 pins. */ 521*fd84aaa8SChester Lin 522*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PH_00), 523*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PH_01), 524*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PH_02), 525*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PH_03), 526*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PH_04), 527*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PH_05), 528*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PH_06), 529*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PH_07), 530*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PH_08), 531*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PH_09), 532*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PH_10), 533*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PJ_00), 534*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PJ_01), 535*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PJ_02), 536*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PJ_03), 537*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PJ_04), 538*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PJ_05), 539*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PJ_06), 540*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PJ_07), 541*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PJ_08), 542*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PJ_09), 543*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PJ_10), 544*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PJ_11), 545*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PJ_12), 546*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PJ_13), 547*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PJ_14), 548*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PJ_15), 549*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PK_00), 550*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PK_01), 551*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PK_02), 552*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PK_03), 553*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PK_04), 554*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PK_05), 555*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PK_06), 556*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PK_07), 557*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PK_08), 558*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PK_09), 559*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PK_10), 560*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PK_11), 561*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PK_12), 562*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PK_13), 563*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PK_14), 564*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PK_15), 565*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PL_00), 566*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PL_01), 567*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PL_02), 568*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PL_03), 569*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PL_04), 570*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PL_05), 571*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PL_06), 572*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PL_07), 573*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PL_08), 574*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PL_09), 575*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PL_10), 576*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PL_11), 577*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PL_12), 578*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PL_13), 579*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_MSCR_PL_14), 580*fd84aaa8SChester Lin 581*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_FlexRay0_A_RX), 582*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_FlexRay0_B_RX), 583*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_FlexTimer0_CH0), 584*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_FlexTimer1_CH0), 585*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_FlexTimer0_CH1), 586*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_FlexTimer1_CH1), 587*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_FlexTimer0_CH2), 588*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_FlexTimer1_CH2), 589*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_FlexTimer0_CH3), 590*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_FlexTimer1_CH3), 591*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_FlexTimer0_CH4), 592*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_FlexTimer1_CH4), 593*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_FlexTimer0_CH5), 594*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_FlexTimer1_CH5), 595*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_FlexTimer0_EXTCLK), 596*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_FlexTimer1_EXTCLK), 597*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_I2C1_SCL), 598*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_I2C1_SDA), 599*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_I2C2_SCL), 600*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_I2C2_SDA), 601*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_I2C3_SCL), 602*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_I2C3_SDA), 603*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_I2C4_SCL), 604*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_I2C4_SDA), 605*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_LIN1_RX), 606*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_LIN2_RX), 607*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_DSPI0_PCS0), 608*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_DSPI0_SCK), 609*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_DSPI0_SIN), 610*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_DSPI1_PCS0), 611*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_DSPI1_SCK), 612*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_DSPI1_SIN), 613*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_DSPI2_PCS0), 614*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_DSPI2_SCK), 615*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_DSPI2_SIN), 616*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_DSPI3_PCS0), 617*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_DSPI3_SCK), 618*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_DSPI3_SIN), 619*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_DSPI4_PCS0), 620*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_DSPI4_SCK), 621*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_DSPI4_SIN), 622*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_DSPI5_PCS0), 623*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_DSPI5_SCK), 624*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_DSPI5_SIN), 625*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN0_RXD), 626*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN1_RXD), 627*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN2_RXD), 628*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN3_RXD), 629*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN4_RXD), 630*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN5_RXD), 631*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN6_RXD), 632*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN7_RXD), 633*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN8_RXD), 634*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN9_RXD), 635*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN10_RXD), 636*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN11_RXD), 637*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN12_RXD), 638*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN13_RXD), 639*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN14_RXD), 640*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN15_RXD), 641*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_CAN1_RXD), 642*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_CAN2_RXD), 643*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_CAN3_RXD), 644*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_USB_CLK), 645*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_USB_DATA0), 646*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_USB_DATA1), 647*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_USB_DATA2), 648*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_USB_DATA3), 649*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_USB_DATA4), 650*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_USB_DATA5), 651*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_USB_DATA6), 652*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_USB_DATA7), 653*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_USB_DIR), 654*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_USB_NXT), 655*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_MDIO), 656*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_CRS), 657*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_COL), 658*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_RX_D0), 659*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_RX_D1), 660*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_RX_D2), 661*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_RX_D3), 662*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_RX_ER), 663*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_RX_CLK), 664*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_RX_DV), 665*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_TX_CLK), 666*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_REF_CLK), 667*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_MDIO), 668*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_CRS), 669*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_COL), 670*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_RX_D0), 671*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_RX_D1), 672*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_RX_D2), 673*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_RX_D3), 674*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_RX_ER), 675*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_RX_CLK), 676*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_RX_DV), 677*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_TX_CLK), 678*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_REF_CLK), 679*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ0), 680*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ1), 681*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ2), 682*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ3), 683*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ4), 684*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ5), 685*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ6), 686*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ7), 687*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ8), 688*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ9), 689*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ10), 690*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ11), 691*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ12), 692*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ13), 693*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ14), 694*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ15), 695*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ16), 696*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ17), 697*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ18), 698*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ19), 699*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ20), 700*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ21), 701*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ22), 702*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ23), 703*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ24), 704*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ25), 705*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ26), 706*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ27), 707*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ28), 708*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ29), 709*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ30), 710*fd84aaa8SChester Lin S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ31), 711*fd84aaa8SChester Lin }; 712*fd84aaa8SChester Lin 713*fd84aaa8SChester Lin static const struct s32_pin_range s32_pin_ranges_siul2[] = { 714*fd84aaa8SChester Lin /* MSCR pin ID ranges */ 715*fd84aaa8SChester Lin S32_PIN_RANGE(0, 101), 716*fd84aaa8SChester Lin S32_PIN_RANGE(112, 122), 717*fd84aaa8SChester Lin S32_PIN_RANGE(144, 190), 718*fd84aaa8SChester Lin /* IMCR pin ID ranges */ 719*fd84aaa8SChester Lin S32_PIN_RANGE(512, 595), 720*fd84aaa8SChester Lin S32_PIN_RANGE(631, 909), 721*fd84aaa8SChester Lin S32_PIN_RANGE(942, 1007), 722*fd84aaa8SChester Lin }; 723*fd84aaa8SChester Lin 724*fd84aaa8SChester Lin static struct s32_pinctrl_soc_info s32_pinctrl_info = { 725*fd84aaa8SChester Lin .pins = s32_pinctrl_pads_siul2, 726*fd84aaa8SChester Lin .npins = ARRAY_SIZE(s32_pinctrl_pads_siul2), 727*fd84aaa8SChester Lin .mem_pin_ranges = s32_pin_ranges_siul2, 728*fd84aaa8SChester Lin .mem_regions = ARRAY_SIZE(s32_pin_ranges_siul2), 729*fd84aaa8SChester Lin }; 730*fd84aaa8SChester Lin 731*fd84aaa8SChester Lin static const struct of_device_id s32_pinctrl_of_match[] = { 732*fd84aaa8SChester Lin { 733*fd84aaa8SChester Lin 734*fd84aaa8SChester Lin .compatible = "nxp,s32g2-siul2-pinctrl", 735*fd84aaa8SChester Lin .data = (void *) &s32_pinctrl_info, 736*fd84aaa8SChester Lin }, 737*fd84aaa8SChester Lin { /* sentinel */ } 738*fd84aaa8SChester Lin }; 739*fd84aaa8SChester Lin MODULE_DEVICE_TABLE(of, s32_pinctrl_of_match); 740*fd84aaa8SChester Lin 741*fd84aaa8SChester Lin static int s32g_pinctrl_probe(struct platform_device *pdev) 742*fd84aaa8SChester Lin { 743*fd84aaa8SChester Lin const struct of_device_id *of_id = 744*fd84aaa8SChester Lin of_match_device(s32_pinctrl_of_match, &pdev->dev); 745*fd84aaa8SChester Lin 746*fd84aaa8SChester Lin if (!of_id) 747*fd84aaa8SChester Lin return -ENODEV; 748*fd84aaa8SChester Lin 749*fd84aaa8SChester Lin return s32_pinctrl_probe 750*fd84aaa8SChester Lin (pdev, (struct s32_pinctrl_soc_info *) of_id->data); 751*fd84aaa8SChester Lin } 752*fd84aaa8SChester Lin 753*fd84aaa8SChester Lin static const struct dev_pm_ops s32g_pinctrl_pm_ops = { 754*fd84aaa8SChester Lin SET_LATE_SYSTEM_SLEEP_PM_OPS(s32_pinctrl_suspend, 755*fd84aaa8SChester Lin s32_pinctrl_resume) 756*fd84aaa8SChester Lin }; 757*fd84aaa8SChester Lin 758*fd84aaa8SChester Lin static struct platform_driver s32g_pinctrl_driver = { 759*fd84aaa8SChester Lin .driver = { 760*fd84aaa8SChester Lin .name = "s32g-siul2-pinctrl", 761*fd84aaa8SChester Lin .owner = THIS_MODULE, 762*fd84aaa8SChester Lin .of_match_table = s32_pinctrl_of_match, 763*fd84aaa8SChester Lin .pm = &s32g_pinctrl_pm_ops, 764*fd84aaa8SChester Lin .suppress_bind_attrs = true, 765*fd84aaa8SChester Lin }, 766*fd84aaa8SChester Lin .probe = s32g_pinctrl_probe, 767*fd84aaa8SChester Lin }; 768*fd84aaa8SChester Lin 769*fd84aaa8SChester Lin builtin_platform_driver(s32g_pinctrl_driver); 770*fd84aaa8SChester Lin 771*fd84aaa8SChester Lin MODULE_AUTHOR("Matthew Nunez <matthew.nunez@nxp.com>"); 772*fd84aaa8SChester Lin MODULE_DESCRIPTION("NXP S32G pinctrl driver"); 773*fd84aaa8SChester Lin MODULE_LICENSE("GPL"); 774