1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Core driver for the S32 CC (Common Chassis) pin controller 4 * 5 * Copyright 2017-2022 NXP 6 * Copyright (C) 2022 SUSE LLC 7 * Copyright 2015-2016 Freescale Semiconductor, Inc. 8 */ 9 10 #include <linux/bitops.h> 11 #include <linux/err.h> 12 #include <linux/gpio/driver.h> 13 #include <linux/init.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/of_device.h> 18 #include <linux/pinctrl/machine.h> 19 #include <linux/pinctrl/pinconf.h> 20 #include <linux/pinctrl/pinctrl.h> 21 #include <linux/pinctrl/pinmux.h> 22 #include <linux/regmap.h> 23 #include <linux/seq_file.h> 24 #include <linux/slab.h> 25 26 #include "../core.h" 27 #include "../pinconf.h" 28 #include "../pinctrl-utils.h" 29 #include "pinctrl-s32.h" 30 31 #define S32_PIN_ID_SHIFT 4 32 #define S32_PIN_ID_MASK GENMASK(31, S32_PIN_ID_SHIFT) 33 34 #define S32_MSCR_SSS_MASK GENMASK(2, 0) 35 #define S32_MSCR_PUS BIT(12) 36 #define S32_MSCR_PUE BIT(13) 37 #define S32_MSCR_SRE(X) (((X) & GENMASK(3, 0)) << 14) 38 #define S32_MSCR_IBE BIT(19) 39 #define S32_MSCR_ODE BIT(20) 40 #define S32_MSCR_OBE BIT(21) 41 42 static struct regmap_config s32_regmap_config = { 43 .reg_bits = 32, 44 .val_bits = 32, 45 .reg_stride = 4, 46 }; 47 48 static u32 get_pin_no(u32 pinmux) 49 { 50 return (pinmux & S32_PIN_ID_MASK) >> S32_PIN_ID_SHIFT; 51 } 52 53 static u32 get_pin_func(u32 pinmux) 54 { 55 return pinmux & GENMASK(3, 0); 56 } 57 58 struct s32_pinctrl_mem_region { 59 struct regmap *map; 60 const struct s32_pin_range *pin_range; 61 char name[8]; 62 }; 63 64 /* 65 * Holds pin configuration for GPIO's. 66 * @pin_id: Pin ID for this GPIO 67 * @config: Pin settings 68 * @list: Linked list entry for each gpio pin 69 */ 70 struct gpio_pin_config { 71 unsigned int pin_id; 72 unsigned int config; 73 struct list_head list; 74 }; 75 76 /* 77 * Pad config save/restore for power suspend/resume. 78 */ 79 struct s32_pinctrl_context { 80 unsigned int *pads; 81 }; 82 83 /* 84 * @dev: a pointer back to containing device 85 * @pctl: a pointer to the pinctrl device structure 86 * @regions: reserved memory regions with start/end pin 87 * @info: structure containing information about the pin 88 * @gpio_configs: Saved configurations for GPIO pins 89 * @gpiop_configs_lock: lock for the `gpio_configs` list 90 * @s32_pinctrl_context: Configuration saved over system sleep 91 */ 92 struct s32_pinctrl { 93 struct device *dev; 94 struct pinctrl_dev *pctl; 95 struct s32_pinctrl_mem_region *regions; 96 struct s32_pinctrl_soc_info *info; 97 struct list_head gpio_configs; 98 spinlock_t gpio_configs_lock; 99 #ifdef CONFIG_PM_SLEEP 100 struct s32_pinctrl_context saved_context; 101 #endif 102 }; 103 104 static struct s32_pinctrl_mem_region * 105 s32_get_region(struct pinctrl_dev *pctldev, unsigned int pin) 106 { 107 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 108 const struct s32_pin_range *pin_range; 109 unsigned int mem_regions = ipctl->info->mem_regions; 110 unsigned int i; 111 112 for (i = 0; i < mem_regions; i++) { 113 pin_range = ipctl->regions[i].pin_range; 114 if (pin >= pin_range->start && pin <= pin_range->end) 115 return &ipctl->regions[i]; 116 } 117 118 return NULL; 119 } 120 121 static inline int s32_check_pin(struct pinctrl_dev *pctldev, 122 unsigned int pin) 123 { 124 return s32_get_region(pctldev, pin) ? 0 : -EINVAL; 125 } 126 127 static inline int s32_regmap_read(struct pinctrl_dev *pctldev, 128 unsigned int pin, unsigned int *val) 129 { 130 struct s32_pinctrl_mem_region *region; 131 unsigned int offset; 132 133 region = s32_get_region(pctldev, pin); 134 if (!region) 135 return -EINVAL; 136 137 offset = (pin - region->pin_range->start) * 138 regmap_get_reg_stride(region->map); 139 140 return regmap_read(region->map, offset, val); 141 } 142 143 static inline int s32_regmap_write(struct pinctrl_dev *pctldev, 144 unsigned int pin, 145 unsigned int val) 146 { 147 struct s32_pinctrl_mem_region *region; 148 unsigned int offset; 149 150 region = s32_get_region(pctldev, pin); 151 if (!region) 152 return -EINVAL; 153 154 offset = (pin - region->pin_range->start) * 155 regmap_get_reg_stride(region->map); 156 157 return regmap_write(region->map, offset, val); 158 159 } 160 161 static inline int s32_regmap_update(struct pinctrl_dev *pctldev, unsigned int pin, 162 unsigned int mask, unsigned int val) 163 { 164 struct s32_pinctrl_mem_region *region; 165 unsigned int offset; 166 167 region = s32_get_region(pctldev, pin); 168 if (!region) 169 return -EINVAL; 170 171 offset = (pin - region->pin_range->start) * 172 regmap_get_reg_stride(region->map); 173 174 return regmap_update_bits(region->map, offset, mask, val); 175 } 176 177 static int s32_get_groups_count(struct pinctrl_dev *pctldev) 178 { 179 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 180 const struct s32_pinctrl_soc_info *info = ipctl->info; 181 182 return info->ngroups; 183 } 184 185 static const char *s32_get_group_name(struct pinctrl_dev *pctldev, 186 unsigned int selector) 187 { 188 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 189 const struct s32_pinctrl_soc_info *info = ipctl->info; 190 191 return info->groups[selector].data.name; 192 } 193 194 static int s32_get_group_pins(struct pinctrl_dev *pctldev, 195 unsigned int selector, const unsigned int **pins, 196 unsigned int *npins) 197 { 198 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 199 const struct s32_pinctrl_soc_info *info = ipctl->info; 200 201 *pins = info->groups[selector].data.pins; 202 *npins = info->groups[selector].data.npins; 203 204 return 0; 205 } 206 207 static void s32_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 208 unsigned int offset) 209 { 210 seq_printf(s, "%s", dev_name(pctldev->dev)); 211 } 212 213 static int s32_dt_group_node_to_map(struct pinctrl_dev *pctldev, 214 struct device_node *np, 215 struct pinctrl_map **map, 216 unsigned int *reserved_maps, 217 unsigned int *num_maps, 218 const char *func_name) 219 { 220 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 221 struct device *dev = ipctl->dev; 222 unsigned long *cfgs = NULL; 223 unsigned int n_cfgs, reserve = 1; 224 int n_pins, ret; 225 226 n_pins = of_property_count_elems_of_size(np, "pinmux", sizeof(u32)); 227 if (n_pins < 0) { 228 dev_warn(dev, "Can't find 'pinmux' property in node %pOFn\n", np); 229 } else if (!n_pins) { 230 return -EINVAL; 231 } 232 233 ret = pinconf_generic_parse_dt_config(np, pctldev, &cfgs, &n_cfgs); 234 if (ret) { 235 dev_err(dev, "%pOF: could not parse node property\n", np); 236 return ret; 237 } 238 239 if (n_cfgs) 240 reserve++; 241 242 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps, 243 reserve); 244 if (ret < 0) 245 goto free_cfgs; 246 247 ret = pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps, 248 np->name, func_name); 249 if (ret < 0) 250 goto free_cfgs; 251 252 if (n_cfgs) { 253 ret = pinctrl_utils_add_map_configs(pctldev, map, reserved_maps, 254 num_maps, np->name, cfgs, n_cfgs, 255 PIN_MAP_TYPE_CONFIGS_GROUP); 256 if (ret < 0) 257 goto free_cfgs; 258 } 259 260 free_cfgs: 261 kfree(cfgs); 262 return ret; 263 } 264 265 static int s32_dt_node_to_map(struct pinctrl_dev *pctldev, 266 struct device_node *np_config, 267 struct pinctrl_map **map, 268 unsigned int *num_maps) 269 { 270 unsigned int reserved_maps; 271 struct device_node *np; 272 int ret = 0; 273 274 reserved_maps = 0; 275 *map = NULL; 276 *num_maps = 0; 277 278 for_each_available_child_of_node(np_config, np) { 279 ret = s32_dt_group_node_to_map(pctldev, np, map, 280 &reserved_maps, num_maps, 281 np_config->name); 282 if (ret < 0) 283 break; 284 } 285 286 if (ret) 287 pinctrl_utils_free_map(pctldev, *map, *num_maps); 288 289 return ret; 290 291 } 292 293 static const struct pinctrl_ops s32_pctrl_ops = { 294 .get_groups_count = s32_get_groups_count, 295 .get_group_name = s32_get_group_name, 296 .get_group_pins = s32_get_group_pins, 297 .pin_dbg_show = s32_pin_dbg_show, 298 .dt_node_to_map = s32_dt_node_to_map, 299 .dt_free_map = pinctrl_utils_free_map, 300 }; 301 302 static int s32_pmx_set(struct pinctrl_dev *pctldev, unsigned int selector, 303 unsigned int group) 304 { 305 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 306 const struct s32_pinctrl_soc_info *info = ipctl->info; 307 int i, ret; 308 struct s32_pin_group *grp; 309 310 /* 311 * Configure the mux mode for each pin in the group for a specific 312 * function. 313 */ 314 grp = &info->groups[group]; 315 316 dev_dbg(ipctl->dev, "set mux for function %s group %s\n", 317 info->functions[selector].name, grp->data.name); 318 319 /* Check beforehand so we don't have a partial config. */ 320 for (i = 0; i < grp->data.npins; i++) { 321 if (s32_check_pin(pctldev, grp->data.pins[i]) != 0) { 322 dev_err(info->dev, "invalid pin: %u in group: %u\n", 323 grp->data.pins[i], group); 324 return -EINVAL; 325 } 326 } 327 328 for (i = 0, ret = 0; i < grp->data.npins && !ret; i++) { 329 ret = s32_regmap_update(pctldev, grp->data.pins[i], 330 S32_MSCR_SSS_MASK, grp->pin_sss[i]); 331 if (ret) { 332 dev_err(info->dev, "Failed to set pin %u\n", 333 grp->data.pins[i]); 334 return ret; 335 } 336 } 337 338 return 0; 339 } 340 341 static int s32_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 342 { 343 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 344 const struct s32_pinctrl_soc_info *info = ipctl->info; 345 346 return info->nfunctions; 347 } 348 349 static const char *s32_pmx_get_func_name(struct pinctrl_dev *pctldev, 350 unsigned int selector) 351 { 352 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 353 const struct s32_pinctrl_soc_info *info = ipctl->info; 354 355 return info->functions[selector].name; 356 } 357 358 static int s32_pmx_get_groups(struct pinctrl_dev *pctldev, 359 unsigned int selector, 360 const char * const **groups, 361 unsigned int * const num_groups) 362 { 363 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 364 const struct s32_pinctrl_soc_info *info = ipctl->info; 365 366 *groups = info->functions[selector].groups; 367 *num_groups = info->functions[selector].ngroups; 368 369 return 0; 370 } 371 372 static int s32_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, 373 struct pinctrl_gpio_range *range, 374 unsigned int offset) 375 { 376 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 377 struct gpio_pin_config *gpio_pin; 378 unsigned int config; 379 unsigned long flags; 380 int ret; 381 382 ret = s32_regmap_read(pctldev, offset, &config); 383 if (ret) 384 return ret; 385 386 /* Save current configuration */ 387 gpio_pin = kmalloc(sizeof(*gpio_pin), GFP_KERNEL); 388 if (!gpio_pin) 389 return -ENOMEM; 390 391 gpio_pin->pin_id = offset; 392 gpio_pin->config = config; 393 394 spin_lock_irqsave(&ipctl->gpio_configs_lock, flags); 395 list_add(&gpio_pin->list, &ipctl->gpio_configs); 396 spin_unlock_irqrestore(&ipctl->gpio_configs_lock, flags); 397 398 /* GPIO pin means SSS = 0 */ 399 config &= ~S32_MSCR_SSS_MASK; 400 401 return s32_regmap_write(pctldev, offset, config); 402 } 403 404 static void s32_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, 405 struct pinctrl_gpio_range *range, 406 unsigned int offset) 407 { 408 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 409 struct gpio_pin_config *gpio_pin, *tmp; 410 unsigned long flags; 411 int ret; 412 413 spin_lock_irqsave(&ipctl->gpio_configs_lock, flags); 414 415 list_for_each_entry_safe(gpio_pin, tmp, &ipctl->gpio_configs, list) { 416 if (gpio_pin->pin_id == offset) { 417 ret = s32_regmap_write(pctldev, gpio_pin->pin_id, 418 gpio_pin->config); 419 if (ret != 0) 420 goto unlock; 421 422 list_del(&gpio_pin->list); 423 kfree(gpio_pin); 424 break; 425 } 426 } 427 428 unlock: 429 spin_unlock_irqrestore(&ipctl->gpio_configs_lock, flags); 430 } 431 432 static int s32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 433 struct pinctrl_gpio_range *range, 434 unsigned int offset, 435 bool input) 436 { 437 unsigned int config; 438 unsigned int mask = S32_MSCR_IBE | S32_MSCR_OBE; 439 440 if (input) { 441 /* Disable output buffer and enable input buffer */ 442 config = S32_MSCR_IBE; 443 } else { 444 /* Disable input buffer and enable output buffer */ 445 config = S32_MSCR_OBE; 446 } 447 448 return s32_regmap_update(pctldev, offset, mask, config); 449 } 450 451 static const struct pinmux_ops s32_pmx_ops = { 452 .get_functions_count = s32_pmx_get_funcs_count, 453 .get_function_name = s32_pmx_get_func_name, 454 .get_function_groups = s32_pmx_get_groups, 455 .set_mux = s32_pmx_set, 456 .gpio_request_enable = s32_pmx_gpio_request_enable, 457 .gpio_disable_free = s32_pmx_gpio_disable_free, 458 .gpio_set_direction = s32_pmx_gpio_set_direction, 459 }; 460 461 /* Set the reserved elements as -1 */ 462 static const int support_slew[] = {208, -1, -1, -1, 166, 150, 133, 83}; 463 464 static int s32_get_slew_regval(int arg) 465 { 466 unsigned int i; 467 468 /* Translate a real slew rate (MHz) to a register value */ 469 for (i = 0; i < ARRAY_SIZE(support_slew); i++) { 470 if (arg == support_slew[i]) 471 return i; 472 } 473 474 return -EINVAL; 475 } 476 477 static inline void s32_pin_set_pull(enum pin_config_param param, 478 unsigned int *mask, unsigned int *config) 479 { 480 switch (param) { 481 case PIN_CONFIG_BIAS_DISABLE: 482 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 483 *config &= ~(S32_MSCR_PUS | S32_MSCR_PUE); 484 break; 485 case PIN_CONFIG_BIAS_PULL_UP: 486 *config |= S32_MSCR_PUS | S32_MSCR_PUE; 487 break; 488 case PIN_CONFIG_BIAS_PULL_DOWN: 489 *config &= ~S32_MSCR_PUS; 490 *config |= S32_MSCR_PUE; 491 break; 492 default: 493 return; 494 } 495 496 *mask |= S32_MSCR_PUS | S32_MSCR_PUE; 497 } 498 499 static int s32_parse_pincfg(unsigned long pincfg, unsigned int *mask, 500 unsigned int *config) 501 { 502 enum pin_config_param param; 503 u32 arg; 504 int ret; 505 506 param = pinconf_to_config_param(pincfg); 507 arg = pinconf_to_config_argument(pincfg); 508 509 switch (param) { 510 /* All pins are persistent over suspend */ 511 case PIN_CONFIG_PERSIST_STATE: 512 return 0; 513 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 514 *config |= S32_MSCR_ODE; 515 *mask |= S32_MSCR_ODE; 516 break; 517 case PIN_CONFIG_OUTPUT_ENABLE: 518 if (arg) 519 *config |= S32_MSCR_OBE; 520 else 521 *config &= ~S32_MSCR_OBE; 522 *mask |= S32_MSCR_OBE; 523 break; 524 case PIN_CONFIG_INPUT_ENABLE: 525 if (arg) 526 *config |= S32_MSCR_IBE; 527 else 528 *config &= ~S32_MSCR_IBE; 529 *mask |= S32_MSCR_IBE; 530 break; 531 case PIN_CONFIG_SLEW_RATE: 532 ret = s32_get_slew_regval(arg); 533 if (ret < 0) 534 return ret; 535 *config |= S32_MSCR_SRE((u32)ret); 536 *mask |= S32_MSCR_SRE(~0); 537 break; 538 case PIN_CONFIG_BIAS_DISABLE: 539 case PIN_CONFIG_BIAS_PULL_UP: 540 case PIN_CONFIG_BIAS_PULL_DOWN: 541 s32_pin_set_pull(param, mask, config); 542 break; 543 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 544 *config &= ~(S32_MSCR_ODE | S32_MSCR_OBE | S32_MSCR_IBE); 545 *mask |= S32_MSCR_ODE | S32_MSCR_OBE | S32_MSCR_IBE; 546 s32_pin_set_pull(param, mask, config); 547 break; 548 default: 549 return -EOPNOTSUPP; 550 } 551 552 return 0; 553 } 554 555 static int s32_pinconf_mscr_update(struct pinctrl_dev *pctldev, 556 unsigned int pin_id, 557 unsigned long *configs, 558 unsigned int num_configs) 559 { 560 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 561 unsigned int config = 0, mask = 0; 562 int i, ret; 563 564 ret = s32_check_pin(pctldev, pin_id); 565 if (ret) 566 return ret; 567 568 dev_dbg(ipctl->dev, "pinconf set pin %s with %u configs\n", 569 pin_get_name(pctldev, pin_id), num_configs); 570 571 for (i = 0; i < num_configs; i++) { 572 ret = s32_parse_pincfg(configs[i], &mask, &config); 573 if (ret) 574 return ret; 575 } 576 577 if (!config && !mask) 578 return 0; 579 580 dev_dbg(ipctl->dev, "update: pin %u cfg 0x%x\n", pin_id, config); 581 582 return s32_regmap_update(pctldev, pin_id, mask, config); 583 } 584 585 static int s32_pinconf_get(struct pinctrl_dev *pctldev, 586 unsigned int pin_id, 587 unsigned long *config) 588 { 589 return s32_regmap_read(pctldev, pin_id, (unsigned int *)config); 590 } 591 592 static int s32_pinconf_set(struct pinctrl_dev *pctldev, 593 unsigned int pin_id, unsigned long *configs, 594 unsigned int num_configs) 595 { 596 return s32_pinconf_mscr_update(pctldev, pin_id, configs, 597 num_configs); 598 } 599 600 static int s32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned int selector, 601 unsigned long *configs, unsigned int num_configs) 602 { 603 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 604 const struct s32_pinctrl_soc_info *info = ipctl->info; 605 struct s32_pin_group *grp; 606 int i, ret; 607 608 grp = &info->groups[selector]; 609 for (i = 0; i < grp->data.npins; i++) { 610 ret = s32_pinconf_mscr_update(pctldev, grp->data.pins[i], 611 configs, num_configs); 612 if (ret) 613 return ret; 614 } 615 616 return 0; 617 } 618 619 static void s32_pinconf_dbg_show(struct pinctrl_dev *pctldev, 620 struct seq_file *s, unsigned int pin_id) 621 { 622 unsigned int config; 623 int ret; 624 625 ret = s32_regmap_read(pctldev, pin_id, &config); 626 if (ret) 627 return; 628 629 seq_printf(s, "0x%x", config); 630 } 631 632 static void s32_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 633 struct seq_file *s, unsigned int selector) 634 { 635 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 636 const struct s32_pinctrl_soc_info *info = ipctl->info; 637 struct s32_pin_group *grp; 638 unsigned int config; 639 const char *name; 640 int i, ret; 641 642 seq_puts(s, "\n"); 643 grp = &info->groups[selector]; 644 for (i = 0; i < grp->data.npins; i++) { 645 name = pin_get_name(pctldev, grp->data.pins[i]); 646 ret = s32_regmap_read(pctldev, grp->data.pins[i], &config); 647 if (ret) 648 return; 649 seq_printf(s, "%s: 0x%x\n", name, config); 650 } 651 } 652 653 static const struct pinconf_ops s32_pinconf_ops = { 654 .pin_config_get = s32_pinconf_get, 655 .pin_config_set = s32_pinconf_set, 656 .pin_config_group_set = s32_pconf_group_set, 657 .pin_config_dbg_show = s32_pinconf_dbg_show, 658 .pin_config_group_dbg_show = s32_pinconf_group_dbg_show, 659 }; 660 661 #ifdef CONFIG_PM_SLEEP 662 static bool s32_pinctrl_should_save(struct s32_pinctrl *ipctl, 663 unsigned int pin) 664 { 665 const struct pin_desc *pd = pin_desc_get(ipctl->pctl, pin); 666 667 if (!pd) 668 return false; 669 670 /* 671 * Only restore the pin if it is actually in use by the kernel (or 672 * by userspace). 673 */ 674 if (pd->mux_owner || pd->gpio_owner) 675 return true; 676 677 return false; 678 } 679 680 int s32_pinctrl_suspend(struct device *dev) 681 { 682 struct platform_device *pdev = to_platform_device(dev); 683 struct s32_pinctrl *ipctl = platform_get_drvdata(pdev); 684 const struct pinctrl_pin_desc *pin; 685 const struct s32_pinctrl_soc_info *info = ipctl->info; 686 struct s32_pinctrl_context *saved_context = &ipctl->saved_context; 687 int i; 688 int ret; 689 unsigned int config; 690 691 for (i = 0; i < info->npins; i++) { 692 pin = &info->pins[i]; 693 694 if (!s32_pinctrl_should_save(ipctl, pin->number)) 695 continue; 696 697 ret = s32_regmap_read(ipctl->pctl, pin->number, &config); 698 if (ret) 699 return -EINVAL; 700 701 saved_context->pads[i] = config; 702 } 703 704 return 0; 705 } 706 707 int s32_pinctrl_resume(struct device *dev) 708 { 709 struct platform_device *pdev = to_platform_device(dev); 710 struct s32_pinctrl *ipctl = platform_get_drvdata(pdev); 711 const struct s32_pinctrl_soc_info *info = ipctl->info; 712 const struct pinctrl_pin_desc *pin; 713 struct s32_pinctrl_context *saved_context = &ipctl->saved_context; 714 int ret, i; 715 716 for (i = 0; i < info->npins; i++) { 717 pin = &info->pins[i]; 718 719 if (!s32_pinctrl_should_save(ipctl, pin->number)) 720 continue; 721 722 ret = s32_regmap_write(ipctl->pctl, pin->number, 723 saved_context->pads[i]); 724 if (ret) 725 return ret; 726 } 727 728 return 0; 729 } 730 #endif 731 732 static int s32_pinctrl_parse_groups(struct device_node *np, 733 struct s32_pin_group *grp, 734 struct s32_pinctrl_soc_info *info) 735 { 736 const __be32 *p; 737 struct device *dev; 738 struct property *prop; 739 unsigned int *pins, *sss; 740 int i, npins; 741 u32 pinmux; 742 743 dev = info->dev; 744 745 dev_dbg(dev, "group: %pOFn\n", np); 746 747 /* Initialise group */ 748 grp->data.name = np->name; 749 750 npins = of_property_count_elems_of_size(np, "pinmux", sizeof(u32)); 751 if (npins < 0) { 752 dev_err(dev, "Failed to read 'pinmux' property in node %s.\n", 753 grp->data.name); 754 return -EINVAL; 755 } 756 if (!npins) { 757 dev_err(dev, "The group %s has no pins.\n", grp->data.name); 758 return -EINVAL; 759 } 760 761 grp->data.npins = npins; 762 763 pins = devm_kcalloc(info->dev, npins, sizeof(*pins), GFP_KERNEL); 764 sss = devm_kcalloc(info->dev, npins, sizeof(*sss), GFP_KERNEL); 765 if (!pins || !sss) 766 return -ENOMEM; 767 768 i = 0; 769 of_property_for_each_u32(np, "pinmux", prop, p, pinmux) { 770 pins[i] = get_pin_no(pinmux); 771 sss[i] = get_pin_func(pinmux); 772 773 dev_dbg(info->dev, "pin: 0x%x, sss: 0x%x", pins[i], sss[i]); 774 i++; 775 } 776 777 grp->data.pins = pins; 778 grp->pin_sss = sss; 779 780 return 0; 781 } 782 783 static int s32_pinctrl_parse_functions(struct device_node *np, 784 struct s32_pinctrl_soc_info *info, 785 u32 index) 786 { 787 struct device_node *child; 788 struct pinfunction *func; 789 struct s32_pin_group *grp; 790 const char **groups; 791 u32 i = 0; 792 int ret = 0; 793 794 dev_dbg(info->dev, "parse function(%u): %pOFn\n", index, np); 795 796 func = &info->functions[index]; 797 798 /* Initialise function */ 799 func->name = np->name; 800 func->ngroups = of_get_child_count(np); 801 if (func->ngroups == 0) { 802 dev_err(info->dev, "no groups defined in %pOF\n", np); 803 return -EINVAL; 804 } 805 806 groups = devm_kcalloc(info->dev, func->ngroups, 807 sizeof(*func->groups), GFP_KERNEL); 808 if (!groups) 809 return -ENOMEM; 810 811 for_each_child_of_node(np, child) { 812 groups[i] = child->name; 813 grp = &info->groups[info->grp_index++]; 814 ret = s32_pinctrl_parse_groups(child, grp, info); 815 if (ret) 816 return ret; 817 i++; 818 } 819 820 func->groups = groups; 821 822 return 0; 823 } 824 825 static int s32_pinctrl_probe_dt(struct platform_device *pdev, 826 struct s32_pinctrl *ipctl) 827 { 828 struct s32_pinctrl_soc_info *info = ipctl->info; 829 struct device_node *np = pdev->dev.of_node; 830 struct device_node *child; 831 struct resource *res; 832 struct regmap *map; 833 void __iomem *base; 834 int mem_regions = info->mem_regions; 835 int ret; 836 u32 nfuncs = 0; 837 u32 i = 0; 838 839 if (!np) 840 return -ENODEV; 841 842 if (mem_regions == 0) { 843 dev_err(&pdev->dev, "mem_regions is 0\n"); 844 return -EINVAL; 845 } 846 847 ipctl->regions = devm_kcalloc(&pdev->dev, mem_regions, 848 sizeof(*ipctl->regions), GFP_KERNEL); 849 if (!ipctl->regions) 850 return -ENOMEM; 851 852 for (i = 0; i < mem_regions; i++) { 853 base = devm_platform_get_and_ioremap_resource(pdev, i, &res); 854 if (IS_ERR(base)) 855 return PTR_ERR(base); 856 857 snprintf(ipctl->regions[i].name, 858 sizeof(ipctl->regions[i].name), "map%u", i); 859 860 s32_regmap_config.name = ipctl->regions[i].name; 861 s32_regmap_config.max_register = resource_size(res) - 862 s32_regmap_config.reg_stride; 863 864 map = devm_regmap_init_mmio(&pdev->dev, base, 865 &s32_regmap_config); 866 if (IS_ERR(map)) { 867 dev_err(&pdev->dev, "Failed to init regmap[%u]\n", i); 868 return PTR_ERR(map); 869 } 870 871 ipctl->regions[i].map = map; 872 ipctl->regions[i].pin_range = &info->mem_pin_ranges[i]; 873 } 874 875 nfuncs = of_get_child_count(np); 876 if (nfuncs <= 0) { 877 dev_err(&pdev->dev, "no functions defined\n"); 878 return -EINVAL; 879 } 880 881 info->nfunctions = nfuncs; 882 info->functions = devm_kcalloc(&pdev->dev, nfuncs, 883 sizeof(*info->functions), GFP_KERNEL); 884 if (!info->functions) 885 return -ENOMEM; 886 887 info->ngroups = 0; 888 for_each_child_of_node(np, child) 889 info->ngroups += of_get_child_count(child); 890 891 info->groups = devm_kcalloc(&pdev->dev, info->ngroups, 892 sizeof(*info->groups), GFP_KERNEL); 893 if (!info->groups) 894 return -ENOMEM; 895 896 i = 0; 897 for_each_child_of_node(np, child) { 898 ret = s32_pinctrl_parse_functions(child, info, i++); 899 if (ret) 900 return ret; 901 } 902 903 return 0; 904 } 905 906 int s32_pinctrl_probe(struct platform_device *pdev, 907 struct s32_pinctrl_soc_info *info) 908 { 909 struct s32_pinctrl *ipctl; 910 int ret; 911 struct pinctrl_desc *s32_pinctrl_desc; 912 #ifdef CONFIG_PM_SLEEP 913 struct s32_pinctrl_context *saved_context; 914 #endif 915 916 if (!info || !info->pins || !info->npins) { 917 dev_err(&pdev->dev, "wrong pinctrl info\n"); 918 return -EINVAL; 919 } 920 921 info->dev = &pdev->dev; 922 923 /* Create state holders etc for this driver */ 924 ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL); 925 if (!ipctl) 926 return -ENOMEM; 927 928 ipctl->info = info; 929 ipctl->dev = info->dev; 930 platform_set_drvdata(pdev, ipctl); 931 932 INIT_LIST_HEAD(&ipctl->gpio_configs); 933 spin_lock_init(&ipctl->gpio_configs_lock); 934 935 s32_pinctrl_desc = 936 devm_kmalloc(&pdev->dev, sizeof(*s32_pinctrl_desc), GFP_KERNEL); 937 if (!s32_pinctrl_desc) 938 return -ENOMEM; 939 940 s32_pinctrl_desc->name = dev_name(&pdev->dev); 941 s32_pinctrl_desc->pins = info->pins; 942 s32_pinctrl_desc->npins = info->npins; 943 s32_pinctrl_desc->pctlops = &s32_pctrl_ops; 944 s32_pinctrl_desc->pmxops = &s32_pmx_ops; 945 s32_pinctrl_desc->confops = &s32_pinconf_ops; 946 s32_pinctrl_desc->owner = THIS_MODULE; 947 948 ret = s32_pinctrl_probe_dt(pdev, ipctl); 949 if (ret) { 950 dev_err(&pdev->dev, "fail to probe dt properties\n"); 951 return ret; 952 } 953 954 ipctl->pctl = devm_pinctrl_register(&pdev->dev, s32_pinctrl_desc, 955 ipctl); 956 if (IS_ERR(ipctl->pctl)) 957 return dev_err_probe(&pdev->dev, PTR_ERR(ipctl->pctl), 958 "could not register s32 pinctrl driver\n"); 959 960 #ifdef CONFIG_PM_SLEEP 961 saved_context = &ipctl->saved_context; 962 saved_context->pads = 963 devm_kcalloc(&pdev->dev, info->npins, 964 sizeof(*saved_context->pads), 965 GFP_KERNEL); 966 if (!saved_context->pads) 967 return -ENOMEM; 968 #endif 969 970 dev_info(&pdev->dev, "initialized s32 pinctrl driver\n"); 971 972 return 0; 973 } 974