1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2016-2018 Nuvoton Technology corporation.
3 // Copyright (c) 2016, Dell Inc
4 // Copyright (c) 2021-2022 Jonathan Neuschäfer
5 //
6 // This driver uses the following registers:
7 // - Pin mux registers, in the GCR (general control registers) block
8 // - GPIO registers, specific to each GPIO bank
9 // - GPIO event (interrupt) registers, located centrally in the GPIO register
10 //   block, shared between all GPIO banks
11 
12 #include <linux/device.h>
13 #include <linux/fwnode.h>
14 #include <linux/gpio/driver.h>
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/module.h>
19 #include <linux/mod_devicetable.h>
20 #include <linux/platform_device.h>
21 #include <linux/regmap.h>
22 
23 #include <linux/pinctrl/pinconf.h>
24 #include <linux/pinctrl/pinconf-generic.h>
25 #include <linux/pinctrl/pinctrl.h>
26 #include <linux/pinctrl/pinmux.h>
27 
28 #include "../core.h"
29 
30 /* GCR registers */
31 #define WPCM450_GCR_MFSEL1	0x0c
32 #define WPCM450_GCR_MFSEL2	0x10
33 #define WPCM450_GCR_NONE	0
34 
35 /* GPIO event (interrupt) registers */
36 #define WPCM450_GPEVTYPE	0x00
37 #define WPCM450_GPEVPOL		0x04
38 #define WPCM450_GPEVDBNC	0x08
39 #define WPCM450_GPEVEN		0x0c
40 #define WPCM450_GPEVST		0x10
41 
42 #define WPCM450_NUM_BANKS	8
43 #define WPCM450_NUM_GPIOS	128
44 #define WPCM450_NUM_GPIO_IRQS	4
45 
46 struct wpcm450_pinctrl;
47 struct wpcm450_bank;
48 
49 struct wpcm450_gpio {
50 	struct gpio_chip	gc;
51 	struct wpcm450_pinctrl	*pctrl;
52 	struct irq_chip		irqc;
53 	const struct wpcm450_bank *bank;
54 };
55 
56 struct wpcm450_pinctrl {
57 	struct pinctrl_dev	*pctldev;
58 	struct device		*dev;
59 	struct irq_domain	*domain;
60 	struct regmap		*gcr_regmap;
61 	void __iomem		*gpio_base;
62 	struct wpcm450_gpio	gpio_bank[WPCM450_NUM_BANKS];
63 	unsigned long		both_edges;
64 
65 	/*
66 	 * This spin lock protects registers and struct wpcm450_pinctrl fields
67 	 * against concurrent access.
68 	 */
69 	raw_spinlock_t		lock;
70 };
71 
72 struct wpcm450_bank {
73 	/* Range of GPIOs in this port */
74 	u8 base;
75 	u8 length;
76 
77 	/* Register offsets (0 = register doesn't exist in this port) */
78 	u8 cfg0, cfg1, cfg2;
79 	u8 blink;
80 	u8 dataout, datain;
81 
82 	/* Interrupt bit mapping */
83 	u8 first_irq_bit;   /* First bit in GPEVST that belongs to this bank */
84 	u8 num_irqs;        /* Number of IRQ-capable GPIOs in this bank */
85 	u8 first_irq_gpio;  /* First IRQ-capable GPIO in this bank */
86 };
87 
88 static const struct wpcm450_bank wpcm450_banks[WPCM450_NUM_BANKS] = {
89 	/*  range   cfg0  cfg1  cfg2 blink  out   in     IRQ map */
90 	{   0, 16,  0x14, 0x18,    0,    0, 0x1c, 0x20,  0, 16, 0 },
91 	{  16, 16,  0x24, 0x28, 0x2c, 0x30, 0x34, 0x38, 16,  2, 8 },
92 	{  32, 16,  0x3c, 0x40, 0x44,    0, 0x48, 0x4c,  0,  0, 0 },
93 	{  48, 16,  0x50, 0x54, 0x58,    0, 0x5c, 0x60,  0,  0, 0 },
94 	{  64, 16,  0x64, 0x68, 0x6c,    0, 0x70, 0x74,  0,  0, 0 },
95 	{  80, 16,  0x78, 0x7c, 0x80,    0, 0x84, 0x88,  0,  0, 0 },
96 	{  96, 18,     0,    0,    0,    0,    0, 0x8c,  0,  0, 0 },
97 	{ 114, 14,  0x90, 0x94, 0x98,    0, 0x9c, 0xa0,  0,  0, 0 },
98 };
99 
100 static int wpcm450_gpio_irq_bitnum(struct wpcm450_gpio *gpio, struct irq_data *d)
101 {
102 	const struct wpcm450_bank *bank = gpio->bank;
103 	int hwirq = irqd_to_hwirq(d);
104 
105 	if (hwirq < bank->first_irq_gpio)
106 		return -EINVAL;
107 
108 	if (hwirq - bank->first_irq_gpio >= bank->num_irqs)
109 		return -EINVAL;
110 
111 	return hwirq - bank->first_irq_gpio + bank->first_irq_bit;
112 }
113 
114 static int wpcm450_irq_bitnum_to_gpio(struct wpcm450_gpio *gpio, int bitnum)
115 {
116 	const struct wpcm450_bank *bank = gpio->bank;
117 
118 	if (bitnum < bank->first_irq_bit)
119 		return -EINVAL;
120 
121 	if (bitnum - bank->first_irq_bit > bank->num_irqs)
122 		return -EINVAL;
123 
124 	return bitnum - bank->first_irq_bit + bank->first_irq_gpio;
125 }
126 
127 static void wpcm450_gpio_irq_ack(struct irq_data *d)
128 {
129 	struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d));
130 	struct wpcm450_pinctrl *pctrl = gpio->pctrl;
131 	unsigned long flags;
132 	int bit;
133 
134 	bit = wpcm450_gpio_irq_bitnum(gpio, d);
135 	if (bit < 0)
136 		return;
137 
138 	raw_spin_lock_irqsave(&pctrl->lock, flags);
139 	iowrite32(BIT(bit), pctrl->gpio_base + WPCM450_GPEVST);
140 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
141 }
142 
143 static void wpcm450_gpio_irq_mask(struct irq_data *d)
144 {
145 	struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d));
146 	struct wpcm450_pinctrl *pctrl = gpio->pctrl;
147 	unsigned long flags;
148 	unsigned long even;
149 	int bit;
150 
151 	bit = wpcm450_gpio_irq_bitnum(gpio, d);
152 	if (bit < 0)
153 		return;
154 
155 	raw_spin_lock_irqsave(&pctrl->lock, flags);
156 	even = ioread32(pctrl->gpio_base + WPCM450_GPEVEN);
157 	__assign_bit(bit, &even, 0);
158 	iowrite32(even, pctrl->gpio_base + WPCM450_GPEVEN);
159 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
160 }
161 
162 static void wpcm450_gpio_irq_unmask(struct irq_data *d)
163 {
164 	struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d));
165 	struct wpcm450_pinctrl *pctrl = gpio->pctrl;
166 	unsigned long flags;
167 	unsigned long even;
168 	int bit;
169 
170 	bit = wpcm450_gpio_irq_bitnum(gpio, d);
171 	if (bit < 0)
172 		return;
173 
174 	raw_spin_lock_irqsave(&pctrl->lock, flags);
175 	even = ioread32(pctrl->gpio_base + WPCM450_GPEVEN);
176 	__assign_bit(bit, &even, 1);
177 	iowrite32(even, pctrl->gpio_base + WPCM450_GPEVEN);
178 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
179 }
180 
181 /*
182  * This is an implementation of the gpio_chip->get() function, for use in
183  * wpcm450_gpio_fix_evpol. Unfortunately, we can't use the bgpio-provided
184  * implementation there, because it would require taking gpio_chip->bgpio_lock,
185  * which is a spin lock, but wpcm450_gpio_fix_evpol must work in contexts where
186  * a raw spin lock is held.
187  */
188 static int wpcm450_gpio_get(struct wpcm450_gpio *gpio, int offset)
189 {
190 	void __iomem *reg = gpio->pctrl->gpio_base + gpio->bank->datain;
191 	unsigned long flags;
192 	u32 level;
193 
194 	raw_spin_lock_irqsave(&gpio->pctrl->lock, flags);
195 	level = !!(ioread32(reg) & BIT(offset));
196 	raw_spin_unlock_irqrestore(&gpio->pctrl->lock, flags);
197 
198 	return level;
199 }
200 
201 /*
202  * Since the GPIO controller does not support dual-edge triggered interrupts
203  * (IRQ_TYPE_EDGE_BOTH), they are emulated using rising/falling edge triggered
204  * interrupts. wpcm450_gpio_fix_evpol sets the interrupt polarity for the
205  * specified emulated dual-edge triggered interrupts, so that the next edge can
206  * be detected.
207  */
208 static void wpcm450_gpio_fix_evpol(struct wpcm450_gpio *gpio, unsigned long all)
209 {
210 	struct wpcm450_pinctrl *pctrl = gpio->pctrl;
211 	unsigned int bit;
212 
213 	for_each_set_bit(bit, &all, 32) {
214 		int offset = wpcm450_irq_bitnum_to_gpio(gpio, bit);
215 		unsigned long evpol;
216 		unsigned long flags;
217 		int level;
218 
219 		do {
220 			level = wpcm450_gpio_get(gpio, offset);
221 
222 			/* Switch event polarity to the opposite of the current level */
223 			raw_spin_lock_irqsave(&pctrl->lock, flags);
224 			evpol = ioread32(pctrl->gpio_base + WPCM450_GPEVPOL);
225 			__assign_bit(bit, &evpol, !level);
226 			iowrite32(evpol, pctrl->gpio_base + WPCM450_GPEVPOL);
227 			raw_spin_unlock_irqrestore(&pctrl->lock, flags);
228 
229 		} while (wpcm450_gpio_get(gpio, offset) != level);
230 	}
231 }
232 
233 static int wpcm450_gpio_set_irq_type(struct irq_data *d, unsigned int flow_type)
234 {
235 	struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d));
236 	struct wpcm450_pinctrl *pctrl = gpio->pctrl;
237 	unsigned long evtype, evpol;
238 	unsigned long flags;
239 	int ret = 0;
240 	int bit;
241 
242 	bit = wpcm450_gpio_irq_bitnum(gpio, d);
243 	if (bit < 0)
244 		return bit;
245 
246 	irq_set_handler_locked(d, handle_level_irq);
247 
248 	raw_spin_lock_irqsave(&pctrl->lock, flags);
249 	evtype = ioread32(pctrl->gpio_base + WPCM450_GPEVTYPE);
250 	evpol = ioread32(pctrl->gpio_base + WPCM450_GPEVPOL);
251 	__assign_bit(bit, &pctrl->both_edges, 0);
252 	switch (flow_type) {
253 	case IRQ_TYPE_LEVEL_LOW:
254 		__assign_bit(bit, &evtype, 1);
255 		__assign_bit(bit, &evpol, 0);
256 		break;
257 	case IRQ_TYPE_LEVEL_HIGH:
258 		__assign_bit(bit, &evtype, 1);
259 		__assign_bit(bit, &evpol, 1);
260 		break;
261 	case IRQ_TYPE_EDGE_FALLING:
262 		__assign_bit(bit, &evtype, 0);
263 		__assign_bit(bit, &evpol, 0);
264 		break;
265 	case IRQ_TYPE_EDGE_RISING:
266 		__assign_bit(bit, &evtype, 0);
267 		__assign_bit(bit, &evpol, 1);
268 		break;
269 	case IRQ_TYPE_EDGE_BOTH:
270 		__assign_bit(bit, &evtype, 0);
271 		__assign_bit(bit, &pctrl->both_edges, 1);
272 		break;
273 	default:
274 		ret = -EINVAL;
275 	}
276 	iowrite32(evtype, pctrl->gpio_base + WPCM450_GPEVTYPE);
277 	iowrite32(evpol, pctrl->gpio_base + WPCM450_GPEVPOL);
278 
279 	/* clear the event status for good measure */
280 	iowrite32(BIT(bit), pctrl->gpio_base + WPCM450_GPEVST);
281 
282 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
283 
284 	/* fix event polarity after clearing event status */
285 	wpcm450_gpio_fix_evpol(gpio, BIT(bit));
286 
287 	return ret;
288 }
289 
290 static const struct irq_chip wpcm450_gpio_irqchip = {
291 	.name = "WPCM450-GPIO-IRQ",
292 	.irq_ack = wpcm450_gpio_irq_ack,
293 	.irq_unmask = wpcm450_gpio_irq_unmask,
294 	.irq_mask = wpcm450_gpio_irq_mask,
295 	.irq_set_type = wpcm450_gpio_set_irq_type,
296 };
297 
298 static void wpcm450_gpio_irqhandler(struct irq_desc *desc)
299 {
300 	struct wpcm450_gpio *gpio = gpiochip_get_data(irq_desc_get_handler_data(desc));
301 	struct wpcm450_pinctrl *pctrl = gpio->pctrl;
302 	struct irq_chip *chip = irq_desc_get_chip(desc);
303 	unsigned long pending;
304 	unsigned long flags;
305 	unsigned long ours;
306 	unsigned int bit;
307 
308 	ours = GENMASK(gpio->bank->num_irqs - 1, 0) << gpio->bank->first_irq_bit;
309 
310 	raw_spin_lock_irqsave(&pctrl->lock, flags);
311 
312 	pending = ioread32(pctrl->gpio_base + WPCM450_GPEVST);
313 	pending &= ioread32(pctrl->gpio_base + WPCM450_GPEVEN);
314 	pending &= ours;
315 
316 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
317 
318 	if (pending & pctrl->both_edges)
319 		wpcm450_gpio_fix_evpol(gpio, pending & pctrl->both_edges);
320 
321 	chained_irq_enter(chip, desc);
322 	for_each_set_bit(bit, &pending, 32) {
323 		int offset = wpcm450_irq_bitnum_to_gpio(gpio, bit);
324 
325 		generic_handle_domain_irq(gpio->gc.irq.domain, offset);
326 	}
327 	chained_irq_exit(chip, desc);
328 }
329 
330 static int smb0_pins[]  = { 115, 114 };
331 static int smb1_pins[]  = { 117, 116 };
332 static int smb2_pins[]  = { 119, 118 };
333 static int smb3_pins[]  = { 30, 31 };
334 static int smb4_pins[]  = { 28, 29 };
335 static int smb5_pins[]  = { 26, 27 };
336 
337 static int scs1_pins[] = { 32 };
338 static int scs2_pins[] = { 33 };
339 static int scs3_pins[] = { 34 };
340 
341 static int bsp_pins[] = { 41, 42 };
342 static int hsp1_pins[] = { 43, 44, 45, 46, 47, 61, 62, 63 };
343 static int hsp2_pins[] = { 48, 49, 50, 51, 52, 53, 54, 55 };
344 
345 static int r1err_pins[] = { 56 };
346 static int r1md_pins[] = { 57, 58 };
347 static int rmii2_pins[] = { 84, 85, 86, 87, 88, 89 };
348 static int r2err_pins[] = { 90 };
349 static int r2md_pins[] = { 91, 92 };
350 
351 static int kbcc_pins[] = { 94, 93 };
352 static int clko_pins[] = { 96 };
353 static int smi_pins[] = { 97 };
354 static int uinc_pins[] = { 19 };
355 static int mben_pins[] = {};
356 
357 static int gspi_pins[] = { 12, 13, 14, 15 };
358 static int sspi_pins[] = { 12, 13, 14, 15 };
359 
360 static int xcs1_pins[] = { 35 };
361 static int xcs2_pins[] = { 36 };
362 
363 static int sdio_pins[] = { 7, 22, 43, 44, 45, 46, 47, 60 };
364 
365 static int fi0_pins[] = { 64 };
366 static int fi1_pins[] = { 65 };
367 static int fi2_pins[] = { 66 };
368 static int fi3_pins[] = { 67 };
369 static int fi4_pins[] = { 68 };
370 static int fi5_pins[] = { 69 };
371 static int fi6_pins[] = { 70 };
372 static int fi7_pins[] = { 71 };
373 static int fi8_pins[] = { 72 };
374 static int fi9_pins[] = { 73 };
375 static int fi10_pins[] = { 74 };
376 static int fi11_pins[] = { 75 };
377 static int fi12_pins[] = { 76 };
378 static int fi13_pins[] = { 77 };
379 static int fi14_pins[] = { 78 };
380 static int fi15_pins[] = { 79 };
381 
382 static int pwm0_pins[] = { 80 };
383 static int pwm1_pins[] = { 81 };
384 static int pwm2_pins[] = { 82 };
385 static int pwm3_pins[] = { 83 };
386 static int pwm4_pins[] = { 20 };
387 static int pwm5_pins[] = { 21 };
388 static int pwm6_pins[] = { 16 };
389 static int pwm7_pins[] = { 17 };
390 
391 static int hg0_pins[] = { 20 };
392 static int hg1_pins[] = { 21 };
393 static int hg2_pins[] = { 22 };
394 static int hg3_pins[] = { 23 };
395 static int hg4_pins[] = { 24 };
396 static int hg5_pins[] = { 25 };
397 static int hg6_pins[] = { 59 };
398 static int hg7_pins[] = { 60 };
399 
400 #define WPCM450_GRPS \
401 	WPCM450_GRP(smb3), \
402 	WPCM450_GRP(smb4), \
403 	WPCM450_GRP(smb5), \
404 	WPCM450_GRP(scs1), \
405 	WPCM450_GRP(scs2), \
406 	WPCM450_GRP(scs3), \
407 	WPCM450_GRP(smb0), \
408 	WPCM450_GRP(smb1), \
409 	WPCM450_GRP(smb2), \
410 	WPCM450_GRP(bsp), \
411 	WPCM450_GRP(hsp1), \
412 	WPCM450_GRP(hsp2), \
413 	WPCM450_GRP(r1err), \
414 	WPCM450_GRP(r1md), \
415 	WPCM450_GRP(rmii2), \
416 	WPCM450_GRP(r2err), \
417 	WPCM450_GRP(r2md), \
418 	WPCM450_GRP(kbcc), \
419 	WPCM450_GRP(clko), \
420 	WPCM450_GRP(smi), \
421 	WPCM450_GRP(uinc), \
422 	WPCM450_GRP(gspi), \
423 	WPCM450_GRP(mben), \
424 	WPCM450_GRP(xcs2), \
425 	WPCM450_GRP(xcs1), \
426 	WPCM450_GRP(sdio), \
427 	WPCM450_GRP(sspi), \
428 	WPCM450_GRP(fi0), \
429 	WPCM450_GRP(fi1), \
430 	WPCM450_GRP(fi2), \
431 	WPCM450_GRP(fi3), \
432 	WPCM450_GRP(fi4), \
433 	WPCM450_GRP(fi5), \
434 	WPCM450_GRP(fi6), \
435 	WPCM450_GRP(fi7), \
436 	WPCM450_GRP(fi8), \
437 	WPCM450_GRP(fi9), \
438 	WPCM450_GRP(fi10), \
439 	WPCM450_GRP(fi11), \
440 	WPCM450_GRP(fi12), \
441 	WPCM450_GRP(fi13), \
442 	WPCM450_GRP(fi14), \
443 	WPCM450_GRP(fi15), \
444 	WPCM450_GRP(pwm0), \
445 	WPCM450_GRP(pwm1), \
446 	WPCM450_GRP(pwm2), \
447 	WPCM450_GRP(pwm3), \
448 	WPCM450_GRP(pwm4), \
449 	WPCM450_GRP(pwm5), \
450 	WPCM450_GRP(pwm6), \
451 	WPCM450_GRP(pwm7), \
452 	WPCM450_GRP(hg0), \
453 	WPCM450_GRP(hg1), \
454 	WPCM450_GRP(hg2), \
455 	WPCM450_GRP(hg3), \
456 	WPCM450_GRP(hg4), \
457 	WPCM450_GRP(hg5), \
458 	WPCM450_GRP(hg6), \
459 	WPCM450_GRP(hg7), \
460 
461 enum {
462 #define WPCM450_GRP(x) fn_ ## x
463 	WPCM450_GRPS
464 	/* add placeholder for none/gpio */
465 	WPCM450_GRP(gpio),
466 	WPCM450_GRP(none),
467 #undef WPCM450_GRP
468 };
469 
470 static struct group_desc wpcm450_groups[] = {
471 #define WPCM450_GRP(x) { .name = #x, .pins = x ## _pins, \
472 			.num_pins = ARRAY_SIZE(x ## _pins) }
473 	WPCM450_GRPS
474 #undef WPCM450_GRP
475 };
476 
477 #define WPCM450_SFUNC(a) WPCM450_FUNC(a, #a)
478 #define WPCM450_FUNC(a, b...) static const char *a ## _grp[] = { b }
479 #define WPCM450_MKFUNC(nm) { .name = #nm, .ngroups = ARRAY_SIZE(nm ## _grp), \
480 			.groups = nm ## _grp }
481 struct wpcm450_func {
482 	const char *name;
483 	const unsigned int ngroups;
484 	const char *const *groups;
485 };
486 
487 WPCM450_SFUNC(smb3);
488 WPCM450_SFUNC(smb4);
489 WPCM450_SFUNC(smb5);
490 WPCM450_SFUNC(scs1);
491 WPCM450_SFUNC(scs2);
492 WPCM450_SFUNC(scs3);
493 WPCM450_SFUNC(smb0);
494 WPCM450_SFUNC(smb1);
495 WPCM450_SFUNC(smb2);
496 WPCM450_SFUNC(bsp);
497 WPCM450_SFUNC(hsp1);
498 WPCM450_SFUNC(hsp2);
499 WPCM450_SFUNC(r1err);
500 WPCM450_SFUNC(r1md);
501 WPCM450_SFUNC(rmii2);
502 WPCM450_SFUNC(r2err);
503 WPCM450_SFUNC(r2md);
504 WPCM450_SFUNC(kbcc);
505 WPCM450_SFUNC(clko);
506 WPCM450_SFUNC(smi);
507 WPCM450_SFUNC(uinc);
508 WPCM450_SFUNC(gspi);
509 WPCM450_SFUNC(mben);
510 WPCM450_SFUNC(xcs2);
511 WPCM450_SFUNC(xcs1);
512 WPCM450_SFUNC(sdio);
513 WPCM450_SFUNC(sspi);
514 WPCM450_SFUNC(fi0);
515 WPCM450_SFUNC(fi1);
516 WPCM450_SFUNC(fi2);
517 WPCM450_SFUNC(fi3);
518 WPCM450_SFUNC(fi4);
519 WPCM450_SFUNC(fi5);
520 WPCM450_SFUNC(fi6);
521 WPCM450_SFUNC(fi7);
522 WPCM450_SFUNC(fi8);
523 WPCM450_SFUNC(fi9);
524 WPCM450_SFUNC(fi10);
525 WPCM450_SFUNC(fi11);
526 WPCM450_SFUNC(fi12);
527 WPCM450_SFUNC(fi13);
528 WPCM450_SFUNC(fi14);
529 WPCM450_SFUNC(fi15);
530 WPCM450_SFUNC(pwm0);
531 WPCM450_SFUNC(pwm1);
532 WPCM450_SFUNC(pwm2);
533 WPCM450_SFUNC(pwm3);
534 WPCM450_SFUNC(pwm4);
535 WPCM450_SFUNC(pwm5);
536 WPCM450_SFUNC(pwm6);
537 WPCM450_SFUNC(pwm7);
538 WPCM450_SFUNC(hg0);
539 WPCM450_SFUNC(hg1);
540 WPCM450_SFUNC(hg2);
541 WPCM450_SFUNC(hg3);
542 WPCM450_SFUNC(hg4);
543 WPCM450_SFUNC(hg5);
544 WPCM450_SFUNC(hg6);
545 WPCM450_SFUNC(hg7);
546 
547 #define WPCM450_GRP(x) #x
548 WPCM450_FUNC(gpio, WPCM450_GRPS);
549 #undef WPCM450_GRP
550 
551 /* Function names */
552 static struct wpcm450_func wpcm450_funcs[] = {
553 	WPCM450_MKFUNC(smb3),
554 	WPCM450_MKFUNC(smb4),
555 	WPCM450_MKFUNC(smb5),
556 	WPCM450_MKFUNC(scs1),
557 	WPCM450_MKFUNC(scs2),
558 	WPCM450_MKFUNC(scs3),
559 	WPCM450_MKFUNC(smb0),
560 	WPCM450_MKFUNC(smb1),
561 	WPCM450_MKFUNC(smb2),
562 	WPCM450_MKFUNC(bsp),
563 	WPCM450_MKFUNC(hsp1),
564 	WPCM450_MKFUNC(hsp2),
565 	WPCM450_MKFUNC(r1err),
566 	WPCM450_MKFUNC(r1md),
567 	WPCM450_MKFUNC(rmii2),
568 	WPCM450_MKFUNC(r2err),
569 	WPCM450_MKFUNC(r2md),
570 	WPCM450_MKFUNC(kbcc),
571 	WPCM450_MKFUNC(clko),
572 	WPCM450_MKFUNC(smi),
573 	WPCM450_MKFUNC(uinc),
574 	WPCM450_MKFUNC(gspi),
575 	WPCM450_MKFUNC(mben),
576 	WPCM450_MKFUNC(xcs2),
577 	WPCM450_MKFUNC(xcs1),
578 	WPCM450_MKFUNC(sdio),
579 	WPCM450_MKFUNC(sspi),
580 	WPCM450_MKFUNC(fi0),
581 	WPCM450_MKFUNC(fi1),
582 	WPCM450_MKFUNC(fi2),
583 	WPCM450_MKFUNC(fi3),
584 	WPCM450_MKFUNC(fi4),
585 	WPCM450_MKFUNC(fi5),
586 	WPCM450_MKFUNC(fi6),
587 	WPCM450_MKFUNC(fi7),
588 	WPCM450_MKFUNC(fi8),
589 	WPCM450_MKFUNC(fi9),
590 	WPCM450_MKFUNC(fi10),
591 	WPCM450_MKFUNC(fi11),
592 	WPCM450_MKFUNC(fi12),
593 	WPCM450_MKFUNC(fi13),
594 	WPCM450_MKFUNC(fi14),
595 	WPCM450_MKFUNC(fi15),
596 	WPCM450_MKFUNC(pwm0),
597 	WPCM450_MKFUNC(pwm1),
598 	WPCM450_MKFUNC(pwm2),
599 	WPCM450_MKFUNC(pwm3),
600 	WPCM450_MKFUNC(pwm4),
601 	WPCM450_MKFUNC(pwm5),
602 	WPCM450_MKFUNC(pwm6),
603 	WPCM450_MKFUNC(pwm7),
604 	WPCM450_MKFUNC(hg0),
605 	WPCM450_MKFUNC(hg1),
606 	WPCM450_MKFUNC(hg2),
607 	WPCM450_MKFUNC(hg3),
608 	WPCM450_MKFUNC(hg4),
609 	WPCM450_MKFUNC(hg5),
610 	WPCM450_MKFUNC(hg6),
611 	WPCM450_MKFUNC(hg7),
612 	WPCM450_MKFUNC(gpio),
613 };
614 
615 #define WPCM450_PINCFG(a, b, c, d, e, f, g) \
616 	[a] = { .fn0 = fn_ ## b, .reg0 = WPCM450_GCR_ ## c, .bit0 = d, \
617 	        .fn1 = fn_ ## e, .reg1 = WPCM450_GCR_ ## f, .bit1 = g }
618 
619 struct wpcm450_pincfg {
620 	int fn0, reg0, bit0;
621 	int fn1, reg1, bit1;
622 };
623 
624 static const struct wpcm450_pincfg pincfg[] = {
625 	/*		PIN	  FUNCTION 1		   FUNCTION 2 */
626 	WPCM450_PINCFG(0,	 none, NONE, 0,		  none, NONE, 0),
627 	WPCM450_PINCFG(1,	 none, NONE, 0,		  none, NONE, 0),
628 	WPCM450_PINCFG(2,	 none, NONE, 0,		  none, NONE, 0),
629 	WPCM450_PINCFG(3,	 none, NONE, 0,		  none, NONE, 0),
630 	WPCM450_PINCFG(4,	 none, NONE, 0,		  none, NONE, 0),
631 	WPCM450_PINCFG(5,	 none, NONE, 0,		  none, NONE, 0),
632 	WPCM450_PINCFG(6,	 none, NONE, 0,		  none, NONE, 0),
633 	WPCM450_PINCFG(7,	 none, NONE, 0,		  sdio, MFSEL1, 30),
634 	WPCM450_PINCFG(8,	 none, NONE, 0,		  none, NONE, 0),
635 	WPCM450_PINCFG(9,	 none, NONE, 0,		  none, NONE, 0),
636 	WPCM450_PINCFG(10,	 none, NONE, 0,		  none, NONE, 0),
637 	WPCM450_PINCFG(11,	 none, NONE, 0,		  none, NONE, 0),
638 	WPCM450_PINCFG(12,	 gspi, MFSEL1, 24,	  sspi, MFSEL1, 31),
639 	WPCM450_PINCFG(13,	 gspi, MFSEL1, 24,	  sspi, MFSEL1, 31),
640 	WPCM450_PINCFG(14,	 gspi, MFSEL1, 24,	  sspi, MFSEL1, 31),
641 	WPCM450_PINCFG(15,	 gspi, MFSEL1, 24,	  sspi, MFSEL1, 31),
642 	WPCM450_PINCFG(16,	 none, NONE, 0,		  pwm6, MFSEL2, 22),
643 	WPCM450_PINCFG(17,	 none, NONE, 0,		  pwm7, MFSEL2, 23),
644 	WPCM450_PINCFG(18,	 none, NONE, 0,		  none, NONE, 0),
645 	WPCM450_PINCFG(19,	 uinc, MFSEL1, 23,	  none, NONE, 0),
646 	WPCM450_PINCFG(20,	  hg0, MFSEL2, 24,	  pwm4, MFSEL2, 20),
647 	WPCM450_PINCFG(21,	  hg1, MFSEL2, 25,	  pwm5, MFSEL2, 21),
648 	WPCM450_PINCFG(22,	  hg2, MFSEL2, 26,	  none, NONE, 0),
649 	WPCM450_PINCFG(23,	  hg3, MFSEL2, 27,	  none, NONE, 0),
650 	WPCM450_PINCFG(24,	  hg4, MFSEL2, 28,	  none, NONE, 0),
651 	WPCM450_PINCFG(25,	  hg5, MFSEL2, 29,	  none, NONE, 0),
652 	WPCM450_PINCFG(26,	 smb5, MFSEL1, 2,	  none, NONE, 0),
653 	WPCM450_PINCFG(27,	 smb5, MFSEL1, 2,	  none, NONE, 0),
654 	WPCM450_PINCFG(28,	 smb4, MFSEL1, 1,	  none, NONE, 0),
655 	WPCM450_PINCFG(29,	 smb4, MFSEL1, 1,	  none, NONE, 0),
656 	WPCM450_PINCFG(30,	 smb3, MFSEL1, 0,	  none, NONE, 0),
657 	WPCM450_PINCFG(31,	 smb3, MFSEL1, 0,	  none, NONE, 0),
658 
659 	WPCM450_PINCFG(32,	 scs1, MFSEL1, 3,	  none, NONE, 0),
660 	WPCM450_PINCFG(33,	 scs2, MFSEL1, 4,	  none, NONE, 0),
661 	WPCM450_PINCFG(34,	 scs3, MFSEL1, 5,	  none, NONE, 0),
662 	WPCM450_PINCFG(35,	 xcs1, MFSEL1, 29,	  none, NONE, 0),
663 	WPCM450_PINCFG(36,	 xcs2, MFSEL1, 28,	  none, NONE, 0),
664 	WPCM450_PINCFG(37,	 none, NONE, 0,		  none, NONE, 0), /* DVO */
665 	WPCM450_PINCFG(38,	 none, NONE, 0,		  none, NONE, 0), /* DVO */
666 	WPCM450_PINCFG(39,	 none, NONE, 0,		  none, NONE, 0), /* DVO */
667 	WPCM450_PINCFG(40,	 none, NONE, 0,		  none, NONE, 0), /* DVO */
668 	WPCM450_PINCFG(41,	  bsp, MFSEL1, 9,	  none, NONE, 0),
669 	WPCM450_PINCFG(42,	  bsp, MFSEL1, 9,	  none, NONE, 0),
670 	WPCM450_PINCFG(43,	 hsp1, MFSEL1, 10,	  sdio, MFSEL1, 30),
671 	WPCM450_PINCFG(44,	 hsp1, MFSEL1, 10,	  sdio, MFSEL1, 30),
672 	WPCM450_PINCFG(45,	 hsp1, MFSEL1, 10,	  sdio, MFSEL1, 30),
673 	WPCM450_PINCFG(46,	 hsp1, MFSEL1, 10,	  sdio, MFSEL1, 30),
674 	WPCM450_PINCFG(47,	 hsp1, MFSEL1, 10,	  sdio, MFSEL1, 30),
675 	WPCM450_PINCFG(48,	 hsp2, MFSEL1, 11,	  none, NONE, 0),
676 	WPCM450_PINCFG(49,	 hsp2, MFSEL1, 11,	  none, NONE, 0),
677 	WPCM450_PINCFG(50,	 hsp2, MFSEL1, 11,	  none, NONE, 0),
678 	WPCM450_PINCFG(51,	 hsp2, MFSEL1, 11,	  none, NONE, 0),
679 	WPCM450_PINCFG(52,	 hsp2, MFSEL1, 11,	  none, NONE, 0),
680 	WPCM450_PINCFG(53,	 hsp2, MFSEL1, 11,	  none, NONE, 0),
681 	WPCM450_PINCFG(54,	 hsp2, MFSEL1, 11,	  none, NONE, 0),
682 	WPCM450_PINCFG(55,	 hsp2, MFSEL1, 11,	  none, NONE, 0),
683 	WPCM450_PINCFG(56,	r1err, MFSEL1, 12,	  none, NONE, 0),
684 	WPCM450_PINCFG(57,	 r1md, MFSEL1, 13,	  none, NONE, 0),
685 	WPCM450_PINCFG(58,	 r1md, MFSEL1, 13,	  none, NONE, 0),
686 	WPCM450_PINCFG(59,	  hg6, MFSEL2, 30,	  none, NONE, 0),
687 	WPCM450_PINCFG(60,	  hg7, MFSEL2, 31,	  sdio, MFSEL1, 30),
688 	WPCM450_PINCFG(61,	 hsp1, MFSEL1, 10,	  none, NONE, 0),
689 	WPCM450_PINCFG(62,	 hsp1, MFSEL1, 10,	  none, NONE, 0),
690 	WPCM450_PINCFG(63,	 hsp1, MFSEL1, 10,	  none, NONE, 0),
691 
692 	WPCM450_PINCFG(64,	  fi0, MFSEL2, 0,	  none, NONE, 0),
693 	WPCM450_PINCFG(65,	  fi1, MFSEL2, 1,	  none, NONE, 0),
694 	WPCM450_PINCFG(66,	  fi2, MFSEL2, 2,	  none, NONE, 0),
695 	WPCM450_PINCFG(67,	  fi3, MFSEL2, 3,	  none, NONE, 0),
696 	WPCM450_PINCFG(68,	  fi4, MFSEL2, 4,	  none, NONE, 0),
697 	WPCM450_PINCFG(69,	  fi5, MFSEL2, 5,	  none, NONE, 0),
698 	WPCM450_PINCFG(70,	  fi6, MFSEL2, 6,	  none, NONE, 0),
699 	WPCM450_PINCFG(71,	  fi7, MFSEL2, 7,	  none, NONE, 0),
700 	WPCM450_PINCFG(72,	  fi8, MFSEL2, 8,	  none, NONE, 0),
701 	WPCM450_PINCFG(73,	  fi9, MFSEL2, 9,	  none, NONE, 0),
702 	WPCM450_PINCFG(74,	 fi10, MFSEL2, 10,	  none, NONE, 0),
703 	WPCM450_PINCFG(75,	 fi11, MFSEL2, 11,	  none, NONE, 0),
704 	WPCM450_PINCFG(76,	 fi12, MFSEL2, 12,	  none, NONE, 0),
705 	WPCM450_PINCFG(77,	 fi13, MFSEL2, 13,	  none, NONE, 0),
706 	WPCM450_PINCFG(78,	 fi14, MFSEL2, 14,	  none, NONE, 0),
707 	WPCM450_PINCFG(79,	 fi15, MFSEL2, 15,	  none, NONE, 0),
708 	WPCM450_PINCFG(80,	 pwm0, MFSEL2, 16,	  none, NONE, 0),
709 	WPCM450_PINCFG(81,	 pwm1, MFSEL2, 17,	  none, NONE, 0),
710 	WPCM450_PINCFG(82,	 pwm2, MFSEL2, 18,	  none, NONE, 0),
711 	WPCM450_PINCFG(83,	 pwm3, MFSEL2, 19,	  none, NONE, 0),
712 	WPCM450_PINCFG(84,	rmii2, MFSEL1, 14,	  none, NONE, 0),
713 	WPCM450_PINCFG(85,	rmii2, MFSEL1, 14,	  none, NONE, 0),
714 	WPCM450_PINCFG(86,	rmii2, MFSEL1, 14,	  none, NONE, 0),
715 	WPCM450_PINCFG(87,	rmii2, MFSEL1, 14,	  none, NONE, 0),
716 	WPCM450_PINCFG(88,	rmii2, MFSEL1, 14,	  none, NONE, 0),
717 	WPCM450_PINCFG(89,	rmii2, MFSEL1, 14,	  none, NONE, 0),
718 	WPCM450_PINCFG(90,	r2err, MFSEL1, 15,	  none, NONE, 0),
719 	WPCM450_PINCFG(91,	 r2md, MFSEL1, 16,	  none, NONE, 0),
720 	WPCM450_PINCFG(92,	 r2md, MFSEL1, 16,	  none, NONE, 0),
721 	WPCM450_PINCFG(93,	 kbcc, MFSEL1, 17,	  none, NONE, 0),
722 	WPCM450_PINCFG(94,	 kbcc, MFSEL1, 17,	  none, NONE, 0),
723 	WPCM450_PINCFG(95,	 none, NONE, 0,		  none, NONE, 0),
724 
725 	WPCM450_PINCFG(96,	 none, NONE, 0,		  none, NONE, 0),
726 	WPCM450_PINCFG(97,	 none, NONE, 0,		  none, NONE, 0),
727 	WPCM450_PINCFG(98,	 none, NONE, 0,		  none, NONE, 0),
728 	WPCM450_PINCFG(99,	 none, NONE, 0,		  none, NONE, 0),
729 	WPCM450_PINCFG(100,	 none, NONE, 0,		  none, NONE, 0),
730 	WPCM450_PINCFG(101,	 none, NONE, 0,		  none, NONE, 0),
731 	WPCM450_PINCFG(102,	 none, NONE, 0,		  none, NONE, 0),
732 	WPCM450_PINCFG(103,	 none, NONE, 0,		  none, NONE, 0),
733 	WPCM450_PINCFG(104,	 none, NONE, 0,		  none, NONE, 0),
734 	WPCM450_PINCFG(105,	 none, NONE, 0,		  none, NONE, 0),
735 	WPCM450_PINCFG(106,	 none, NONE, 0,		  none, NONE, 0),
736 	WPCM450_PINCFG(107,	 none, NONE, 0,		  none, NONE, 0),
737 	WPCM450_PINCFG(108,	 none, NONE, 0,		  none, NONE, 0), /* DVO */
738 	WPCM450_PINCFG(109,	 none, NONE, 0,		  none, NONE, 0), /* DVO */
739 	WPCM450_PINCFG(110,	 none, NONE, 0,		  none, NONE, 0), /* DVO */
740 	WPCM450_PINCFG(111,	 none, NONE, 0,		  none, NONE, 0), /* DVO */
741 	WPCM450_PINCFG(112,	 none, NONE, 0,		  none, NONE, 0), /* DVO */
742 	WPCM450_PINCFG(113,	 none, NONE, 0,		  none, NONE, 0), /* DVO */
743 	WPCM450_PINCFG(114,	 smb0, MFSEL1, 6,	  none, NONE, 0),
744 	WPCM450_PINCFG(115,	 smb0, MFSEL1, 6,	  none, NONE, 0),
745 	WPCM450_PINCFG(116,	 smb1, MFSEL1, 7,	  none, NONE, 0),
746 	WPCM450_PINCFG(117,	 smb1, MFSEL1, 7,	  none, NONE, 0),
747 	WPCM450_PINCFG(118,	 smb2, MFSEL1, 8,	  none, NONE, 0),
748 	WPCM450_PINCFG(119,	 smb2, MFSEL1, 8,	  none, NONE, 0),
749 	WPCM450_PINCFG(120,	 none, NONE, 0,		  none, NONE, 0), /* DVO */
750 	WPCM450_PINCFG(121,	 none, NONE, 0,		  none, NONE, 0), /* DVO */
751 	WPCM450_PINCFG(122,	 none, NONE, 0,		  none, NONE, 0), /* DVO */
752 	WPCM450_PINCFG(123,	 none, NONE, 0,		  none, NONE, 0), /* DVO */
753 	WPCM450_PINCFG(124,	 none, NONE, 0,		  none, NONE, 0), /* DVO */
754 	WPCM450_PINCFG(125,	 none, NONE, 0,		  none, NONE, 0), /* DVO */
755 	WPCM450_PINCFG(126,	 none, NONE, 0,		  none, NONE, 0), /* DVO */
756 	WPCM450_PINCFG(127,	 none, NONE, 0,		  none, NONE, 0), /* DVO */
757 };
758 
759 #define WPCM450_PIN(n)		PINCTRL_PIN(n, "gpio" #n)
760 
761 static const struct pinctrl_pin_desc wpcm450_pins[] = {
762 	WPCM450_PIN(0),   WPCM450_PIN(1),   WPCM450_PIN(2),   WPCM450_PIN(3),
763 	WPCM450_PIN(4),   WPCM450_PIN(5),   WPCM450_PIN(6),   WPCM450_PIN(7),
764 	WPCM450_PIN(8),   WPCM450_PIN(9),   WPCM450_PIN(10),  WPCM450_PIN(11),
765 	WPCM450_PIN(12),  WPCM450_PIN(13),  WPCM450_PIN(14),  WPCM450_PIN(15),
766 	WPCM450_PIN(16),  WPCM450_PIN(17),  WPCM450_PIN(18),  WPCM450_PIN(19),
767 	WPCM450_PIN(20),  WPCM450_PIN(21),  WPCM450_PIN(22),  WPCM450_PIN(23),
768 	WPCM450_PIN(24),  WPCM450_PIN(25),  WPCM450_PIN(26),  WPCM450_PIN(27),
769 	WPCM450_PIN(28),  WPCM450_PIN(29),  WPCM450_PIN(30),  WPCM450_PIN(31),
770 	WPCM450_PIN(32),  WPCM450_PIN(33),  WPCM450_PIN(34),  WPCM450_PIN(35),
771 	WPCM450_PIN(36),  WPCM450_PIN(37),  WPCM450_PIN(38),  WPCM450_PIN(39),
772 	WPCM450_PIN(40),  WPCM450_PIN(41),  WPCM450_PIN(42),  WPCM450_PIN(43),
773 	WPCM450_PIN(44),  WPCM450_PIN(45),  WPCM450_PIN(46),  WPCM450_PIN(47),
774 	WPCM450_PIN(48),  WPCM450_PIN(49),  WPCM450_PIN(50),  WPCM450_PIN(51),
775 	WPCM450_PIN(52),  WPCM450_PIN(53),  WPCM450_PIN(54),  WPCM450_PIN(55),
776 	WPCM450_PIN(56),  WPCM450_PIN(57),  WPCM450_PIN(58),  WPCM450_PIN(59),
777 	WPCM450_PIN(60),  WPCM450_PIN(61),  WPCM450_PIN(62),  WPCM450_PIN(63),
778 	WPCM450_PIN(64),  WPCM450_PIN(65),  WPCM450_PIN(66),  WPCM450_PIN(67),
779 	WPCM450_PIN(68),  WPCM450_PIN(69),  WPCM450_PIN(70),  WPCM450_PIN(71),
780 	WPCM450_PIN(72),  WPCM450_PIN(73),  WPCM450_PIN(74),  WPCM450_PIN(75),
781 	WPCM450_PIN(76),  WPCM450_PIN(77),  WPCM450_PIN(78),  WPCM450_PIN(79),
782 	WPCM450_PIN(80),  WPCM450_PIN(81),  WPCM450_PIN(82),  WPCM450_PIN(83),
783 	WPCM450_PIN(84),  WPCM450_PIN(85),  WPCM450_PIN(86),  WPCM450_PIN(87),
784 	WPCM450_PIN(88),  WPCM450_PIN(89),  WPCM450_PIN(90),  WPCM450_PIN(91),
785 	WPCM450_PIN(92),  WPCM450_PIN(93),  WPCM450_PIN(94),  WPCM450_PIN(95),
786 	WPCM450_PIN(96),  WPCM450_PIN(97),  WPCM450_PIN(98),  WPCM450_PIN(99),
787 	WPCM450_PIN(100), WPCM450_PIN(101), WPCM450_PIN(102), WPCM450_PIN(103),
788 	WPCM450_PIN(104), WPCM450_PIN(105), WPCM450_PIN(106), WPCM450_PIN(107),
789 	WPCM450_PIN(108), WPCM450_PIN(109), WPCM450_PIN(110), WPCM450_PIN(111),
790 	WPCM450_PIN(112), WPCM450_PIN(113), WPCM450_PIN(114), WPCM450_PIN(115),
791 	WPCM450_PIN(116), WPCM450_PIN(117), WPCM450_PIN(118), WPCM450_PIN(119),
792 	WPCM450_PIN(120), WPCM450_PIN(121), WPCM450_PIN(122), WPCM450_PIN(123),
793 	WPCM450_PIN(124), WPCM450_PIN(125), WPCM450_PIN(126), WPCM450_PIN(127),
794 };
795 
796 /* Enable mode in pin group */
797 static void wpcm450_setfunc(struct regmap *gcr_regmap, const unsigned int *pin,
798 			    int npins, int func)
799 {
800 	const struct wpcm450_pincfg *cfg;
801 	int i;
802 
803 	for (i = 0; i < npins; i++) {
804 		cfg = &pincfg[pin[i]];
805 		if (func == fn_gpio || cfg->fn0 == func || cfg->fn1 == func) {
806 			if (cfg->reg0)
807 				regmap_update_bits(gcr_regmap, cfg->reg0,
808 						   BIT(cfg->bit0),
809 						   (cfg->fn0 == func) ?  BIT(cfg->bit0) : 0);
810 			if (cfg->reg1)
811 				regmap_update_bits(gcr_regmap, cfg->reg1,
812 						   BIT(cfg->bit1),
813 						   (cfg->fn1 == func) ?  BIT(cfg->bit1) : 0);
814 		}
815 	}
816 }
817 
818 static int wpcm450_get_groups_count(struct pinctrl_dev *pctldev)
819 {
820 	return ARRAY_SIZE(wpcm450_groups);
821 }
822 
823 static const char *wpcm450_get_group_name(struct pinctrl_dev *pctldev,
824 					  unsigned int selector)
825 {
826 	return wpcm450_groups[selector].name;
827 }
828 
829 static int wpcm450_get_group_pins(struct pinctrl_dev *pctldev,
830 				  unsigned int selector,
831 				  const unsigned int **pins,
832 				  unsigned int *npins)
833 {
834 	*npins = wpcm450_groups[selector].num_pins;
835 	*pins  = wpcm450_groups[selector].pins;
836 
837 	return 0;
838 }
839 
840 static int wpcm450_dt_node_to_map(struct pinctrl_dev *pctldev,
841 				  struct device_node *np_config,
842 				  struct pinctrl_map **map,
843 				  u32 *num_maps)
844 {
845 	return pinconf_generic_dt_node_to_map(pctldev, np_config,
846 					      map, num_maps,
847 					      PIN_MAP_TYPE_INVALID);
848 }
849 
850 static void wpcm450_dt_free_map(struct pinctrl_dev *pctldev,
851 				struct pinctrl_map *map, u32 num_maps)
852 {
853 	kfree(map);
854 }
855 
856 static const struct pinctrl_ops wpcm450_pinctrl_ops = {
857 	.get_groups_count = wpcm450_get_groups_count,
858 	.get_group_name = wpcm450_get_group_name,
859 	.get_group_pins = wpcm450_get_group_pins,
860 	.dt_node_to_map = wpcm450_dt_node_to_map,
861 	.dt_free_map = wpcm450_dt_free_map,
862 };
863 
864 static int wpcm450_get_functions_count(struct pinctrl_dev *pctldev)
865 {
866 	return ARRAY_SIZE(wpcm450_funcs);
867 }
868 
869 static const char *wpcm450_get_function_name(struct pinctrl_dev *pctldev,
870 					     unsigned int function)
871 {
872 	return wpcm450_funcs[function].name;
873 }
874 
875 static int wpcm450_get_function_groups(struct pinctrl_dev *pctldev,
876 				       unsigned int function,
877 				       const char * const **groups,
878 				       unsigned int * const ngroups)
879 {
880 	*ngroups = wpcm450_funcs[function].ngroups;
881 	*groups	 = wpcm450_funcs[function].groups;
882 
883 	return 0;
884 }
885 
886 static int wpcm450_pinmux_set_mux(struct pinctrl_dev *pctldev,
887 				  unsigned int function,
888 				  unsigned int group)
889 {
890 	struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
891 
892 	wpcm450_setfunc(pctrl->gcr_regmap, wpcm450_groups[group].pins,
893 			wpcm450_groups[group].num_pins, function);
894 
895 	return 0;
896 }
897 
898 static const struct pinmux_ops wpcm450_pinmux_ops = {
899 	.get_functions_count = wpcm450_get_functions_count,
900 	.get_function_name = wpcm450_get_function_name,
901 	.get_function_groups = wpcm450_get_function_groups,
902 	.set_mux = wpcm450_pinmux_set_mux,
903 };
904 
905 static int debounce_bitnum(int gpio)
906 {
907 	if (gpio >= 0 && gpio < 16)
908 		return gpio;
909 	return -EINVAL;
910 }
911 
912 static int wpcm450_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
913 			      unsigned long *config)
914 {
915 	struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
916 	enum pin_config_param param = pinconf_to_config_param(*config);
917 	unsigned long flags;
918 	int bit;
919 	u32 reg;
920 
921 	switch (param) {
922 	case PIN_CONFIG_INPUT_DEBOUNCE:
923 		bit = debounce_bitnum(pin);
924 		if (bit < 0)
925 			return bit;
926 
927 		raw_spin_lock_irqsave(&pctrl->lock, flags);
928 		reg = ioread32(pctrl->gpio_base + WPCM450_GPEVDBNC);
929 		raw_spin_unlock_irqrestore(&pctrl->lock, flags);
930 
931 		*config = pinconf_to_config_packed(param, !!(reg & BIT(bit)));
932 		return 0;
933 	default:
934 		return -ENOTSUPP;
935 	}
936 }
937 
938 static int wpcm450_config_set_one(struct wpcm450_pinctrl *pctrl,
939 				  unsigned int pin, unsigned long config)
940 {
941 	enum pin_config_param param = pinconf_to_config_param(config);
942 	unsigned long flags;
943 	unsigned long reg;
944 	int bit;
945 	int arg;
946 
947 	switch (param) {
948 	case PIN_CONFIG_INPUT_DEBOUNCE:
949 		bit = debounce_bitnum(pin);
950 		if (bit < 0)
951 			return bit;
952 
953 		arg = pinconf_to_config_argument(config);
954 
955 		raw_spin_lock_irqsave(&pctrl->lock, flags);
956 		reg = ioread32(pctrl->gpio_base + WPCM450_GPEVDBNC);
957 		__assign_bit(bit, &reg, arg);
958 		iowrite32(reg, pctrl->gpio_base + WPCM450_GPEVDBNC);
959 		raw_spin_unlock_irqrestore(&pctrl->lock, flags);
960 		return 0;
961 	default:
962 		return -ENOTSUPP;
963 	}
964 }
965 
966 static int wpcm450_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
967 			      unsigned long *configs, unsigned int num_configs)
968 {
969 	struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
970 	int ret;
971 
972 	while (num_configs--) {
973 		ret = wpcm450_config_set_one(pctrl, pin, *configs++);
974 		if (ret)
975 			return ret;
976 	}
977 
978 	return 0;
979 }
980 
981 static const struct pinconf_ops wpcm450_pinconf_ops = {
982 	.is_generic = true,
983 	.pin_config_get = wpcm450_config_get,
984 	.pin_config_set = wpcm450_config_set,
985 };
986 
987 static struct pinctrl_desc wpcm450_pinctrl_desc = {
988 	.name = "wpcm450-pinctrl",
989 	.pins = wpcm450_pins,
990 	.npins = ARRAY_SIZE(wpcm450_pins),
991 	.pctlops = &wpcm450_pinctrl_ops,
992 	.pmxops = &wpcm450_pinmux_ops,
993 	.confops = &wpcm450_pinconf_ops,
994 	.owner = THIS_MODULE,
995 };
996 
997 static int wpcm450_gpio_set_config(struct gpio_chip *chip,
998 				   unsigned int offset, unsigned long config)
999 {
1000 	struct wpcm450_gpio *gpio = gpiochip_get_data(chip);
1001 
1002 	return wpcm450_config_set_one(gpio->pctrl, offset, config);
1003 }
1004 
1005 static int wpcm450_gpio_add_pin_ranges(struct gpio_chip *chip)
1006 {
1007 	struct wpcm450_gpio *gpio = gpiochip_get_data(chip);
1008 	const struct wpcm450_bank *bank = gpio->bank;
1009 
1010 	return gpiochip_add_pin_range(&gpio->gc, dev_name(gpio->pctrl->dev),
1011 				      0, bank->base, bank->length);
1012 }
1013 
1014 static int wpcm450_gpio_register(struct platform_device *pdev,
1015 				 struct wpcm450_pinctrl *pctrl)
1016 {
1017 	struct device *dev = &pdev->dev;
1018 	struct fwnode_handle *child;
1019 	int ret;
1020 
1021 	pctrl->gpio_base = devm_platform_ioremap_resource(pdev, 0);
1022 	if (IS_ERR(pctrl->gpio_base))
1023 		return dev_err_probe(dev, PTR_ERR(pctrl->gpio_base),
1024 				     "Resource fail for GPIO controller\n");
1025 
1026 	device_for_each_child_node(dev, child)  {
1027 		void __iomem *dat = NULL;
1028 		void __iomem *set = NULL;
1029 		void __iomem *dirout = NULL;
1030 		unsigned long flags = 0;
1031 		const struct wpcm450_bank *bank;
1032 		struct wpcm450_gpio *gpio;
1033 		struct gpio_irq_chip *girq;
1034 		u32 reg;
1035 		int i;
1036 
1037 		if (!fwnode_property_read_bool(child, "gpio-controller"))
1038 			continue;
1039 
1040 		ret = fwnode_property_read_u32(child, "reg", &reg);
1041 		if (ret < 0)
1042 			return ret;
1043 
1044 		gpio = &pctrl->gpio_bank[reg];
1045 		gpio->pctrl = pctrl;
1046 
1047 		if (reg >= WPCM450_NUM_BANKS)
1048 			return dev_err_probe(dev, -EINVAL,
1049 					     "GPIO index %d out of range!\n", reg);
1050 
1051 		bank = &wpcm450_banks[reg];
1052 		gpio->bank = bank;
1053 
1054 		dat = pctrl->gpio_base + bank->datain;
1055 		if (bank->dataout) {
1056 			set = pctrl->gpio_base + bank->dataout;
1057 			dirout = pctrl->gpio_base + bank->cfg0;
1058 		} else {
1059 			flags = BGPIOF_NO_OUTPUT;
1060 		}
1061 		ret = bgpio_init(&gpio->gc, dev, 4,
1062 				 dat, set, NULL, dirout, NULL, flags);
1063 		if (ret < 0)
1064 			return dev_err_probe(dev, ret, "GPIO initialization failed\n");
1065 
1066 		gpio->gc.ngpio = bank->length;
1067 		gpio->gc.set_config = wpcm450_gpio_set_config;
1068 		gpio->gc.fwnode = child;
1069 		gpio->gc.add_pin_ranges = wpcm450_gpio_add_pin_ranges;
1070 
1071 		gpio->irqc = wpcm450_gpio_irqchip;
1072 		girq = &gpio->gc.irq;
1073 		girq->chip = &gpio->irqc;
1074 		girq->parent_handler = wpcm450_gpio_irqhandler;
1075 		girq->parents = devm_kcalloc(dev, WPCM450_NUM_GPIO_IRQS,
1076 					     sizeof(*girq->parents), GFP_KERNEL);
1077 		if (!girq->parents)
1078 			return -ENOMEM;
1079 		girq->default_type = IRQ_TYPE_NONE;
1080 		girq->handler = handle_bad_irq;
1081 
1082 		girq->num_parents = 0;
1083 		for (i = 0; i < WPCM450_NUM_GPIO_IRQS; i++) {
1084 			int irq;
1085 
1086 			irq = fwnode_irq_get(child, i);
1087 			if (irq < 0)
1088 				break;
1089 			if (!irq)
1090 				continue;
1091 
1092 			girq->parents[i] = irq;
1093 			girq->num_parents++;
1094 		}
1095 
1096 		ret = devm_gpiochip_add_data(dev, &gpio->gc, gpio);
1097 		if (ret)
1098 			return dev_err_probe(dev, ret, "Failed to add GPIO chip\n");
1099 	}
1100 
1101 	return 0;
1102 }
1103 
1104 static int wpcm450_pinctrl_probe(struct platform_device *pdev)
1105 {
1106 	struct device *dev = &pdev->dev;
1107 	struct wpcm450_pinctrl *pctrl;
1108 	int ret;
1109 
1110 	pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
1111 	if (!pctrl)
1112 		return -ENOMEM;
1113 
1114 	pctrl->dev = &pdev->dev;
1115 	raw_spin_lock_init(&pctrl->lock);
1116 	dev_set_drvdata(dev, pctrl);
1117 
1118 	pctrl->gcr_regmap =
1119 		syscon_regmap_lookup_by_compatible("nuvoton,wpcm450-gcr");
1120 	if (IS_ERR(pctrl->gcr_regmap))
1121 		return dev_err_probe(dev, PTR_ERR(pctrl->gcr_regmap),
1122 				     "Failed to find nuvoton,wpcm450-gcr\n");
1123 
1124 	pctrl->pctldev = devm_pinctrl_register(dev,
1125 					       &wpcm450_pinctrl_desc, pctrl);
1126 	if (IS_ERR(pctrl->pctldev))
1127 		return dev_err_probe(dev, PTR_ERR(pctrl->pctldev),
1128 				     "Failed to register pinctrl device\n");
1129 
1130 	ret = wpcm450_gpio_register(pdev, pctrl);
1131 	if (ret < 0)
1132 		return ret;
1133 
1134 	return 0;
1135 }
1136 
1137 static const struct of_device_id wpcm450_pinctrl_match[] = {
1138 	{ .compatible = "nuvoton,wpcm450-pinctrl" },
1139 	{ }
1140 };
1141 MODULE_DEVICE_TABLE(of, wpcm450_pinctrl_match);
1142 
1143 static struct platform_driver wpcm450_pinctrl_driver = {
1144 	.probe = wpcm450_pinctrl_probe,
1145 	.driver = {
1146 		.name = "wpcm450-pinctrl",
1147 		.of_match_table = wpcm450_pinctrl_match,
1148 	},
1149 };
1150 module_platform_driver(wpcm450_pinctrl_driver);
1151 
1152 MODULE_LICENSE("GPL v2");
1153 MODULE_AUTHOR("Jonathan Neuschäfer <j.neuschaefer@gmx.net>");
1154 MODULE_DESCRIPTION("Nuvoton WPCM450 Pinctrl and GPIO driver");
1155