1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2016-2018 Nuvoton Technology corporation.
3 // Copyright (c) 2016, Dell Inc
4
5 #include <linux/device.h>
6 #include <linux/gpio/driver.h>
7 #include <linux/interrupt.h>
8 #include <linux/irq.h>
9 #include <linux/mfd/syscon.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/of_address.h>
13 #include <linux/of_irq.h>
14 #include <linux/platform_device.h>
15 #include <linux/property.h>
16 #include <linux/regmap.h>
17 #include <linux/seq_file.h>
18
19 #include <linux/pinctrl/consumer.h>
20 #include <linux/pinctrl/machine.h>
21 #include <linux/pinctrl/pinconf-generic.h>
22 #include <linux/pinctrl/pinconf.h>
23 #include <linux/pinctrl/pinctrl.h>
24 #include <linux/pinctrl/pinmux.h>
25
26 /* GCR registers */
27 #define NPCM7XX_GCR_PDID 0x00
28 #define NPCM7XX_GCR_MFSEL1 0x0C
29 #define NPCM7XX_GCR_MFSEL2 0x10
30 #define NPCM7XX_GCR_MFSEL3 0x64
31 #define NPCM7XX_GCR_MFSEL4 0xb0
32 #define NPCM7XX_GCR_CPCTL 0xD0
33 #define NPCM7XX_GCR_CP2BST 0xD4
34 #define NPCM7XX_GCR_B2CPNT 0xD8
35 #define NPCM7XX_GCR_I2CSEGSEL 0xE0
36 #define NPCM7XX_GCR_I2CSEGCTL 0xE4
37 #define NPCM7XX_GCR_SRCNT 0x68
38 #define NPCM7XX_GCR_FLOCKR1 0x74
39 #define NPCM7XX_GCR_DSCNT 0x78
40
41 #define SRCNT_ESPI BIT(3)
42
43 /* GPIO registers */
44 #define NPCM7XX_GP_N_TLOCK1 0x00
45 #define NPCM7XX_GP_N_DIN 0x04 /* Data IN */
46 #define NPCM7XX_GP_N_POL 0x08 /* Polarity */
47 #define NPCM7XX_GP_N_DOUT 0x0c /* Data OUT */
48 #define NPCM7XX_GP_N_OE 0x10 /* Output Enable */
49 #define NPCM7XX_GP_N_OTYP 0x14
50 #define NPCM7XX_GP_N_MP 0x18
51 #define NPCM7XX_GP_N_PU 0x1c /* Pull-up */
52 #define NPCM7XX_GP_N_PD 0x20 /* Pull-down */
53 #define NPCM7XX_GP_N_DBNC 0x24 /* Debounce */
54 #define NPCM7XX_GP_N_EVTYP 0x28 /* Event Type */
55 #define NPCM7XX_GP_N_EVBE 0x2c /* Event Both Edge */
56 #define NPCM7XX_GP_N_OBL0 0x30
57 #define NPCM7XX_GP_N_OBL1 0x34
58 #define NPCM7XX_GP_N_OBL2 0x38
59 #define NPCM7XX_GP_N_OBL3 0x3c
60 #define NPCM7XX_GP_N_EVEN 0x40 /* Event Enable */
61 #define NPCM7XX_GP_N_EVENS 0x44 /* Event Set (enable) */
62 #define NPCM7XX_GP_N_EVENC 0x48 /* Event Clear (disable) */
63 #define NPCM7XX_GP_N_EVST 0x4c /* Event Status */
64 #define NPCM7XX_GP_N_SPLCK 0x50
65 #define NPCM7XX_GP_N_MPLCK 0x54
66 #define NPCM7XX_GP_N_IEM 0x58 /* Input Enable */
67 #define NPCM7XX_GP_N_OSRC 0x5c
68 #define NPCM7XX_GP_N_ODSC 0x60
69 #define NPCM7XX_GP_N_DOS 0x68 /* Data OUT Set */
70 #define NPCM7XX_GP_N_DOC 0x6c /* Data OUT Clear */
71 #define NPCM7XX_GP_N_OES 0x70 /* Output Enable Set */
72 #define NPCM7XX_GP_N_OEC 0x74 /* Output Enable Clear */
73 #define NPCM7XX_GP_N_TLOCK2 0x7c
74
75 #define NPCM7XX_GPIO_PER_BANK 32
76 #define NPCM7XX_GPIO_BANK_NUM 8
77 #define NPCM7XX_GCR_NONE 0
78
79 /* Structure for register banks */
80 struct npcm7xx_gpio {
81 void __iomem *base;
82 struct gpio_chip gc;
83 int irqbase;
84 int irq;
85 u32 pinctrl_id;
86 int (*direction_input)(struct gpio_chip *chip, unsigned int offset);
87 int (*direction_output)(struct gpio_chip *chip, unsigned int offset,
88 int value);
89 int (*request)(struct gpio_chip *chip, unsigned int offset);
90 void (*free)(struct gpio_chip *chip, unsigned int offset);
91 };
92
93 struct npcm7xx_pinctrl {
94 struct pinctrl_dev *pctldev;
95 struct device *dev;
96 struct npcm7xx_gpio gpio_bank[NPCM7XX_GPIO_BANK_NUM];
97 struct irq_domain *domain;
98 struct regmap *gcr_regmap;
99 void __iomem *regs;
100 u32 bank_num;
101 };
102
103 /* GPIO handling in the pinctrl driver */
npcm_gpio_set(struct gpio_chip * gc,void __iomem * reg,unsigned int pinmask)104 static void npcm_gpio_set(struct gpio_chip *gc, void __iomem *reg,
105 unsigned int pinmask)
106 {
107 unsigned long flags;
108 unsigned long val;
109
110 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
111
112 val = ioread32(reg) | pinmask;
113 iowrite32(val, reg);
114
115 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
116 }
117
npcm_gpio_clr(struct gpio_chip * gc,void __iomem * reg,unsigned int pinmask)118 static void npcm_gpio_clr(struct gpio_chip *gc, void __iomem *reg,
119 unsigned int pinmask)
120 {
121 unsigned long flags;
122 unsigned long val;
123
124 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
125
126 val = ioread32(reg) & ~pinmask;
127 iowrite32(val, reg);
128
129 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
130 }
131
npcmgpio_dbg_show(struct seq_file * s,struct gpio_chip * chip)132 static void npcmgpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
133 {
134 struct npcm7xx_gpio *bank = gpiochip_get_data(chip);
135
136 seq_printf(s, "-- module %d [gpio%d - %d]\n",
137 bank->gc.base / bank->gc.ngpio,
138 bank->gc.base,
139 bank->gc.base + bank->gc.ngpio);
140 seq_printf(s, "DIN :%.8x DOUT:%.8x IE :%.8x OE :%.8x\n",
141 ioread32(bank->base + NPCM7XX_GP_N_DIN),
142 ioread32(bank->base + NPCM7XX_GP_N_DOUT),
143 ioread32(bank->base + NPCM7XX_GP_N_IEM),
144 ioread32(bank->base + NPCM7XX_GP_N_OE));
145 seq_printf(s, "PU :%.8x PD :%.8x DB :%.8x POL :%.8x\n",
146 ioread32(bank->base + NPCM7XX_GP_N_PU),
147 ioread32(bank->base + NPCM7XX_GP_N_PD),
148 ioread32(bank->base + NPCM7XX_GP_N_DBNC),
149 ioread32(bank->base + NPCM7XX_GP_N_POL));
150 seq_printf(s, "ETYP:%.8x EVBE:%.8x EVEN:%.8x EVST:%.8x\n",
151 ioread32(bank->base + NPCM7XX_GP_N_EVTYP),
152 ioread32(bank->base + NPCM7XX_GP_N_EVBE),
153 ioread32(bank->base + NPCM7XX_GP_N_EVEN),
154 ioread32(bank->base + NPCM7XX_GP_N_EVST));
155 seq_printf(s, "OTYP:%.8x OSRC:%.8x ODSC:%.8x\n",
156 ioread32(bank->base + NPCM7XX_GP_N_OTYP),
157 ioread32(bank->base + NPCM7XX_GP_N_OSRC),
158 ioread32(bank->base + NPCM7XX_GP_N_ODSC));
159 seq_printf(s, "OBL0:%.8x OBL1:%.8x OBL2:%.8x OBL3:%.8x\n",
160 ioread32(bank->base + NPCM7XX_GP_N_OBL0),
161 ioread32(bank->base + NPCM7XX_GP_N_OBL1),
162 ioread32(bank->base + NPCM7XX_GP_N_OBL2),
163 ioread32(bank->base + NPCM7XX_GP_N_OBL3));
164 seq_printf(s, "SLCK:%.8x MLCK:%.8x\n",
165 ioread32(bank->base + NPCM7XX_GP_N_SPLCK),
166 ioread32(bank->base + NPCM7XX_GP_N_MPLCK));
167 }
168
npcmgpio_direction_input(struct gpio_chip * chip,unsigned int offset)169 static int npcmgpio_direction_input(struct gpio_chip *chip, unsigned int offset)
170 {
171 struct npcm7xx_gpio *bank = gpiochip_get_data(chip);
172 int ret;
173
174 ret = pinctrl_gpio_direction_input(offset + chip->base);
175 if (ret)
176 return ret;
177
178 return bank->direction_input(chip, offset);
179 }
180
181 /* Set GPIO to Output with initial value */
npcmgpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)182 static int npcmgpio_direction_output(struct gpio_chip *chip,
183 unsigned int offset, int value)
184 {
185 struct npcm7xx_gpio *bank = gpiochip_get_data(chip);
186 int ret;
187
188 dev_dbg(chip->parent, "gpio_direction_output: offset%d = %x\n", offset,
189 value);
190
191 ret = pinctrl_gpio_direction_output(offset + chip->base);
192 if (ret)
193 return ret;
194
195 return bank->direction_output(chip, offset, value);
196 }
197
npcmgpio_gpio_request(struct gpio_chip * chip,unsigned int offset)198 static int npcmgpio_gpio_request(struct gpio_chip *chip, unsigned int offset)
199 {
200 struct npcm7xx_gpio *bank = gpiochip_get_data(chip);
201 int ret;
202
203 dev_dbg(chip->parent, "gpio_request: offset%d\n", offset);
204 ret = pinctrl_gpio_request(offset + chip->base);
205 if (ret)
206 return ret;
207
208 return bank->request(chip, offset);
209 }
210
npcmgpio_gpio_free(struct gpio_chip * chip,unsigned int offset)211 static void npcmgpio_gpio_free(struct gpio_chip *chip, unsigned int offset)
212 {
213 dev_dbg(chip->parent, "gpio_free: offset%d\n", offset);
214 pinctrl_gpio_free(offset + chip->base);
215 }
216
npcmgpio_irq_handler(struct irq_desc * desc)217 static void npcmgpio_irq_handler(struct irq_desc *desc)
218 {
219 struct gpio_chip *gc;
220 struct irq_chip *chip;
221 struct npcm7xx_gpio *bank;
222 unsigned long sts, en, bit;
223
224 gc = irq_desc_get_handler_data(desc);
225 bank = gpiochip_get_data(gc);
226 chip = irq_desc_get_chip(desc);
227
228 chained_irq_enter(chip, desc);
229 sts = ioread32(bank->base + NPCM7XX_GP_N_EVST);
230 en = ioread32(bank->base + NPCM7XX_GP_N_EVEN);
231 dev_dbg(bank->gc.parent, "==> got irq sts %.8lx %.8lx\n", sts,
232 en);
233
234 sts &= en;
235 for_each_set_bit(bit, &sts, NPCM7XX_GPIO_PER_BANK)
236 generic_handle_domain_irq(gc->irq.domain, bit);
237 chained_irq_exit(chip, desc);
238 }
239
npcmgpio_set_irq_type(struct irq_data * d,unsigned int type)240 static int npcmgpio_set_irq_type(struct irq_data *d, unsigned int type)
241 {
242 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
243 struct npcm7xx_gpio *bank = gpiochip_get_data(gc);
244 unsigned int gpio = BIT(irqd_to_hwirq(d));
245
246 dev_dbg(bank->gc.parent, "setirqtype: %u.%u = %u\n", gpio,
247 d->irq, type);
248 switch (type) {
249 case IRQ_TYPE_EDGE_RISING:
250 dev_dbg(bank->gc.parent, "edge.rising\n");
251 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio);
252 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);
253 break;
254 case IRQ_TYPE_EDGE_FALLING:
255 dev_dbg(bank->gc.parent, "edge.falling\n");
256 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio);
257 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);
258 break;
259 case IRQ_TYPE_EDGE_BOTH:
260 dev_dbg(bank->gc.parent, "edge.both\n");
261 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio);
262 break;
263 case IRQ_TYPE_LEVEL_LOW:
264 dev_dbg(bank->gc.parent, "level.low\n");
265 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);
266 break;
267 case IRQ_TYPE_LEVEL_HIGH:
268 dev_dbg(bank->gc.parent, "level.high\n");
269 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);
270 break;
271 default:
272 dev_dbg(bank->gc.parent, "invalid irq type\n");
273 return -EINVAL;
274 }
275
276 if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
277 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio);
278 irq_set_handler_locked(d, handle_level_irq);
279 } else if (type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_EDGE_RISING
280 | IRQ_TYPE_EDGE_FALLING)) {
281 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio);
282 irq_set_handler_locked(d, handle_edge_irq);
283 }
284
285 return 0;
286 }
287
npcmgpio_irq_ack(struct irq_data * d)288 static void npcmgpio_irq_ack(struct irq_data *d)
289 {
290 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
291 struct npcm7xx_gpio *bank = gpiochip_get_data(gc);
292 unsigned int gpio = irqd_to_hwirq(d);
293
294 dev_dbg(bank->gc.parent, "irq_ack: %u.%u\n", gpio, d->irq);
295 iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVST);
296 }
297
298 /* Disable GPIO interrupt */
npcmgpio_irq_mask(struct irq_data * d)299 static void npcmgpio_irq_mask(struct irq_data *d)
300 {
301 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
302 struct npcm7xx_gpio *bank = gpiochip_get_data(gc);
303 unsigned int gpio = irqd_to_hwirq(d);
304
305 /* Clear events */
306 dev_dbg(bank->gc.parent, "irq_mask: %u.%u\n", gpio, d->irq);
307 iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENC);
308 gpiochip_disable_irq(gc, gpio);
309 }
310
311 /* Enable GPIO interrupt */
npcmgpio_irq_unmask(struct irq_data * d)312 static void npcmgpio_irq_unmask(struct irq_data *d)
313 {
314 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
315 struct npcm7xx_gpio *bank = gpiochip_get_data(gc);
316 unsigned int gpio = irqd_to_hwirq(d);
317
318 /* Enable events */
319 gpiochip_enable_irq(gc, gpio);
320 dev_dbg(bank->gc.parent, "irq_unmask: %u.%u\n", gpio, d->irq);
321 iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENS);
322 }
323
npcmgpio_irq_startup(struct irq_data * d)324 static unsigned int npcmgpio_irq_startup(struct irq_data *d)
325 {
326 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
327 unsigned int gpio = irqd_to_hwirq(d);
328
329 /* active-high, input, clear interrupt, enable interrupt */
330 dev_dbg(gc->parent, "startup: %u.%u\n", gpio, d->irq);
331 npcmgpio_direction_input(gc, gpio);
332 npcmgpio_irq_ack(d);
333 npcmgpio_irq_unmask(d);
334
335 return 0;
336 }
337
338 static const struct irq_chip npcmgpio_irqchip = {
339 .name = "NPCM7XX-GPIO-IRQ",
340 .irq_ack = npcmgpio_irq_ack,
341 .irq_unmask = npcmgpio_irq_unmask,
342 .irq_mask = npcmgpio_irq_mask,
343 .irq_set_type = npcmgpio_set_irq_type,
344 .irq_startup = npcmgpio_irq_startup,
345 .flags = IRQCHIP_IMMUTABLE,
346 GPIOCHIP_IRQ_RESOURCE_HELPERS,
347 };
348
349 /* pinmux handing in the pinctrl driver*/
350 static const int smb0_pins[] = { 115, 114 };
351 static const int smb0b_pins[] = { 195, 194 };
352 static const int smb0c_pins[] = { 202, 196 };
353 static const int smb0d_pins[] = { 198, 199 };
354 static const int smb0den_pins[] = { 197 };
355
356 static const int smb1_pins[] = { 117, 116 };
357 static const int smb1b_pins[] = { 126, 127 };
358 static const int smb1c_pins[] = { 124, 125 };
359 static const int smb1d_pins[] = { 4, 5 };
360
361 static const int smb2_pins[] = { 119, 118 };
362 static const int smb2b_pins[] = { 122, 123 };
363 static const int smb2c_pins[] = { 120, 121 };
364 static const int smb2d_pins[] = { 6, 7 };
365
366 static const int smb3_pins[] = { 30, 31 };
367 static const int smb3b_pins[] = { 39, 40 };
368 static const int smb3c_pins[] = { 37, 38 };
369 static const int smb3d_pins[] = { 59, 60 };
370
371 static const int smb4_pins[] = { 28, 29 };
372 static const int smb4b_pins[] = { 18, 19 };
373 static const int smb4c_pins[] = { 20, 21 };
374 static const int smb4d_pins[] = { 22, 23 };
375 static const int smb4den_pins[] = { 17 };
376
377 static const int smb5_pins[] = { 26, 27 };
378 static const int smb5b_pins[] = { 13, 12 };
379 static const int smb5c_pins[] = { 15, 14 };
380 static const int smb5d_pins[] = { 94, 93 };
381 static const int ga20kbc_pins[] = { 94, 93 };
382
383 static const int smb6_pins[] = { 172, 171 };
384 static const int smb7_pins[] = { 174, 173 };
385 static const int smb8_pins[] = { 129, 128 };
386 static const int smb9_pins[] = { 131, 130 };
387 static const int smb10_pins[] = { 133, 132 };
388 static const int smb11_pins[] = { 135, 134 };
389 static const int smb12_pins[] = { 221, 220 };
390 static const int smb13_pins[] = { 223, 222 };
391 static const int smb14_pins[] = { 22, 23 };
392 static const int smb15_pins[] = { 20, 21 };
393
394 static const int fanin0_pins[] = { 64 };
395 static const int fanin1_pins[] = { 65 };
396 static const int fanin2_pins[] = { 66 };
397 static const int fanin3_pins[] = { 67 };
398 static const int fanin4_pins[] = { 68 };
399 static const int fanin5_pins[] = { 69 };
400 static const int fanin6_pins[] = { 70 };
401 static const int fanin7_pins[] = { 71 };
402 static const int fanin8_pins[] = { 72 };
403 static const int fanin9_pins[] = { 73 };
404 static const int fanin10_pins[] = { 74 };
405 static const int fanin11_pins[] = { 75 };
406 static const int fanin12_pins[] = { 76 };
407 static const int fanin13_pins[] = { 77 };
408 static const int fanin14_pins[] = { 78 };
409 static const int fanin15_pins[] = { 79 };
410 static const int faninx_pins[] = { 175, 176, 177, 203 };
411
412 static const int pwm0_pins[] = { 80 };
413 static const int pwm1_pins[] = { 81 };
414 static const int pwm2_pins[] = { 82 };
415 static const int pwm3_pins[] = { 83 };
416 static const int pwm4_pins[] = { 144 };
417 static const int pwm5_pins[] = { 145 };
418 static const int pwm6_pins[] = { 146 };
419 static const int pwm7_pins[] = { 147 };
420
421 static const int uart1_pins[] = { 43, 44, 45, 46, 47, 61, 62, 63 };
422 static const int uart2_pins[] = { 48, 49, 50, 51, 52, 53, 54, 55 };
423
424 /* RGMII 1 pin group */
425 static const int rg1_pins[] = { 96, 97, 98, 99, 100, 101, 102, 103, 104, 105,
426 106, 107 };
427 /* RGMII 1 MD interface pin group */
428 static const int rg1mdio_pins[] = { 108, 109 };
429
430 /* RGMII 2 pin group */
431 static const int rg2_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,
432 213, 214, 215 };
433 /* RGMII 2 MD interface pin group */
434 static const int rg2mdio_pins[] = { 216, 217 };
435
436 static const int ddr_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,
437 213, 214, 215, 216, 217 };
438 /* Serial I/O Expander 1 */
439 static const int iox1_pins[] = { 0, 1, 2, 3 };
440 /* Serial I/O Expander 2 */
441 static const int iox2_pins[] = { 4, 5, 6, 7 };
442 /* Host Serial I/O Expander 2 */
443 static const int ioxh_pins[] = { 10, 11, 24, 25 };
444
445 static const int mmc_pins[] = { 152, 154, 156, 157, 158, 159 };
446 static const int mmcwp_pins[] = { 153 };
447 static const int mmccd_pins[] = { 155 };
448 static const int mmcrst_pins[] = { 155 };
449 static const int mmc8_pins[] = { 148, 149, 150, 151 };
450
451 /* RMII 1 pin groups */
452 static const int r1_pins[] = { 178, 179, 180, 181, 182, 193, 201 };
453 static const int r1err_pins[] = { 56 };
454 static const int r1md_pins[] = { 57, 58 };
455
456 /* RMII 2 pin groups */
457 static const int r2_pins[] = { 84, 85, 86, 87, 88, 89, 200 };
458 static const int r2err_pins[] = { 90 };
459 static const int r2md_pins[] = { 91, 92 };
460
461 static const int sd1_pins[] = { 136, 137, 138, 139, 140, 141, 142, 143 };
462 static const int sd1pwr_pins[] = { 143 };
463
464 static const int wdog1_pins[] = { 218 };
465 static const int wdog2_pins[] = { 219 };
466
467 /* BMC serial port 0 */
468 static const int bmcuart0a_pins[] = { 41, 42 };
469 static const int bmcuart0b_pins[] = { 48, 49 };
470
471 static const int bmcuart1_pins[] = { 43, 44, 62, 63 };
472
473 /* System Control Interrupt and Power Management Event pin group */
474 static const int scipme_pins[] = { 169 };
475 /* System Management Interrupt pin group */
476 static const int sci_pins[] = { 170 };
477 /* Serial Interrupt Line pin group */
478 static const int serirq_pins[] = { 162 };
479
480 static const int clkout_pins[] = { 160 };
481 static const int clkreq_pins[] = { 231 };
482
483 static const int jtag2_pins[] = { 43, 44, 45, 46, 47 };
484 /* Graphics SPI Clock pin group */
485 static const int gspi_pins[] = { 12, 13, 14, 15 };
486
487 static const int spix_pins[] = { 224, 225, 226, 227, 229, 230 };
488 static const int spixcs1_pins[] = { 228 };
489
490 static const int pspi1_pins[] = { 175, 176, 177 };
491 static const int pspi2_pins[] = { 17, 18, 19 };
492
493 static const int spi0cs1_pins[] = { 32 };
494
495 static const int spi3_pins[] = { 183, 184, 185, 186 };
496 static const int spi3cs1_pins[] = { 187 };
497 static const int spi3quad_pins[] = { 188, 189 };
498 static const int spi3cs2_pins[] = { 188 };
499 static const int spi3cs3_pins[] = { 189 };
500
501 static const int ddc_pins[] = { 204, 205, 206, 207 };
502
503 static const int lpc_pins[] = { 95, 161, 163, 164, 165, 166, 167 };
504 static const int lpcclk_pins[] = { 168 };
505 static const int espi_pins[] = { 95, 161, 163, 164, 165, 166, 167, 168 };
506
507 static const int lkgpo0_pins[] = { 16 };
508 static const int lkgpo1_pins[] = { 8 };
509 static const int lkgpo2_pins[] = { 9 };
510
511 static const int nprd_smi_pins[] = { 190 };
512
513 /*
514 * pin: name, number
515 * group: name, npins, pins
516 * function: name, ngroups, groups
517 */
518 struct npcm7xx_group {
519 const char *name;
520 const unsigned int *pins;
521 int npins;
522 };
523
524 #define NPCM7XX_GRPS \
525 NPCM7XX_GRP(smb0), \
526 NPCM7XX_GRP(smb0b), \
527 NPCM7XX_GRP(smb0c), \
528 NPCM7XX_GRP(smb0d), \
529 NPCM7XX_GRP(smb0den), \
530 NPCM7XX_GRP(smb1), \
531 NPCM7XX_GRP(smb1b), \
532 NPCM7XX_GRP(smb1c), \
533 NPCM7XX_GRP(smb1d), \
534 NPCM7XX_GRP(smb2), \
535 NPCM7XX_GRP(smb2b), \
536 NPCM7XX_GRP(smb2c), \
537 NPCM7XX_GRP(smb2d), \
538 NPCM7XX_GRP(smb3), \
539 NPCM7XX_GRP(smb3b), \
540 NPCM7XX_GRP(smb3c), \
541 NPCM7XX_GRP(smb3d), \
542 NPCM7XX_GRP(smb4), \
543 NPCM7XX_GRP(smb4b), \
544 NPCM7XX_GRP(smb4c), \
545 NPCM7XX_GRP(smb4d), \
546 NPCM7XX_GRP(smb4den), \
547 NPCM7XX_GRP(smb5), \
548 NPCM7XX_GRP(smb5b), \
549 NPCM7XX_GRP(smb5c), \
550 NPCM7XX_GRP(smb5d), \
551 NPCM7XX_GRP(ga20kbc), \
552 NPCM7XX_GRP(smb6), \
553 NPCM7XX_GRP(smb7), \
554 NPCM7XX_GRP(smb8), \
555 NPCM7XX_GRP(smb9), \
556 NPCM7XX_GRP(smb10), \
557 NPCM7XX_GRP(smb11), \
558 NPCM7XX_GRP(smb12), \
559 NPCM7XX_GRP(smb13), \
560 NPCM7XX_GRP(smb14), \
561 NPCM7XX_GRP(smb15), \
562 NPCM7XX_GRP(fanin0), \
563 NPCM7XX_GRP(fanin1), \
564 NPCM7XX_GRP(fanin2), \
565 NPCM7XX_GRP(fanin3), \
566 NPCM7XX_GRP(fanin4), \
567 NPCM7XX_GRP(fanin5), \
568 NPCM7XX_GRP(fanin6), \
569 NPCM7XX_GRP(fanin7), \
570 NPCM7XX_GRP(fanin8), \
571 NPCM7XX_GRP(fanin9), \
572 NPCM7XX_GRP(fanin10), \
573 NPCM7XX_GRP(fanin11), \
574 NPCM7XX_GRP(fanin12), \
575 NPCM7XX_GRP(fanin13), \
576 NPCM7XX_GRP(fanin14), \
577 NPCM7XX_GRP(fanin15), \
578 NPCM7XX_GRP(faninx), \
579 NPCM7XX_GRP(pwm0), \
580 NPCM7XX_GRP(pwm1), \
581 NPCM7XX_GRP(pwm2), \
582 NPCM7XX_GRP(pwm3), \
583 NPCM7XX_GRP(pwm4), \
584 NPCM7XX_GRP(pwm5), \
585 NPCM7XX_GRP(pwm6), \
586 NPCM7XX_GRP(pwm7), \
587 NPCM7XX_GRP(rg1), \
588 NPCM7XX_GRP(rg1mdio), \
589 NPCM7XX_GRP(rg2), \
590 NPCM7XX_GRP(rg2mdio), \
591 NPCM7XX_GRP(ddr), \
592 NPCM7XX_GRP(uart1), \
593 NPCM7XX_GRP(uart2), \
594 NPCM7XX_GRP(bmcuart0a), \
595 NPCM7XX_GRP(bmcuart0b), \
596 NPCM7XX_GRP(bmcuart1), \
597 NPCM7XX_GRP(iox1), \
598 NPCM7XX_GRP(iox2), \
599 NPCM7XX_GRP(ioxh), \
600 NPCM7XX_GRP(gspi), \
601 NPCM7XX_GRP(mmc), \
602 NPCM7XX_GRP(mmcwp), \
603 NPCM7XX_GRP(mmccd), \
604 NPCM7XX_GRP(mmcrst), \
605 NPCM7XX_GRP(mmc8), \
606 NPCM7XX_GRP(r1), \
607 NPCM7XX_GRP(r1err), \
608 NPCM7XX_GRP(r1md), \
609 NPCM7XX_GRP(r2), \
610 NPCM7XX_GRP(r2err), \
611 NPCM7XX_GRP(r2md), \
612 NPCM7XX_GRP(sd1), \
613 NPCM7XX_GRP(sd1pwr), \
614 NPCM7XX_GRP(wdog1), \
615 NPCM7XX_GRP(wdog2), \
616 NPCM7XX_GRP(scipme), \
617 NPCM7XX_GRP(sci), \
618 NPCM7XX_GRP(serirq), \
619 NPCM7XX_GRP(jtag2), \
620 NPCM7XX_GRP(spix), \
621 NPCM7XX_GRP(spixcs1), \
622 NPCM7XX_GRP(pspi1), \
623 NPCM7XX_GRP(pspi2), \
624 NPCM7XX_GRP(ddc), \
625 NPCM7XX_GRP(clkreq), \
626 NPCM7XX_GRP(clkout), \
627 NPCM7XX_GRP(spi3), \
628 NPCM7XX_GRP(spi3cs1), \
629 NPCM7XX_GRP(spi3quad), \
630 NPCM7XX_GRP(spi3cs2), \
631 NPCM7XX_GRP(spi3cs3), \
632 NPCM7XX_GRP(spi0cs1), \
633 NPCM7XX_GRP(lpc), \
634 NPCM7XX_GRP(lpcclk), \
635 NPCM7XX_GRP(espi), \
636 NPCM7XX_GRP(lkgpo0), \
637 NPCM7XX_GRP(lkgpo1), \
638 NPCM7XX_GRP(lkgpo2), \
639 NPCM7XX_GRP(nprd_smi), \
640 \
641
642 enum {
643 #define NPCM7XX_GRP(x) fn_ ## x
644 NPCM7XX_GRPS
645 /* add placeholder for none/gpio */
646 NPCM7XX_GRP(none),
647 NPCM7XX_GRP(gpio),
648 #undef NPCM7XX_GRP
649 };
650
651 static struct npcm7xx_group npcm7xx_groups[] = {
652 #define NPCM7XX_GRP(x) { .name = #x, .pins = x ## _pins, \
653 .npins = ARRAY_SIZE(x ## _pins) }
654 NPCM7XX_GRPS
655 #undef NPCM7XX_GRP
656 };
657
658 #define NPCM7XX_SFUNC(a) NPCM7XX_FUNC(a, #a)
659 #define NPCM7XX_FUNC(a, b...) static const char *a ## _grp[] = { b }
660 #define NPCM7XX_MKFUNC(nm) { .name = #nm, .ngroups = ARRAY_SIZE(nm ## _grp), \
661 .groups = nm ## _grp }
662 struct npcm7xx_func {
663 const char *name;
664 const unsigned int ngroups;
665 const char *const *groups;
666 };
667
668 NPCM7XX_SFUNC(smb0);
669 NPCM7XX_SFUNC(smb0b);
670 NPCM7XX_SFUNC(smb0c);
671 NPCM7XX_SFUNC(smb0d);
672 NPCM7XX_SFUNC(smb0den);
673 NPCM7XX_SFUNC(smb1);
674 NPCM7XX_SFUNC(smb1b);
675 NPCM7XX_SFUNC(smb1c);
676 NPCM7XX_SFUNC(smb1d);
677 NPCM7XX_SFUNC(smb2);
678 NPCM7XX_SFUNC(smb2b);
679 NPCM7XX_SFUNC(smb2c);
680 NPCM7XX_SFUNC(smb2d);
681 NPCM7XX_SFUNC(smb3);
682 NPCM7XX_SFUNC(smb3b);
683 NPCM7XX_SFUNC(smb3c);
684 NPCM7XX_SFUNC(smb3d);
685 NPCM7XX_SFUNC(smb4);
686 NPCM7XX_SFUNC(smb4b);
687 NPCM7XX_SFUNC(smb4c);
688 NPCM7XX_SFUNC(smb4d);
689 NPCM7XX_SFUNC(smb4den);
690 NPCM7XX_SFUNC(smb5);
691 NPCM7XX_SFUNC(smb5b);
692 NPCM7XX_SFUNC(smb5c);
693 NPCM7XX_SFUNC(smb5d);
694 NPCM7XX_SFUNC(ga20kbc);
695 NPCM7XX_SFUNC(smb6);
696 NPCM7XX_SFUNC(smb7);
697 NPCM7XX_SFUNC(smb8);
698 NPCM7XX_SFUNC(smb9);
699 NPCM7XX_SFUNC(smb10);
700 NPCM7XX_SFUNC(smb11);
701 NPCM7XX_SFUNC(smb12);
702 NPCM7XX_SFUNC(smb13);
703 NPCM7XX_SFUNC(smb14);
704 NPCM7XX_SFUNC(smb15);
705 NPCM7XX_SFUNC(fanin0);
706 NPCM7XX_SFUNC(fanin1);
707 NPCM7XX_SFUNC(fanin2);
708 NPCM7XX_SFUNC(fanin3);
709 NPCM7XX_SFUNC(fanin4);
710 NPCM7XX_SFUNC(fanin5);
711 NPCM7XX_SFUNC(fanin6);
712 NPCM7XX_SFUNC(fanin7);
713 NPCM7XX_SFUNC(fanin8);
714 NPCM7XX_SFUNC(fanin9);
715 NPCM7XX_SFUNC(fanin10);
716 NPCM7XX_SFUNC(fanin11);
717 NPCM7XX_SFUNC(fanin12);
718 NPCM7XX_SFUNC(fanin13);
719 NPCM7XX_SFUNC(fanin14);
720 NPCM7XX_SFUNC(fanin15);
721 NPCM7XX_SFUNC(faninx);
722 NPCM7XX_SFUNC(pwm0);
723 NPCM7XX_SFUNC(pwm1);
724 NPCM7XX_SFUNC(pwm2);
725 NPCM7XX_SFUNC(pwm3);
726 NPCM7XX_SFUNC(pwm4);
727 NPCM7XX_SFUNC(pwm5);
728 NPCM7XX_SFUNC(pwm6);
729 NPCM7XX_SFUNC(pwm7);
730 NPCM7XX_SFUNC(rg1);
731 NPCM7XX_SFUNC(rg1mdio);
732 NPCM7XX_SFUNC(rg2);
733 NPCM7XX_SFUNC(rg2mdio);
734 NPCM7XX_SFUNC(ddr);
735 NPCM7XX_SFUNC(uart1);
736 NPCM7XX_SFUNC(uart2);
737 NPCM7XX_SFUNC(bmcuart0a);
738 NPCM7XX_SFUNC(bmcuart0b);
739 NPCM7XX_SFUNC(bmcuart1);
740 NPCM7XX_SFUNC(iox1);
741 NPCM7XX_SFUNC(iox2);
742 NPCM7XX_SFUNC(ioxh);
743 NPCM7XX_SFUNC(gspi);
744 NPCM7XX_SFUNC(mmc);
745 NPCM7XX_SFUNC(mmcwp);
746 NPCM7XX_SFUNC(mmccd);
747 NPCM7XX_SFUNC(mmcrst);
748 NPCM7XX_SFUNC(mmc8);
749 NPCM7XX_SFUNC(r1);
750 NPCM7XX_SFUNC(r1err);
751 NPCM7XX_SFUNC(r1md);
752 NPCM7XX_SFUNC(r2);
753 NPCM7XX_SFUNC(r2err);
754 NPCM7XX_SFUNC(r2md);
755 NPCM7XX_SFUNC(sd1);
756 NPCM7XX_SFUNC(sd1pwr);
757 NPCM7XX_SFUNC(wdog1);
758 NPCM7XX_SFUNC(wdog2);
759 NPCM7XX_SFUNC(scipme);
760 NPCM7XX_SFUNC(sci);
761 NPCM7XX_SFUNC(serirq);
762 NPCM7XX_SFUNC(jtag2);
763 NPCM7XX_SFUNC(spix);
764 NPCM7XX_SFUNC(spixcs1);
765 NPCM7XX_SFUNC(pspi1);
766 NPCM7XX_SFUNC(pspi2);
767 NPCM7XX_SFUNC(ddc);
768 NPCM7XX_SFUNC(clkreq);
769 NPCM7XX_SFUNC(clkout);
770 NPCM7XX_SFUNC(spi3);
771 NPCM7XX_SFUNC(spi3cs1);
772 NPCM7XX_SFUNC(spi3quad);
773 NPCM7XX_SFUNC(spi3cs2);
774 NPCM7XX_SFUNC(spi3cs3);
775 NPCM7XX_SFUNC(spi0cs1);
776 NPCM7XX_SFUNC(lpc);
777 NPCM7XX_SFUNC(lpcclk);
778 NPCM7XX_SFUNC(espi);
779 NPCM7XX_SFUNC(lkgpo0);
780 NPCM7XX_SFUNC(lkgpo1);
781 NPCM7XX_SFUNC(lkgpo2);
782 NPCM7XX_SFUNC(nprd_smi);
783
784 /* Function names */
785 static struct npcm7xx_func npcm7xx_funcs[] = {
786 NPCM7XX_MKFUNC(smb0),
787 NPCM7XX_MKFUNC(smb0b),
788 NPCM7XX_MKFUNC(smb0c),
789 NPCM7XX_MKFUNC(smb0d),
790 NPCM7XX_MKFUNC(smb0den),
791 NPCM7XX_MKFUNC(smb1),
792 NPCM7XX_MKFUNC(smb1b),
793 NPCM7XX_MKFUNC(smb1c),
794 NPCM7XX_MKFUNC(smb1d),
795 NPCM7XX_MKFUNC(smb2),
796 NPCM7XX_MKFUNC(smb2b),
797 NPCM7XX_MKFUNC(smb2c),
798 NPCM7XX_MKFUNC(smb2d),
799 NPCM7XX_MKFUNC(smb3),
800 NPCM7XX_MKFUNC(smb3b),
801 NPCM7XX_MKFUNC(smb3c),
802 NPCM7XX_MKFUNC(smb3d),
803 NPCM7XX_MKFUNC(smb4),
804 NPCM7XX_MKFUNC(smb4b),
805 NPCM7XX_MKFUNC(smb4c),
806 NPCM7XX_MKFUNC(smb4d),
807 NPCM7XX_MKFUNC(smb4den),
808 NPCM7XX_MKFUNC(smb5),
809 NPCM7XX_MKFUNC(smb5b),
810 NPCM7XX_MKFUNC(smb5c),
811 NPCM7XX_MKFUNC(smb5d),
812 NPCM7XX_MKFUNC(ga20kbc),
813 NPCM7XX_MKFUNC(smb6),
814 NPCM7XX_MKFUNC(smb7),
815 NPCM7XX_MKFUNC(smb8),
816 NPCM7XX_MKFUNC(smb9),
817 NPCM7XX_MKFUNC(smb10),
818 NPCM7XX_MKFUNC(smb11),
819 NPCM7XX_MKFUNC(smb12),
820 NPCM7XX_MKFUNC(smb13),
821 NPCM7XX_MKFUNC(smb14),
822 NPCM7XX_MKFUNC(smb15),
823 NPCM7XX_MKFUNC(fanin0),
824 NPCM7XX_MKFUNC(fanin1),
825 NPCM7XX_MKFUNC(fanin2),
826 NPCM7XX_MKFUNC(fanin3),
827 NPCM7XX_MKFUNC(fanin4),
828 NPCM7XX_MKFUNC(fanin5),
829 NPCM7XX_MKFUNC(fanin6),
830 NPCM7XX_MKFUNC(fanin7),
831 NPCM7XX_MKFUNC(fanin8),
832 NPCM7XX_MKFUNC(fanin9),
833 NPCM7XX_MKFUNC(fanin10),
834 NPCM7XX_MKFUNC(fanin11),
835 NPCM7XX_MKFUNC(fanin12),
836 NPCM7XX_MKFUNC(fanin13),
837 NPCM7XX_MKFUNC(fanin14),
838 NPCM7XX_MKFUNC(fanin15),
839 NPCM7XX_MKFUNC(faninx),
840 NPCM7XX_MKFUNC(pwm0),
841 NPCM7XX_MKFUNC(pwm1),
842 NPCM7XX_MKFUNC(pwm2),
843 NPCM7XX_MKFUNC(pwm3),
844 NPCM7XX_MKFUNC(pwm4),
845 NPCM7XX_MKFUNC(pwm5),
846 NPCM7XX_MKFUNC(pwm6),
847 NPCM7XX_MKFUNC(pwm7),
848 NPCM7XX_MKFUNC(rg1),
849 NPCM7XX_MKFUNC(rg1mdio),
850 NPCM7XX_MKFUNC(rg2),
851 NPCM7XX_MKFUNC(rg2mdio),
852 NPCM7XX_MKFUNC(ddr),
853 NPCM7XX_MKFUNC(uart1),
854 NPCM7XX_MKFUNC(uart2),
855 NPCM7XX_MKFUNC(bmcuart0a),
856 NPCM7XX_MKFUNC(bmcuart0b),
857 NPCM7XX_MKFUNC(bmcuart1),
858 NPCM7XX_MKFUNC(iox1),
859 NPCM7XX_MKFUNC(iox2),
860 NPCM7XX_MKFUNC(ioxh),
861 NPCM7XX_MKFUNC(gspi),
862 NPCM7XX_MKFUNC(mmc),
863 NPCM7XX_MKFUNC(mmcwp),
864 NPCM7XX_MKFUNC(mmccd),
865 NPCM7XX_MKFUNC(mmcrst),
866 NPCM7XX_MKFUNC(mmc8),
867 NPCM7XX_MKFUNC(r1),
868 NPCM7XX_MKFUNC(r1err),
869 NPCM7XX_MKFUNC(r1md),
870 NPCM7XX_MKFUNC(r2),
871 NPCM7XX_MKFUNC(r2err),
872 NPCM7XX_MKFUNC(r2md),
873 NPCM7XX_MKFUNC(sd1),
874 NPCM7XX_MKFUNC(sd1pwr),
875 NPCM7XX_MKFUNC(wdog1),
876 NPCM7XX_MKFUNC(wdog2),
877 NPCM7XX_MKFUNC(scipme),
878 NPCM7XX_MKFUNC(sci),
879 NPCM7XX_MKFUNC(serirq),
880 NPCM7XX_MKFUNC(jtag2),
881 NPCM7XX_MKFUNC(spix),
882 NPCM7XX_MKFUNC(spixcs1),
883 NPCM7XX_MKFUNC(pspi1),
884 NPCM7XX_MKFUNC(pspi2),
885 NPCM7XX_MKFUNC(ddc),
886 NPCM7XX_MKFUNC(clkreq),
887 NPCM7XX_MKFUNC(clkout),
888 NPCM7XX_MKFUNC(spi3),
889 NPCM7XX_MKFUNC(spi3cs1),
890 NPCM7XX_MKFUNC(spi3quad),
891 NPCM7XX_MKFUNC(spi3cs2),
892 NPCM7XX_MKFUNC(spi3cs3),
893 NPCM7XX_MKFUNC(spi0cs1),
894 NPCM7XX_MKFUNC(lpc),
895 NPCM7XX_MKFUNC(lpcclk),
896 NPCM7XX_MKFUNC(espi),
897 NPCM7XX_MKFUNC(lkgpo0),
898 NPCM7XX_MKFUNC(lkgpo1),
899 NPCM7XX_MKFUNC(lkgpo2),
900 NPCM7XX_MKFUNC(nprd_smi),
901 };
902
903 #define NPCM7XX_PINCFG(a, b, c, d, e, f, g, h, i, j, k) \
904 [a] = { .fn0 = fn_ ## b, .reg0 = NPCM7XX_GCR_ ## c, .bit0 = d, \
905 .fn1 = fn_ ## e, .reg1 = NPCM7XX_GCR_ ## f, .bit1 = g, \
906 .fn2 = fn_ ## h, .reg2 = NPCM7XX_GCR_ ## i, .bit2 = j, \
907 .flag = k }
908
909 /* Drive strength controlled by NPCM7XX_GP_N_ODSC */
910 #define DRIVE_STRENGTH_LO_SHIFT 8
911 #define DRIVE_STRENGTH_HI_SHIFT 12
912 #define DRIVE_STRENGTH_MASK 0x0000FF00
913
914 #define DSTR(lo, hi) (((lo) << DRIVE_STRENGTH_LO_SHIFT) | \
915 ((hi) << DRIVE_STRENGTH_HI_SHIFT))
916 #define DSLO(x) (((x) >> DRIVE_STRENGTH_LO_SHIFT) & 0xF)
917 #define DSHI(x) (((x) >> DRIVE_STRENGTH_HI_SHIFT) & 0xF)
918
919 #define GPI 0x1 /* Not GPO */
920 #define GPO 0x2 /* Not GPI */
921 #define SLEW 0x4 /* Has Slew Control, NPCM7XX_GP_N_OSRC */
922 #define SLEWLPC 0x8 /* Has Slew Control, SRCNT.3 */
923
924 struct npcm7xx_pincfg {
925 int flag;
926 int fn0, reg0, bit0;
927 int fn1, reg1, bit1;
928 int fn2, reg2, bit2;
929 };
930
931 static const struct npcm7xx_pincfg pincfg[] = {
932 /* PIN FUNCTION 1 FUNCTION 2 FUNCTION 3 FLAGS */
933 NPCM7XX_PINCFG(0, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0),
934 NPCM7XX_PINCFG(1, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
935 NPCM7XX_PINCFG(2, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
936 NPCM7XX_PINCFG(3, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0),
937 NPCM7XX_PINCFG(4, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, SLEW),
938 NPCM7XX_PINCFG(5, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, SLEW),
939 NPCM7XX_PINCFG(6, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, SLEW),
940 NPCM7XX_PINCFG(7, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, SLEW),
941 NPCM7XX_PINCFG(8, lkgpo1, FLOCKR1, 4, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
942 NPCM7XX_PINCFG(9, lkgpo2, FLOCKR1, 8, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
943 NPCM7XX_PINCFG(10, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
944 NPCM7XX_PINCFG(11, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
945 NPCM7XX_PINCFG(12, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, SLEW),
946 NPCM7XX_PINCFG(13, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, SLEW),
947 NPCM7XX_PINCFG(14, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, SLEW),
948 NPCM7XX_PINCFG(15, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, SLEW),
949 NPCM7XX_PINCFG(16, lkgpo0, FLOCKR1, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
950 NPCM7XX_PINCFG(17, pspi2, MFSEL3, 13, smb4den, I2CSEGSEL, 23, none, NONE, 0, DSTR(8, 12)),
951 NPCM7XX_PINCFG(18, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DSTR(8, 12)),
952 NPCM7XX_PINCFG(19, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DSTR(8, 12)),
953 NPCM7XX_PINCFG(20, smb4c, I2CSEGSEL, 15, smb15, MFSEL3, 8, none, NONE, 0, 0),
954 NPCM7XX_PINCFG(21, smb4c, I2CSEGSEL, 15, smb15, MFSEL3, 8, none, NONE, 0, 0),
955 NPCM7XX_PINCFG(22, smb4d, I2CSEGSEL, 16, smb14, MFSEL3, 7, none, NONE, 0, 0),
956 NPCM7XX_PINCFG(23, smb4d, I2CSEGSEL, 16, smb14, MFSEL3, 7, none, NONE, 0, 0),
957 NPCM7XX_PINCFG(24, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
958 NPCM7XX_PINCFG(25, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
959 NPCM7XX_PINCFG(26, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, 0),
960 NPCM7XX_PINCFG(27, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, 0),
961 NPCM7XX_PINCFG(28, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, 0),
962 NPCM7XX_PINCFG(29, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, 0),
963 NPCM7XX_PINCFG(30, smb3, MFSEL1, 0, none, NONE, 0, none, NONE, 0, 0),
964 NPCM7XX_PINCFG(31, smb3, MFSEL1, 0, none, NONE, 0, none, NONE, 0, 0),
965
966 NPCM7XX_PINCFG(32, spi0cs1, MFSEL1, 3, none, NONE, 0, none, NONE, 0, 0),
967 NPCM7XX_PINCFG(33, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
968 NPCM7XX_PINCFG(34, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
969 NPCM7XX_PINCFG(37, smb3c, I2CSEGSEL, 12, none, NONE, 0, none, NONE, 0, SLEW),
970 NPCM7XX_PINCFG(38, smb3c, I2CSEGSEL, 12, none, NONE, 0, none, NONE, 0, SLEW),
971 NPCM7XX_PINCFG(39, smb3b, I2CSEGSEL, 11, none, NONE, 0, none, NONE, 0, SLEW),
972 NPCM7XX_PINCFG(40, smb3b, I2CSEGSEL, 11, none, NONE, 0, none, NONE, 0, SLEW),
973 NPCM7XX_PINCFG(41, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, 0),
974 NPCM7XX_PINCFG(42, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, DSTR(2, 4) | GPO),
975 NPCM7XX_PINCFG(43, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, bmcuart1, MFSEL3, 24, 0),
976 NPCM7XX_PINCFG(44, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, bmcuart1, MFSEL3, 24, 0),
977 NPCM7XX_PINCFG(45, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, 0),
978 NPCM7XX_PINCFG(46, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DSTR(2, 8)),
979 NPCM7XX_PINCFG(47, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DSTR(2, 8)),
980 NPCM7XX_PINCFG(48, uart2, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, GPO),
981 NPCM7XX_PINCFG(49, uart2, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, 0),
982 NPCM7XX_PINCFG(50, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),
983 NPCM7XX_PINCFG(51, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, GPO),
984 NPCM7XX_PINCFG(52, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),
985 NPCM7XX_PINCFG(53, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, GPO),
986 NPCM7XX_PINCFG(54, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),
987 NPCM7XX_PINCFG(55, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),
988 NPCM7XX_PINCFG(56, r1err, MFSEL1, 12, none, NONE, 0, none, NONE, 0, 0),
989 NPCM7XX_PINCFG(57, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
990 NPCM7XX_PINCFG(58, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
991 NPCM7XX_PINCFG(59, smb3d, I2CSEGSEL, 13, none, NONE, 0, none, NONE, 0, 0),
992 NPCM7XX_PINCFG(60, smb3d, I2CSEGSEL, 13, none, NONE, 0, none, NONE, 0, 0),
993 NPCM7XX_PINCFG(61, uart1, MFSEL1, 10, none, NONE, 0, none, NONE, 0, GPO),
994 NPCM7XX_PINCFG(62, uart1, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, GPO),
995 NPCM7XX_PINCFG(63, uart1, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, GPO),
996
997 NPCM7XX_PINCFG(64, fanin0, MFSEL2, 0, none, NONE, 0, none, NONE, 0, 0),
998 NPCM7XX_PINCFG(65, fanin1, MFSEL2, 1, none, NONE, 0, none, NONE, 0, 0),
999 NPCM7XX_PINCFG(66, fanin2, MFSEL2, 2, none, NONE, 0, none, NONE, 0, 0),
1000 NPCM7XX_PINCFG(67, fanin3, MFSEL2, 3, none, NONE, 0, none, NONE, 0, 0),
1001 NPCM7XX_PINCFG(68, fanin4, MFSEL2, 4, none, NONE, 0, none, NONE, 0, 0),
1002 NPCM7XX_PINCFG(69, fanin5, MFSEL2, 5, none, NONE, 0, none, NONE, 0, 0),
1003 NPCM7XX_PINCFG(70, fanin6, MFSEL2, 6, none, NONE, 0, none, NONE, 0, 0),
1004 NPCM7XX_PINCFG(71, fanin7, MFSEL2, 7, none, NONE, 0, none, NONE, 0, 0),
1005 NPCM7XX_PINCFG(72, fanin8, MFSEL2, 8, none, NONE, 0, none, NONE, 0, 0),
1006 NPCM7XX_PINCFG(73, fanin9, MFSEL2, 9, none, NONE, 0, none, NONE, 0, 0),
1007 NPCM7XX_PINCFG(74, fanin10, MFSEL2, 10, none, NONE, 0, none, NONE, 0, 0),
1008 NPCM7XX_PINCFG(75, fanin11, MFSEL2, 11, none, NONE, 0, none, NONE, 0, 0),
1009 NPCM7XX_PINCFG(76, fanin12, MFSEL2, 12, none, NONE, 0, none, NONE, 0, 0),
1010 NPCM7XX_PINCFG(77, fanin13, MFSEL2, 13, none, NONE, 0, none, NONE, 0, 0),
1011 NPCM7XX_PINCFG(78, fanin14, MFSEL2, 14, none, NONE, 0, none, NONE, 0, 0),
1012 NPCM7XX_PINCFG(79, fanin15, MFSEL2, 15, none, NONE, 0, none, NONE, 0, 0),
1013 NPCM7XX_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
1014 NPCM7XX_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
1015 NPCM7XX_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
1016 NPCM7XX_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
1017 NPCM7XX_PINCFG(84, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1018 NPCM7XX_PINCFG(85, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1019 NPCM7XX_PINCFG(86, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1020 NPCM7XX_PINCFG(87, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),
1021 NPCM7XX_PINCFG(88, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),
1022 NPCM7XX_PINCFG(89, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),
1023 NPCM7XX_PINCFG(90, r2err, MFSEL1, 15, none, NONE, 0, none, NONE, 0, 0),
1024 NPCM7XX_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
1025 NPCM7XX_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
1026 NPCM7XX_PINCFG(93, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, 0),
1027 NPCM7XX_PINCFG(94, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, 0),
1028 NPCM7XX_PINCFG(95, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0),
1029
1030 NPCM7XX_PINCFG(96, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
1031 NPCM7XX_PINCFG(97, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
1032 NPCM7XX_PINCFG(98, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
1033 NPCM7XX_PINCFG(99, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
1034 NPCM7XX_PINCFG(100, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
1035 NPCM7XX_PINCFG(101, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
1036 NPCM7XX_PINCFG(102, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
1037 NPCM7XX_PINCFG(103, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
1038 NPCM7XX_PINCFG(104, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
1039 NPCM7XX_PINCFG(105, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
1040 NPCM7XX_PINCFG(106, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
1041 NPCM7XX_PINCFG(107, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
1042 NPCM7XX_PINCFG(108, rg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, 0),
1043 NPCM7XX_PINCFG(109, rg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, 0),
1044 NPCM7XX_PINCFG(110, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
1045 NPCM7XX_PINCFG(111, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
1046 NPCM7XX_PINCFG(112, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
1047 NPCM7XX_PINCFG(113, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
1048 NPCM7XX_PINCFG(114, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, 0),
1049 NPCM7XX_PINCFG(115, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, 0),
1050 NPCM7XX_PINCFG(116, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, 0),
1051 NPCM7XX_PINCFG(117, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, 0),
1052 NPCM7XX_PINCFG(118, smb2, MFSEL1, 8, none, NONE, 0, none, NONE, 0, 0),
1053 NPCM7XX_PINCFG(119, smb2, MFSEL1, 8, none, NONE, 0, none, NONE, 0, 0),
1054 NPCM7XX_PINCFG(120, smb2c, I2CSEGSEL, 9, none, NONE, 0, none, NONE, 0, SLEW),
1055 NPCM7XX_PINCFG(121, smb2c, I2CSEGSEL, 9, none, NONE, 0, none, NONE, 0, SLEW),
1056 NPCM7XX_PINCFG(122, smb2b, I2CSEGSEL, 8, none, NONE, 0, none, NONE, 0, SLEW),
1057 NPCM7XX_PINCFG(123, smb2b, I2CSEGSEL, 8, none, NONE, 0, none, NONE, 0, SLEW),
1058 NPCM7XX_PINCFG(124, smb1c, I2CSEGSEL, 6, none, NONE, 0, none, NONE, 0, SLEW),
1059 NPCM7XX_PINCFG(125, smb1c, I2CSEGSEL, 6, none, NONE, 0, none, NONE, 0, SLEW),
1060 NPCM7XX_PINCFG(126, smb1b, I2CSEGSEL, 5, none, NONE, 0, none, NONE, 0, SLEW),
1061 NPCM7XX_PINCFG(127, smb1b, I2CSEGSEL, 5, none, NONE, 0, none, NONE, 0, SLEW),
1062
1063 NPCM7XX_PINCFG(128, smb8, MFSEL4, 11, none, NONE, 0, none, NONE, 0, 0),
1064 NPCM7XX_PINCFG(129, smb8, MFSEL4, 11, none, NONE, 0, none, NONE, 0, 0),
1065 NPCM7XX_PINCFG(130, smb9, MFSEL4, 12, none, NONE, 0, none, NONE, 0, 0),
1066 NPCM7XX_PINCFG(131, smb9, MFSEL4, 12, none, NONE, 0, none, NONE, 0, 0),
1067 NPCM7XX_PINCFG(132, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, 0),
1068 NPCM7XX_PINCFG(133, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, 0),
1069 NPCM7XX_PINCFG(134, smb11, MFSEL4, 14, none, NONE, 0, none, NONE, 0, 0),
1070 NPCM7XX_PINCFG(135, smb11, MFSEL4, 14, none, NONE, 0, none, NONE, 0, 0),
1071 NPCM7XX_PINCFG(136, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1072 NPCM7XX_PINCFG(137, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1073 NPCM7XX_PINCFG(138, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1074 NPCM7XX_PINCFG(139, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1075 NPCM7XX_PINCFG(140, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1076 NPCM7XX_PINCFG(141, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, 0),
1077 NPCM7XX_PINCFG(142, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1078 NPCM7XX_PINCFG(143, sd1, MFSEL3, 12, sd1pwr, MFSEL4, 5, none, NONE, 0, 0),
1079 NPCM7XX_PINCFG(144, pwm4, MFSEL2, 20, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
1080 NPCM7XX_PINCFG(145, pwm5, MFSEL2, 21, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
1081 NPCM7XX_PINCFG(146, pwm6, MFSEL2, 22, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
1082 NPCM7XX_PINCFG(147, pwm7, MFSEL2, 23, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
1083 NPCM7XX_PINCFG(148, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1084 NPCM7XX_PINCFG(149, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1085 NPCM7XX_PINCFG(150, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1086 NPCM7XX_PINCFG(151, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1087 NPCM7XX_PINCFG(152, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1088 NPCM7XX_PINCFG(153, mmcwp, FLOCKR1, 24, none, NONE, 0, none, NONE, 0, 0), /* Z1/A1 */
1089 NPCM7XX_PINCFG(154, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1090 NPCM7XX_PINCFG(155, mmccd, MFSEL3, 25, mmcrst, MFSEL4, 6, none, NONE, 0, 0), /* Z1/A1 */
1091 NPCM7XX_PINCFG(156, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1092 NPCM7XX_PINCFG(157, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1093 NPCM7XX_PINCFG(158, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1094 NPCM7XX_PINCFG(159, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1095
1096 NPCM7XX_PINCFG(160, clkout, MFSEL1, 21, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1097 NPCM7XX_PINCFG(161, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, DSTR(8, 12)),
1098 NPCM7XX_PINCFG(162, serirq, NONE, 0, gpio, MFSEL1, 31, none, NONE, 0, DSTR(8, 12)),
1099 NPCM7XX_PINCFG(163, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0),
1100 NPCM7XX_PINCFG(164, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),
1101 NPCM7XX_PINCFG(165, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),
1102 NPCM7XX_PINCFG(166, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),
1103 NPCM7XX_PINCFG(167, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),
1104 NPCM7XX_PINCFG(168, lpcclk, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL3, 16, 0),
1105 NPCM7XX_PINCFG(169, scipme, MFSEL3, 0, none, NONE, 0, none, NONE, 0, 0),
1106 NPCM7XX_PINCFG(170, sci, MFSEL1, 22, none, NONE, 0, none, NONE, 0, 0),
1107 NPCM7XX_PINCFG(171, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, 0),
1108 NPCM7XX_PINCFG(172, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, 0),
1109 NPCM7XX_PINCFG(173, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, 0),
1110 NPCM7XX_PINCFG(174, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, 0),
1111 NPCM7XX_PINCFG(175, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)),
1112 NPCM7XX_PINCFG(176, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)),
1113 NPCM7XX_PINCFG(177, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)),
1114 NPCM7XX_PINCFG(178, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1115 NPCM7XX_PINCFG(179, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1116 NPCM7XX_PINCFG(180, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1117 NPCM7XX_PINCFG(181, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),
1118 NPCM7XX_PINCFG(182, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),
1119 NPCM7XX_PINCFG(183, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1120 NPCM7XX_PINCFG(184, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO),
1121 NPCM7XX_PINCFG(185, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO),
1122 NPCM7XX_PINCFG(186, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
1123 NPCM7XX_PINCFG(187, spi3cs1, MFSEL4, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
1124 NPCM7XX_PINCFG(188, spi3quad, MFSEL4, 20, spi3cs2, MFSEL4, 18, none, NONE, 0, DSTR(8, 12) | SLEW),
1125 NPCM7XX_PINCFG(189, spi3quad, MFSEL4, 20, spi3cs3, MFSEL4, 19, none, NONE, 0, DSTR(8, 12) | SLEW),
1126 NPCM7XX_PINCFG(190, gpio, FLOCKR1, 20, nprd_smi, NONE, 0, none, NONE, 0, DSTR(2, 4)),
1127 NPCM7XX_PINCFG(191, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), /* XX */
1128
1129 NPCM7XX_PINCFG(192, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), /* XX */
1130 NPCM7XX_PINCFG(193, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),
1131 NPCM7XX_PINCFG(194, smb0b, I2CSEGSEL, 0, none, NONE, 0, none, NONE, 0, 0),
1132 NPCM7XX_PINCFG(195, smb0b, I2CSEGSEL, 0, none, NONE, 0, none, NONE, 0, 0),
1133 NPCM7XX_PINCFG(196, smb0c, I2CSEGSEL, 1, none, NONE, 0, none, NONE, 0, 0),
1134 NPCM7XX_PINCFG(197, smb0den, I2CSEGSEL, 22, none, NONE, 0, none, NONE, 0, SLEW),
1135 NPCM7XX_PINCFG(198, smb0d, I2CSEGSEL, 2, none, NONE, 0, none, NONE, 0, 0),
1136 NPCM7XX_PINCFG(199, smb0d, I2CSEGSEL, 2, none, NONE, 0, none, NONE, 0, 0),
1137 NPCM7XX_PINCFG(200, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),
1138 NPCM7XX_PINCFG(201, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),
1139 NPCM7XX_PINCFG(202, smb0c, I2CSEGSEL, 1, none, NONE, 0, none, NONE, 0, 0),
1140 NPCM7XX_PINCFG(203, faninx, MFSEL3, 3, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
1141 NPCM7XX_PINCFG(204, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW),
1142 NPCM7XX_PINCFG(205, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW),
1143 NPCM7XX_PINCFG(206, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DSTR(4, 8)),
1144 NPCM7XX_PINCFG(207, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DSTR(4, 8)),
1145 NPCM7XX_PINCFG(208, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
1146 NPCM7XX_PINCFG(209, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
1147 NPCM7XX_PINCFG(210, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
1148 NPCM7XX_PINCFG(211, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
1149 NPCM7XX_PINCFG(212, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
1150 NPCM7XX_PINCFG(213, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
1151 NPCM7XX_PINCFG(214, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
1152 NPCM7XX_PINCFG(215, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
1153 NPCM7XX_PINCFG(216, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, 0),
1154 NPCM7XX_PINCFG(217, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, 0),
1155 NPCM7XX_PINCFG(218, wdog1, MFSEL3, 19, none, NONE, 0, none, NONE, 0, 0),
1156 NPCM7XX_PINCFG(219, wdog2, MFSEL3, 20, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
1157 NPCM7XX_PINCFG(220, smb12, MFSEL3, 5, none, NONE, 0, none, NONE, 0, 0),
1158 NPCM7XX_PINCFG(221, smb12, MFSEL3, 5, none, NONE, 0, none, NONE, 0, 0),
1159 NPCM7XX_PINCFG(222, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, 0),
1160 NPCM7XX_PINCFG(223, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, 0),
1161
1162 NPCM7XX_PINCFG(224, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, SLEW),
1163 NPCM7XX_PINCFG(225, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO),
1164 NPCM7XX_PINCFG(226, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO),
1165 NPCM7XX_PINCFG(227, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1166 NPCM7XX_PINCFG(228, spixcs1, MFSEL4, 28, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1167 NPCM7XX_PINCFG(229, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1168 NPCM7XX_PINCFG(230, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1169 NPCM7XX_PINCFG(231, clkreq, MFSEL4, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
1170 NPCM7XX_PINCFG(253, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC1 power */
1171 NPCM7XX_PINCFG(254, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC2 power */
1172 NPCM7XX_PINCFG(255, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* DACOSEL */
1173 };
1174
1175 /* number, name, drv_data */
1176 static const struct pinctrl_pin_desc npcm7xx_pins[] = {
1177 PINCTRL_PIN(0, "GPIO0/IOX1DI"),
1178 PINCTRL_PIN(1, "GPIO1/IOX1LD"),
1179 PINCTRL_PIN(2, "GPIO2/IOX1CK"),
1180 PINCTRL_PIN(3, "GPIO3/IOX1D0"),
1181 PINCTRL_PIN(4, "GPIO4/IOX2DI/SMB1DSDA"),
1182 PINCTRL_PIN(5, "GPIO5/IOX2LD/SMB1DSCL"),
1183 PINCTRL_PIN(6, "GPIO6/IOX2CK/SMB2DSDA"),
1184 PINCTRL_PIN(7, "GPIO7/IOX2D0/SMB2DSCL"),
1185 PINCTRL_PIN(8, "GPIO8/LKGPO1"),
1186 PINCTRL_PIN(9, "GPIO9/LKGPO2"),
1187 PINCTRL_PIN(10, "GPIO10/IOXHLD"),
1188 PINCTRL_PIN(11, "GPIO11/IOXHCK"),
1189 PINCTRL_PIN(12, "GPIO12/GSPICK/SMB5BSCL"),
1190 PINCTRL_PIN(13, "GPIO13/GSPIDO/SMB5BSDA"),
1191 PINCTRL_PIN(14, "GPIO14/GSPIDI/SMB5CSCL"),
1192 PINCTRL_PIN(15, "GPIO15/GSPICS/SMB5CSDA"),
1193 PINCTRL_PIN(16, "GPIO16/LKGPO0"),
1194 PINCTRL_PIN(17, "GPIO17/PSPI2DI/SMB4DEN"),
1195 PINCTRL_PIN(18, "GPIO18/PSPI2D0/SMB4BSDA"),
1196 PINCTRL_PIN(19, "GPIO19/PSPI2CK/SMB4BSCL"),
1197 PINCTRL_PIN(20, "GPIO20/SMB4CSDA/SMB15SDA"),
1198 PINCTRL_PIN(21, "GPIO21/SMB4CSCL/SMB15SCL"),
1199 PINCTRL_PIN(22, "GPIO22/SMB4DSDA/SMB14SDA"),
1200 PINCTRL_PIN(23, "GPIO23/SMB4DSCL/SMB14SCL"),
1201 PINCTRL_PIN(24, "GPIO24/IOXHDO"),
1202 PINCTRL_PIN(25, "GPIO25/IOXHDI"),
1203 PINCTRL_PIN(26, "GPIO26/SMB5SDA"),
1204 PINCTRL_PIN(27, "GPIO27/SMB5SCL"),
1205 PINCTRL_PIN(28, "GPIO28/SMB4SDA"),
1206 PINCTRL_PIN(29, "GPIO29/SMB4SCL"),
1207 PINCTRL_PIN(30, "GPIO30/SMB3SDA"),
1208 PINCTRL_PIN(31, "GPIO31/SMB3SCL"),
1209
1210 PINCTRL_PIN(32, "GPIO32/nSPI0CS1"),
1211 PINCTRL_PIN(33, "SPI0D2"),
1212 PINCTRL_PIN(34, "SPI0D3"),
1213 PINCTRL_PIN(37, "GPIO37/SMB3CSDA"),
1214 PINCTRL_PIN(38, "GPIO38/SMB3CSCL"),
1215 PINCTRL_PIN(39, "GPIO39/SMB3BSDA"),
1216 PINCTRL_PIN(40, "GPIO40/SMB3BSCL"),
1217 PINCTRL_PIN(41, "GPIO41/BSPRXD"),
1218 PINCTRL_PIN(42, "GPO42/BSPTXD/STRAP11"),
1219 PINCTRL_PIN(43, "GPIO43/RXD1/JTMS2/BU1RXD"),
1220 PINCTRL_PIN(44, "GPIO44/nCTS1/JTDI2/BU1CTS"),
1221 PINCTRL_PIN(45, "GPIO45/nDCD1/JTDO2"),
1222 PINCTRL_PIN(46, "GPIO46/nDSR1/JTCK2"),
1223 PINCTRL_PIN(47, "GPIO47/nRI1/JCP_RDY2"),
1224 PINCTRL_PIN(48, "GPIO48/TXD2/BSPTXD"),
1225 PINCTRL_PIN(49, "GPIO49/RXD2/BSPRXD"),
1226 PINCTRL_PIN(50, "GPIO50/nCTS2"),
1227 PINCTRL_PIN(51, "GPO51/nRTS2/STRAP2"),
1228 PINCTRL_PIN(52, "GPIO52/nDCD2"),
1229 PINCTRL_PIN(53, "GPO53/nDTR2_BOUT2/STRAP1"),
1230 PINCTRL_PIN(54, "GPIO54/nDSR2"),
1231 PINCTRL_PIN(55, "GPIO55/nRI2"),
1232 PINCTRL_PIN(56, "GPIO56/R1RXERR"),
1233 PINCTRL_PIN(57, "GPIO57/R1MDC"),
1234 PINCTRL_PIN(58, "GPIO58/R1MDIO"),
1235 PINCTRL_PIN(59, "GPIO59/SMB3DSDA"),
1236 PINCTRL_PIN(60, "GPIO60/SMB3DSCL"),
1237 PINCTRL_PIN(61, "GPO61/nDTR1_BOUT1/STRAP6"),
1238 PINCTRL_PIN(62, "GPO62/nRTST1/STRAP5"),
1239 PINCTRL_PIN(63, "GPO63/TXD1/STRAP4"),
1240
1241 PINCTRL_PIN(64, "GPIO64/FANIN0"),
1242 PINCTRL_PIN(65, "GPIO65/FANIN1"),
1243 PINCTRL_PIN(66, "GPIO66/FANIN2"),
1244 PINCTRL_PIN(67, "GPIO67/FANIN3"),
1245 PINCTRL_PIN(68, "GPIO68/FANIN4"),
1246 PINCTRL_PIN(69, "GPIO69/FANIN5"),
1247 PINCTRL_PIN(70, "GPIO70/FANIN6"),
1248 PINCTRL_PIN(71, "GPIO71/FANIN7"),
1249 PINCTRL_PIN(72, "GPIO72/FANIN8"),
1250 PINCTRL_PIN(73, "GPIO73/FANIN9"),
1251 PINCTRL_PIN(74, "GPIO74/FANIN10"),
1252 PINCTRL_PIN(75, "GPIO75/FANIN11"),
1253 PINCTRL_PIN(76, "GPIO76/FANIN12"),
1254 PINCTRL_PIN(77, "GPIO77/FANIN13"),
1255 PINCTRL_PIN(78, "GPIO78/FANIN14"),
1256 PINCTRL_PIN(79, "GPIO79/FANIN15"),
1257 PINCTRL_PIN(80, "GPIO80/PWM0"),
1258 PINCTRL_PIN(81, "GPIO81/PWM1"),
1259 PINCTRL_PIN(82, "GPIO82/PWM2"),
1260 PINCTRL_PIN(83, "GPIO83/PWM3"),
1261 PINCTRL_PIN(84, "GPIO84/R2TXD0"),
1262 PINCTRL_PIN(85, "GPIO85/R2TXD1"),
1263 PINCTRL_PIN(86, "GPIO86/R2TXEN"),
1264 PINCTRL_PIN(87, "GPIO87/R2RXD0"),
1265 PINCTRL_PIN(88, "GPIO88/R2RXD1"),
1266 PINCTRL_PIN(89, "GPIO89/R2CRSDV"),
1267 PINCTRL_PIN(90, "GPIO90/R2RXERR"),
1268 PINCTRL_PIN(91, "GPIO91/R2MDC"),
1269 PINCTRL_PIN(92, "GPIO92/R2MDIO"),
1270 PINCTRL_PIN(93, "GPIO93/GA20/SMB5DSCL"),
1271 PINCTRL_PIN(94, "GPIO94/nKBRST/SMB5DSDA"),
1272 PINCTRL_PIN(95, "GPIO95/nLRESET/nESPIRST"),
1273
1274 PINCTRL_PIN(96, "GPIO96/RG1TXD0"),
1275 PINCTRL_PIN(97, "GPIO97/RG1TXD1"),
1276 PINCTRL_PIN(98, "GPIO98/RG1TXD2"),
1277 PINCTRL_PIN(99, "GPIO99/RG1TXD3"),
1278 PINCTRL_PIN(100, "GPIO100/RG1TXC"),
1279 PINCTRL_PIN(101, "GPIO101/RG1TXCTL"),
1280 PINCTRL_PIN(102, "GPIO102/RG1RXD0"),
1281 PINCTRL_PIN(103, "GPIO103/RG1RXD1"),
1282 PINCTRL_PIN(104, "GPIO104/RG1RXD2"),
1283 PINCTRL_PIN(105, "GPIO105/RG1RXD3"),
1284 PINCTRL_PIN(106, "GPIO106/RG1RXC"),
1285 PINCTRL_PIN(107, "GPIO107/RG1RXCTL"),
1286 PINCTRL_PIN(108, "GPIO108/RG1MDC"),
1287 PINCTRL_PIN(109, "GPIO109/RG1MDIO"),
1288 PINCTRL_PIN(110, "GPIO110/RG2TXD0/DDRV0"),
1289 PINCTRL_PIN(111, "GPIO111/RG2TXD1/DDRV1"),
1290 PINCTRL_PIN(112, "GPIO112/RG2TXD2/DDRV2"),
1291 PINCTRL_PIN(113, "GPIO113/RG2TXD3/DDRV3"),
1292 PINCTRL_PIN(114, "GPIO114/SMB0SCL"),
1293 PINCTRL_PIN(115, "GPIO115/SMB0SDA"),
1294 PINCTRL_PIN(116, "GPIO116/SMB1SCL"),
1295 PINCTRL_PIN(117, "GPIO117/SMB1SDA"),
1296 PINCTRL_PIN(118, "GPIO118/SMB2SCL"),
1297 PINCTRL_PIN(119, "GPIO119/SMB2SDA"),
1298 PINCTRL_PIN(120, "GPIO120/SMB2CSDA"),
1299 PINCTRL_PIN(121, "GPIO121/SMB2CSCL"),
1300 PINCTRL_PIN(122, "GPIO122/SMB2BSDA"),
1301 PINCTRL_PIN(123, "GPIO123/SMB2BSCL"),
1302 PINCTRL_PIN(124, "GPIO124/SMB1CSDA"),
1303 PINCTRL_PIN(125, "GPIO125/SMB1CSCL"),
1304 PINCTRL_PIN(126, "GPIO126/SMB1BSDA"),
1305 PINCTRL_PIN(127, "GPIO127/SMB1BSCL"),
1306
1307 PINCTRL_PIN(128, "GPIO128/SMB8SCL"),
1308 PINCTRL_PIN(129, "GPIO129/SMB8SDA"),
1309 PINCTRL_PIN(130, "GPIO130/SMB9SCL"),
1310 PINCTRL_PIN(131, "GPIO131/SMB9SDA"),
1311 PINCTRL_PIN(132, "GPIO132/SMB10SCL"),
1312 PINCTRL_PIN(133, "GPIO133/SMB10SDA"),
1313 PINCTRL_PIN(134, "GPIO134/SMB11SCL"),
1314 PINCTRL_PIN(135, "GPIO135/SMB11SDA"),
1315 PINCTRL_PIN(136, "GPIO136/SD1DT0"),
1316 PINCTRL_PIN(137, "GPIO137/SD1DT1"),
1317 PINCTRL_PIN(138, "GPIO138/SD1DT2"),
1318 PINCTRL_PIN(139, "GPIO139/SD1DT3"),
1319 PINCTRL_PIN(140, "GPIO140/SD1CLK"),
1320 PINCTRL_PIN(141, "GPIO141/SD1WP"),
1321 PINCTRL_PIN(142, "GPIO142/SD1CMD"),
1322 PINCTRL_PIN(143, "GPIO143/SD1CD/SD1PWR"),
1323 PINCTRL_PIN(144, "GPIO144/PWM4"),
1324 PINCTRL_PIN(145, "GPIO145/PWM5"),
1325 PINCTRL_PIN(146, "GPIO146/PWM6"),
1326 PINCTRL_PIN(147, "GPIO147/PWM7"),
1327 PINCTRL_PIN(148, "GPIO148/MMCDT4"),
1328 PINCTRL_PIN(149, "GPIO149/MMCDT5"),
1329 PINCTRL_PIN(150, "GPIO150/MMCDT6"),
1330 PINCTRL_PIN(151, "GPIO151/MMCDT7"),
1331 PINCTRL_PIN(152, "GPIO152/MMCCLK"),
1332 PINCTRL_PIN(153, "GPIO153/MMCWP"),
1333 PINCTRL_PIN(154, "GPIO154/MMCCMD"),
1334 PINCTRL_PIN(155, "GPIO155/nMMCCD/nMMCRST"),
1335 PINCTRL_PIN(156, "GPIO156/MMCDT0"),
1336 PINCTRL_PIN(157, "GPIO157/MMCDT1"),
1337 PINCTRL_PIN(158, "GPIO158/MMCDT2"),
1338 PINCTRL_PIN(159, "GPIO159/MMCDT3"),
1339
1340 PINCTRL_PIN(160, "GPIO160/CLKOUT/RNGOSCOUT"),
1341 PINCTRL_PIN(161, "GPIO161/nLFRAME/nESPICS"),
1342 PINCTRL_PIN(162, "GPIO162/SERIRQ"),
1343 PINCTRL_PIN(163, "GPIO163/LCLK/ESPICLK"),
1344 PINCTRL_PIN(164, "GPIO164/LAD0/ESPI_IO0"/*dscnt6*/),
1345 PINCTRL_PIN(165, "GPIO165/LAD1/ESPI_IO1"/*dscnt6*/),
1346 PINCTRL_PIN(166, "GPIO166/LAD2/ESPI_IO2"/*dscnt6*/),
1347 PINCTRL_PIN(167, "GPIO167/LAD3/ESPI_IO3"/*dscnt6*/),
1348 PINCTRL_PIN(168, "GPIO168/nCLKRUN/nESPIALERT"),
1349 PINCTRL_PIN(169, "GPIO169/nSCIPME"),
1350 PINCTRL_PIN(170, "GPIO170/nSMI"),
1351 PINCTRL_PIN(171, "GPIO171/SMB6SCL"),
1352 PINCTRL_PIN(172, "GPIO172/SMB6SDA"),
1353 PINCTRL_PIN(173, "GPIO173/SMB7SCL"),
1354 PINCTRL_PIN(174, "GPIO174/SMB7SDA"),
1355 PINCTRL_PIN(175, "GPIO175/PSPI1CK/FANIN19"),
1356 PINCTRL_PIN(176, "GPIO176/PSPI1DO/FANIN18"),
1357 PINCTRL_PIN(177, "GPIO177/PSPI1DI/FANIN17"),
1358 PINCTRL_PIN(178, "GPIO178/R1TXD0"),
1359 PINCTRL_PIN(179, "GPIO179/R1TXD1"),
1360 PINCTRL_PIN(180, "GPIO180/R1TXEN"),
1361 PINCTRL_PIN(181, "GPIO181/R1RXD0"),
1362 PINCTRL_PIN(182, "GPIO182/R1RXD1"),
1363 PINCTRL_PIN(183, "GPIO183/SPI3CK"),
1364 PINCTRL_PIN(184, "GPO184/SPI3D0/STRAP9"),
1365 PINCTRL_PIN(185, "GPO185/SPI3D1/STRAP10"),
1366 PINCTRL_PIN(186, "GPIO186/nSPI3CS0"),
1367 PINCTRL_PIN(187, "GPIO187/nSPI3CS1"),
1368 PINCTRL_PIN(188, "GPIO188/SPI3D2/nSPI3CS2"),
1369 PINCTRL_PIN(189, "GPIO189/SPI3D3/nSPI3CS3"),
1370 PINCTRL_PIN(190, "GPIO190/nPRD_SMI"),
1371 PINCTRL_PIN(191, "GPIO191"),
1372
1373 PINCTRL_PIN(192, "GPIO192"),
1374 PINCTRL_PIN(193, "GPIO193/R1CRSDV"),
1375 PINCTRL_PIN(194, "GPIO194/SMB0BSCL"),
1376 PINCTRL_PIN(195, "GPIO195/SMB0BSDA"),
1377 PINCTRL_PIN(196, "GPIO196/SMB0CSCL"),
1378 PINCTRL_PIN(197, "GPIO197/SMB0DEN"),
1379 PINCTRL_PIN(198, "GPIO198/SMB0DSDA"),
1380 PINCTRL_PIN(199, "GPIO199/SMB0DSCL"),
1381 PINCTRL_PIN(200, "GPIO200/R2CK"),
1382 PINCTRL_PIN(201, "GPIO201/R1CK"),
1383 PINCTRL_PIN(202, "GPIO202/SMB0CSDA"),
1384 PINCTRL_PIN(203, "GPIO203/FANIN16"),
1385 PINCTRL_PIN(204, "GPIO204/DDC2SCL"),
1386 PINCTRL_PIN(205, "GPIO205/DDC2SDA"),
1387 PINCTRL_PIN(206, "GPIO206/HSYNC2"),
1388 PINCTRL_PIN(207, "GPIO207/VSYNC2"),
1389 PINCTRL_PIN(208, "GPIO208/RG2TXC/DVCK"),
1390 PINCTRL_PIN(209, "GPIO209/RG2TXCTL/DDRV4"),
1391 PINCTRL_PIN(210, "GPIO210/RG2RXD0/DDRV5"),
1392 PINCTRL_PIN(211, "GPIO211/RG2RXD1/DDRV6"),
1393 PINCTRL_PIN(212, "GPIO212/RG2RXD2/DDRV7"),
1394 PINCTRL_PIN(213, "GPIO213/RG2RXD3/DDRV8"),
1395 PINCTRL_PIN(214, "GPIO214/RG2RXC/DDRV9"),
1396 PINCTRL_PIN(215, "GPIO215/RG2RXCTL/DDRV10"),
1397 PINCTRL_PIN(216, "GPIO216/RG2MDC/DDRV11"),
1398 PINCTRL_PIN(217, "GPIO217/RG2MDIO/DVHSYNC"),
1399 PINCTRL_PIN(218, "GPIO218/nWDO1"),
1400 PINCTRL_PIN(219, "GPIO219/nWDO2"),
1401 PINCTRL_PIN(220, "GPIO220/SMB12SCL"),
1402 PINCTRL_PIN(221, "GPIO221/SMB12SDA"),
1403 PINCTRL_PIN(222, "GPIO222/SMB13SCL"),
1404 PINCTRL_PIN(223, "GPIO223/SMB13SDA"),
1405
1406 PINCTRL_PIN(224, "GPIO224/SPIXCK"),
1407 PINCTRL_PIN(225, "GPO225/SPIXD0/STRAP12"),
1408 PINCTRL_PIN(226, "GPO226/SPIXD1/STRAP13"),
1409 PINCTRL_PIN(227, "GPIO227/nSPIXCS0"),
1410 PINCTRL_PIN(228, "GPIO228/nSPIXCS1"),
1411 PINCTRL_PIN(229, "GPO229/SPIXD2/STRAP3"),
1412 PINCTRL_PIN(230, "GPIO230/SPIXD3"),
1413 PINCTRL_PIN(231, "GPIO231/nCLKREQ"),
1414 PINCTRL_PIN(255, "GPI255/DACOSEL"),
1415 };
1416
1417 /* Enable mode in pin group */
npcm7xx_setfunc(struct regmap * gcr_regmap,const unsigned int * pin,int pin_number,int mode)1418 static void npcm7xx_setfunc(struct regmap *gcr_regmap, const unsigned int *pin,
1419 int pin_number, int mode)
1420 {
1421 const struct npcm7xx_pincfg *cfg;
1422 int i;
1423
1424 for (i = 0 ; i < pin_number ; i++) {
1425 cfg = &pincfg[pin[i]];
1426 if (mode == fn_gpio || cfg->fn0 == mode || cfg->fn1 == mode || cfg->fn2 == mode) {
1427 if (cfg->reg0)
1428 regmap_update_bits(gcr_regmap, cfg->reg0,
1429 BIT(cfg->bit0),
1430 !!(cfg->fn0 == mode) ?
1431 BIT(cfg->bit0) : 0);
1432 if (cfg->reg1)
1433 regmap_update_bits(gcr_regmap, cfg->reg1,
1434 BIT(cfg->bit1),
1435 !!(cfg->fn1 == mode) ?
1436 BIT(cfg->bit1) : 0);
1437 if (cfg->reg2)
1438 regmap_update_bits(gcr_regmap, cfg->reg2,
1439 BIT(cfg->bit2),
1440 !!(cfg->fn2 == mode) ?
1441 BIT(cfg->bit2) : 0);
1442 }
1443 }
1444 }
1445
1446 /* Get slew rate of pin (high/low) */
npcm7xx_get_slew_rate(struct npcm7xx_gpio * bank,struct regmap * gcr_regmap,unsigned int pin)1447 static int npcm7xx_get_slew_rate(struct npcm7xx_gpio *bank,
1448 struct regmap *gcr_regmap, unsigned int pin)
1449 {
1450 u32 val;
1451 int gpio = (pin % bank->gc.ngpio);
1452 unsigned long pinmask = BIT(gpio);
1453
1454 if (pincfg[pin].flag & SLEW)
1455 return ioread32(bank->base + NPCM7XX_GP_N_OSRC)
1456 & pinmask;
1457 /* LPC Slew rate in SRCNT register */
1458 if (pincfg[pin].flag & SLEWLPC) {
1459 regmap_read(gcr_regmap, NPCM7XX_GCR_SRCNT, &val);
1460 return !!(val & SRCNT_ESPI);
1461 }
1462
1463 return -EINVAL;
1464 }
1465
1466 /* Set slew rate of pin (high/low) */
npcm7xx_set_slew_rate(struct npcm7xx_gpio * bank,struct regmap * gcr_regmap,unsigned int pin,int arg)1467 static int npcm7xx_set_slew_rate(struct npcm7xx_gpio *bank,
1468 struct regmap *gcr_regmap, unsigned int pin,
1469 int arg)
1470 {
1471 int gpio = BIT(pin % bank->gc.ngpio);
1472
1473 if (pincfg[pin].flag & SLEW) {
1474 switch (arg) {
1475 case 0:
1476 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC,
1477 gpio);
1478 return 0;
1479 case 1:
1480 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC,
1481 gpio);
1482 return 0;
1483 default:
1484 return -EINVAL;
1485 }
1486 }
1487 /* LPC Slew rate in SRCNT register */
1488 if (pincfg[pin].flag & SLEWLPC) {
1489 switch (arg) {
1490 case 0:
1491 regmap_update_bits(gcr_regmap, NPCM7XX_GCR_SRCNT,
1492 SRCNT_ESPI, 0);
1493 return 0;
1494 case 1:
1495 regmap_update_bits(gcr_regmap, NPCM7XX_GCR_SRCNT,
1496 SRCNT_ESPI, SRCNT_ESPI);
1497 return 0;
1498 default:
1499 return -EINVAL;
1500 }
1501 }
1502
1503 return -EINVAL;
1504 }
1505
1506 /* Get drive strength for a pin, if supported */
npcm7xx_get_drive_strength(struct pinctrl_dev * pctldev,unsigned int pin)1507 static int npcm7xx_get_drive_strength(struct pinctrl_dev *pctldev,
1508 unsigned int pin)
1509 {
1510 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
1511 struct npcm7xx_gpio *bank =
1512 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK];
1513 int gpio = (pin % bank->gc.ngpio);
1514 unsigned long pinmask = BIT(gpio);
1515 u32 ds = 0;
1516 int flg, val;
1517
1518 flg = pincfg[pin].flag;
1519 if (flg & DRIVE_STRENGTH_MASK) {
1520 /* Get standard reading */
1521 val = ioread32(bank->base + NPCM7XX_GP_N_ODSC)
1522 & pinmask;
1523 ds = val ? DSHI(flg) : DSLO(flg);
1524 dev_dbg(bank->gc.parent,
1525 "pin %d strength %d = %d\n", pin, val, ds);
1526 return ds;
1527 }
1528
1529 return -EINVAL;
1530 }
1531
1532 /* Set drive strength for a pin, if supported */
npcm7xx_set_drive_strength(struct npcm7xx_pinctrl * npcm,unsigned int pin,int nval)1533 static int npcm7xx_set_drive_strength(struct npcm7xx_pinctrl *npcm,
1534 unsigned int pin, int nval)
1535 {
1536 int v;
1537 struct npcm7xx_gpio *bank =
1538 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK];
1539 int gpio = BIT(pin % bank->gc.ngpio);
1540
1541 v = (pincfg[pin].flag & DRIVE_STRENGTH_MASK);
1542 if (!nval || !v)
1543 return -ENOTSUPP;
1544 if (DSLO(v) == nval) {
1545 dev_dbg(bank->gc.parent,
1546 "setting pin %d to low strength [%d]\n", pin, nval);
1547 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio);
1548 return 0;
1549 } else if (DSHI(v) == nval) {
1550 dev_dbg(bank->gc.parent,
1551 "setting pin %d to high strength [%d]\n", pin, nval);
1552 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio);
1553 return 0;
1554 }
1555
1556 return -ENOTSUPP;
1557 }
1558
1559 /* pinctrl_ops */
npcm7xx_pin_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned int offset)1560 static void npcm7xx_pin_dbg_show(struct pinctrl_dev *pctldev,
1561 struct seq_file *s, unsigned int offset)
1562 {
1563 seq_printf(s, "pinctrl_ops.dbg: %d", offset);
1564 }
1565
npcm7xx_get_groups_count(struct pinctrl_dev * pctldev)1566 static int npcm7xx_get_groups_count(struct pinctrl_dev *pctldev)
1567 {
1568 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
1569
1570 dev_dbg(npcm->dev, "group size: %zu\n", ARRAY_SIZE(npcm7xx_groups));
1571 return ARRAY_SIZE(npcm7xx_groups);
1572 }
1573
npcm7xx_get_group_name(struct pinctrl_dev * pctldev,unsigned int selector)1574 static const char *npcm7xx_get_group_name(struct pinctrl_dev *pctldev,
1575 unsigned int selector)
1576 {
1577 return npcm7xx_groups[selector].name;
1578 }
1579
npcm7xx_get_group_pins(struct pinctrl_dev * pctldev,unsigned int selector,const unsigned int ** pins,unsigned int * npins)1580 static int npcm7xx_get_group_pins(struct pinctrl_dev *pctldev,
1581 unsigned int selector,
1582 const unsigned int **pins,
1583 unsigned int *npins)
1584 {
1585 *npins = npcm7xx_groups[selector].npins;
1586 *pins = npcm7xx_groups[selector].pins;
1587
1588 return 0;
1589 }
1590
npcm7xx_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np_config,struct pinctrl_map ** map,u32 * num_maps)1591 static int npcm7xx_dt_node_to_map(struct pinctrl_dev *pctldev,
1592 struct device_node *np_config,
1593 struct pinctrl_map **map,
1594 u32 *num_maps)
1595 {
1596 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
1597
1598 dev_dbg(npcm->dev, "dt_node_to_map: %s\n", np_config->name);
1599 return pinconf_generic_dt_node_to_map(pctldev, np_config,
1600 map, num_maps,
1601 PIN_MAP_TYPE_INVALID);
1602 }
1603
npcm7xx_dt_free_map(struct pinctrl_dev * pctldev,struct pinctrl_map * map,u32 num_maps)1604 static void npcm7xx_dt_free_map(struct pinctrl_dev *pctldev,
1605 struct pinctrl_map *map, u32 num_maps)
1606 {
1607 kfree(map);
1608 }
1609
1610 static const struct pinctrl_ops npcm7xx_pinctrl_ops = {
1611 .get_groups_count = npcm7xx_get_groups_count,
1612 .get_group_name = npcm7xx_get_group_name,
1613 .get_group_pins = npcm7xx_get_group_pins,
1614 .pin_dbg_show = npcm7xx_pin_dbg_show,
1615 .dt_node_to_map = npcm7xx_dt_node_to_map,
1616 .dt_free_map = npcm7xx_dt_free_map,
1617 };
1618
1619 /* pinmux_ops */
npcm7xx_get_functions_count(struct pinctrl_dev * pctldev)1620 static int npcm7xx_get_functions_count(struct pinctrl_dev *pctldev)
1621 {
1622 return ARRAY_SIZE(npcm7xx_funcs);
1623 }
1624
npcm7xx_get_function_name(struct pinctrl_dev * pctldev,unsigned int function)1625 static const char *npcm7xx_get_function_name(struct pinctrl_dev *pctldev,
1626 unsigned int function)
1627 {
1628 return npcm7xx_funcs[function].name;
1629 }
1630
npcm7xx_get_function_groups(struct pinctrl_dev * pctldev,unsigned int function,const char * const ** groups,unsigned int * const ngroups)1631 static int npcm7xx_get_function_groups(struct pinctrl_dev *pctldev,
1632 unsigned int function,
1633 const char * const **groups,
1634 unsigned int * const ngroups)
1635 {
1636 *ngroups = npcm7xx_funcs[function].ngroups;
1637 *groups = npcm7xx_funcs[function].groups;
1638
1639 return 0;
1640 }
1641
npcm7xx_pinmux_set_mux(struct pinctrl_dev * pctldev,unsigned int function,unsigned int group)1642 static int npcm7xx_pinmux_set_mux(struct pinctrl_dev *pctldev,
1643 unsigned int function,
1644 unsigned int group)
1645 {
1646 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
1647
1648 dev_dbg(npcm->dev, "set_mux: %d, %d[%s]\n", function, group,
1649 npcm7xx_groups[group].name);
1650
1651 npcm7xx_setfunc(npcm->gcr_regmap, npcm7xx_groups[group].pins,
1652 npcm7xx_groups[group].npins, group);
1653
1654 return 0;
1655 }
1656
npcm7xx_gpio_request_enable(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int offset)1657 static int npcm7xx_gpio_request_enable(struct pinctrl_dev *pctldev,
1658 struct pinctrl_gpio_range *range,
1659 unsigned int offset)
1660 {
1661 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
1662
1663 if (!range) {
1664 dev_err(npcm->dev, "invalid range\n");
1665 return -EINVAL;
1666 }
1667 if (!range->gc) {
1668 dev_err(npcm->dev, "invalid gpiochip\n");
1669 return -EINVAL;
1670 }
1671
1672 npcm7xx_setfunc(npcm->gcr_regmap, &offset, 1, fn_gpio);
1673
1674 return 0;
1675 }
1676
1677 /* Release GPIO back to pinctrl mode */
npcm7xx_gpio_request_free(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int offset)1678 static void npcm7xx_gpio_request_free(struct pinctrl_dev *pctldev,
1679 struct pinctrl_gpio_range *range,
1680 unsigned int offset)
1681 {
1682 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
1683 int virq;
1684
1685 virq = irq_find_mapping(npcm->domain, offset);
1686 if (virq)
1687 irq_dispose_mapping(virq);
1688 }
1689
1690 /* Set GPIO direction */
npcm_gpio_set_direction(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int offset,bool input)1691 static int npcm_gpio_set_direction(struct pinctrl_dev *pctldev,
1692 struct pinctrl_gpio_range *range,
1693 unsigned int offset, bool input)
1694 {
1695 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
1696 struct npcm7xx_gpio *bank =
1697 &npcm->gpio_bank[offset / NPCM7XX_GPIO_PER_BANK];
1698 int gpio = BIT(offset % bank->gc.ngpio);
1699
1700 dev_dbg(bank->gc.parent, "GPIO Set Direction: %d = %d\n", offset,
1701 input);
1702 if (input)
1703 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC);
1704 else
1705 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES);
1706
1707 return 0;
1708 }
1709
1710 static const struct pinmux_ops npcm7xx_pinmux_ops = {
1711 .get_functions_count = npcm7xx_get_functions_count,
1712 .get_function_name = npcm7xx_get_function_name,
1713 .get_function_groups = npcm7xx_get_function_groups,
1714 .set_mux = npcm7xx_pinmux_set_mux,
1715 .gpio_request_enable = npcm7xx_gpio_request_enable,
1716 .gpio_disable_free = npcm7xx_gpio_request_free,
1717 .gpio_set_direction = npcm_gpio_set_direction,
1718 };
1719
1720 /* pinconf_ops */
npcm7xx_config_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)1721 static int npcm7xx_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
1722 unsigned long *config)
1723 {
1724 enum pin_config_param param = pinconf_to_config_param(*config);
1725 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
1726 struct npcm7xx_gpio *bank =
1727 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK];
1728 int gpio = (pin % bank->gc.ngpio);
1729 unsigned long pinmask = BIT(gpio);
1730 u32 ie, oe, pu, pd;
1731 int rc = 0;
1732
1733 switch (param) {
1734 case PIN_CONFIG_BIAS_DISABLE:
1735 case PIN_CONFIG_BIAS_PULL_UP:
1736 case PIN_CONFIG_BIAS_PULL_DOWN:
1737 pu = ioread32(bank->base + NPCM7XX_GP_N_PU) & pinmask;
1738 pd = ioread32(bank->base + NPCM7XX_GP_N_PD) & pinmask;
1739 if (param == PIN_CONFIG_BIAS_DISABLE)
1740 rc = (!pu && !pd);
1741 else if (param == PIN_CONFIG_BIAS_PULL_UP)
1742 rc = (pu && !pd);
1743 else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
1744 rc = (!pu && pd);
1745 break;
1746 case PIN_CONFIG_OUTPUT:
1747 case PIN_CONFIG_INPUT_ENABLE:
1748 ie = ioread32(bank->base + NPCM7XX_GP_N_IEM) & pinmask;
1749 oe = ioread32(bank->base + NPCM7XX_GP_N_OE) & pinmask;
1750 if (param == PIN_CONFIG_INPUT_ENABLE)
1751 rc = (ie && !oe);
1752 else if (param == PIN_CONFIG_OUTPUT)
1753 rc = (!ie && oe);
1754 break;
1755 case PIN_CONFIG_DRIVE_PUSH_PULL:
1756 rc = !(ioread32(bank->base + NPCM7XX_GP_N_OTYP) & pinmask);
1757 break;
1758 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1759 rc = ioread32(bank->base + NPCM7XX_GP_N_OTYP) & pinmask;
1760 break;
1761 case PIN_CONFIG_INPUT_DEBOUNCE:
1762 rc = ioread32(bank->base + NPCM7XX_GP_N_DBNC) & pinmask;
1763 break;
1764 case PIN_CONFIG_DRIVE_STRENGTH:
1765 rc = npcm7xx_get_drive_strength(pctldev, pin);
1766 if (rc)
1767 *config = pinconf_to_config_packed(param, rc);
1768 break;
1769 case PIN_CONFIG_SLEW_RATE:
1770 rc = npcm7xx_get_slew_rate(bank, npcm->gcr_regmap, pin);
1771 if (rc >= 0)
1772 *config = pinconf_to_config_packed(param, rc);
1773 break;
1774 default:
1775 return -ENOTSUPP;
1776 }
1777
1778 if (!rc)
1779 return -EINVAL;
1780
1781 return 0;
1782 }
1783
npcm7xx_config_set_one(struct npcm7xx_pinctrl * npcm,unsigned int pin,unsigned long config)1784 static int npcm7xx_config_set_one(struct npcm7xx_pinctrl *npcm,
1785 unsigned int pin, unsigned long config)
1786 {
1787 enum pin_config_param param = pinconf_to_config_param(config);
1788 u16 arg = pinconf_to_config_argument(config);
1789 struct npcm7xx_gpio *bank =
1790 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK];
1791 int gpio = BIT(pin % bank->gc.ngpio);
1792
1793 dev_dbg(bank->gc.parent, "param=%d %d[GPIO]\n", param, pin);
1794 switch (param) {
1795 case PIN_CONFIG_BIAS_DISABLE:
1796 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio);
1797 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio);
1798 break;
1799 case PIN_CONFIG_BIAS_PULL_DOWN:
1800 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio);
1801 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio);
1802 break;
1803 case PIN_CONFIG_BIAS_PULL_UP:
1804 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio);
1805 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio);
1806 break;
1807 case PIN_CONFIG_INPUT_ENABLE:
1808 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC);
1809 bank->direction_input(&bank->gc, pin % bank->gc.ngpio);
1810 break;
1811 case PIN_CONFIG_OUTPUT:
1812 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES);
1813 bank->direction_output(&bank->gc, pin % bank->gc.ngpio, arg);
1814 break;
1815 case PIN_CONFIG_DRIVE_PUSH_PULL:
1816 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio);
1817 break;
1818 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1819 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio);
1820 break;
1821 case PIN_CONFIG_INPUT_DEBOUNCE:
1822 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_DBNC, gpio);
1823 break;
1824 case PIN_CONFIG_SLEW_RATE:
1825 return npcm7xx_set_slew_rate(bank, npcm->gcr_regmap, pin, arg);
1826 case PIN_CONFIG_DRIVE_STRENGTH:
1827 return npcm7xx_set_drive_strength(npcm, pin, arg);
1828 default:
1829 return -ENOTSUPP;
1830 }
1831
1832 return 0;
1833 }
1834
1835 /* Set multiple configuration settings for a pin */
npcm7xx_config_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)1836 static int npcm7xx_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
1837 unsigned long *configs, unsigned int num_configs)
1838 {
1839 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
1840 int rc;
1841
1842 while (num_configs--) {
1843 rc = npcm7xx_config_set_one(npcm, pin, *configs++);
1844 if (rc)
1845 return rc;
1846 }
1847
1848 return 0;
1849 }
1850
1851 static const struct pinconf_ops npcm7xx_pinconf_ops = {
1852 .is_generic = true,
1853 .pin_config_get = npcm7xx_config_get,
1854 .pin_config_set = npcm7xx_config_set,
1855 };
1856
1857 /* pinctrl_desc */
1858 static struct pinctrl_desc npcm7xx_pinctrl_desc = {
1859 .name = "npcm7xx-pinctrl",
1860 .pins = npcm7xx_pins,
1861 .npins = ARRAY_SIZE(npcm7xx_pins),
1862 .pctlops = &npcm7xx_pinctrl_ops,
1863 .pmxops = &npcm7xx_pinmux_ops,
1864 .confops = &npcm7xx_pinconf_ops,
1865 .owner = THIS_MODULE,
1866 };
1867
npcm7xx_gpio_of(struct npcm7xx_pinctrl * pctrl)1868 static int npcm7xx_gpio_of(struct npcm7xx_pinctrl *pctrl)
1869 {
1870 int ret = -ENXIO;
1871 struct resource res;
1872 struct device *dev = pctrl->dev;
1873 struct fwnode_reference_args args;
1874 struct fwnode_handle *child;
1875 int id = 0;
1876
1877 for_each_gpiochip_node(dev, child) {
1878 struct device_node *np = to_of_node(child);
1879
1880 ret = of_address_to_resource(np, 0, &res);
1881 if (ret < 0) {
1882 dev_err(dev, "Resource fail for GPIO bank %u\n", id);
1883 return ret;
1884 }
1885
1886 pctrl->gpio_bank[id].base = ioremap(res.start, resource_size(&res));
1887 if (!pctrl->gpio_bank[id].base)
1888 return -EINVAL;
1889
1890 ret = bgpio_init(&pctrl->gpio_bank[id].gc, dev, 4,
1891 pctrl->gpio_bank[id].base + NPCM7XX_GP_N_DIN,
1892 pctrl->gpio_bank[id].base + NPCM7XX_GP_N_DOUT,
1893 NULL,
1894 NULL,
1895 pctrl->gpio_bank[id].base + NPCM7XX_GP_N_IEM,
1896 BGPIOF_READ_OUTPUT_REG_SET);
1897 if (ret) {
1898 dev_err(dev, "bgpio_init() failed\n");
1899 return ret;
1900 }
1901
1902 ret = fwnode_property_get_reference_args(child, "gpio-ranges", NULL, 3, 0, &args);
1903 if (ret < 0) {
1904 dev_err(dev, "gpio-ranges fail for GPIO bank %u\n", id);
1905 return ret;
1906 }
1907
1908 ret = irq_of_parse_and_map(np, 0);
1909 if (!ret) {
1910 dev_err(dev, "No IRQ for GPIO bank %u\n", id);
1911 return -EINVAL;
1912 }
1913 pctrl->gpio_bank[id].irq = ret;
1914 pctrl->gpio_bank[id].irqbase = id * NPCM7XX_GPIO_PER_BANK;
1915 pctrl->gpio_bank[id].pinctrl_id = args.args[0];
1916 pctrl->gpio_bank[id].gc.base = args.args[1];
1917 pctrl->gpio_bank[id].gc.ngpio = args.args[2];
1918 pctrl->gpio_bank[id].gc.owner = THIS_MODULE;
1919 pctrl->gpio_bank[id].gc.parent = dev;
1920 pctrl->gpio_bank[id].gc.fwnode = child;
1921 pctrl->gpio_bank[id].gc.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", child);
1922 if (pctrl->gpio_bank[id].gc.label == NULL)
1923 return -ENOMEM;
1924
1925 pctrl->gpio_bank[id].gc.dbg_show = npcmgpio_dbg_show;
1926 pctrl->gpio_bank[id].direction_input = pctrl->gpio_bank[id].gc.direction_input;
1927 pctrl->gpio_bank[id].gc.direction_input = npcmgpio_direction_input;
1928 pctrl->gpio_bank[id].direction_output = pctrl->gpio_bank[id].gc.direction_output;
1929 pctrl->gpio_bank[id].gc.direction_output = npcmgpio_direction_output;
1930 pctrl->gpio_bank[id].request = pctrl->gpio_bank[id].gc.request;
1931 pctrl->gpio_bank[id].gc.request = npcmgpio_gpio_request;
1932 pctrl->gpio_bank[id].gc.free = npcmgpio_gpio_free;
1933 id++;
1934 }
1935
1936 pctrl->bank_num = id;
1937 return ret;
1938 }
1939
npcm7xx_gpio_register(struct npcm7xx_pinctrl * pctrl)1940 static int npcm7xx_gpio_register(struct npcm7xx_pinctrl *pctrl)
1941 {
1942 int ret, id;
1943
1944 for (id = 0 ; id < pctrl->bank_num ; id++) {
1945 struct gpio_irq_chip *girq;
1946
1947 girq = &pctrl->gpio_bank[id].gc.irq;
1948 gpio_irq_chip_set_chip(girq, &npcmgpio_irqchip);
1949 girq->parent_handler = npcmgpio_irq_handler;
1950 girq->num_parents = 1;
1951 girq->parents = devm_kcalloc(pctrl->dev, 1,
1952 sizeof(*girq->parents),
1953 GFP_KERNEL);
1954 if (!girq->parents) {
1955 ret = -ENOMEM;
1956 goto err_register;
1957 }
1958 girq->parents[0] = pctrl->gpio_bank[id].irq;
1959 girq->default_type = IRQ_TYPE_NONE;
1960 girq->handler = handle_level_irq;
1961 ret = devm_gpiochip_add_data(pctrl->dev,
1962 &pctrl->gpio_bank[id].gc,
1963 &pctrl->gpio_bank[id]);
1964 if (ret) {
1965 dev_err(pctrl->dev, "Failed to add GPIO chip %u\n", id);
1966 goto err_register;
1967 }
1968
1969 ret = gpiochip_add_pin_range(&pctrl->gpio_bank[id].gc,
1970 dev_name(pctrl->dev),
1971 pctrl->gpio_bank[id].pinctrl_id,
1972 pctrl->gpio_bank[id].gc.base,
1973 pctrl->gpio_bank[id].gc.ngpio);
1974 if (ret < 0) {
1975 dev_err(pctrl->dev, "Failed to add GPIO bank %u\n", id);
1976 gpiochip_remove(&pctrl->gpio_bank[id].gc);
1977 goto err_register;
1978 }
1979 }
1980
1981 return 0;
1982
1983 err_register:
1984 for (; id > 0; id--)
1985 gpiochip_remove(&pctrl->gpio_bank[id - 1].gc);
1986
1987 return ret;
1988 }
1989
npcm7xx_pinctrl_probe(struct platform_device * pdev)1990 static int npcm7xx_pinctrl_probe(struct platform_device *pdev)
1991 {
1992 struct npcm7xx_pinctrl *pctrl;
1993 int ret;
1994
1995 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1996 if (!pctrl)
1997 return -ENOMEM;
1998
1999 pctrl->dev = &pdev->dev;
2000 dev_set_drvdata(&pdev->dev, pctrl);
2001
2002 pctrl->gcr_regmap =
2003 syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");
2004 if (IS_ERR(pctrl->gcr_regmap)) {
2005 dev_err(pctrl->dev, "didn't find nuvoton,npcm750-gcr\n");
2006 return PTR_ERR(pctrl->gcr_regmap);
2007 }
2008
2009 ret = npcm7xx_gpio_of(pctrl);
2010 if (ret < 0) {
2011 dev_err(pctrl->dev, "Failed to gpio dt-binding %u\n", ret);
2012 return ret;
2013 }
2014
2015 pctrl->pctldev = devm_pinctrl_register(&pdev->dev,
2016 &npcm7xx_pinctrl_desc, pctrl);
2017 if (IS_ERR(pctrl->pctldev)) {
2018 dev_err(&pdev->dev, "Failed to register pinctrl device\n");
2019 return PTR_ERR(pctrl->pctldev);
2020 }
2021
2022 ret = npcm7xx_gpio_register(pctrl);
2023 if (ret < 0) {
2024 dev_err(pctrl->dev, "Failed to register gpio %u\n", ret);
2025 return ret;
2026 }
2027
2028 pr_info("NPCM7xx Pinctrl driver probed\n");
2029 return 0;
2030 }
2031
2032 static const struct of_device_id npcm7xx_pinctrl_match[] = {
2033 { .compatible = "nuvoton,npcm750-pinctrl" },
2034 { },
2035 };
2036 MODULE_DEVICE_TABLE(of, npcm7xx_pinctrl_match);
2037
2038 static struct platform_driver npcm7xx_pinctrl_driver = {
2039 .probe = npcm7xx_pinctrl_probe,
2040 .driver = {
2041 .name = "npcm7xx-pinctrl",
2042 .of_match_table = npcm7xx_pinctrl_match,
2043 .suppress_bind_attrs = true,
2044 },
2045 };
2046
npcm7xx_pinctrl_register(void)2047 static int __init npcm7xx_pinctrl_register(void)
2048 {
2049 return platform_driver_register(&npcm7xx_pinctrl_driver);
2050 }
2051 arch_initcall(npcm7xx_pinctrl_register);
2052
2053 MODULE_AUTHOR("jordan_hargrave@dell.com");
2054 MODULE_AUTHOR("tomer.maimon@nuvoton.com");
2055 MODULE_DESCRIPTION("Nuvoton NPCM7XX Pinctrl and GPIO driver");
2056