1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Generic GPIO driver for logic cells found in the Nomadik SoC 4 * 5 * Copyright (C) 2008,2009 STMicroelectronics 6 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> 7 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> 8 * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org> 9 */ 10 #include <linux/kernel.h> 11 #include <linux/init.h> 12 #include <linux/device.h> 13 #include <linux/platform_device.h> 14 #include <linux/io.h> 15 #include <linux/clk.h> 16 #include <linux/err.h> 17 #include <linux/gpio/driver.h> 18 #include <linux/spinlock.h> 19 #include <linux/interrupt.h> 20 #include <linux/slab.h> 21 #include <linux/of_device.h> 22 #include <linux/of_address.h> 23 #include <linux/bitops.h> 24 #include <linux/pinctrl/machine.h> 25 #include <linux/pinctrl/pinctrl.h> 26 #include <linux/pinctrl/pinmux.h> 27 #include <linux/pinctrl/pinconf.h> 28 /* Since we request GPIOs from ourself */ 29 #include <linux/pinctrl/consumer.h> 30 #include "pinctrl-nomadik.h" 31 #include "../core.h" 32 #include "../pinctrl-utils.h" 33 34 /* 35 * The GPIO module in the Nomadik family of Systems-on-Chip is an 36 * AMBA device, managing 32 pins and alternate functions. The logic block 37 * is currently used in the Nomadik and ux500. 38 * 39 * Symbols in this file are called "nmk_gpio" for "nomadik gpio" 40 */ 41 42 /* 43 * pin configurations are represented by 32-bit integers: 44 * 45 * bit 0.. 8 - Pin Number (512 Pins Maximum) 46 * bit 9..10 - Alternate Function Selection 47 * bit 11..12 - Pull up/down state 48 * bit 13 - Sleep mode behaviour 49 * bit 14 - Direction 50 * bit 15 - Value (if output) 51 * bit 16..18 - SLPM pull up/down state 52 * bit 19..20 - SLPM direction 53 * bit 21..22 - SLPM Value (if output) 54 * bit 23..25 - PDIS value (if input) 55 * bit 26 - Gpio mode 56 * bit 27 - Sleep mode 57 * 58 * to facilitate the definition, the following macros are provided 59 * 60 * PIN_CFG_DEFAULT - default config (0): 61 * pull up/down = disabled 62 * sleep mode = input/wakeup 63 * direction = input 64 * value = low 65 * SLPM direction = same as normal 66 * SLPM pull = same as normal 67 * SLPM value = same as normal 68 * 69 * PIN_CFG - default config with alternate function 70 */ 71 72 typedef unsigned long pin_cfg_t; 73 74 #define PIN_NUM_MASK 0x1ff 75 #define PIN_NUM(x) ((x) & PIN_NUM_MASK) 76 77 #define PIN_ALT_SHIFT 9 78 #define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT) 79 #define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT) 80 #define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT) 81 #define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT) 82 #define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT) 83 #define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT) 84 85 #define PIN_PULL_SHIFT 11 86 #define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT) 87 #define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT) 88 #define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT) 89 #define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT) 90 #define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT) 91 92 #define PIN_SLPM_SHIFT 13 93 #define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT) 94 #define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT) 95 #define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT) 96 #define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT) 97 /* These two replace the above in DB8500v2+ */ 98 #define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT) 99 #define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT) 100 #define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE 101 102 #define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */ 103 #define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */ 104 105 #define PIN_DIR_SHIFT 14 106 #define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT) 107 #define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT) 108 #define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT) 109 #define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT) 110 111 #define PIN_VAL_SHIFT 15 112 #define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT) 113 #define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT) 114 #define PIN_VAL_LOW (0 << PIN_VAL_SHIFT) 115 #define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT) 116 117 #define PIN_SLPM_PULL_SHIFT 16 118 #define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT) 119 #define PIN_SLPM_PULL(x) \ 120 (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT) 121 #define PIN_SLPM_PULL_NONE \ 122 ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT) 123 #define PIN_SLPM_PULL_UP \ 124 ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT) 125 #define PIN_SLPM_PULL_DOWN \ 126 ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT) 127 128 #define PIN_SLPM_DIR_SHIFT 19 129 #define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT) 130 #define PIN_SLPM_DIR(x) \ 131 (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT) 132 #define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT) 133 #define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT) 134 135 #define PIN_SLPM_VAL_SHIFT 21 136 #define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT) 137 #define PIN_SLPM_VAL(x) \ 138 (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT) 139 #define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT) 140 #define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT) 141 142 #define PIN_SLPM_PDIS_SHIFT 23 143 #define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT) 144 #define PIN_SLPM_PDIS(x) \ 145 (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT) 146 #define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT) 147 #define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT) 148 #define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT) 149 150 #define PIN_LOWEMI_SHIFT 25 151 #define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT) 152 #define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT) 153 #define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT) 154 #define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT) 155 156 #define PIN_GPIOMODE_SHIFT 26 157 #define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT) 158 #define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT) 159 #define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT) 160 #define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT) 161 162 #define PIN_SLEEPMODE_SHIFT 27 163 #define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT) 164 #define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT) 165 #define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT) 166 #define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT) 167 168 169 /* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */ 170 #define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN) 171 #define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP) 172 #define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE) 173 #define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW) 174 #define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH) 175 176 #define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN) 177 #define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP) 178 #define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE) 179 #define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW) 180 #define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH) 181 182 #define PIN_CFG_DEFAULT (0) 183 184 #define PIN_CFG(num, alt) \ 185 (PIN_CFG_DEFAULT |\ 186 (PIN_NUM(num) | PIN_##alt)) 187 188 #define PIN_CFG_INPUT(num, alt, pull) \ 189 (PIN_CFG_DEFAULT |\ 190 (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull)) 191 192 #define PIN_CFG_OUTPUT(num, alt, val) \ 193 (PIN_CFG_DEFAULT |\ 194 (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val)) 195 196 /* 197 * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving 198 * the "gpio" namespace for generic and cross-machine functions 199 */ 200 201 #define GPIO_BLOCK_SHIFT 5 202 #define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT) 203 #define NMK_MAX_BANKS DIV_ROUND_UP(512, NMK_GPIO_PER_CHIP) 204 205 /* Register in the logic block */ 206 #define NMK_GPIO_DAT 0x00 207 #define NMK_GPIO_DATS 0x04 208 #define NMK_GPIO_DATC 0x08 209 #define NMK_GPIO_PDIS 0x0c 210 #define NMK_GPIO_DIR 0x10 211 #define NMK_GPIO_DIRS 0x14 212 #define NMK_GPIO_DIRC 0x18 213 #define NMK_GPIO_SLPC 0x1c 214 #define NMK_GPIO_AFSLA 0x20 215 #define NMK_GPIO_AFSLB 0x24 216 #define NMK_GPIO_LOWEMI 0x28 217 218 #define NMK_GPIO_RIMSC 0x40 219 #define NMK_GPIO_FIMSC 0x44 220 #define NMK_GPIO_IS 0x48 221 #define NMK_GPIO_IC 0x4c 222 #define NMK_GPIO_RWIMSC 0x50 223 #define NMK_GPIO_FWIMSC 0x54 224 #define NMK_GPIO_WKS 0x58 225 /* These appear in DB8540 and later ASICs */ 226 #define NMK_GPIO_EDGELEVEL 0x5C 227 #define NMK_GPIO_LEVEL 0x60 228 229 230 /* Pull up/down values */ 231 enum nmk_gpio_pull { 232 NMK_GPIO_PULL_NONE, 233 NMK_GPIO_PULL_UP, 234 NMK_GPIO_PULL_DOWN, 235 }; 236 237 /* Sleep mode */ 238 enum nmk_gpio_slpm { 239 NMK_GPIO_SLPM_INPUT, 240 NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT, 241 NMK_GPIO_SLPM_NOCHANGE, 242 NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE, 243 }; 244 245 struct nmk_gpio_chip { 246 struct gpio_chip chip; 247 struct irq_chip irqchip; 248 void __iomem *addr; 249 struct clk *clk; 250 unsigned int bank; 251 unsigned int parent_irq; 252 void (*set_ioforce)(bool enable); 253 spinlock_t lock; 254 bool sleepmode; 255 /* Keep track of configured edges */ 256 u32 edge_rising; 257 u32 edge_falling; 258 u32 real_wake; 259 u32 rwimsc; 260 u32 fwimsc; 261 u32 rimsc; 262 u32 fimsc; 263 u32 pull_up; 264 u32 lowemi; 265 }; 266 267 /** 268 * struct nmk_pinctrl - state container for the Nomadik pin controller 269 * @dev: containing device pointer 270 * @pctl: corresponding pin controller device 271 * @soc: SoC data for this specific chip 272 * @prcm_base: PRCM register range virtual base 273 */ 274 struct nmk_pinctrl { 275 struct device *dev; 276 struct pinctrl_dev *pctl; 277 const struct nmk_pinctrl_soc_data *soc; 278 void __iomem *prcm_base; 279 }; 280 281 static struct nmk_gpio_chip *nmk_gpio_chips[NMK_MAX_BANKS]; 282 283 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock); 284 285 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips) 286 287 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, 288 unsigned offset, int gpio_mode) 289 { 290 u32 afunc, bfunc; 291 292 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~BIT(offset); 293 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~BIT(offset); 294 if (gpio_mode & NMK_GPIO_ALT_A) 295 afunc |= BIT(offset); 296 if (gpio_mode & NMK_GPIO_ALT_B) 297 bfunc |= BIT(offset); 298 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); 299 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); 300 } 301 302 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, 303 unsigned offset, enum nmk_gpio_slpm mode) 304 { 305 u32 slpm; 306 307 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); 308 if (mode == NMK_GPIO_SLPM_NOCHANGE) 309 slpm |= BIT(offset); 310 else 311 slpm &= ~BIT(offset); 312 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); 313 } 314 315 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, 316 unsigned offset, enum nmk_gpio_pull pull) 317 { 318 u32 pdis; 319 320 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); 321 if (pull == NMK_GPIO_PULL_NONE) { 322 pdis |= BIT(offset); 323 nmk_chip->pull_up &= ~BIT(offset); 324 } else { 325 pdis &= ~BIT(offset); 326 } 327 328 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); 329 330 if (pull == NMK_GPIO_PULL_UP) { 331 nmk_chip->pull_up |= BIT(offset); 332 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS); 333 } else if (pull == NMK_GPIO_PULL_DOWN) { 334 nmk_chip->pull_up &= ~BIT(offset); 335 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC); 336 } 337 } 338 339 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip, 340 unsigned offset, bool lowemi) 341 { 342 bool enabled = nmk_chip->lowemi & BIT(offset); 343 344 if (lowemi == enabled) 345 return; 346 347 if (lowemi) 348 nmk_chip->lowemi |= BIT(offset); 349 else 350 nmk_chip->lowemi &= ~BIT(offset); 351 352 writel_relaxed(nmk_chip->lowemi, 353 nmk_chip->addr + NMK_GPIO_LOWEMI); 354 } 355 356 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, 357 unsigned offset) 358 { 359 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC); 360 } 361 362 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, 363 unsigned offset, int val) 364 { 365 if (val) 366 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS); 367 else 368 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC); 369 } 370 371 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, 372 unsigned offset, int val) 373 { 374 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRS); 375 __nmk_gpio_set_output(nmk_chip, offset, val); 376 } 377 378 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, 379 unsigned offset, int gpio_mode, 380 bool glitch) 381 { 382 u32 rwimsc = nmk_chip->rwimsc; 383 u32 fwimsc = nmk_chip->fwimsc; 384 385 if (glitch && nmk_chip->set_ioforce) { 386 u32 bit = BIT(offset); 387 388 /* Prevent spurious wakeups */ 389 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC); 390 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC); 391 392 nmk_chip->set_ioforce(true); 393 } 394 395 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode); 396 397 if (glitch && nmk_chip->set_ioforce) { 398 nmk_chip->set_ioforce(false); 399 400 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC); 401 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC); 402 } 403 } 404 405 static void 406 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset) 407 { 408 u32 falling = nmk_chip->fimsc & BIT(offset); 409 u32 rising = nmk_chip->rimsc & BIT(offset); 410 int gpio = nmk_chip->chip.base + offset; 411 int irq = irq_find_mapping(nmk_chip->chip.irq.domain, offset); 412 struct irq_data *d = irq_get_irq_data(irq); 413 414 if (!rising && !falling) 415 return; 416 417 if (!d || !irqd_irq_disabled(d)) 418 return; 419 420 if (rising) { 421 nmk_chip->rimsc &= ~BIT(offset); 422 writel_relaxed(nmk_chip->rimsc, 423 nmk_chip->addr + NMK_GPIO_RIMSC); 424 } 425 426 if (falling) { 427 nmk_chip->fimsc &= ~BIT(offset); 428 writel_relaxed(nmk_chip->fimsc, 429 nmk_chip->addr + NMK_GPIO_FIMSC); 430 } 431 432 dev_dbg(nmk_chip->chip.parent, "%d: clearing interrupt mask\n", gpio); 433 } 434 435 static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value) 436 { 437 u32 val; 438 439 val = readl(reg); 440 val = ((val & ~mask) | (value & mask)); 441 writel(val, reg); 442 } 443 444 static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct, 445 unsigned offset, unsigned alt_num) 446 { 447 int i; 448 u16 reg; 449 u8 bit; 450 u8 alt_index; 451 const struct prcm_gpiocr_altcx_pin_desc *pin_desc; 452 const u16 *gpiocr_regs; 453 454 if (!npct->prcm_base) 455 return; 456 457 if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) { 458 dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n", 459 alt_num); 460 return; 461 } 462 463 for (i = 0 ; i < npct->soc->npins_altcx ; i++) { 464 if (npct->soc->altcx_pins[i].pin == offset) 465 break; 466 } 467 if (i == npct->soc->npins_altcx) { 468 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n", 469 offset); 470 return; 471 } 472 473 pin_desc = npct->soc->altcx_pins + i; 474 gpiocr_regs = npct->soc->prcm_gpiocr_registers; 475 476 /* 477 * If alt_num is NULL, just clear current ALTCx selection 478 * to make sure we come back to a pure ALTC selection 479 */ 480 if (!alt_num) { 481 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { 482 if (pin_desc->altcx[i].used == true) { 483 reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; 484 bit = pin_desc->altcx[i].control_bit; 485 if (readl(npct->prcm_base + reg) & BIT(bit)) { 486 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); 487 dev_dbg(npct->dev, 488 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", 489 offset, i+1); 490 } 491 } 492 } 493 return; 494 } 495 496 alt_index = alt_num - 1; 497 if (pin_desc->altcx[alt_index].used == false) { 498 dev_warn(npct->dev, 499 "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n", 500 offset, alt_num); 501 return; 502 } 503 504 /* 505 * Check if any other ALTCx functions are activated on this pin 506 * and disable it first. 507 */ 508 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { 509 if (i == alt_index) 510 continue; 511 if (pin_desc->altcx[i].used == true) { 512 reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; 513 bit = pin_desc->altcx[i].control_bit; 514 if (readl(npct->prcm_base + reg) & BIT(bit)) { 515 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); 516 dev_dbg(npct->dev, 517 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", 518 offset, i+1); 519 } 520 } 521 } 522 523 reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index]; 524 bit = pin_desc->altcx[alt_index].control_bit; 525 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n", 526 offset, alt_index+1); 527 nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit)); 528 } 529 530 /* 531 * Safe sequence used to switch IOs between GPIO and Alternate-C mode: 532 * - Save SLPM registers 533 * - Set SLPM=0 for the IOs you want to switch and others to 1 534 * - Configure the GPIO registers for the IOs that are being switched 535 * - Set IOFORCE=1 536 * - Modify the AFLSA/B registers for the IOs that are being switched 537 * - Set IOFORCE=0 538 * - Restore SLPM registers 539 * - Any spurious wake up event during switch sequence to be ignored and 540 * cleared 541 */ 542 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm) 543 { 544 int i; 545 546 for (i = 0; i < NUM_BANKS; i++) { 547 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 548 unsigned int temp = slpm[i]; 549 550 if (!chip) 551 break; 552 553 clk_enable(chip->clk); 554 555 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC); 556 writel(temp, chip->addr + NMK_GPIO_SLPC); 557 } 558 } 559 560 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm) 561 { 562 int i; 563 564 for (i = 0; i < NUM_BANKS; i++) { 565 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 566 567 if (!chip) 568 break; 569 570 writel(slpm[i], chip->addr + NMK_GPIO_SLPC); 571 572 clk_disable(chip->clk); 573 } 574 } 575 576 static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio) 577 { 578 int i; 579 u16 reg; 580 u8 bit; 581 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 582 const struct prcm_gpiocr_altcx_pin_desc *pin_desc; 583 const u16 *gpiocr_regs; 584 585 if (!npct->prcm_base) 586 return NMK_GPIO_ALT_C; 587 588 for (i = 0; i < npct->soc->npins_altcx; i++) { 589 if (npct->soc->altcx_pins[i].pin == gpio) 590 break; 591 } 592 if (i == npct->soc->npins_altcx) 593 return NMK_GPIO_ALT_C; 594 595 pin_desc = npct->soc->altcx_pins + i; 596 gpiocr_regs = npct->soc->prcm_gpiocr_registers; 597 for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) { 598 if (pin_desc->altcx[i].used == true) { 599 reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; 600 bit = pin_desc->altcx[i].control_bit; 601 if (readl(npct->prcm_base + reg) & BIT(bit)) 602 return NMK_GPIO_ALT_C+i+1; 603 } 604 } 605 return NMK_GPIO_ALT_C; 606 } 607 608 /* IRQ functions */ 609 610 static void nmk_gpio_irq_ack(struct irq_data *d) 611 { 612 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 613 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 614 615 clk_enable(nmk_chip->clk); 616 writel(BIT(d->hwirq), nmk_chip->addr + NMK_GPIO_IC); 617 clk_disable(nmk_chip->clk); 618 } 619 620 enum nmk_gpio_irq_type { 621 NORMAL, 622 WAKE, 623 }; 624 625 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, 626 int offset, enum nmk_gpio_irq_type which, 627 bool enable) 628 { 629 u32 *rimscval; 630 u32 *fimscval; 631 u32 rimscreg; 632 u32 fimscreg; 633 634 if (which == NORMAL) { 635 rimscreg = NMK_GPIO_RIMSC; 636 fimscreg = NMK_GPIO_FIMSC; 637 rimscval = &nmk_chip->rimsc; 638 fimscval = &nmk_chip->fimsc; 639 } else { 640 rimscreg = NMK_GPIO_RWIMSC; 641 fimscreg = NMK_GPIO_FWIMSC; 642 rimscval = &nmk_chip->rwimsc; 643 fimscval = &nmk_chip->fwimsc; 644 } 645 646 /* we must individually set/clear the two edges */ 647 if (nmk_chip->edge_rising & BIT(offset)) { 648 if (enable) 649 *rimscval |= BIT(offset); 650 else 651 *rimscval &= ~BIT(offset); 652 writel(*rimscval, nmk_chip->addr + rimscreg); 653 } 654 if (nmk_chip->edge_falling & BIT(offset)) { 655 if (enable) 656 *fimscval |= BIT(offset); 657 else 658 *fimscval &= ~BIT(offset); 659 writel(*fimscval, nmk_chip->addr + fimscreg); 660 } 661 } 662 663 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, 664 int offset, bool on) 665 { 666 /* 667 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is 668 * disabled, since setting SLPM to 1 increases power consumption, and 669 * wakeup is anyhow controlled by the RIMSC and FIMSC registers. 670 */ 671 if (nmk_chip->sleepmode && on) { 672 __nmk_gpio_set_slpm(nmk_chip, offset, 673 NMK_GPIO_SLPM_WAKEUP_ENABLE); 674 } 675 676 __nmk_gpio_irq_modify(nmk_chip, offset, WAKE, on); 677 } 678 679 static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) 680 { 681 struct nmk_gpio_chip *nmk_chip; 682 unsigned long flags; 683 684 nmk_chip = irq_data_get_irq_chip_data(d); 685 if (!nmk_chip) 686 return -EINVAL; 687 688 clk_enable(nmk_chip->clk); 689 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 690 spin_lock(&nmk_chip->lock); 691 692 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable); 693 694 if (!(nmk_chip->real_wake & BIT(d->hwirq))) 695 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable); 696 697 spin_unlock(&nmk_chip->lock); 698 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 699 clk_disable(nmk_chip->clk); 700 701 return 0; 702 } 703 704 static void nmk_gpio_irq_mask(struct irq_data *d) 705 { 706 nmk_gpio_irq_maskunmask(d, false); 707 } 708 709 static void nmk_gpio_irq_unmask(struct irq_data *d) 710 { 711 nmk_gpio_irq_maskunmask(d, true); 712 } 713 714 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 715 { 716 struct nmk_gpio_chip *nmk_chip; 717 unsigned long flags; 718 719 nmk_chip = irq_data_get_irq_chip_data(d); 720 if (!nmk_chip) 721 return -EINVAL; 722 723 clk_enable(nmk_chip->clk); 724 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 725 spin_lock(&nmk_chip->lock); 726 727 if (irqd_irq_disabled(d)) 728 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on); 729 730 if (on) 731 nmk_chip->real_wake |= BIT(d->hwirq); 732 else 733 nmk_chip->real_wake &= ~BIT(d->hwirq); 734 735 spin_unlock(&nmk_chip->lock); 736 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 737 clk_disable(nmk_chip->clk); 738 739 return 0; 740 } 741 742 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) 743 { 744 bool enabled = !irqd_irq_disabled(d); 745 bool wake = irqd_is_wakeup_set(d); 746 struct nmk_gpio_chip *nmk_chip; 747 unsigned long flags; 748 749 nmk_chip = irq_data_get_irq_chip_data(d); 750 if (!nmk_chip) 751 return -EINVAL; 752 if (type & IRQ_TYPE_LEVEL_HIGH) 753 return -EINVAL; 754 if (type & IRQ_TYPE_LEVEL_LOW) 755 return -EINVAL; 756 757 clk_enable(nmk_chip->clk); 758 spin_lock_irqsave(&nmk_chip->lock, flags); 759 760 if (enabled) 761 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false); 762 763 if (enabled || wake) 764 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false); 765 766 nmk_chip->edge_rising &= ~BIT(d->hwirq); 767 if (type & IRQ_TYPE_EDGE_RISING) 768 nmk_chip->edge_rising |= BIT(d->hwirq); 769 770 nmk_chip->edge_falling &= ~BIT(d->hwirq); 771 if (type & IRQ_TYPE_EDGE_FALLING) 772 nmk_chip->edge_falling |= BIT(d->hwirq); 773 774 if (enabled) 775 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true); 776 777 if (enabled || wake) 778 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true); 779 780 spin_unlock_irqrestore(&nmk_chip->lock, flags); 781 clk_disable(nmk_chip->clk); 782 783 return 0; 784 } 785 786 static unsigned int nmk_gpio_irq_startup(struct irq_data *d) 787 { 788 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); 789 790 clk_enable(nmk_chip->clk); 791 nmk_gpio_irq_unmask(d); 792 return 0; 793 } 794 795 static void nmk_gpio_irq_shutdown(struct irq_data *d) 796 { 797 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); 798 799 nmk_gpio_irq_mask(d); 800 clk_disable(nmk_chip->clk); 801 } 802 803 static void __nmk_gpio_irq_handler(struct irq_desc *desc, u32 status) 804 { 805 struct irq_chip *host_chip = irq_desc_get_chip(desc); 806 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 807 808 chained_irq_enter(host_chip, desc); 809 810 while (status) { 811 int bit = __ffs(status); 812 813 generic_handle_irq(irq_find_mapping(chip->irq.domain, bit)); 814 status &= ~BIT(bit); 815 } 816 817 chained_irq_exit(host_chip, desc); 818 } 819 820 static void nmk_gpio_irq_handler(struct irq_desc *desc) 821 { 822 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 823 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 824 u32 status; 825 826 clk_enable(nmk_chip->clk); 827 status = readl(nmk_chip->addr + NMK_GPIO_IS); 828 clk_disable(nmk_chip->clk); 829 830 __nmk_gpio_irq_handler(desc, status); 831 } 832 833 /* I/O Functions */ 834 835 static int nmk_gpio_get_dir(struct gpio_chip *chip, unsigned offset) 836 { 837 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 838 int dir; 839 840 clk_enable(nmk_chip->clk); 841 842 dir = !(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset)); 843 844 clk_disable(nmk_chip->clk); 845 846 return dir; 847 } 848 849 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) 850 { 851 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 852 853 clk_enable(nmk_chip->clk); 854 855 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC); 856 857 clk_disable(nmk_chip->clk); 858 859 return 0; 860 } 861 862 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset) 863 { 864 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 865 int value; 866 867 clk_enable(nmk_chip->clk); 868 869 value = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset)); 870 871 clk_disable(nmk_chip->clk); 872 873 return value; 874 } 875 876 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset, 877 int val) 878 { 879 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 880 881 clk_enable(nmk_chip->clk); 882 883 __nmk_gpio_set_output(nmk_chip, offset, val); 884 885 clk_disable(nmk_chip->clk); 886 } 887 888 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, 889 int val) 890 { 891 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 892 893 clk_enable(nmk_chip->clk); 894 895 __nmk_gpio_make_output(nmk_chip, offset, val); 896 897 clk_disable(nmk_chip->clk); 898 899 return 0; 900 } 901 902 #ifdef CONFIG_DEBUG_FS 903 static int nmk_gpio_get_mode(struct nmk_gpio_chip *nmk_chip, int offset) 904 { 905 u32 afunc, bfunc; 906 907 clk_enable(nmk_chip->clk); 908 909 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & BIT(offset); 910 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & BIT(offset); 911 912 clk_disable(nmk_chip->clk); 913 914 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0); 915 } 916 917 #include <linux/seq_file.h> 918 919 static void nmk_gpio_dbg_show_one(struct seq_file *s, 920 struct pinctrl_dev *pctldev, struct gpio_chip *chip, 921 unsigned offset, unsigned gpio) 922 { 923 const char *label = gpiochip_is_requested(chip, offset); 924 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 925 int mode; 926 bool is_out; 927 bool data_out; 928 bool pull; 929 const char *modes[] = { 930 [NMK_GPIO_ALT_GPIO] = "gpio", 931 [NMK_GPIO_ALT_A] = "altA", 932 [NMK_GPIO_ALT_B] = "altB", 933 [NMK_GPIO_ALT_C] = "altC", 934 [NMK_GPIO_ALT_C+1] = "altC1", 935 [NMK_GPIO_ALT_C+2] = "altC2", 936 [NMK_GPIO_ALT_C+3] = "altC3", 937 [NMK_GPIO_ALT_C+4] = "altC4", 938 }; 939 const char *pulls[] = { 940 "none ", 941 "pull down", 942 "pull up ", 943 }; 944 945 clk_enable(nmk_chip->clk); 946 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset)); 947 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & BIT(offset)); 948 data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset)); 949 mode = nmk_gpio_get_mode(nmk_chip, offset); 950 if ((mode == NMK_GPIO_ALT_C) && pctldev) 951 mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio); 952 953 if (is_out) { 954 seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s", 955 gpio, 956 label ?: "(none)", 957 data_out ? "hi" : "lo", 958 (mode < 0) ? "unknown" : modes[mode]); 959 } else { 960 int irq = chip->to_irq(chip, offset); 961 struct irq_desc *desc = irq_to_desc(irq); 962 int pullidx = 0; 963 int val; 964 965 if (pull) 966 pullidx = data_out ? 2 : 1; 967 968 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s", 969 gpio, 970 label ?: "(none)", 971 pulls[pullidx], 972 (mode < 0) ? "unknown" : modes[mode]); 973 974 val = nmk_gpio_get_input(chip, offset); 975 seq_printf(s, " VAL %d", val); 976 977 /* 978 * This races with request_irq(), set_irq_type(), 979 * and set_irq_wake() ... but those are "rare". 980 */ 981 if (irq > 0 && desc && desc->action) { 982 char *trigger; 983 984 if (nmk_chip->edge_rising & BIT(offset)) 985 trigger = "edge-rising"; 986 else if (nmk_chip->edge_falling & BIT(offset)) 987 trigger = "edge-falling"; 988 else 989 trigger = "edge-undefined"; 990 991 seq_printf(s, " irq-%d %s%s", 992 irq, trigger, 993 irqd_is_wakeup_set(&desc->irq_data) 994 ? " wakeup" : ""); 995 } 996 } 997 clk_disable(nmk_chip->clk); 998 } 999 1000 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 1001 { 1002 unsigned i; 1003 unsigned gpio = chip->base; 1004 1005 for (i = 0; i < chip->ngpio; i++, gpio++) { 1006 nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio); 1007 seq_printf(s, "\n"); 1008 } 1009 } 1010 1011 #else 1012 static inline void nmk_gpio_dbg_show_one(struct seq_file *s, 1013 struct pinctrl_dev *pctldev, 1014 struct gpio_chip *chip, 1015 unsigned offset, unsigned gpio) 1016 { 1017 } 1018 #define nmk_gpio_dbg_show NULL 1019 #endif 1020 1021 /* 1022 * We will allocate memory for the state container using devm* allocators 1023 * binding to the first device reaching this point, it doesn't matter if 1024 * it is the pin controller or GPIO driver. However we need to use the right 1025 * platform device when looking up resources so pay attention to pdev. 1026 */ 1027 static struct nmk_gpio_chip *nmk_gpio_populate_chip(struct device_node *np, 1028 struct platform_device *pdev) 1029 { 1030 struct nmk_gpio_chip *nmk_chip; 1031 struct platform_device *gpio_pdev; 1032 struct gpio_chip *chip; 1033 struct resource *res; 1034 struct clk *clk; 1035 void __iomem *base; 1036 u32 id; 1037 1038 gpio_pdev = of_find_device_by_node(np); 1039 if (!gpio_pdev) { 1040 pr_err("populate \"%pOFn\": device not found\n", np); 1041 return ERR_PTR(-ENODEV); 1042 } 1043 if (of_property_read_u32(np, "gpio-bank", &id)) { 1044 dev_err(&pdev->dev, "populate: gpio-bank property not found\n"); 1045 platform_device_put(gpio_pdev); 1046 return ERR_PTR(-EINVAL); 1047 } 1048 1049 /* Already populated? */ 1050 nmk_chip = nmk_gpio_chips[id]; 1051 if (nmk_chip) { 1052 platform_device_put(gpio_pdev); 1053 return nmk_chip; 1054 } 1055 1056 nmk_chip = devm_kzalloc(&pdev->dev, sizeof(*nmk_chip), GFP_KERNEL); 1057 if (!nmk_chip) { 1058 platform_device_put(gpio_pdev); 1059 return ERR_PTR(-ENOMEM); 1060 } 1061 1062 nmk_chip->bank = id; 1063 chip = &nmk_chip->chip; 1064 chip->base = id * NMK_GPIO_PER_CHIP; 1065 chip->ngpio = NMK_GPIO_PER_CHIP; 1066 chip->label = dev_name(&gpio_pdev->dev); 1067 chip->parent = &gpio_pdev->dev; 1068 1069 res = platform_get_resource(gpio_pdev, IORESOURCE_MEM, 0); 1070 base = devm_ioremap_resource(&pdev->dev, res); 1071 if (IS_ERR(base)) { 1072 platform_device_put(gpio_pdev); 1073 return ERR_CAST(base); 1074 } 1075 nmk_chip->addr = base; 1076 1077 clk = clk_get(&gpio_pdev->dev, NULL); 1078 if (IS_ERR(clk)) { 1079 platform_device_put(gpio_pdev); 1080 return (void *) clk; 1081 } 1082 clk_prepare(clk); 1083 nmk_chip->clk = clk; 1084 1085 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); 1086 nmk_gpio_chips[id] = nmk_chip; 1087 return nmk_chip; 1088 } 1089 1090 static int nmk_gpio_probe(struct platform_device *dev) 1091 { 1092 struct device_node *np = dev->dev.of_node; 1093 struct nmk_gpio_chip *nmk_chip; 1094 struct gpio_chip *chip; 1095 struct irq_chip *irqchip; 1096 bool supports_sleepmode; 1097 int irq; 1098 int ret; 1099 1100 nmk_chip = nmk_gpio_populate_chip(np, dev); 1101 if (IS_ERR(nmk_chip)) { 1102 dev_err(&dev->dev, "could not populate nmk chip struct\n"); 1103 return PTR_ERR(nmk_chip); 1104 } 1105 1106 supports_sleepmode = 1107 of_property_read_bool(np, "st,supports-sleepmode"); 1108 1109 /* Correct platform device ID */ 1110 dev->id = nmk_chip->bank; 1111 1112 irq = platform_get_irq(dev, 0); 1113 if (irq < 0) 1114 return irq; 1115 1116 /* 1117 * The virt address in nmk_chip->addr is in the nomadik register space, 1118 * so we can simply convert the resource address, without remapping 1119 */ 1120 nmk_chip->parent_irq = irq; 1121 nmk_chip->sleepmode = supports_sleepmode; 1122 spin_lock_init(&nmk_chip->lock); 1123 1124 chip = &nmk_chip->chip; 1125 chip->request = gpiochip_generic_request; 1126 chip->free = gpiochip_generic_free; 1127 chip->get_direction = nmk_gpio_get_dir; 1128 chip->direction_input = nmk_gpio_make_input; 1129 chip->get = nmk_gpio_get_input; 1130 chip->direction_output = nmk_gpio_make_output; 1131 chip->set = nmk_gpio_set_output; 1132 chip->dbg_show = nmk_gpio_dbg_show; 1133 chip->can_sleep = false; 1134 chip->owner = THIS_MODULE; 1135 1136 irqchip = &nmk_chip->irqchip; 1137 irqchip->irq_ack = nmk_gpio_irq_ack; 1138 irqchip->irq_mask = nmk_gpio_irq_mask; 1139 irqchip->irq_unmask = nmk_gpio_irq_unmask; 1140 irqchip->irq_set_type = nmk_gpio_irq_set_type; 1141 irqchip->irq_set_wake = nmk_gpio_irq_set_wake; 1142 irqchip->irq_startup = nmk_gpio_irq_startup; 1143 irqchip->irq_shutdown = nmk_gpio_irq_shutdown; 1144 irqchip->flags = IRQCHIP_MASK_ON_SUSPEND; 1145 irqchip->name = kasprintf(GFP_KERNEL, "nmk%u-%u-%u", 1146 dev->id, 1147 chip->base, 1148 chip->base + chip->ngpio - 1); 1149 1150 clk_enable(nmk_chip->clk); 1151 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); 1152 clk_disable(nmk_chip->clk); 1153 chip->of_node = np; 1154 1155 ret = gpiochip_add_data(chip, nmk_chip); 1156 if (ret) 1157 return ret; 1158 1159 platform_set_drvdata(dev, nmk_chip); 1160 1161 /* 1162 * Let the generic code handle this edge IRQ, the the chained 1163 * handler will perform the actual work of handling the parent 1164 * interrupt. 1165 */ 1166 ret = gpiochip_irqchip_add(chip, 1167 irqchip, 1168 0, 1169 handle_edge_irq, 1170 IRQ_TYPE_NONE); 1171 if (ret) { 1172 dev_err(&dev->dev, "could not add irqchip\n"); 1173 gpiochip_remove(&nmk_chip->chip); 1174 return -ENODEV; 1175 } 1176 /* Then register the chain on the parent IRQ */ 1177 gpiochip_set_chained_irqchip(chip, 1178 irqchip, 1179 nmk_chip->parent_irq, 1180 nmk_gpio_irq_handler); 1181 1182 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr); 1183 1184 return 0; 1185 } 1186 1187 static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev) 1188 { 1189 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1190 1191 return npct->soc->ngroups; 1192 } 1193 1194 static const char *nmk_get_group_name(struct pinctrl_dev *pctldev, 1195 unsigned selector) 1196 { 1197 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1198 1199 return npct->soc->groups[selector].name; 1200 } 1201 1202 static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, 1203 const unsigned **pins, 1204 unsigned *num_pins) 1205 { 1206 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1207 1208 *pins = npct->soc->groups[selector].pins; 1209 *num_pins = npct->soc->groups[selector].npins; 1210 return 0; 1211 } 1212 1213 static struct nmk_gpio_chip *find_nmk_gpio_from_pin(unsigned pin) 1214 { 1215 int i; 1216 struct nmk_gpio_chip *nmk_gpio; 1217 1218 for(i = 0; i < NMK_MAX_BANKS; i++) { 1219 nmk_gpio = nmk_gpio_chips[i]; 1220 if (!nmk_gpio) 1221 continue; 1222 if (pin >= nmk_gpio->chip.base && 1223 pin < nmk_gpio->chip.base + nmk_gpio->chip.ngpio) 1224 return nmk_gpio; 1225 } 1226 return NULL; 1227 } 1228 1229 static struct gpio_chip *find_gc_from_pin(unsigned pin) 1230 { 1231 struct nmk_gpio_chip *nmk_gpio = find_nmk_gpio_from_pin(pin); 1232 1233 if (nmk_gpio) 1234 return &nmk_gpio->chip; 1235 return NULL; 1236 } 1237 1238 static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 1239 unsigned offset) 1240 { 1241 struct gpio_chip *chip = find_gc_from_pin(offset); 1242 1243 if (!chip) { 1244 seq_printf(s, "invalid pin offset"); 1245 return; 1246 } 1247 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset); 1248 } 1249 1250 static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps, 1251 unsigned *num_maps, const char *group, 1252 const char *function) 1253 { 1254 if (*num_maps == *reserved_maps) 1255 return -ENOSPC; 1256 1257 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 1258 (*map)[*num_maps].data.mux.group = group; 1259 (*map)[*num_maps].data.mux.function = function; 1260 (*num_maps)++; 1261 1262 return 0; 1263 } 1264 1265 static int nmk_dt_add_map_configs(struct pinctrl_map **map, 1266 unsigned *reserved_maps, 1267 unsigned *num_maps, const char *group, 1268 unsigned long *configs, unsigned num_configs) 1269 { 1270 unsigned long *dup_configs; 1271 1272 if (*num_maps == *reserved_maps) 1273 return -ENOSPC; 1274 1275 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), 1276 GFP_KERNEL); 1277 if (!dup_configs) 1278 return -ENOMEM; 1279 1280 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN; 1281 1282 (*map)[*num_maps].data.configs.group_or_pin = group; 1283 (*map)[*num_maps].data.configs.configs = dup_configs; 1284 (*map)[*num_maps].data.configs.num_configs = num_configs; 1285 (*num_maps)++; 1286 1287 return 0; 1288 } 1289 1290 #define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, } 1291 #define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \ 1292 .size = ARRAY_SIZE(y), } 1293 1294 static const unsigned long nmk_pin_input_modes[] = { 1295 PIN_INPUT_NOPULL, 1296 PIN_INPUT_PULLUP, 1297 PIN_INPUT_PULLDOWN, 1298 }; 1299 1300 static const unsigned long nmk_pin_output_modes[] = { 1301 PIN_OUTPUT_LOW, 1302 PIN_OUTPUT_HIGH, 1303 PIN_DIR_OUTPUT, 1304 }; 1305 1306 static const unsigned long nmk_pin_sleep_modes[] = { 1307 PIN_SLEEPMODE_DISABLED, 1308 PIN_SLEEPMODE_ENABLED, 1309 }; 1310 1311 static const unsigned long nmk_pin_sleep_input_modes[] = { 1312 PIN_SLPM_INPUT_NOPULL, 1313 PIN_SLPM_INPUT_PULLUP, 1314 PIN_SLPM_INPUT_PULLDOWN, 1315 PIN_SLPM_DIR_INPUT, 1316 }; 1317 1318 static const unsigned long nmk_pin_sleep_output_modes[] = { 1319 PIN_SLPM_OUTPUT_LOW, 1320 PIN_SLPM_OUTPUT_HIGH, 1321 PIN_SLPM_DIR_OUTPUT, 1322 }; 1323 1324 static const unsigned long nmk_pin_sleep_wakeup_modes[] = { 1325 PIN_SLPM_WAKEUP_DISABLE, 1326 PIN_SLPM_WAKEUP_ENABLE, 1327 }; 1328 1329 static const unsigned long nmk_pin_gpio_modes[] = { 1330 PIN_GPIOMODE_DISABLED, 1331 PIN_GPIOMODE_ENABLED, 1332 }; 1333 1334 static const unsigned long nmk_pin_sleep_pdis_modes[] = { 1335 PIN_SLPM_PDIS_DISABLED, 1336 PIN_SLPM_PDIS_ENABLED, 1337 }; 1338 1339 struct nmk_cfg_param { 1340 const char *property; 1341 unsigned long config; 1342 const unsigned long *choice; 1343 int size; 1344 }; 1345 1346 static const struct nmk_cfg_param nmk_cfg_params[] = { 1347 NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes), 1348 NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes), 1349 NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes), 1350 NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes), 1351 NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes), 1352 NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes), 1353 NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes), 1354 NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes), 1355 }; 1356 1357 static int nmk_dt_pin_config(int index, int val, unsigned long *config) 1358 { 1359 int ret = 0; 1360 1361 if (nmk_cfg_params[index].choice == NULL) 1362 *config = nmk_cfg_params[index].config; 1363 else { 1364 /* test if out of range */ 1365 if (val < nmk_cfg_params[index].size) { 1366 *config = nmk_cfg_params[index].config | 1367 nmk_cfg_params[index].choice[val]; 1368 } 1369 } 1370 return ret; 1371 } 1372 1373 static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name) 1374 { 1375 int i, pin_number; 1376 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1377 1378 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1) 1379 for (i = 0; i < npct->soc->npins; i++) 1380 if (npct->soc->pins[i].number == pin_number) 1381 return npct->soc->pins[i].name; 1382 return NULL; 1383 } 1384 1385 static bool nmk_pinctrl_dt_get_config(struct device_node *np, 1386 unsigned long *configs) 1387 { 1388 bool has_config = 0; 1389 unsigned long cfg = 0; 1390 int i, val, ret; 1391 1392 for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) { 1393 ret = of_property_read_u32(np, 1394 nmk_cfg_params[i].property, &val); 1395 if (ret != -EINVAL) { 1396 if (nmk_dt_pin_config(i, val, &cfg) == 0) { 1397 *configs |= cfg; 1398 has_config = 1; 1399 } 1400 } 1401 } 1402 1403 return has_config; 1404 } 1405 1406 static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 1407 struct device_node *np, 1408 struct pinctrl_map **map, 1409 unsigned *reserved_maps, 1410 unsigned *num_maps) 1411 { 1412 int ret; 1413 const char *function = NULL; 1414 unsigned long configs = 0; 1415 bool has_config = 0; 1416 struct property *prop; 1417 struct device_node *np_config; 1418 1419 ret = of_property_read_string(np, "function", &function); 1420 if (ret >= 0) { 1421 const char *group; 1422 1423 ret = of_property_count_strings(np, "groups"); 1424 if (ret < 0) 1425 goto exit; 1426 1427 ret = pinctrl_utils_reserve_map(pctldev, map, 1428 reserved_maps, 1429 num_maps, ret); 1430 if (ret < 0) 1431 goto exit; 1432 1433 of_property_for_each_string(np, "groups", prop, group) { 1434 ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps, 1435 group, function); 1436 if (ret < 0) 1437 goto exit; 1438 } 1439 } 1440 1441 has_config = nmk_pinctrl_dt_get_config(np, &configs); 1442 np_config = of_parse_phandle(np, "ste,config", 0); 1443 if (np_config) 1444 has_config |= nmk_pinctrl_dt_get_config(np_config, &configs); 1445 if (has_config) { 1446 const char *gpio_name; 1447 const char *pin; 1448 1449 ret = of_property_count_strings(np, "pins"); 1450 if (ret < 0) 1451 goto exit; 1452 ret = pinctrl_utils_reserve_map(pctldev, map, 1453 reserved_maps, 1454 num_maps, ret); 1455 if (ret < 0) 1456 goto exit; 1457 1458 of_property_for_each_string(np, "pins", prop, pin) { 1459 gpio_name = nmk_find_pin_name(pctldev, pin); 1460 1461 ret = nmk_dt_add_map_configs(map, reserved_maps, 1462 num_maps, 1463 gpio_name, &configs, 1); 1464 if (ret < 0) 1465 goto exit; 1466 } 1467 } 1468 1469 exit: 1470 return ret; 1471 } 1472 1473 static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 1474 struct device_node *np_config, 1475 struct pinctrl_map **map, unsigned *num_maps) 1476 { 1477 unsigned reserved_maps; 1478 struct device_node *np; 1479 int ret; 1480 1481 reserved_maps = 0; 1482 *map = NULL; 1483 *num_maps = 0; 1484 1485 for_each_child_of_node(np_config, np) { 1486 ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map, 1487 &reserved_maps, num_maps); 1488 if (ret < 0) { 1489 pinctrl_utils_free_map(pctldev, *map, *num_maps); 1490 of_node_put(np); 1491 return ret; 1492 } 1493 } 1494 1495 return 0; 1496 } 1497 1498 static const struct pinctrl_ops nmk_pinctrl_ops = { 1499 .get_groups_count = nmk_get_groups_cnt, 1500 .get_group_name = nmk_get_group_name, 1501 .get_group_pins = nmk_get_group_pins, 1502 .pin_dbg_show = nmk_pin_dbg_show, 1503 .dt_node_to_map = nmk_pinctrl_dt_node_to_map, 1504 .dt_free_map = pinctrl_utils_free_map, 1505 }; 1506 1507 static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 1508 { 1509 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1510 1511 return npct->soc->nfunctions; 1512 } 1513 1514 static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev, 1515 unsigned function) 1516 { 1517 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1518 1519 return npct->soc->functions[function].name; 1520 } 1521 1522 static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev, 1523 unsigned function, 1524 const char * const **groups, 1525 unsigned * const num_groups) 1526 { 1527 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1528 1529 *groups = npct->soc->functions[function].groups; 1530 *num_groups = npct->soc->functions[function].ngroups; 1531 1532 return 0; 1533 } 1534 1535 static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned function, 1536 unsigned group) 1537 { 1538 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1539 const struct nmk_pingroup *g; 1540 static unsigned int slpm[NUM_BANKS]; 1541 unsigned long flags = 0; 1542 bool glitch; 1543 int ret = -EINVAL; 1544 int i; 1545 1546 g = &npct->soc->groups[group]; 1547 1548 if (g->altsetting < 0) 1549 return -EINVAL; 1550 1551 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins); 1552 1553 /* 1554 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1, 1555 * we may pass through an undesired state. In this case we take 1556 * some extra care. 1557 * 1558 * Safe sequence used to switch IOs between GPIO and Alternate-C mode: 1559 * - Save SLPM registers (since we have a shadow register in the 1560 * nmk_chip we're using that as backup) 1561 * - Set SLPM=0 for the IOs you want to switch and others to 1 1562 * - Configure the GPIO registers for the IOs that are being switched 1563 * - Set IOFORCE=1 1564 * - Modify the AFLSA/B registers for the IOs that are being switched 1565 * - Set IOFORCE=0 1566 * - Restore SLPM registers 1567 * - Any spurious wake up event during switch sequence to be ignored 1568 * and cleared 1569 * 1570 * We REALLY need to save ALL slpm registers, because the external 1571 * IOFORCE will switch *all* ports to their sleepmode setting to as 1572 * to avoid glitches. (Not just one port!) 1573 */ 1574 glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C); 1575 1576 if (glitch) { 1577 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 1578 1579 /* Initially don't put any pins to sleep when switching */ 1580 memset(slpm, 0xff, sizeof(slpm)); 1581 1582 /* 1583 * Then mask the pins that need to be sleeping now when we're 1584 * switching to the ALT C function. 1585 */ 1586 for (i = 0; i < g->npins; i++) 1587 slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]); 1588 nmk_gpio_glitch_slpm_init(slpm); 1589 } 1590 1591 for (i = 0; i < g->npins; i++) { 1592 struct nmk_gpio_chip *nmk_chip; 1593 unsigned bit; 1594 1595 nmk_chip = find_nmk_gpio_from_pin(g->pins[i]); 1596 if (!nmk_chip) { 1597 dev_err(npct->dev, 1598 "invalid pin offset %d in group %s at index %d\n", 1599 g->pins[i], g->name, i); 1600 goto out_glitch; 1601 } 1602 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting); 1603 1604 clk_enable(nmk_chip->clk); 1605 bit = g->pins[i] % NMK_GPIO_PER_CHIP; 1606 /* 1607 * If the pin is switching to altfunc, and there was an 1608 * interrupt installed on it which has been lazy disabled, 1609 * actually mask the interrupt to prevent spurious interrupts 1610 * that would occur while the pin is under control of the 1611 * peripheral. Only SKE does this. 1612 */ 1613 nmk_gpio_disable_lazy_irq(nmk_chip, bit); 1614 1615 __nmk_gpio_set_mode_safe(nmk_chip, bit, 1616 (g->altsetting & NMK_GPIO_ALT_C), glitch); 1617 clk_disable(nmk_chip->clk); 1618 1619 /* 1620 * Call PRCM GPIOCR config function in case ALTC 1621 * has been selected: 1622 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers 1623 * must be set. 1624 * - If selection is pure ALTC and previous selection was ALTCx, 1625 * then some bits in PRCM GPIOCR registers must be cleared. 1626 */ 1627 if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C) 1628 nmk_prcm_altcx_set_mode(npct, g->pins[i], 1629 g->altsetting >> NMK_GPIO_ALT_CX_SHIFT); 1630 } 1631 1632 /* When all pins are successfully reconfigured we get here */ 1633 ret = 0; 1634 1635 out_glitch: 1636 if (glitch) { 1637 nmk_gpio_glitch_slpm_restore(slpm); 1638 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 1639 } 1640 1641 return ret; 1642 } 1643 1644 static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev, 1645 struct pinctrl_gpio_range *range, 1646 unsigned offset) 1647 { 1648 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1649 struct nmk_gpio_chip *nmk_chip; 1650 struct gpio_chip *chip; 1651 unsigned bit; 1652 1653 if (!range) { 1654 dev_err(npct->dev, "invalid range\n"); 1655 return -EINVAL; 1656 } 1657 if (!range->gc) { 1658 dev_err(npct->dev, "missing GPIO chip in range\n"); 1659 return -EINVAL; 1660 } 1661 chip = range->gc; 1662 nmk_chip = gpiochip_get_data(chip); 1663 1664 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); 1665 1666 clk_enable(nmk_chip->clk); 1667 bit = offset % NMK_GPIO_PER_CHIP; 1668 /* There is no glitch when converting any pin to GPIO */ 1669 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); 1670 clk_disable(nmk_chip->clk); 1671 1672 return 0; 1673 } 1674 1675 static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev, 1676 struct pinctrl_gpio_range *range, 1677 unsigned offset) 1678 { 1679 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1680 1681 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); 1682 /* Set the pin to some default state, GPIO is usually default */ 1683 } 1684 1685 static const struct pinmux_ops nmk_pinmux_ops = { 1686 .get_functions_count = nmk_pmx_get_funcs_cnt, 1687 .get_function_name = nmk_pmx_get_func_name, 1688 .get_function_groups = nmk_pmx_get_func_groups, 1689 .set_mux = nmk_pmx_set, 1690 .gpio_request_enable = nmk_gpio_request_enable, 1691 .gpio_disable_free = nmk_gpio_disable_free, 1692 .strict = true, 1693 }; 1694 1695 static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, 1696 unsigned long *config) 1697 { 1698 /* Not implemented */ 1699 return -EINVAL; 1700 } 1701 1702 static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, 1703 unsigned long *configs, unsigned num_configs) 1704 { 1705 static const char *pullnames[] = { 1706 [NMK_GPIO_PULL_NONE] = "none", 1707 [NMK_GPIO_PULL_UP] = "up", 1708 [NMK_GPIO_PULL_DOWN] = "down", 1709 [3] /* illegal */ = "??" 1710 }; 1711 static const char *slpmnames[] = { 1712 [NMK_GPIO_SLPM_INPUT] = "input/wakeup", 1713 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", 1714 }; 1715 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1716 struct nmk_gpio_chip *nmk_chip; 1717 unsigned bit; 1718 pin_cfg_t cfg; 1719 int pull, slpm, output, val, i; 1720 bool lowemi, gpiomode, sleep; 1721 1722 nmk_chip = find_nmk_gpio_from_pin(pin); 1723 if (!nmk_chip) { 1724 dev_err(npct->dev, 1725 "invalid pin offset %d\n", pin); 1726 return -EINVAL; 1727 } 1728 1729 for (i = 0; i < num_configs; i++) { 1730 /* 1731 * The pin config contains pin number and altfunction fields, 1732 * here we just ignore that part. It's being handled by the 1733 * framework and pinmux callback respectively. 1734 */ 1735 cfg = (pin_cfg_t) configs[i]; 1736 pull = PIN_PULL(cfg); 1737 slpm = PIN_SLPM(cfg); 1738 output = PIN_DIR(cfg); 1739 val = PIN_VAL(cfg); 1740 lowemi = PIN_LOWEMI(cfg); 1741 gpiomode = PIN_GPIOMODE(cfg); 1742 sleep = PIN_SLEEPMODE(cfg); 1743 1744 if (sleep) { 1745 int slpm_pull = PIN_SLPM_PULL(cfg); 1746 int slpm_output = PIN_SLPM_DIR(cfg); 1747 int slpm_val = PIN_SLPM_VAL(cfg); 1748 1749 /* All pins go into GPIO mode at sleep */ 1750 gpiomode = true; 1751 1752 /* 1753 * The SLPM_* values are normal values + 1 to allow zero 1754 * to mean "same as normal". 1755 */ 1756 if (slpm_pull) 1757 pull = slpm_pull - 1; 1758 if (slpm_output) 1759 output = slpm_output - 1; 1760 if (slpm_val) 1761 val = slpm_val - 1; 1762 1763 dev_dbg(nmk_chip->chip.parent, 1764 "pin %d: sleep pull %s, dir %s, val %s\n", 1765 pin, 1766 slpm_pull ? pullnames[pull] : "same", 1767 slpm_output ? (output ? "output" : "input") 1768 : "same", 1769 slpm_val ? (val ? "high" : "low") : "same"); 1770 } 1771 1772 dev_dbg(nmk_chip->chip.parent, 1773 "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n", 1774 pin, cfg, pullnames[pull], slpmnames[slpm], 1775 output ? "output " : "input", 1776 output ? (val ? "high" : "low") : "", 1777 lowemi ? "on" : "off"); 1778 1779 clk_enable(nmk_chip->clk); 1780 bit = pin % NMK_GPIO_PER_CHIP; 1781 if (gpiomode) 1782 /* No glitch when going to GPIO mode */ 1783 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); 1784 if (output) 1785 __nmk_gpio_make_output(nmk_chip, bit, val); 1786 else { 1787 __nmk_gpio_make_input(nmk_chip, bit); 1788 __nmk_gpio_set_pull(nmk_chip, bit, pull); 1789 } 1790 /* TODO: isn't this only applicable on output pins? */ 1791 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi); 1792 1793 __nmk_gpio_set_slpm(nmk_chip, bit, slpm); 1794 clk_disable(nmk_chip->clk); 1795 } /* for each config */ 1796 1797 return 0; 1798 } 1799 1800 static const struct pinconf_ops nmk_pinconf_ops = { 1801 .pin_config_get = nmk_pin_config_get, 1802 .pin_config_set = nmk_pin_config_set, 1803 }; 1804 1805 static struct pinctrl_desc nmk_pinctrl_desc = { 1806 .name = "pinctrl-nomadik", 1807 .pctlops = &nmk_pinctrl_ops, 1808 .pmxops = &nmk_pinmux_ops, 1809 .confops = &nmk_pinconf_ops, 1810 .owner = THIS_MODULE, 1811 }; 1812 1813 static const struct of_device_id nmk_pinctrl_match[] = { 1814 { 1815 .compatible = "stericsson,stn8815-pinctrl", 1816 .data = (void *)PINCTRL_NMK_STN8815, 1817 }, 1818 { 1819 .compatible = "stericsson,db8500-pinctrl", 1820 .data = (void *)PINCTRL_NMK_DB8500, 1821 }, 1822 { 1823 .compatible = "stericsson,db8540-pinctrl", 1824 .data = (void *)PINCTRL_NMK_DB8540, 1825 }, 1826 {}, 1827 }; 1828 1829 #ifdef CONFIG_PM_SLEEP 1830 static int nmk_pinctrl_suspend(struct device *dev) 1831 { 1832 struct nmk_pinctrl *npct; 1833 1834 npct = dev_get_drvdata(dev); 1835 if (!npct) 1836 return -EINVAL; 1837 1838 return pinctrl_force_sleep(npct->pctl); 1839 } 1840 1841 static int nmk_pinctrl_resume(struct device *dev) 1842 { 1843 struct nmk_pinctrl *npct; 1844 1845 npct = dev_get_drvdata(dev); 1846 if (!npct) 1847 return -EINVAL; 1848 1849 return pinctrl_force_default(npct->pctl); 1850 } 1851 #endif 1852 1853 static int nmk_pinctrl_probe(struct platform_device *pdev) 1854 { 1855 const struct of_device_id *match; 1856 struct device_node *np = pdev->dev.of_node; 1857 struct device_node *prcm_np; 1858 struct nmk_pinctrl *npct; 1859 unsigned int version = 0; 1860 int i; 1861 1862 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL); 1863 if (!npct) 1864 return -ENOMEM; 1865 1866 match = of_match_device(nmk_pinctrl_match, &pdev->dev); 1867 if (!match) 1868 return -ENODEV; 1869 version = (unsigned int) match->data; 1870 1871 /* Poke in other ASIC variants here */ 1872 if (version == PINCTRL_NMK_STN8815) 1873 nmk_pinctrl_stn8815_init(&npct->soc); 1874 if (version == PINCTRL_NMK_DB8500) 1875 nmk_pinctrl_db8500_init(&npct->soc); 1876 if (version == PINCTRL_NMK_DB8540) 1877 nmk_pinctrl_db8540_init(&npct->soc); 1878 1879 /* 1880 * Since we depend on the GPIO chips to provide clock and register base 1881 * for the pin control operations, make sure that we have these 1882 * populated before we continue. Follow the phandles to instantiate 1883 * them. The GPIO portion of the actual hardware may be probed before 1884 * or after this point: it shouldn't matter as the APIs are orthogonal. 1885 */ 1886 for (i = 0; i < NMK_MAX_BANKS; i++) { 1887 struct device_node *gpio_np; 1888 struct nmk_gpio_chip *nmk_chip; 1889 1890 gpio_np = of_parse_phandle(np, "nomadik-gpio-chips", i); 1891 if (gpio_np) { 1892 dev_info(&pdev->dev, 1893 "populate NMK GPIO %d \"%pOFn\"\n", 1894 i, gpio_np); 1895 nmk_chip = nmk_gpio_populate_chip(gpio_np, pdev); 1896 if (IS_ERR(nmk_chip)) 1897 dev_err(&pdev->dev, 1898 "could not populate nmk chip struct " 1899 "- continue anyway\n"); 1900 of_node_put(gpio_np); 1901 } 1902 } 1903 1904 prcm_np = of_parse_phandle(np, "prcm", 0); 1905 if (prcm_np) 1906 npct->prcm_base = of_iomap(prcm_np, 0); 1907 if (!npct->prcm_base) { 1908 if (version == PINCTRL_NMK_STN8815) { 1909 dev_info(&pdev->dev, 1910 "No PRCM base, " 1911 "assuming no ALT-Cx control is available\n"); 1912 } else { 1913 dev_err(&pdev->dev, "missing PRCM base address\n"); 1914 return -EINVAL; 1915 } 1916 } 1917 1918 nmk_pinctrl_desc.pins = npct->soc->pins; 1919 nmk_pinctrl_desc.npins = npct->soc->npins; 1920 npct->dev = &pdev->dev; 1921 1922 npct->pctl = devm_pinctrl_register(&pdev->dev, &nmk_pinctrl_desc, npct); 1923 if (IS_ERR(npct->pctl)) { 1924 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n"); 1925 return PTR_ERR(npct->pctl); 1926 } 1927 1928 platform_set_drvdata(pdev, npct); 1929 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n"); 1930 1931 return 0; 1932 } 1933 1934 static const struct of_device_id nmk_gpio_match[] = { 1935 { .compatible = "st,nomadik-gpio", }, 1936 {} 1937 }; 1938 1939 static struct platform_driver nmk_gpio_driver = { 1940 .driver = { 1941 .name = "gpio", 1942 .of_match_table = nmk_gpio_match, 1943 }, 1944 .probe = nmk_gpio_probe, 1945 }; 1946 1947 static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops, 1948 nmk_pinctrl_suspend, 1949 nmk_pinctrl_resume); 1950 1951 static struct platform_driver nmk_pinctrl_driver = { 1952 .driver = { 1953 .name = "pinctrl-nomadik", 1954 .of_match_table = nmk_pinctrl_match, 1955 .pm = &nmk_pinctrl_pm_ops, 1956 }, 1957 .probe = nmk_pinctrl_probe, 1958 }; 1959 1960 static int __init nmk_gpio_init(void) 1961 { 1962 return platform_driver_register(&nmk_gpio_driver); 1963 } 1964 subsys_initcall(nmk_gpio_init); 1965 1966 static int __init nmk_pinctrl_init(void) 1967 { 1968 return platform_driver_register(&nmk_pinctrl_driver); 1969 } 1970 core_initcall(nmk_pinctrl_init); 1971