1 /* 2 * Generic GPIO driver for logic cells found in the Nomadik SoC 3 * 4 * Copyright (C) 2008,2009 STMicroelectronics 5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> 6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> 7 * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/init.h> 16 #include <linux/device.h> 17 #include <linux/platform_device.h> 18 #include <linux/io.h> 19 #include <linux/clk.h> 20 #include <linux/err.h> 21 #include <linux/gpio.h> 22 #include <linux/spinlock.h> 23 #include <linux/interrupt.h> 24 #include <linux/slab.h> 25 #include <linux/of_device.h> 26 #include <linux/of_address.h> 27 #include <linux/bitops.h> 28 #include <linux/pinctrl/machine.h> 29 #include <linux/pinctrl/pinctrl.h> 30 #include <linux/pinctrl/pinmux.h> 31 #include <linux/pinctrl/pinconf.h> 32 /* Since we request GPIOs from ourself */ 33 #include <linux/pinctrl/consumer.h> 34 #include "pinctrl-nomadik.h" 35 #include "../core.h" 36 #include "../pinctrl-utils.h" 37 38 /* 39 * The GPIO module in the Nomadik family of Systems-on-Chip is an 40 * AMBA device, managing 32 pins and alternate functions. The logic block 41 * is currently used in the Nomadik and ux500. 42 * 43 * Symbols in this file are called "nmk_gpio" for "nomadik gpio" 44 */ 45 46 /* 47 * pin configurations are represented by 32-bit integers: 48 * 49 * bit 0.. 8 - Pin Number (512 Pins Maximum) 50 * bit 9..10 - Alternate Function Selection 51 * bit 11..12 - Pull up/down state 52 * bit 13 - Sleep mode behaviour 53 * bit 14 - Direction 54 * bit 15 - Value (if output) 55 * bit 16..18 - SLPM pull up/down state 56 * bit 19..20 - SLPM direction 57 * bit 21..22 - SLPM Value (if output) 58 * bit 23..25 - PDIS value (if input) 59 * bit 26 - Gpio mode 60 * bit 27 - Sleep mode 61 * 62 * to facilitate the definition, the following macros are provided 63 * 64 * PIN_CFG_DEFAULT - default config (0): 65 * pull up/down = disabled 66 * sleep mode = input/wakeup 67 * direction = input 68 * value = low 69 * SLPM direction = same as normal 70 * SLPM pull = same as normal 71 * SLPM value = same as normal 72 * 73 * PIN_CFG - default config with alternate function 74 */ 75 76 typedef unsigned long pin_cfg_t; 77 78 #define PIN_NUM_MASK 0x1ff 79 #define PIN_NUM(x) ((x) & PIN_NUM_MASK) 80 81 #define PIN_ALT_SHIFT 9 82 #define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT) 83 #define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT) 84 #define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT) 85 #define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT) 86 #define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT) 87 #define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT) 88 89 #define PIN_PULL_SHIFT 11 90 #define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT) 91 #define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT) 92 #define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT) 93 #define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT) 94 #define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT) 95 96 #define PIN_SLPM_SHIFT 13 97 #define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT) 98 #define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT) 99 #define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT) 100 #define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT) 101 /* These two replace the above in DB8500v2+ */ 102 #define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT) 103 #define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT) 104 #define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE 105 106 #define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */ 107 #define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */ 108 109 #define PIN_DIR_SHIFT 14 110 #define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT) 111 #define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT) 112 #define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT) 113 #define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT) 114 115 #define PIN_VAL_SHIFT 15 116 #define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT) 117 #define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT) 118 #define PIN_VAL_LOW (0 << PIN_VAL_SHIFT) 119 #define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT) 120 121 #define PIN_SLPM_PULL_SHIFT 16 122 #define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT) 123 #define PIN_SLPM_PULL(x) \ 124 (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT) 125 #define PIN_SLPM_PULL_NONE \ 126 ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT) 127 #define PIN_SLPM_PULL_UP \ 128 ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT) 129 #define PIN_SLPM_PULL_DOWN \ 130 ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT) 131 132 #define PIN_SLPM_DIR_SHIFT 19 133 #define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT) 134 #define PIN_SLPM_DIR(x) \ 135 (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT) 136 #define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT) 137 #define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT) 138 139 #define PIN_SLPM_VAL_SHIFT 21 140 #define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT) 141 #define PIN_SLPM_VAL(x) \ 142 (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT) 143 #define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT) 144 #define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT) 145 146 #define PIN_SLPM_PDIS_SHIFT 23 147 #define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT) 148 #define PIN_SLPM_PDIS(x) \ 149 (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT) 150 #define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT) 151 #define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT) 152 #define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT) 153 154 #define PIN_LOWEMI_SHIFT 25 155 #define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT) 156 #define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT) 157 #define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT) 158 #define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT) 159 160 #define PIN_GPIOMODE_SHIFT 26 161 #define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT) 162 #define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT) 163 #define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT) 164 #define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT) 165 166 #define PIN_SLEEPMODE_SHIFT 27 167 #define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT) 168 #define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT) 169 #define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT) 170 #define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT) 171 172 173 /* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */ 174 #define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN) 175 #define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP) 176 #define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE) 177 #define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW) 178 #define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH) 179 180 #define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN) 181 #define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP) 182 #define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE) 183 #define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW) 184 #define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH) 185 186 #define PIN_CFG_DEFAULT (0) 187 188 #define PIN_CFG(num, alt) \ 189 (PIN_CFG_DEFAULT |\ 190 (PIN_NUM(num) | PIN_##alt)) 191 192 #define PIN_CFG_INPUT(num, alt, pull) \ 193 (PIN_CFG_DEFAULT |\ 194 (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull)) 195 196 #define PIN_CFG_OUTPUT(num, alt, val) \ 197 (PIN_CFG_DEFAULT |\ 198 (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val)) 199 200 /* 201 * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving 202 * the "gpio" namespace for generic and cross-machine functions 203 */ 204 205 #define GPIO_BLOCK_SHIFT 5 206 #define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT) 207 #define NMK_MAX_BANKS DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP) 208 209 /* Register in the logic block */ 210 #define NMK_GPIO_DAT 0x00 211 #define NMK_GPIO_DATS 0x04 212 #define NMK_GPIO_DATC 0x08 213 #define NMK_GPIO_PDIS 0x0c 214 #define NMK_GPIO_DIR 0x10 215 #define NMK_GPIO_DIRS 0x14 216 #define NMK_GPIO_DIRC 0x18 217 #define NMK_GPIO_SLPC 0x1c 218 #define NMK_GPIO_AFSLA 0x20 219 #define NMK_GPIO_AFSLB 0x24 220 #define NMK_GPIO_LOWEMI 0x28 221 222 #define NMK_GPIO_RIMSC 0x40 223 #define NMK_GPIO_FIMSC 0x44 224 #define NMK_GPIO_IS 0x48 225 #define NMK_GPIO_IC 0x4c 226 #define NMK_GPIO_RWIMSC 0x50 227 #define NMK_GPIO_FWIMSC 0x54 228 #define NMK_GPIO_WKS 0x58 229 /* These appear in DB8540 and later ASICs */ 230 #define NMK_GPIO_EDGELEVEL 0x5C 231 #define NMK_GPIO_LEVEL 0x60 232 233 234 /* Pull up/down values */ 235 enum nmk_gpio_pull { 236 NMK_GPIO_PULL_NONE, 237 NMK_GPIO_PULL_UP, 238 NMK_GPIO_PULL_DOWN, 239 }; 240 241 /* Sleep mode */ 242 enum nmk_gpio_slpm { 243 NMK_GPIO_SLPM_INPUT, 244 NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT, 245 NMK_GPIO_SLPM_NOCHANGE, 246 NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE, 247 }; 248 249 struct nmk_gpio_chip { 250 struct gpio_chip chip; 251 struct irq_chip irqchip; 252 void __iomem *addr; 253 struct clk *clk; 254 unsigned int bank; 255 unsigned int parent_irq; 256 int latent_parent_irq; 257 u32 (*get_latent_status)(unsigned int bank); 258 void (*set_ioforce)(bool enable); 259 spinlock_t lock; 260 bool sleepmode; 261 /* Keep track of configured edges */ 262 u32 edge_rising; 263 u32 edge_falling; 264 u32 real_wake; 265 u32 rwimsc; 266 u32 fwimsc; 267 u32 rimsc; 268 u32 fimsc; 269 u32 pull_up; 270 u32 lowemi; 271 }; 272 273 /** 274 * struct nmk_pinctrl - state container for the Nomadik pin controller 275 * @dev: containing device pointer 276 * @pctl: corresponding pin controller device 277 * @soc: SoC data for this specific chip 278 * @prcm_base: PRCM register range virtual base 279 */ 280 struct nmk_pinctrl { 281 struct device *dev; 282 struct pinctrl_dev *pctl; 283 const struct nmk_pinctrl_soc_data *soc; 284 void __iomem *prcm_base; 285 }; 286 287 static struct nmk_gpio_chip *nmk_gpio_chips[NMK_MAX_BANKS]; 288 289 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock); 290 291 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips) 292 293 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, 294 unsigned offset, int gpio_mode) 295 { 296 u32 afunc, bfunc; 297 298 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~BIT(offset); 299 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~BIT(offset); 300 if (gpio_mode & NMK_GPIO_ALT_A) 301 afunc |= BIT(offset); 302 if (gpio_mode & NMK_GPIO_ALT_B) 303 bfunc |= BIT(offset); 304 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); 305 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); 306 } 307 308 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, 309 unsigned offset, enum nmk_gpio_slpm mode) 310 { 311 u32 slpm; 312 313 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); 314 if (mode == NMK_GPIO_SLPM_NOCHANGE) 315 slpm |= BIT(offset); 316 else 317 slpm &= ~BIT(offset); 318 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); 319 } 320 321 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, 322 unsigned offset, enum nmk_gpio_pull pull) 323 { 324 u32 pdis; 325 326 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); 327 if (pull == NMK_GPIO_PULL_NONE) { 328 pdis |= BIT(offset); 329 nmk_chip->pull_up &= ~BIT(offset); 330 } else { 331 pdis &= ~BIT(offset); 332 } 333 334 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); 335 336 if (pull == NMK_GPIO_PULL_UP) { 337 nmk_chip->pull_up |= BIT(offset); 338 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS); 339 } else if (pull == NMK_GPIO_PULL_DOWN) { 340 nmk_chip->pull_up &= ~BIT(offset); 341 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC); 342 } 343 } 344 345 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip, 346 unsigned offset, bool lowemi) 347 { 348 bool enabled = nmk_chip->lowemi & BIT(offset); 349 350 if (lowemi == enabled) 351 return; 352 353 if (lowemi) 354 nmk_chip->lowemi |= BIT(offset); 355 else 356 nmk_chip->lowemi &= ~BIT(offset); 357 358 writel_relaxed(nmk_chip->lowemi, 359 nmk_chip->addr + NMK_GPIO_LOWEMI); 360 } 361 362 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, 363 unsigned offset) 364 { 365 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC); 366 } 367 368 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, 369 unsigned offset, int val) 370 { 371 if (val) 372 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS); 373 else 374 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC); 375 } 376 377 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, 378 unsigned offset, int val) 379 { 380 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRS); 381 __nmk_gpio_set_output(nmk_chip, offset, val); 382 } 383 384 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, 385 unsigned offset, int gpio_mode, 386 bool glitch) 387 { 388 u32 rwimsc = nmk_chip->rwimsc; 389 u32 fwimsc = nmk_chip->fwimsc; 390 391 if (glitch && nmk_chip->set_ioforce) { 392 u32 bit = BIT(offset); 393 394 /* Prevent spurious wakeups */ 395 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC); 396 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC); 397 398 nmk_chip->set_ioforce(true); 399 } 400 401 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode); 402 403 if (glitch && nmk_chip->set_ioforce) { 404 nmk_chip->set_ioforce(false); 405 406 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC); 407 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC); 408 } 409 } 410 411 static void 412 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset) 413 { 414 u32 falling = nmk_chip->fimsc & BIT(offset); 415 u32 rising = nmk_chip->rimsc & BIT(offset); 416 int gpio = nmk_chip->chip.base + offset; 417 int irq = irq_find_mapping(nmk_chip->chip.irqdomain, offset); 418 struct irq_data *d = irq_get_irq_data(irq); 419 420 if (!rising && !falling) 421 return; 422 423 if (!d || !irqd_irq_disabled(d)) 424 return; 425 426 if (rising) { 427 nmk_chip->rimsc &= ~BIT(offset); 428 writel_relaxed(nmk_chip->rimsc, 429 nmk_chip->addr + NMK_GPIO_RIMSC); 430 } 431 432 if (falling) { 433 nmk_chip->fimsc &= ~BIT(offset); 434 writel_relaxed(nmk_chip->fimsc, 435 nmk_chip->addr + NMK_GPIO_FIMSC); 436 } 437 438 dev_dbg(nmk_chip->chip.parent, "%d: clearing interrupt mask\n", gpio); 439 } 440 441 static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value) 442 { 443 u32 val; 444 445 val = readl(reg); 446 val = ((val & ~mask) | (value & mask)); 447 writel(val, reg); 448 } 449 450 static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct, 451 unsigned offset, unsigned alt_num) 452 { 453 int i; 454 u16 reg; 455 u8 bit; 456 u8 alt_index; 457 const struct prcm_gpiocr_altcx_pin_desc *pin_desc; 458 const u16 *gpiocr_regs; 459 460 if (!npct->prcm_base) 461 return; 462 463 if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) { 464 dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n", 465 alt_num); 466 return; 467 } 468 469 for (i = 0 ; i < npct->soc->npins_altcx ; i++) { 470 if (npct->soc->altcx_pins[i].pin == offset) 471 break; 472 } 473 if (i == npct->soc->npins_altcx) { 474 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n", 475 offset); 476 return; 477 } 478 479 pin_desc = npct->soc->altcx_pins + i; 480 gpiocr_regs = npct->soc->prcm_gpiocr_registers; 481 482 /* 483 * If alt_num is NULL, just clear current ALTCx selection 484 * to make sure we come back to a pure ALTC selection 485 */ 486 if (!alt_num) { 487 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { 488 if (pin_desc->altcx[i].used == true) { 489 reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; 490 bit = pin_desc->altcx[i].control_bit; 491 if (readl(npct->prcm_base + reg) & BIT(bit)) { 492 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); 493 dev_dbg(npct->dev, 494 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", 495 offset, i+1); 496 } 497 } 498 } 499 return; 500 } 501 502 alt_index = alt_num - 1; 503 if (pin_desc->altcx[alt_index].used == false) { 504 dev_warn(npct->dev, 505 "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n", 506 offset, alt_num); 507 return; 508 } 509 510 /* 511 * Check if any other ALTCx functions are activated on this pin 512 * and disable it first. 513 */ 514 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { 515 if (i == alt_index) 516 continue; 517 if (pin_desc->altcx[i].used == true) { 518 reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; 519 bit = pin_desc->altcx[i].control_bit; 520 if (readl(npct->prcm_base + reg) & BIT(bit)) { 521 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); 522 dev_dbg(npct->dev, 523 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", 524 offset, i+1); 525 } 526 } 527 } 528 529 reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index]; 530 bit = pin_desc->altcx[alt_index].control_bit; 531 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n", 532 offset, alt_index+1); 533 nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit)); 534 } 535 536 /* 537 * Safe sequence used to switch IOs between GPIO and Alternate-C mode: 538 * - Save SLPM registers 539 * - Set SLPM=0 for the IOs you want to switch and others to 1 540 * - Configure the GPIO registers for the IOs that are being switched 541 * - Set IOFORCE=1 542 * - Modify the AFLSA/B registers for the IOs that are being switched 543 * - Set IOFORCE=0 544 * - Restore SLPM registers 545 * - Any spurious wake up event during switch sequence to be ignored and 546 * cleared 547 */ 548 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm) 549 { 550 int i; 551 552 for (i = 0; i < NUM_BANKS; i++) { 553 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 554 unsigned int temp = slpm[i]; 555 556 if (!chip) 557 break; 558 559 clk_enable(chip->clk); 560 561 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC); 562 writel(temp, chip->addr + NMK_GPIO_SLPC); 563 } 564 } 565 566 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm) 567 { 568 int i; 569 570 for (i = 0; i < NUM_BANKS; i++) { 571 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 572 573 if (!chip) 574 break; 575 576 writel(slpm[i], chip->addr + NMK_GPIO_SLPC); 577 578 clk_disable(chip->clk); 579 } 580 } 581 582 static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio) 583 { 584 int i; 585 u16 reg; 586 u8 bit; 587 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 588 const struct prcm_gpiocr_altcx_pin_desc *pin_desc; 589 const u16 *gpiocr_regs; 590 591 if (!npct->prcm_base) 592 return NMK_GPIO_ALT_C; 593 594 for (i = 0; i < npct->soc->npins_altcx; i++) { 595 if (npct->soc->altcx_pins[i].pin == gpio) 596 break; 597 } 598 if (i == npct->soc->npins_altcx) 599 return NMK_GPIO_ALT_C; 600 601 pin_desc = npct->soc->altcx_pins + i; 602 gpiocr_regs = npct->soc->prcm_gpiocr_registers; 603 for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) { 604 if (pin_desc->altcx[i].used == true) { 605 reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; 606 bit = pin_desc->altcx[i].control_bit; 607 if (readl(npct->prcm_base + reg) & BIT(bit)) 608 return NMK_GPIO_ALT_C+i+1; 609 } 610 } 611 return NMK_GPIO_ALT_C; 612 } 613 614 static int nmk_gpio_get_mode(struct nmk_gpio_chip *nmk_chip, int offset) 615 { 616 u32 afunc, bfunc; 617 618 clk_enable(nmk_chip->clk); 619 620 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & BIT(offset); 621 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & BIT(offset); 622 623 clk_disable(nmk_chip->clk); 624 625 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0); 626 } 627 628 /* IRQ functions */ 629 630 static void nmk_gpio_irq_ack(struct irq_data *d) 631 { 632 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 633 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 634 635 clk_enable(nmk_chip->clk); 636 writel(BIT(d->hwirq), nmk_chip->addr + NMK_GPIO_IC); 637 clk_disable(nmk_chip->clk); 638 } 639 640 enum nmk_gpio_irq_type { 641 NORMAL, 642 WAKE, 643 }; 644 645 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, 646 int offset, enum nmk_gpio_irq_type which, 647 bool enable) 648 { 649 u32 *rimscval; 650 u32 *fimscval; 651 u32 rimscreg; 652 u32 fimscreg; 653 654 if (which == NORMAL) { 655 rimscreg = NMK_GPIO_RIMSC; 656 fimscreg = NMK_GPIO_FIMSC; 657 rimscval = &nmk_chip->rimsc; 658 fimscval = &nmk_chip->fimsc; 659 } else { 660 rimscreg = NMK_GPIO_RWIMSC; 661 fimscreg = NMK_GPIO_FWIMSC; 662 rimscval = &nmk_chip->rwimsc; 663 fimscval = &nmk_chip->fwimsc; 664 } 665 666 /* we must individually set/clear the two edges */ 667 if (nmk_chip->edge_rising & BIT(offset)) { 668 if (enable) 669 *rimscval |= BIT(offset); 670 else 671 *rimscval &= ~BIT(offset); 672 writel(*rimscval, nmk_chip->addr + rimscreg); 673 } 674 if (nmk_chip->edge_falling & BIT(offset)) { 675 if (enable) 676 *fimscval |= BIT(offset); 677 else 678 *fimscval &= ~BIT(offset); 679 writel(*fimscval, nmk_chip->addr + fimscreg); 680 } 681 } 682 683 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, 684 int offset, bool on) 685 { 686 /* 687 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is 688 * disabled, since setting SLPM to 1 increases power consumption, and 689 * wakeup is anyhow controlled by the RIMSC and FIMSC registers. 690 */ 691 if (nmk_chip->sleepmode && on) { 692 __nmk_gpio_set_slpm(nmk_chip, offset, 693 NMK_GPIO_SLPM_WAKEUP_ENABLE); 694 } 695 696 __nmk_gpio_irq_modify(nmk_chip, offset, WAKE, on); 697 } 698 699 static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) 700 { 701 struct nmk_gpio_chip *nmk_chip; 702 unsigned long flags; 703 704 nmk_chip = irq_data_get_irq_chip_data(d); 705 if (!nmk_chip) 706 return -EINVAL; 707 708 clk_enable(nmk_chip->clk); 709 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 710 spin_lock(&nmk_chip->lock); 711 712 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable); 713 714 if (!(nmk_chip->real_wake & BIT(d->hwirq))) 715 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable); 716 717 spin_unlock(&nmk_chip->lock); 718 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 719 clk_disable(nmk_chip->clk); 720 721 return 0; 722 } 723 724 static void nmk_gpio_irq_mask(struct irq_data *d) 725 { 726 nmk_gpio_irq_maskunmask(d, false); 727 } 728 729 static void nmk_gpio_irq_unmask(struct irq_data *d) 730 { 731 nmk_gpio_irq_maskunmask(d, true); 732 } 733 734 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 735 { 736 struct nmk_gpio_chip *nmk_chip; 737 unsigned long flags; 738 739 nmk_chip = irq_data_get_irq_chip_data(d); 740 if (!nmk_chip) 741 return -EINVAL; 742 743 clk_enable(nmk_chip->clk); 744 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 745 spin_lock(&nmk_chip->lock); 746 747 if (irqd_irq_disabled(d)) 748 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on); 749 750 if (on) 751 nmk_chip->real_wake |= BIT(d->hwirq); 752 else 753 nmk_chip->real_wake &= ~BIT(d->hwirq); 754 755 spin_unlock(&nmk_chip->lock); 756 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 757 clk_disable(nmk_chip->clk); 758 759 return 0; 760 } 761 762 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) 763 { 764 bool enabled = !irqd_irq_disabled(d); 765 bool wake = irqd_is_wakeup_set(d); 766 struct nmk_gpio_chip *nmk_chip; 767 unsigned long flags; 768 769 nmk_chip = irq_data_get_irq_chip_data(d); 770 if (!nmk_chip) 771 return -EINVAL; 772 if (type & IRQ_TYPE_LEVEL_HIGH) 773 return -EINVAL; 774 if (type & IRQ_TYPE_LEVEL_LOW) 775 return -EINVAL; 776 777 clk_enable(nmk_chip->clk); 778 spin_lock_irqsave(&nmk_chip->lock, flags); 779 780 if (enabled) 781 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false); 782 783 if (enabled || wake) 784 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false); 785 786 nmk_chip->edge_rising &= ~BIT(d->hwirq); 787 if (type & IRQ_TYPE_EDGE_RISING) 788 nmk_chip->edge_rising |= BIT(d->hwirq); 789 790 nmk_chip->edge_falling &= ~BIT(d->hwirq); 791 if (type & IRQ_TYPE_EDGE_FALLING) 792 nmk_chip->edge_falling |= BIT(d->hwirq); 793 794 if (enabled) 795 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true); 796 797 if (enabled || wake) 798 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true); 799 800 spin_unlock_irqrestore(&nmk_chip->lock, flags); 801 clk_disable(nmk_chip->clk); 802 803 return 0; 804 } 805 806 static unsigned int nmk_gpio_irq_startup(struct irq_data *d) 807 { 808 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); 809 810 clk_enable(nmk_chip->clk); 811 nmk_gpio_irq_unmask(d); 812 return 0; 813 } 814 815 static void nmk_gpio_irq_shutdown(struct irq_data *d) 816 { 817 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); 818 819 nmk_gpio_irq_mask(d); 820 clk_disable(nmk_chip->clk); 821 } 822 823 static void __nmk_gpio_irq_handler(struct irq_desc *desc, u32 status) 824 { 825 struct irq_chip *host_chip = irq_desc_get_chip(desc); 826 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 827 828 chained_irq_enter(host_chip, desc); 829 830 while (status) { 831 int bit = __ffs(status); 832 833 generic_handle_irq(irq_find_mapping(chip->irqdomain, bit)); 834 status &= ~BIT(bit); 835 } 836 837 chained_irq_exit(host_chip, desc); 838 } 839 840 static void nmk_gpio_irq_handler(struct irq_desc *desc) 841 { 842 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 843 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 844 u32 status; 845 846 clk_enable(nmk_chip->clk); 847 status = readl(nmk_chip->addr + NMK_GPIO_IS); 848 clk_disable(nmk_chip->clk); 849 850 __nmk_gpio_irq_handler(desc, status); 851 } 852 853 static void nmk_gpio_latent_irq_handler(struct irq_desc *desc) 854 { 855 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 856 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 857 u32 status = nmk_chip->get_latent_status(nmk_chip->bank); 858 859 __nmk_gpio_irq_handler(desc, status); 860 } 861 862 /* I/O Functions */ 863 864 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) 865 { 866 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 867 868 clk_enable(nmk_chip->clk); 869 870 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC); 871 872 clk_disable(nmk_chip->clk); 873 874 return 0; 875 } 876 877 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset) 878 { 879 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 880 int value; 881 882 clk_enable(nmk_chip->clk); 883 884 value = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset)); 885 886 clk_disable(nmk_chip->clk); 887 888 return value; 889 } 890 891 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset, 892 int val) 893 { 894 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 895 896 clk_enable(nmk_chip->clk); 897 898 __nmk_gpio_set_output(nmk_chip, offset, val); 899 900 clk_disable(nmk_chip->clk); 901 } 902 903 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, 904 int val) 905 { 906 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 907 908 clk_enable(nmk_chip->clk); 909 910 __nmk_gpio_make_output(nmk_chip, offset, val); 911 912 clk_disable(nmk_chip->clk); 913 914 return 0; 915 } 916 917 #ifdef CONFIG_DEBUG_FS 918 919 #include <linux/seq_file.h> 920 921 static void nmk_gpio_dbg_show_one(struct seq_file *s, 922 struct pinctrl_dev *pctldev, struct gpio_chip *chip, 923 unsigned offset, unsigned gpio) 924 { 925 const char *label = gpiochip_is_requested(chip, offset); 926 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 927 int mode; 928 bool is_out; 929 bool data_out; 930 bool pull; 931 const char *modes[] = { 932 [NMK_GPIO_ALT_GPIO] = "gpio", 933 [NMK_GPIO_ALT_A] = "altA", 934 [NMK_GPIO_ALT_B] = "altB", 935 [NMK_GPIO_ALT_C] = "altC", 936 [NMK_GPIO_ALT_C+1] = "altC1", 937 [NMK_GPIO_ALT_C+2] = "altC2", 938 [NMK_GPIO_ALT_C+3] = "altC3", 939 [NMK_GPIO_ALT_C+4] = "altC4", 940 }; 941 const char *pulls[] = { 942 "none ", 943 "pull down", 944 "pull up ", 945 }; 946 947 clk_enable(nmk_chip->clk); 948 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset)); 949 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & BIT(offset)); 950 data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset)); 951 mode = nmk_gpio_get_mode(nmk_chip, offset); 952 if ((mode == NMK_GPIO_ALT_C) && pctldev) 953 mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio); 954 955 if (is_out) { 956 seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s", 957 gpio, 958 label ?: "(none)", 959 data_out ? "hi" : "lo", 960 (mode < 0) ? "unknown" : modes[mode]); 961 } else { 962 int irq = gpio_to_irq(gpio); 963 struct irq_desc *desc = irq_to_desc(irq); 964 int pullidx = 0; 965 int val; 966 967 if (pull) 968 pullidx = data_out ? 1 : 2; 969 970 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s", 971 gpio, 972 label ?: "(none)", 973 pulls[pullidx], 974 (mode < 0) ? "unknown" : modes[mode]); 975 976 val = nmk_gpio_get_input(chip, offset); 977 seq_printf(s, " VAL %d", val); 978 979 /* 980 * This races with request_irq(), set_irq_type(), 981 * and set_irq_wake() ... but those are "rare". 982 */ 983 if (irq > 0 && desc && desc->action) { 984 char *trigger; 985 986 if (nmk_chip->edge_rising & BIT(offset)) 987 trigger = "edge-rising"; 988 else if (nmk_chip->edge_falling & BIT(offset)) 989 trigger = "edge-falling"; 990 else 991 trigger = "edge-undefined"; 992 993 seq_printf(s, " irq-%d %s%s", 994 irq, trigger, 995 irqd_is_wakeup_set(&desc->irq_data) 996 ? " wakeup" : ""); 997 } 998 } 999 clk_disable(nmk_chip->clk); 1000 } 1001 1002 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 1003 { 1004 unsigned i; 1005 unsigned gpio = chip->base; 1006 1007 for (i = 0; i < chip->ngpio; i++, gpio++) { 1008 nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio); 1009 seq_printf(s, "\n"); 1010 } 1011 } 1012 1013 #else 1014 static inline void nmk_gpio_dbg_show_one(struct seq_file *s, 1015 struct pinctrl_dev *pctldev, 1016 struct gpio_chip *chip, 1017 unsigned offset, unsigned gpio) 1018 { 1019 } 1020 #define nmk_gpio_dbg_show NULL 1021 #endif 1022 1023 void nmk_gpio_clocks_enable(void) 1024 { 1025 int i; 1026 1027 for (i = 0; i < NUM_BANKS; i++) { 1028 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 1029 1030 if (!chip) 1031 continue; 1032 1033 clk_enable(chip->clk); 1034 } 1035 } 1036 1037 void nmk_gpio_clocks_disable(void) 1038 { 1039 int i; 1040 1041 for (i = 0; i < NUM_BANKS; i++) { 1042 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 1043 1044 if (!chip) 1045 continue; 1046 1047 clk_disable(chip->clk); 1048 } 1049 } 1050 1051 /* 1052 * Called from the suspend/resume path to only keep the real wakeup interrupts 1053 * (those that have had set_irq_wake() called on them) as wakeup interrupts, 1054 * and not the rest of the interrupts which we needed to have as wakeups for 1055 * cpuidle. 1056 * 1057 * PM ops are not used since this needs to be done at the end, after all the 1058 * other drivers are done with their suspend callbacks. 1059 */ 1060 void nmk_gpio_wakeups_suspend(void) 1061 { 1062 int i; 1063 1064 for (i = 0; i < NUM_BANKS; i++) { 1065 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 1066 1067 if (!chip) 1068 break; 1069 1070 clk_enable(chip->clk); 1071 1072 writel(chip->rwimsc & chip->real_wake, 1073 chip->addr + NMK_GPIO_RWIMSC); 1074 writel(chip->fwimsc & chip->real_wake, 1075 chip->addr + NMK_GPIO_FWIMSC); 1076 1077 clk_disable(chip->clk); 1078 } 1079 } 1080 1081 void nmk_gpio_wakeups_resume(void) 1082 { 1083 int i; 1084 1085 for (i = 0; i < NUM_BANKS; i++) { 1086 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 1087 1088 if (!chip) 1089 break; 1090 1091 clk_enable(chip->clk); 1092 1093 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC); 1094 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC); 1095 1096 clk_disable(chip->clk); 1097 } 1098 } 1099 1100 /* 1101 * Read the pull up/pull down status. 1102 * A bit set in 'pull_up' means that pull up 1103 * is selected if pull is enabled in PDIS register. 1104 * Note: only pull up/down set via this driver can 1105 * be detected due to HW limitations. 1106 */ 1107 void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up) 1108 { 1109 if (gpio_bank < NUM_BANKS) { 1110 struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank]; 1111 1112 if (!chip) 1113 return; 1114 1115 *pull_up = chip->pull_up; 1116 } 1117 } 1118 1119 /* 1120 * We will allocate memory for the state container using devm* allocators 1121 * binding to the first device reaching this point, it doesn't matter if 1122 * it is the pin controller or GPIO driver. However we need to use the right 1123 * platform device when looking up resources so pay attention to pdev. 1124 */ 1125 static struct nmk_gpio_chip *nmk_gpio_populate_chip(struct device_node *np, 1126 struct platform_device *pdev) 1127 { 1128 struct nmk_gpio_chip *nmk_chip; 1129 struct platform_device *gpio_pdev; 1130 struct gpio_chip *chip; 1131 struct resource *res; 1132 struct clk *clk; 1133 void __iomem *base; 1134 u32 id; 1135 1136 gpio_pdev = of_find_device_by_node(np); 1137 if (!gpio_pdev) { 1138 pr_err("populate \"%s\": device not found\n", np->name); 1139 return ERR_PTR(-ENODEV); 1140 } 1141 if (of_property_read_u32(np, "gpio-bank", &id)) { 1142 dev_err(&pdev->dev, "populate: gpio-bank property not found\n"); 1143 return ERR_PTR(-EINVAL); 1144 } 1145 1146 /* Already populated? */ 1147 nmk_chip = nmk_gpio_chips[id]; 1148 if (nmk_chip) 1149 return nmk_chip; 1150 1151 nmk_chip = devm_kzalloc(&pdev->dev, sizeof(*nmk_chip), GFP_KERNEL); 1152 if (!nmk_chip) 1153 return ERR_PTR(-ENOMEM); 1154 1155 nmk_chip->bank = id; 1156 chip = &nmk_chip->chip; 1157 chip->base = id * NMK_GPIO_PER_CHIP; 1158 chip->ngpio = NMK_GPIO_PER_CHIP; 1159 chip->label = dev_name(&gpio_pdev->dev); 1160 chip->parent = &gpio_pdev->dev; 1161 1162 res = platform_get_resource(gpio_pdev, IORESOURCE_MEM, 0); 1163 base = devm_ioremap_resource(&pdev->dev, res); 1164 if (IS_ERR(base)) 1165 return base; 1166 nmk_chip->addr = base; 1167 1168 clk = clk_get(&gpio_pdev->dev, NULL); 1169 if (IS_ERR(clk)) 1170 return (void *) clk; 1171 clk_prepare(clk); 1172 nmk_chip->clk = clk; 1173 1174 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); 1175 nmk_gpio_chips[id] = nmk_chip; 1176 return nmk_chip; 1177 } 1178 1179 static int nmk_gpio_probe(struct platform_device *dev) 1180 { 1181 struct device_node *np = dev->dev.of_node; 1182 struct nmk_gpio_chip *nmk_chip; 1183 struct gpio_chip *chip; 1184 struct irq_chip *irqchip; 1185 int latent_irq; 1186 bool supports_sleepmode; 1187 int irq; 1188 int ret; 1189 1190 nmk_chip = nmk_gpio_populate_chip(np, dev); 1191 if (IS_ERR(nmk_chip)) { 1192 dev_err(&dev->dev, "could not populate nmk chip struct\n"); 1193 return PTR_ERR(nmk_chip); 1194 } 1195 1196 if (of_get_property(np, "st,supports-sleepmode", NULL)) 1197 supports_sleepmode = true; 1198 else 1199 supports_sleepmode = false; 1200 1201 /* Correct platform device ID */ 1202 dev->id = nmk_chip->bank; 1203 1204 irq = platform_get_irq(dev, 0); 1205 if (irq < 0) 1206 return irq; 1207 1208 /* It's OK for this IRQ not to be present */ 1209 latent_irq = platform_get_irq(dev, 1); 1210 1211 /* 1212 * The virt address in nmk_chip->addr is in the nomadik register space, 1213 * so we can simply convert the resource address, without remapping 1214 */ 1215 nmk_chip->parent_irq = irq; 1216 nmk_chip->latent_parent_irq = latent_irq; 1217 nmk_chip->sleepmode = supports_sleepmode; 1218 spin_lock_init(&nmk_chip->lock); 1219 1220 chip = &nmk_chip->chip; 1221 chip->request = gpiochip_generic_request; 1222 chip->free = gpiochip_generic_free; 1223 chip->direction_input = nmk_gpio_make_input; 1224 chip->get = nmk_gpio_get_input; 1225 chip->direction_output = nmk_gpio_make_output; 1226 chip->set = nmk_gpio_set_output; 1227 chip->dbg_show = nmk_gpio_dbg_show; 1228 chip->can_sleep = false; 1229 chip->owner = THIS_MODULE; 1230 1231 irqchip = &nmk_chip->irqchip; 1232 irqchip->irq_ack = nmk_gpio_irq_ack; 1233 irqchip->irq_mask = nmk_gpio_irq_mask; 1234 irqchip->irq_unmask = nmk_gpio_irq_unmask; 1235 irqchip->irq_set_type = nmk_gpio_irq_set_type; 1236 irqchip->irq_set_wake = nmk_gpio_irq_set_wake; 1237 irqchip->irq_startup = nmk_gpio_irq_startup; 1238 irqchip->irq_shutdown = nmk_gpio_irq_shutdown; 1239 irqchip->flags = IRQCHIP_MASK_ON_SUSPEND; 1240 irqchip->name = kasprintf(GFP_KERNEL, "nmk%u-%u-%u", 1241 dev->id, 1242 chip->base, 1243 chip->base + chip->ngpio - 1); 1244 1245 clk_enable(nmk_chip->clk); 1246 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); 1247 clk_disable(nmk_chip->clk); 1248 chip->of_node = np; 1249 1250 ret = gpiochip_add_data(chip, nmk_chip); 1251 if (ret) 1252 return ret; 1253 1254 platform_set_drvdata(dev, nmk_chip); 1255 1256 /* 1257 * Let the generic code handle this edge IRQ, the the chained 1258 * handler will perform the actual work of handling the parent 1259 * interrupt. 1260 */ 1261 ret = gpiochip_irqchip_add(chip, 1262 irqchip, 1263 0, 1264 handle_edge_irq, 1265 IRQ_TYPE_EDGE_FALLING); 1266 if (ret) { 1267 dev_err(&dev->dev, "could not add irqchip\n"); 1268 gpiochip_remove(&nmk_chip->chip); 1269 return -ENODEV; 1270 } 1271 /* Then register the chain on the parent IRQ */ 1272 gpiochip_set_chained_irqchip(chip, 1273 irqchip, 1274 nmk_chip->parent_irq, 1275 nmk_gpio_irq_handler); 1276 if (nmk_chip->latent_parent_irq > 0) 1277 gpiochip_set_chained_irqchip(chip, 1278 irqchip, 1279 nmk_chip->latent_parent_irq, 1280 nmk_gpio_latent_irq_handler); 1281 1282 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr); 1283 1284 return 0; 1285 } 1286 1287 static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev) 1288 { 1289 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1290 1291 return npct->soc->ngroups; 1292 } 1293 1294 static const char *nmk_get_group_name(struct pinctrl_dev *pctldev, 1295 unsigned selector) 1296 { 1297 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1298 1299 return npct->soc->groups[selector].name; 1300 } 1301 1302 static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, 1303 const unsigned **pins, 1304 unsigned *num_pins) 1305 { 1306 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1307 1308 *pins = npct->soc->groups[selector].pins; 1309 *num_pins = npct->soc->groups[selector].npins; 1310 return 0; 1311 } 1312 1313 static struct nmk_gpio_chip *find_nmk_gpio_from_pin(unsigned pin) 1314 { 1315 int i; 1316 struct nmk_gpio_chip *nmk_gpio; 1317 1318 for(i = 0; i < NMK_MAX_BANKS; i++) { 1319 nmk_gpio = nmk_gpio_chips[i]; 1320 if (!nmk_gpio) 1321 continue; 1322 if (pin >= nmk_gpio->chip.base && 1323 pin < nmk_gpio->chip.base + nmk_gpio->chip.ngpio) 1324 return nmk_gpio; 1325 } 1326 return NULL; 1327 } 1328 1329 static struct gpio_chip *find_gc_from_pin(unsigned pin) 1330 { 1331 struct nmk_gpio_chip *nmk_gpio = find_nmk_gpio_from_pin(pin); 1332 1333 if (nmk_gpio) 1334 return &nmk_gpio->chip; 1335 return NULL; 1336 } 1337 1338 static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 1339 unsigned offset) 1340 { 1341 struct gpio_chip *chip = find_gc_from_pin(offset); 1342 1343 if (!chip) { 1344 seq_printf(s, "invalid pin offset"); 1345 return; 1346 } 1347 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset); 1348 } 1349 1350 static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps, 1351 unsigned *num_maps, const char *group, 1352 const char *function) 1353 { 1354 if (*num_maps == *reserved_maps) 1355 return -ENOSPC; 1356 1357 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 1358 (*map)[*num_maps].data.mux.group = group; 1359 (*map)[*num_maps].data.mux.function = function; 1360 (*num_maps)++; 1361 1362 return 0; 1363 } 1364 1365 static int nmk_dt_add_map_configs(struct pinctrl_map **map, 1366 unsigned *reserved_maps, 1367 unsigned *num_maps, const char *group, 1368 unsigned long *configs, unsigned num_configs) 1369 { 1370 unsigned long *dup_configs; 1371 1372 if (*num_maps == *reserved_maps) 1373 return -ENOSPC; 1374 1375 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), 1376 GFP_KERNEL); 1377 if (!dup_configs) 1378 return -ENOMEM; 1379 1380 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN; 1381 1382 (*map)[*num_maps].data.configs.group_or_pin = group; 1383 (*map)[*num_maps].data.configs.configs = dup_configs; 1384 (*map)[*num_maps].data.configs.num_configs = num_configs; 1385 (*num_maps)++; 1386 1387 return 0; 1388 } 1389 1390 #define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, } 1391 #define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \ 1392 .size = ARRAY_SIZE(y), } 1393 1394 static const unsigned long nmk_pin_input_modes[] = { 1395 PIN_INPUT_NOPULL, 1396 PIN_INPUT_PULLUP, 1397 PIN_INPUT_PULLDOWN, 1398 }; 1399 1400 static const unsigned long nmk_pin_output_modes[] = { 1401 PIN_OUTPUT_LOW, 1402 PIN_OUTPUT_HIGH, 1403 PIN_DIR_OUTPUT, 1404 }; 1405 1406 static const unsigned long nmk_pin_sleep_modes[] = { 1407 PIN_SLEEPMODE_DISABLED, 1408 PIN_SLEEPMODE_ENABLED, 1409 }; 1410 1411 static const unsigned long nmk_pin_sleep_input_modes[] = { 1412 PIN_SLPM_INPUT_NOPULL, 1413 PIN_SLPM_INPUT_PULLUP, 1414 PIN_SLPM_INPUT_PULLDOWN, 1415 PIN_SLPM_DIR_INPUT, 1416 }; 1417 1418 static const unsigned long nmk_pin_sleep_output_modes[] = { 1419 PIN_SLPM_OUTPUT_LOW, 1420 PIN_SLPM_OUTPUT_HIGH, 1421 PIN_SLPM_DIR_OUTPUT, 1422 }; 1423 1424 static const unsigned long nmk_pin_sleep_wakeup_modes[] = { 1425 PIN_SLPM_WAKEUP_DISABLE, 1426 PIN_SLPM_WAKEUP_ENABLE, 1427 }; 1428 1429 static const unsigned long nmk_pin_gpio_modes[] = { 1430 PIN_GPIOMODE_DISABLED, 1431 PIN_GPIOMODE_ENABLED, 1432 }; 1433 1434 static const unsigned long nmk_pin_sleep_pdis_modes[] = { 1435 PIN_SLPM_PDIS_DISABLED, 1436 PIN_SLPM_PDIS_ENABLED, 1437 }; 1438 1439 struct nmk_cfg_param { 1440 const char *property; 1441 unsigned long config; 1442 const unsigned long *choice; 1443 int size; 1444 }; 1445 1446 static const struct nmk_cfg_param nmk_cfg_params[] = { 1447 NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes), 1448 NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes), 1449 NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes), 1450 NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes), 1451 NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes), 1452 NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes), 1453 NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes), 1454 NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes), 1455 }; 1456 1457 static int nmk_dt_pin_config(int index, int val, unsigned long *config) 1458 { 1459 int ret = 0; 1460 1461 if (nmk_cfg_params[index].choice == NULL) 1462 *config = nmk_cfg_params[index].config; 1463 else { 1464 /* test if out of range */ 1465 if (val < nmk_cfg_params[index].size) { 1466 *config = nmk_cfg_params[index].config | 1467 nmk_cfg_params[index].choice[val]; 1468 } 1469 } 1470 return ret; 1471 } 1472 1473 static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name) 1474 { 1475 int i, pin_number; 1476 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1477 1478 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1) 1479 for (i = 0; i < npct->soc->npins; i++) 1480 if (npct->soc->pins[i].number == pin_number) 1481 return npct->soc->pins[i].name; 1482 return NULL; 1483 } 1484 1485 static bool nmk_pinctrl_dt_get_config(struct device_node *np, 1486 unsigned long *configs) 1487 { 1488 bool has_config = 0; 1489 unsigned long cfg = 0; 1490 int i, val, ret; 1491 1492 for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) { 1493 ret = of_property_read_u32(np, 1494 nmk_cfg_params[i].property, &val); 1495 if (ret != -EINVAL) { 1496 if (nmk_dt_pin_config(i, val, &cfg) == 0) { 1497 *configs |= cfg; 1498 has_config = 1; 1499 } 1500 } 1501 } 1502 1503 return has_config; 1504 } 1505 1506 static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 1507 struct device_node *np, 1508 struct pinctrl_map **map, 1509 unsigned *reserved_maps, 1510 unsigned *num_maps) 1511 { 1512 int ret; 1513 const char *function = NULL; 1514 unsigned long configs = 0; 1515 bool has_config = 0; 1516 struct property *prop; 1517 struct device_node *np_config; 1518 1519 ret = of_property_read_string(np, "function", &function); 1520 if (ret >= 0) { 1521 const char *group; 1522 1523 ret = of_property_count_strings(np, "groups"); 1524 if (ret < 0) 1525 goto exit; 1526 1527 ret = pinctrl_utils_reserve_map(pctldev, map, 1528 reserved_maps, 1529 num_maps, ret); 1530 if (ret < 0) 1531 goto exit; 1532 1533 of_property_for_each_string(np, "groups", prop, group) { 1534 ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps, 1535 group, function); 1536 if (ret < 0) 1537 goto exit; 1538 } 1539 } 1540 1541 has_config = nmk_pinctrl_dt_get_config(np, &configs); 1542 np_config = of_parse_phandle(np, "ste,config", 0); 1543 if (np_config) 1544 has_config |= nmk_pinctrl_dt_get_config(np_config, &configs); 1545 if (has_config) { 1546 const char *gpio_name; 1547 const char *pin; 1548 1549 ret = of_property_count_strings(np, "pins"); 1550 if (ret < 0) 1551 goto exit; 1552 ret = pinctrl_utils_reserve_map(pctldev, map, 1553 reserved_maps, 1554 num_maps, ret); 1555 if (ret < 0) 1556 goto exit; 1557 1558 of_property_for_each_string(np, "pins", prop, pin) { 1559 gpio_name = nmk_find_pin_name(pctldev, pin); 1560 1561 ret = nmk_dt_add_map_configs(map, reserved_maps, 1562 num_maps, 1563 gpio_name, &configs, 1); 1564 if (ret < 0) 1565 goto exit; 1566 } 1567 } 1568 1569 exit: 1570 return ret; 1571 } 1572 1573 static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 1574 struct device_node *np_config, 1575 struct pinctrl_map **map, unsigned *num_maps) 1576 { 1577 unsigned reserved_maps; 1578 struct device_node *np; 1579 int ret; 1580 1581 reserved_maps = 0; 1582 *map = NULL; 1583 *num_maps = 0; 1584 1585 for_each_child_of_node(np_config, np) { 1586 ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map, 1587 &reserved_maps, num_maps); 1588 if (ret < 0) { 1589 pinctrl_utils_free_map(pctldev, *map, *num_maps); 1590 return ret; 1591 } 1592 } 1593 1594 return 0; 1595 } 1596 1597 static const struct pinctrl_ops nmk_pinctrl_ops = { 1598 .get_groups_count = nmk_get_groups_cnt, 1599 .get_group_name = nmk_get_group_name, 1600 .get_group_pins = nmk_get_group_pins, 1601 .pin_dbg_show = nmk_pin_dbg_show, 1602 .dt_node_to_map = nmk_pinctrl_dt_node_to_map, 1603 .dt_free_map = pinctrl_utils_free_map, 1604 }; 1605 1606 static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 1607 { 1608 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1609 1610 return npct->soc->nfunctions; 1611 } 1612 1613 static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev, 1614 unsigned function) 1615 { 1616 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1617 1618 return npct->soc->functions[function].name; 1619 } 1620 1621 static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev, 1622 unsigned function, 1623 const char * const **groups, 1624 unsigned * const num_groups) 1625 { 1626 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1627 1628 *groups = npct->soc->functions[function].groups; 1629 *num_groups = npct->soc->functions[function].ngroups; 1630 1631 return 0; 1632 } 1633 1634 static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned function, 1635 unsigned group) 1636 { 1637 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1638 const struct nmk_pingroup *g; 1639 static unsigned int slpm[NUM_BANKS]; 1640 unsigned long flags = 0; 1641 bool glitch; 1642 int ret = -EINVAL; 1643 int i; 1644 1645 g = &npct->soc->groups[group]; 1646 1647 if (g->altsetting < 0) 1648 return -EINVAL; 1649 1650 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins); 1651 1652 /* 1653 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1, 1654 * we may pass through an undesired state. In this case we take 1655 * some extra care. 1656 * 1657 * Safe sequence used to switch IOs between GPIO and Alternate-C mode: 1658 * - Save SLPM registers (since we have a shadow register in the 1659 * nmk_chip we're using that as backup) 1660 * - Set SLPM=0 for the IOs you want to switch and others to 1 1661 * - Configure the GPIO registers for the IOs that are being switched 1662 * - Set IOFORCE=1 1663 * - Modify the AFLSA/B registers for the IOs that are being switched 1664 * - Set IOFORCE=0 1665 * - Restore SLPM registers 1666 * - Any spurious wake up event during switch sequence to be ignored 1667 * and cleared 1668 * 1669 * We REALLY need to save ALL slpm registers, because the external 1670 * IOFORCE will switch *all* ports to their sleepmode setting to as 1671 * to avoid glitches. (Not just one port!) 1672 */ 1673 glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C); 1674 1675 if (glitch) { 1676 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 1677 1678 /* Initially don't put any pins to sleep when switching */ 1679 memset(slpm, 0xff, sizeof(slpm)); 1680 1681 /* 1682 * Then mask the pins that need to be sleeping now when we're 1683 * switching to the ALT C function. 1684 */ 1685 for (i = 0; i < g->npins; i++) 1686 slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]); 1687 nmk_gpio_glitch_slpm_init(slpm); 1688 } 1689 1690 for (i = 0; i < g->npins; i++) { 1691 struct nmk_gpio_chip *nmk_chip; 1692 unsigned bit; 1693 1694 nmk_chip = find_nmk_gpio_from_pin(g->pins[i]); 1695 if (!nmk_chip) { 1696 dev_err(npct->dev, 1697 "invalid pin offset %d in group %s at index %d\n", 1698 g->pins[i], g->name, i); 1699 goto out_glitch; 1700 } 1701 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting); 1702 1703 clk_enable(nmk_chip->clk); 1704 bit = g->pins[i] % NMK_GPIO_PER_CHIP; 1705 /* 1706 * If the pin is switching to altfunc, and there was an 1707 * interrupt installed on it which has been lazy disabled, 1708 * actually mask the interrupt to prevent spurious interrupts 1709 * that would occur while the pin is under control of the 1710 * peripheral. Only SKE does this. 1711 */ 1712 nmk_gpio_disable_lazy_irq(nmk_chip, bit); 1713 1714 __nmk_gpio_set_mode_safe(nmk_chip, bit, 1715 (g->altsetting & NMK_GPIO_ALT_C), glitch); 1716 clk_disable(nmk_chip->clk); 1717 1718 /* 1719 * Call PRCM GPIOCR config function in case ALTC 1720 * has been selected: 1721 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers 1722 * must be set. 1723 * - If selection is pure ALTC and previous selection was ALTCx, 1724 * then some bits in PRCM GPIOCR registers must be cleared. 1725 */ 1726 if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C) 1727 nmk_prcm_altcx_set_mode(npct, g->pins[i], 1728 g->altsetting >> NMK_GPIO_ALT_CX_SHIFT); 1729 } 1730 1731 /* When all pins are successfully reconfigured we get here */ 1732 ret = 0; 1733 1734 out_glitch: 1735 if (glitch) { 1736 nmk_gpio_glitch_slpm_restore(slpm); 1737 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 1738 } 1739 1740 return ret; 1741 } 1742 1743 static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev, 1744 struct pinctrl_gpio_range *range, 1745 unsigned offset) 1746 { 1747 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1748 struct nmk_gpio_chip *nmk_chip; 1749 struct gpio_chip *chip; 1750 unsigned bit; 1751 1752 if (!range) { 1753 dev_err(npct->dev, "invalid range\n"); 1754 return -EINVAL; 1755 } 1756 if (!range->gc) { 1757 dev_err(npct->dev, "missing GPIO chip in range\n"); 1758 return -EINVAL; 1759 } 1760 chip = range->gc; 1761 nmk_chip = gpiochip_get_data(chip); 1762 1763 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); 1764 1765 clk_enable(nmk_chip->clk); 1766 bit = offset % NMK_GPIO_PER_CHIP; 1767 /* There is no glitch when converting any pin to GPIO */ 1768 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); 1769 clk_disable(nmk_chip->clk); 1770 1771 return 0; 1772 } 1773 1774 static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev, 1775 struct pinctrl_gpio_range *range, 1776 unsigned offset) 1777 { 1778 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1779 1780 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); 1781 /* Set the pin to some default state, GPIO is usually default */ 1782 } 1783 1784 static const struct pinmux_ops nmk_pinmux_ops = { 1785 .get_functions_count = nmk_pmx_get_funcs_cnt, 1786 .get_function_name = nmk_pmx_get_func_name, 1787 .get_function_groups = nmk_pmx_get_func_groups, 1788 .set_mux = nmk_pmx_set, 1789 .gpio_request_enable = nmk_gpio_request_enable, 1790 .gpio_disable_free = nmk_gpio_disable_free, 1791 .strict = true, 1792 }; 1793 1794 static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, 1795 unsigned long *config) 1796 { 1797 /* Not implemented */ 1798 return -EINVAL; 1799 } 1800 1801 static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, 1802 unsigned long *configs, unsigned num_configs) 1803 { 1804 static const char *pullnames[] = { 1805 [NMK_GPIO_PULL_NONE] = "none", 1806 [NMK_GPIO_PULL_UP] = "up", 1807 [NMK_GPIO_PULL_DOWN] = "down", 1808 [3] /* illegal */ = "??" 1809 }; 1810 static const char *slpmnames[] = { 1811 [NMK_GPIO_SLPM_INPUT] = "input/wakeup", 1812 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", 1813 }; 1814 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1815 struct nmk_gpio_chip *nmk_chip; 1816 unsigned bit; 1817 pin_cfg_t cfg; 1818 int pull, slpm, output, val, i; 1819 bool lowemi, gpiomode, sleep; 1820 1821 nmk_chip = find_nmk_gpio_from_pin(pin); 1822 if (!nmk_chip) { 1823 dev_err(npct->dev, 1824 "invalid pin offset %d\n", pin); 1825 return -EINVAL; 1826 } 1827 1828 for (i = 0; i < num_configs; i++) { 1829 /* 1830 * The pin config contains pin number and altfunction fields, 1831 * here we just ignore that part. It's being handled by the 1832 * framework and pinmux callback respectively. 1833 */ 1834 cfg = (pin_cfg_t) configs[i]; 1835 pull = PIN_PULL(cfg); 1836 slpm = PIN_SLPM(cfg); 1837 output = PIN_DIR(cfg); 1838 val = PIN_VAL(cfg); 1839 lowemi = PIN_LOWEMI(cfg); 1840 gpiomode = PIN_GPIOMODE(cfg); 1841 sleep = PIN_SLEEPMODE(cfg); 1842 1843 if (sleep) { 1844 int slpm_pull = PIN_SLPM_PULL(cfg); 1845 int slpm_output = PIN_SLPM_DIR(cfg); 1846 int slpm_val = PIN_SLPM_VAL(cfg); 1847 1848 /* All pins go into GPIO mode at sleep */ 1849 gpiomode = true; 1850 1851 /* 1852 * The SLPM_* values are normal values + 1 to allow zero 1853 * to mean "same as normal". 1854 */ 1855 if (slpm_pull) 1856 pull = slpm_pull - 1; 1857 if (slpm_output) 1858 output = slpm_output - 1; 1859 if (slpm_val) 1860 val = slpm_val - 1; 1861 1862 dev_dbg(nmk_chip->chip.parent, 1863 "pin %d: sleep pull %s, dir %s, val %s\n", 1864 pin, 1865 slpm_pull ? pullnames[pull] : "same", 1866 slpm_output ? (output ? "output" : "input") 1867 : "same", 1868 slpm_val ? (val ? "high" : "low") : "same"); 1869 } 1870 1871 dev_dbg(nmk_chip->chip.parent, 1872 "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n", 1873 pin, cfg, pullnames[pull], slpmnames[slpm], 1874 output ? "output " : "input", 1875 output ? (val ? "high" : "low") : "", 1876 lowemi ? "on" : "off"); 1877 1878 clk_enable(nmk_chip->clk); 1879 bit = pin % NMK_GPIO_PER_CHIP; 1880 if (gpiomode) 1881 /* No glitch when going to GPIO mode */ 1882 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); 1883 if (output) 1884 __nmk_gpio_make_output(nmk_chip, bit, val); 1885 else { 1886 __nmk_gpio_make_input(nmk_chip, bit); 1887 __nmk_gpio_set_pull(nmk_chip, bit, pull); 1888 } 1889 /* TODO: isn't this only applicable on output pins? */ 1890 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi); 1891 1892 __nmk_gpio_set_slpm(nmk_chip, bit, slpm); 1893 clk_disable(nmk_chip->clk); 1894 } /* for each config */ 1895 1896 return 0; 1897 } 1898 1899 static const struct pinconf_ops nmk_pinconf_ops = { 1900 .pin_config_get = nmk_pin_config_get, 1901 .pin_config_set = nmk_pin_config_set, 1902 }; 1903 1904 static struct pinctrl_desc nmk_pinctrl_desc = { 1905 .name = "pinctrl-nomadik", 1906 .pctlops = &nmk_pinctrl_ops, 1907 .pmxops = &nmk_pinmux_ops, 1908 .confops = &nmk_pinconf_ops, 1909 .owner = THIS_MODULE, 1910 }; 1911 1912 static const struct of_device_id nmk_pinctrl_match[] = { 1913 { 1914 .compatible = "stericsson,stn8815-pinctrl", 1915 .data = (void *)PINCTRL_NMK_STN8815, 1916 }, 1917 { 1918 .compatible = "stericsson,db8500-pinctrl", 1919 .data = (void *)PINCTRL_NMK_DB8500, 1920 }, 1921 { 1922 .compatible = "stericsson,db8540-pinctrl", 1923 .data = (void *)PINCTRL_NMK_DB8540, 1924 }, 1925 {}, 1926 }; 1927 1928 #ifdef CONFIG_PM_SLEEP 1929 static int nmk_pinctrl_suspend(struct device *dev) 1930 { 1931 struct nmk_pinctrl *npct; 1932 1933 npct = dev_get_drvdata(dev); 1934 if (!npct) 1935 return -EINVAL; 1936 1937 return pinctrl_force_sleep(npct->pctl); 1938 } 1939 1940 static int nmk_pinctrl_resume(struct device *dev) 1941 { 1942 struct nmk_pinctrl *npct; 1943 1944 npct = dev_get_drvdata(dev); 1945 if (!npct) 1946 return -EINVAL; 1947 1948 return pinctrl_force_default(npct->pctl); 1949 } 1950 #endif 1951 1952 static int nmk_pinctrl_probe(struct platform_device *pdev) 1953 { 1954 const struct of_device_id *match; 1955 struct device_node *np = pdev->dev.of_node; 1956 struct device_node *prcm_np; 1957 struct nmk_pinctrl *npct; 1958 unsigned int version = 0; 1959 int i; 1960 1961 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL); 1962 if (!npct) 1963 return -ENOMEM; 1964 1965 match = of_match_device(nmk_pinctrl_match, &pdev->dev); 1966 if (!match) 1967 return -ENODEV; 1968 version = (unsigned int) match->data; 1969 1970 /* Poke in other ASIC variants here */ 1971 if (version == PINCTRL_NMK_STN8815) 1972 nmk_pinctrl_stn8815_init(&npct->soc); 1973 if (version == PINCTRL_NMK_DB8500) 1974 nmk_pinctrl_db8500_init(&npct->soc); 1975 if (version == PINCTRL_NMK_DB8540) 1976 nmk_pinctrl_db8540_init(&npct->soc); 1977 1978 /* 1979 * Since we depend on the GPIO chips to provide clock and register base 1980 * for the pin control operations, make sure that we have these 1981 * populated before we continue. Follow the phandles to instantiate 1982 * them. The GPIO portion of the actual hardware may be probed before 1983 * or after this point: it shouldn't matter as the APIs are orthogonal. 1984 */ 1985 for (i = 0; i < NMK_MAX_BANKS; i++) { 1986 struct device_node *gpio_np; 1987 struct nmk_gpio_chip *nmk_chip; 1988 1989 gpio_np = of_parse_phandle(np, "nomadik-gpio-chips", i); 1990 if (gpio_np) { 1991 dev_info(&pdev->dev, 1992 "populate NMK GPIO %d \"%s\"\n", 1993 i, gpio_np->name); 1994 nmk_chip = nmk_gpio_populate_chip(gpio_np, pdev); 1995 if (IS_ERR(nmk_chip)) 1996 dev_err(&pdev->dev, 1997 "could not populate nmk chip struct " 1998 "- continue anyway\n"); 1999 of_node_put(gpio_np); 2000 } 2001 } 2002 2003 prcm_np = of_parse_phandle(np, "prcm", 0); 2004 if (prcm_np) 2005 npct->prcm_base = of_iomap(prcm_np, 0); 2006 if (!npct->prcm_base) { 2007 if (version == PINCTRL_NMK_STN8815) { 2008 dev_info(&pdev->dev, 2009 "No PRCM base, " 2010 "assuming no ALT-Cx control is available\n"); 2011 } else { 2012 dev_err(&pdev->dev, "missing PRCM base address\n"); 2013 return -EINVAL; 2014 } 2015 } 2016 2017 nmk_pinctrl_desc.pins = npct->soc->pins; 2018 nmk_pinctrl_desc.npins = npct->soc->npins; 2019 npct->dev = &pdev->dev; 2020 2021 npct->pctl = devm_pinctrl_register(&pdev->dev, &nmk_pinctrl_desc, npct); 2022 if (IS_ERR(npct->pctl)) { 2023 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n"); 2024 return PTR_ERR(npct->pctl); 2025 } 2026 2027 platform_set_drvdata(pdev, npct); 2028 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n"); 2029 2030 return 0; 2031 } 2032 2033 static const struct of_device_id nmk_gpio_match[] = { 2034 { .compatible = "st,nomadik-gpio", }, 2035 {} 2036 }; 2037 2038 static struct platform_driver nmk_gpio_driver = { 2039 .driver = { 2040 .name = "gpio", 2041 .of_match_table = nmk_gpio_match, 2042 }, 2043 .probe = nmk_gpio_probe, 2044 }; 2045 2046 static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops, 2047 nmk_pinctrl_suspend, 2048 nmk_pinctrl_resume); 2049 2050 static struct platform_driver nmk_pinctrl_driver = { 2051 .driver = { 2052 .name = "pinctrl-nomadik", 2053 .of_match_table = nmk_pinctrl_match, 2054 .pm = &nmk_pinctrl_pm_ops, 2055 }, 2056 .probe = nmk_pinctrl_probe, 2057 }; 2058 2059 static int __init nmk_gpio_init(void) 2060 { 2061 return platform_driver_register(&nmk_gpio_driver); 2062 } 2063 subsys_initcall(nmk_gpio_init); 2064 2065 static int __init nmk_pinctrl_init(void) 2066 { 2067 return platform_driver_register(&nmk_pinctrl_driver); 2068 } 2069 core_initcall(nmk_pinctrl_init); 2070 2071 MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini"); 2072 MODULE_DESCRIPTION("Nomadik GPIO Driver"); 2073 MODULE_LICENSE("GPL"); 2074