1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Generic GPIO driver for logic cells found in the Nomadik SoC 4 * 5 * Copyright (C) 2008,2009 STMicroelectronics 6 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> 7 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> 8 * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org> 9 */ 10 #include <linux/bitops.h> 11 #include <linux/clk.h> 12 #include <linux/device.h> 13 #include <linux/err.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/kernel.h> 19 #include <linux/of.h> 20 #include <linux/of_address.h> 21 #include <linux/of_platform.h> 22 #include <linux/platform_device.h> 23 #include <linux/property.h> 24 #include <linux/seq_file.h> 25 #include <linux/slab.h> 26 #include <linux/spinlock.h> 27 28 /* Since we request GPIOs from ourself */ 29 #include <linux/pinctrl/consumer.h> 30 #include <linux/pinctrl/machine.h> 31 #include <linux/pinctrl/pinconf.h> 32 #include <linux/pinctrl/pinctrl.h> 33 #include <linux/pinctrl/pinmux.h> 34 35 #include "../core.h" 36 #include "../pinctrl-utils.h" 37 38 #include "pinctrl-nomadik.h" 39 40 /* 41 * The GPIO module in the Nomadik family of Systems-on-Chip is an 42 * AMBA device, managing 32 pins and alternate functions. The logic block 43 * is currently used in the Nomadik and ux500. 44 * 45 * Symbols in this file are called "nmk_gpio" for "nomadik gpio" 46 */ 47 48 /* 49 * pin configurations are represented by 32-bit integers: 50 * 51 * bit 0.. 8 - Pin Number (512 Pins Maximum) 52 * bit 9..10 - Alternate Function Selection 53 * bit 11..12 - Pull up/down state 54 * bit 13 - Sleep mode behaviour 55 * bit 14 - Direction 56 * bit 15 - Value (if output) 57 * bit 16..18 - SLPM pull up/down state 58 * bit 19..20 - SLPM direction 59 * bit 21..22 - SLPM Value (if output) 60 * bit 23..25 - PDIS value (if input) 61 * bit 26 - Gpio mode 62 * bit 27 - Sleep mode 63 * 64 * to facilitate the definition, the following macros are provided 65 * 66 * PIN_CFG_DEFAULT - default config (0): 67 * pull up/down = disabled 68 * sleep mode = input/wakeup 69 * direction = input 70 * value = low 71 * SLPM direction = same as normal 72 * SLPM pull = same as normal 73 * SLPM value = same as normal 74 * 75 * PIN_CFG - default config with alternate function 76 */ 77 78 typedef unsigned long pin_cfg_t; 79 80 #define PIN_NUM_MASK 0x1ff 81 #define PIN_NUM(x) ((x) & PIN_NUM_MASK) 82 83 #define PIN_ALT_SHIFT 9 84 #define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT) 85 #define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT) 86 #define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT) 87 #define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT) 88 #define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT) 89 #define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT) 90 91 #define PIN_PULL_SHIFT 11 92 #define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT) 93 #define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT) 94 #define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT) 95 #define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT) 96 #define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT) 97 98 #define PIN_SLPM_SHIFT 13 99 #define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT) 100 #define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT) 101 #define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT) 102 #define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT) 103 /* These two replace the above in DB8500v2+ */ 104 #define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT) 105 #define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT) 106 #define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE 107 108 #define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */ 109 #define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */ 110 111 #define PIN_DIR_SHIFT 14 112 #define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT) 113 #define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT) 114 #define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT) 115 #define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT) 116 117 #define PIN_VAL_SHIFT 15 118 #define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT) 119 #define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT) 120 #define PIN_VAL_LOW (0 << PIN_VAL_SHIFT) 121 #define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT) 122 123 #define PIN_SLPM_PULL_SHIFT 16 124 #define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT) 125 #define PIN_SLPM_PULL(x) \ 126 (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT) 127 #define PIN_SLPM_PULL_NONE \ 128 ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT) 129 #define PIN_SLPM_PULL_UP \ 130 ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT) 131 #define PIN_SLPM_PULL_DOWN \ 132 ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT) 133 134 #define PIN_SLPM_DIR_SHIFT 19 135 #define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT) 136 #define PIN_SLPM_DIR(x) \ 137 (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT) 138 #define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT) 139 #define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT) 140 141 #define PIN_SLPM_VAL_SHIFT 21 142 #define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT) 143 #define PIN_SLPM_VAL(x) \ 144 (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT) 145 #define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT) 146 #define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT) 147 148 #define PIN_SLPM_PDIS_SHIFT 23 149 #define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT) 150 #define PIN_SLPM_PDIS(x) \ 151 (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT) 152 #define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT) 153 #define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT) 154 #define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT) 155 156 #define PIN_LOWEMI_SHIFT 25 157 #define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT) 158 #define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT) 159 #define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT) 160 #define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT) 161 162 #define PIN_GPIOMODE_SHIFT 26 163 #define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT) 164 #define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT) 165 #define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT) 166 #define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT) 167 168 #define PIN_SLEEPMODE_SHIFT 27 169 #define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT) 170 #define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT) 171 #define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT) 172 #define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT) 173 174 175 /* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */ 176 #define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN) 177 #define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP) 178 #define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE) 179 #define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW) 180 #define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH) 181 182 #define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN) 183 #define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP) 184 #define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE) 185 #define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW) 186 #define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH) 187 188 #define PIN_CFG_DEFAULT (0) 189 190 #define PIN_CFG(num, alt) \ 191 (PIN_CFG_DEFAULT |\ 192 (PIN_NUM(num) | PIN_##alt)) 193 194 #define PIN_CFG_INPUT(num, alt, pull) \ 195 (PIN_CFG_DEFAULT |\ 196 (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull)) 197 198 #define PIN_CFG_OUTPUT(num, alt, val) \ 199 (PIN_CFG_DEFAULT |\ 200 (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val)) 201 202 /* 203 * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving 204 * the "gpio" namespace for generic and cross-machine functions 205 */ 206 207 #define GPIO_BLOCK_SHIFT 5 208 #define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT) 209 #define NMK_MAX_BANKS DIV_ROUND_UP(512, NMK_GPIO_PER_CHIP) 210 211 /* Register in the logic block */ 212 #define NMK_GPIO_DAT 0x00 213 #define NMK_GPIO_DATS 0x04 214 #define NMK_GPIO_DATC 0x08 215 #define NMK_GPIO_PDIS 0x0c 216 #define NMK_GPIO_DIR 0x10 217 #define NMK_GPIO_DIRS 0x14 218 #define NMK_GPIO_DIRC 0x18 219 #define NMK_GPIO_SLPC 0x1c 220 #define NMK_GPIO_AFSLA 0x20 221 #define NMK_GPIO_AFSLB 0x24 222 #define NMK_GPIO_LOWEMI 0x28 223 224 #define NMK_GPIO_RIMSC 0x40 225 #define NMK_GPIO_FIMSC 0x44 226 #define NMK_GPIO_IS 0x48 227 #define NMK_GPIO_IC 0x4c 228 #define NMK_GPIO_RWIMSC 0x50 229 #define NMK_GPIO_FWIMSC 0x54 230 #define NMK_GPIO_WKS 0x58 231 /* These appear in DB8540 and later ASICs */ 232 #define NMK_GPIO_EDGELEVEL 0x5C 233 #define NMK_GPIO_LEVEL 0x60 234 235 236 /* Pull up/down values */ 237 enum nmk_gpio_pull { 238 NMK_GPIO_PULL_NONE, 239 NMK_GPIO_PULL_UP, 240 NMK_GPIO_PULL_DOWN, 241 }; 242 243 /* Sleep mode */ 244 enum nmk_gpio_slpm { 245 NMK_GPIO_SLPM_INPUT, 246 NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT, 247 NMK_GPIO_SLPM_NOCHANGE, 248 NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE, 249 }; 250 251 struct nmk_gpio_chip { 252 struct gpio_chip chip; 253 void __iomem *addr; 254 struct clk *clk; 255 unsigned int bank; 256 void (*set_ioforce)(bool enable); 257 spinlock_t lock; 258 bool sleepmode; 259 /* Keep track of configured edges */ 260 u32 edge_rising; 261 u32 edge_falling; 262 u32 real_wake; 263 u32 rwimsc; 264 u32 fwimsc; 265 u32 rimsc; 266 u32 fimsc; 267 u32 pull_up; 268 u32 lowemi; 269 }; 270 271 /** 272 * struct nmk_pinctrl - state container for the Nomadik pin controller 273 * @dev: containing device pointer 274 * @pctl: corresponding pin controller device 275 * @soc: SoC data for this specific chip 276 * @prcm_base: PRCM register range virtual base 277 */ 278 struct nmk_pinctrl { 279 struct device *dev; 280 struct pinctrl_dev *pctl; 281 const struct nmk_pinctrl_soc_data *soc; 282 void __iomem *prcm_base; 283 }; 284 285 static struct nmk_gpio_chip *nmk_gpio_chips[NMK_MAX_BANKS]; 286 287 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock); 288 289 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips) 290 291 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, 292 unsigned offset, int gpio_mode) 293 { 294 u32 afunc, bfunc; 295 296 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~BIT(offset); 297 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~BIT(offset); 298 if (gpio_mode & NMK_GPIO_ALT_A) 299 afunc |= BIT(offset); 300 if (gpio_mode & NMK_GPIO_ALT_B) 301 bfunc |= BIT(offset); 302 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); 303 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); 304 } 305 306 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, 307 unsigned offset, enum nmk_gpio_slpm mode) 308 { 309 u32 slpm; 310 311 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); 312 if (mode == NMK_GPIO_SLPM_NOCHANGE) 313 slpm |= BIT(offset); 314 else 315 slpm &= ~BIT(offset); 316 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); 317 } 318 319 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, 320 unsigned offset, enum nmk_gpio_pull pull) 321 { 322 u32 pdis; 323 324 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); 325 if (pull == NMK_GPIO_PULL_NONE) { 326 pdis |= BIT(offset); 327 nmk_chip->pull_up &= ~BIT(offset); 328 } else { 329 pdis &= ~BIT(offset); 330 } 331 332 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); 333 334 if (pull == NMK_GPIO_PULL_UP) { 335 nmk_chip->pull_up |= BIT(offset); 336 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS); 337 } else if (pull == NMK_GPIO_PULL_DOWN) { 338 nmk_chip->pull_up &= ~BIT(offset); 339 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC); 340 } 341 } 342 343 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip, 344 unsigned offset, bool lowemi) 345 { 346 bool enabled = nmk_chip->lowemi & BIT(offset); 347 348 if (lowemi == enabled) 349 return; 350 351 if (lowemi) 352 nmk_chip->lowemi |= BIT(offset); 353 else 354 nmk_chip->lowemi &= ~BIT(offset); 355 356 writel_relaxed(nmk_chip->lowemi, 357 nmk_chip->addr + NMK_GPIO_LOWEMI); 358 } 359 360 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, 361 unsigned offset) 362 { 363 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC); 364 } 365 366 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, 367 unsigned offset, int val) 368 { 369 if (val) 370 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS); 371 else 372 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC); 373 } 374 375 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, 376 unsigned offset, int val) 377 { 378 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRS); 379 __nmk_gpio_set_output(nmk_chip, offset, val); 380 } 381 382 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, 383 unsigned offset, int gpio_mode, 384 bool glitch) 385 { 386 u32 rwimsc = nmk_chip->rwimsc; 387 u32 fwimsc = nmk_chip->fwimsc; 388 389 if (glitch && nmk_chip->set_ioforce) { 390 u32 bit = BIT(offset); 391 392 /* Prevent spurious wakeups */ 393 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC); 394 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC); 395 396 nmk_chip->set_ioforce(true); 397 } 398 399 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode); 400 401 if (glitch && nmk_chip->set_ioforce) { 402 nmk_chip->set_ioforce(false); 403 404 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC); 405 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC); 406 } 407 } 408 409 static void 410 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset) 411 { 412 u32 falling = nmk_chip->fimsc & BIT(offset); 413 u32 rising = nmk_chip->rimsc & BIT(offset); 414 int gpio = nmk_chip->chip.base + offset; 415 int irq = irq_find_mapping(nmk_chip->chip.irq.domain, offset); 416 struct irq_data *d = irq_get_irq_data(irq); 417 418 if (!rising && !falling) 419 return; 420 421 if (!d || !irqd_irq_disabled(d)) 422 return; 423 424 if (rising) { 425 nmk_chip->rimsc &= ~BIT(offset); 426 writel_relaxed(nmk_chip->rimsc, 427 nmk_chip->addr + NMK_GPIO_RIMSC); 428 } 429 430 if (falling) { 431 nmk_chip->fimsc &= ~BIT(offset); 432 writel_relaxed(nmk_chip->fimsc, 433 nmk_chip->addr + NMK_GPIO_FIMSC); 434 } 435 436 dev_dbg(nmk_chip->chip.parent, "%d: clearing interrupt mask\n", gpio); 437 } 438 439 static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value) 440 { 441 u32 val; 442 443 val = readl(reg); 444 val = ((val & ~mask) | (value & mask)); 445 writel(val, reg); 446 } 447 448 static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct, 449 unsigned offset, unsigned alt_num) 450 { 451 int i; 452 u16 reg; 453 u8 bit; 454 u8 alt_index; 455 const struct prcm_gpiocr_altcx_pin_desc *pin_desc; 456 const u16 *gpiocr_regs; 457 458 if (!npct->prcm_base) 459 return; 460 461 if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) { 462 dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n", 463 alt_num); 464 return; 465 } 466 467 for (i = 0 ; i < npct->soc->npins_altcx ; i++) { 468 if (npct->soc->altcx_pins[i].pin == offset) 469 break; 470 } 471 if (i == npct->soc->npins_altcx) { 472 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n", 473 offset); 474 return; 475 } 476 477 pin_desc = npct->soc->altcx_pins + i; 478 gpiocr_regs = npct->soc->prcm_gpiocr_registers; 479 480 /* 481 * If alt_num is NULL, just clear current ALTCx selection 482 * to make sure we come back to a pure ALTC selection 483 */ 484 if (!alt_num) { 485 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { 486 if (pin_desc->altcx[i].used == true) { 487 reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; 488 bit = pin_desc->altcx[i].control_bit; 489 if (readl(npct->prcm_base + reg) & BIT(bit)) { 490 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); 491 dev_dbg(npct->dev, 492 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", 493 offset, i+1); 494 } 495 } 496 } 497 return; 498 } 499 500 alt_index = alt_num - 1; 501 if (pin_desc->altcx[alt_index].used == false) { 502 dev_warn(npct->dev, 503 "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n", 504 offset, alt_num); 505 return; 506 } 507 508 /* 509 * Check if any other ALTCx functions are activated on this pin 510 * and disable it first. 511 */ 512 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { 513 if (i == alt_index) 514 continue; 515 if (pin_desc->altcx[i].used == true) { 516 reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; 517 bit = pin_desc->altcx[i].control_bit; 518 if (readl(npct->prcm_base + reg) & BIT(bit)) { 519 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); 520 dev_dbg(npct->dev, 521 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", 522 offset, i+1); 523 } 524 } 525 } 526 527 reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index]; 528 bit = pin_desc->altcx[alt_index].control_bit; 529 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n", 530 offset, alt_index+1); 531 nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit)); 532 } 533 534 /* 535 * Safe sequence used to switch IOs between GPIO and Alternate-C mode: 536 * - Save SLPM registers 537 * - Set SLPM=0 for the IOs you want to switch and others to 1 538 * - Configure the GPIO registers for the IOs that are being switched 539 * - Set IOFORCE=1 540 * - Modify the AFLSA/B registers for the IOs that are being switched 541 * - Set IOFORCE=0 542 * - Restore SLPM registers 543 * - Any spurious wake up event during switch sequence to be ignored and 544 * cleared 545 */ 546 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm) 547 { 548 int i; 549 550 for (i = 0; i < NUM_BANKS; i++) { 551 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 552 unsigned int temp = slpm[i]; 553 554 if (!chip) 555 break; 556 557 clk_enable(chip->clk); 558 559 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC); 560 writel(temp, chip->addr + NMK_GPIO_SLPC); 561 } 562 } 563 564 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm) 565 { 566 int i; 567 568 for (i = 0; i < NUM_BANKS; i++) { 569 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 570 571 if (!chip) 572 break; 573 574 writel(slpm[i], chip->addr + NMK_GPIO_SLPC); 575 576 clk_disable(chip->clk); 577 } 578 } 579 580 static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio) 581 { 582 int i; 583 u16 reg; 584 u8 bit; 585 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 586 const struct prcm_gpiocr_altcx_pin_desc *pin_desc; 587 const u16 *gpiocr_regs; 588 589 if (!npct->prcm_base) 590 return NMK_GPIO_ALT_C; 591 592 for (i = 0; i < npct->soc->npins_altcx; i++) { 593 if (npct->soc->altcx_pins[i].pin == gpio) 594 break; 595 } 596 if (i == npct->soc->npins_altcx) 597 return NMK_GPIO_ALT_C; 598 599 pin_desc = npct->soc->altcx_pins + i; 600 gpiocr_regs = npct->soc->prcm_gpiocr_registers; 601 for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) { 602 if (pin_desc->altcx[i].used == true) { 603 reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; 604 bit = pin_desc->altcx[i].control_bit; 605 if (readl(npct->prcm_base + reg) & BIT(bit)) 606 return NMK_GPIO_ALT_C+i+1; 607 } 608 } 609 return NMK_GPIO_ALT_C; 610 } 611 612 /* IRQ functions */ 613 614 static void nmk_gpio_irq_ack(struct irq_data *d) 615 { 616 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 617 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc); 618 619 clk_enable(nmk_chip->clk); 620 writel(BIT(d->hwirq), nmk_chip->addr + NMK_GPIO_IC); 621 clk_disable(nmk_chip->clk); 622 } 623 624 enum nmk_gpio_irq_type { 625 NORMAL, 626 WAKE, 627 }; 628 629 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, 630 int offset, enum nmk_gpio_irq_type which, 631 bool enable) 632 { 633 u32 *rimscval; 634 u32 *fimscval; 635 u32 rimscreg; 636 u32 fimscreg; 637 638 if (which == NORMAL) { 639 rimscreg = NMK_GPIO_RIMSC; 640 fimscreg = NMK_GPIO_FIMSC; 641 rimscval = &nmk_chip->rimsc; 642 fimscval = &nmk_chip->fimsc; 643 } else { 644 rimscreg = NMK_GPIO_RWIMSC; 645 fimscreg = NMK_GPIO_FWIMSC; 646 rimscval = &nmk_chip->rwimsc; 647 fimscval = &nmk_chip->fwimsc; 648 } 649 650 /* we must individually set/clear the two edges */ 651 if (nmk_chip->edge_rising & BIT(offset)) { 652 if (enable) 653 *rimscval |= BIT(offset); 654 else 655 *rimscval &= ~BIT(offset); 656 writel(*rimscval, nmk_chip->addr + rimscreg); 657 } 658 if (nmk_chip->edge_falling & BIT(offset)) { 659 if (enable) 660 *fimscval |= BIT(offset); 661 else 662 *fimscval &= ~BIT(offset); 663 writel(*fimscval, nmk_chip->addr + fimscreg); 664 } 665 } 666 667 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, 668 int offset, bool on) 669 { 670 /* 671 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is 672 * disabled, since setting SLPM to 1 increases power consumption, and 673 * wakeup is anyhow controlled by the RIMSC and FIMSC registers. 674 */ 675 if (nmk_chip->sleepmode && on) { 676 __nmk_gpio_set_slpm(nmk_chip, offset, 677 NMK_GPIO_SLPM_WAKEUP_ENABLE); 678 } 679 680 __nmk_gpio_irq_modify(nmk_chip, offset, WAKE, on); 681 } 682 683 static void nmk_gpio_irq_maskunmask(struct nmk_gpio_chip *nmk_chip, 684 struct irq_data *d, bool enable) 685 { 686 unsigned long flags; 687 688 clk_enable(nmk_chip->clk); 689 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 690 spin_lock(&nmk_chip->lock); 691 692 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable); 693 694 if (!(nmk_chip->real_wake & BIT(d->hwirq))) 695 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable); 696 697 spin_unlock(&nmk_chip->lock); 698 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 699 clk_disable(nmk_chip->clk); 700 } 701 702 static void nmk_gpio_irq_mask(struct irq_data *d) 703 { 704 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 705 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc); 706 707 nmk_gpio_irq_maskunmask(nmk_chip, d, false); 708 gpiochip_disable_irq(gc, irqd_to_hwirq(d)); 709 } 710 711 static void nmk_gpio_irq_unmask(struct irq_data *d) 712 { 713 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 714 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc); 715 716 gpiochip_enable_irq(gc, irqd_to_hwirq(d)); 717 nmk_gpio_irq_maskunmask(nmk_chip, d, true); 718 } 719 720 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 721 { 722 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 723 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc); 724 unsigned long flags; 725 726 clk_enable(nmk_chip->clk); 727 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 728 spin_lock(&nmk_chip->lock); 729 730 if (irqd_irq_disabled(d)) 731 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on); 732 733 if (on) 734 nmk_chip->real_wake |= BIT(d->hwirq); 735 else 736 nmk_chip->real_wake &= ~BIT(d->hwirq); 737 738 spin_unlock(&nmk_chip->lock); 739 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 740 clk_disable(nmk_chip->clk); 741 742 return 0; 743 } 744 745 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) 746 { 747 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 748 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc); 749 bool enabled = !irqd_irq_disabled(d); 750 bool wake = irqd_is_wakeup_set(d); 751 unsigned long flags; 752 753 if (type & IRQ_TYPE_LEVEL_HIGH) 754 return -EINVAL; 755 if (type & IRQ_TYPE_LEVEL_LOW) 756 return -EINVAL; 757 758 clk_enable(nmk_chip->clk); 759 spin_lock_irqsave(&nmk_chip->lock, flags); 760 761 if (enabled) 762 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false); 763 764 if (enabled || wake) 765 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false); 766 767 nmk_chip->edge_rising &= ~BIT(d->hwirq); 768 if (type & IRQ_TYPE_EDGE_RISING) 769 nmk_chip->edge_rising |= BIT(d->hwirq); 770 771 nmk_chip->edge_falling &= ~BIT(d->hwirq); 772 if (type & IRQ_TYPE_EDGE_FALLING) 773 nmk_chip->edge_falling |= BIT(d->hwirq); 774 775 if (enabled) 776 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true); 777 778 if (enabled || wake) 779 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true); 780 781 spin_unlock_irqrestore(&nmk_chip->lock, flags); 782 clk_disable(nmk_chip->clk); 783 784 return 0; 785 } 786 787 static unsigned int nmk_gpio_irq_startup(struct irq_data *d) 788 { 789 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 790 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc); 791 792 clk_enable(nmk_chip->clk); 793 nmk_gpio_irq_unmask(d); 794 return 0; 795 } 796 797 static void nmk_gpio_irq_shutdown(struct irq_data *d) 798 { 799 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 800 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc); 801 802 nmk_gpio_irq_mask(d); 803 clk_disable(nmk_chip->clk); 804 } 805 806 static void nmk_gpio_irq_handler(struct irq_desc *desc) 807 { 808 struct irq_chip *host_chip = irq_desc_get_chip(desc); 809 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 810 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 811 u32 status; 812 813 chained_irq_enter(host_chip, desc); 814 815 clk_enable(nmk_chip->clk); 816 status = readl(nmk_chip->addr + NMK_GPIO_IS); 817 clk_disable(nmk_chip->clk); 818 819 while (status) { 820 int bit = __ffs(status); 821 822 generic_handle_domain_irq(chip->irq.domain, bit); 823 status &= ~BIT(bit); 824 } 825 826 chained_irq_exit(host_chip, desc); 827 } 828 829 /* I/O Functions */ 830 831 static int nmk_gpio_get_dir(struct gpio_chip *chip, unsigned offset) 832 { 833 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 834 int dir; 835 836 clk_enable(nmk_chip->clk); 837 838 dir = readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset); 839 840 clk_disable(nmk_chip->clk); 841 842 if (dir) 843 return GPIO_LINE_DIRECTION_OUT; 844 845 return GPIO_LINE_DIRECTION_IN; 846 } 847 848 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) 849 { 850 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 851 852 clk_enable(nmk_chip->clk); 853 854 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC); 855 856 clk_disable(nmk_chip->clk); 857 858 return 0; 859 } 860 861 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset) 862 { 863 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 864 int value; 865 866 clk_enable(nmk_chip->clk); 867 868 value = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset)); 869 870 clk_disable(nmk_chip->clk); 871 872 return value; 873 } 874 875 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset, 876 int val) 877 { 878 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 879 880 clk_enable(nmk_chip->clk); 881 882 __nmk_gpio_set_output(nmk_chip, offset, val); 883 884 clk_disable(nmk_chip->clk); 885 } 886 887 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, 888 int val) 889 { 890 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 891 892 clk_enable(nmk_chip->clk); 893 894 __nmk_gpio_make_output(nmk_chip, offset, val); 895 896 clk_disable(nmk_chip->clk); 897 898 return 0; 899 } 900 901 #ifdef CONFIG_DEBUG_FS 902 static int nmk_gpio_get_mode(struct nmk_gpio_chip *nmk_chip, int offset) 903 { 904 u32 afunc, bfunc; 905 906 clk_enable(nmk_chip->clk); 907 908 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & BIT(offset); 909 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & BIT(offset); 910 911 clk_disable(nmk_chip->clk); 912 913 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0); 914 } 915 916 static void nmk_gpio_dbg_show_one(struct seq_file *s, 917 struct pinctrl_dev *pctldev, struct gpio_chip *chip, 918 unsigned offset, unsigned gpio) 919 { 920 const char *label = gpiochip_is_requested(chip, offset); 921 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 922 int mode; 923 bool is_out; 924 bool data_out; 925 bool pull; 926 const char *modes[] = { 927 [NMK_GPIO_ALT_GPIO] = "gpio", 928 [NMK_GPIO_ALT_A] = "altA", 929 [NMK_GPIO_ALT_B] = "altB", 930 [NMK_GPIO_ALT_C] = "altC", 931 [NMK_GPIO_ALT_C+1] = "altC1", 932 [NMK_GPIO_ALT_C+2] = "altC2", 933 [NMK_GPIO_ALT_C+3] = "altC3", 934 [NMK_GPIO_ALT_C+4] = "altC4", 935 }; 936 937 clk_enable(nmk_chip->clk); 938 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset)); 939 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & BIT(offset)); 940 data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset)); 941 mode = nmk_gpio_get_mode(nmk_chip, offset); 942 if ((mode == NMK_GPIO_ALT_C) && pctldev) 943 mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio); 944 945 if (is_out) { 946 seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s", 947 gpio, 948 label ?: "(none)", 949 data_out ? "hi" : "lo", 950 (mode < 0) ? "unknown" : modes[mode]); 951 } else { 952 int irq = chip->to_irq(chip, offset); 953 const int pullidx = pull ? 1 : 0; 954 int val; 955 static const char * const pulls[] = { 956 "none ", 957 "pull enabled", 958 }; 959 960 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s", 961 gpio, 962 label ?: "(none)", 963 pulls[pullidx], 964 (mode < 0) ? "unknown" : modes[mode]); 965 966 val = nmk_gpio_get_input(chip, offset); 967 seq_printf(s, " VAL %d", val); 968 969 /* 970 * This races with request_irq(), set_irq_type(), 971 * and set_irq_wake() ... but those are "rare". 972 */ 973 if (irq > 0 && irq_has_action(irq)) { 974 char *trigger; 975 bool wake; 976 977 if (nmk_chip->edge_rising & BIT(offset)) 978 trigger = "edge-rising"; 979 else if (nmk_chip->edge_falling & BIT(offset)) 980 trigger = "edge-falling"; 981 else 982 trigger = "edge-undefined"; 983 984 wake = !!(nmk_chip->real_wake & BIT(offset)); 985 986 seq_printf(s, " irq-%d %s%s", 987 irq, trigger, wake ? " wakeup" : ""); 988 } 989 } 990 clk_disable(nmk_chip->clk); 991 } 992 993 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 994 { 995 unsigned i; 996 unsigned gpio = chip->base; 997 998 for (i = 0; i < chip->ngpio; i++, gpio++) { 999 nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio); 1000 seq_printf(s, "\n"); 1001 } 1002 } 1003 1004 #else 1005 static inline void nmk_gpio_dbg_show_one(struct seq_file *s, 1006 struct pinctrl_dev *pctldev, 1007 struct gpio_chip *chip, 1008 unsigned offset, unsigned gpio) 1009 { 1010 } 1011 #define nmk_gpio_dbg_show NULL 1012 #endif 1013 1014 /* 1015 * We will allocate memory for the state container using devm* allocators 1016 * binding to the first device reaching this point, it doesn't matter if 1017 * it is the pin controller or GPIO driver. However we need to use the right 1018 * platform device when looking up resources so pay attention to pdev. 1019 */ 1020 static struct nmk_gpio_chip *nmk_gpio_populate_chip(struct device_node *np, 1021 struct platform_device *pdev) 1022 { 1023 struct nmk_gpio_chip *nmk_chip; 1024 struct platform_device *gpio_pdev; 1025 struct gpio_chip *chip; 1026 struct resource *res; 1027 struct clk *clk; 1028 void __iomem *base; 1029 u32 id; 1030 1031 gpio_pdev = of_find_device_by_node(np); 1032 if (!gpio_pdev) { 1033 pr_err("populate \"%pOFn\": device not found\n", np); 1034 return ERR_PTR(-ENODEV); 1035 } 1036 if (of_property_read_u32(np, "gpio-bank", &id)) { 1037 dev_err(&pdev->dev, "populate: gpio-bank property not found\n"); 1038 platform_device_put(gpio_pdev); 1039 return ERR_PTR(-EINVAL); 1040 } 1041 1042 /* Already populated? */ 1043 nmk_chip = nmk_gpio_chips[id]; 1044 if (nmk_chip) { 1045 platform_device_put(gpio_pdev); 1046 return nmk_chip; 1047 } 1048 1049 nmk_chip = devm_kzalloc(&pdev->dev, sizeof(*nmk_chip), GFP_KERNEL); 1050 if (!nmk_chip) { 1051 platform_device_put(gpio_pdev); 1052 return ERR_PTR(-ENOMEM); 1053 } 1054 1055 nmk_chip->bank = id; 1056 chip = &nmk_chip->chip; 1057 chip->base = id * NMK_GPIO_PER_CHIP; 1058 chip->ngpio = NMK_GPIO_PER_CHIP; 1059 chip->label = dev_name(&gpio_pdev->dev); 1060 chip->parent = &gpio_pdev->dev; 1061 1062 res = platform_get_resource(gpio_pdev, IORESOURCE_MEM, 0); 1063 base = devm_ioremap_resource(&pdev->dev, res); 1064 if (IS_ERR(base)) { 1065 platform_device_put(gpio_pdev); 1066 return ERR_CAST(base); 1067 } 1068 nmk_chip->addr = base; 1069 1070 clk = clk_get(&gpio_pdev->dev, NULL); 1071 if (IS_ERR(clk)) { 1072 platform_device_put(gpio_pdev); 1073 return (void *) clk; 1074 } 1075 clk_prepare(clk); 1076 nmk_chip->clk = clk; 1077 1078 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); 1079 nmk_gpio_chips[id] = nmk_chip; 1080 return nmk_chip; 1081 } 1082 1083 static void nmk_gpio_irq_print_chip(struct irq_data *d, struct seq_file *p) 1084 { 1085 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1086 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc); 1087 1088 seq_printf(p, "nmk%u-%u-%u", nmk_chip->bank, 1089 gc->base, gc->base + gc->ngpio - 1); 1090 } 1091 1092 static const struct irq_chip nmk_irq_chip = { 1093 .irq_ack = nmk_gpio_irq_ack, 1094 .irq_mask = nmk_gpio_irq_mask, 1095 .irq_unmask = nmk_gpio_irq_unmask, 1096 .irq_set_type = nmk_gpio_irq_set_type, 1097 .irq_set_wake = nmk_gpio_irq_set_wake, 1098 .irq_startup = nmk_gpio_irq_startup, 1099 .irq_shutdown = nmk_gpio_irq_shutdown, 1100 .irq_print_chip = nmk_gpio_irq_print_chip, 1101 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE, 1102 GPIOCHIP_IRQ_RESOURCE_HELPERS, 1103 }; 1104 1105 static int nmk_gpio_probe(struct platform_device *dev) 1106 { 1107 struct device_node *np = dev->dev.of_node; 1108 struct nmk_gpio_chip *nmk_chip; 1109 struct gpio_chip *chip; 1110 struct gpio_irq_chip *girq; 1111 bool supports_sleepmode; 1112 int irq; 1113 int ret; 1114 1115 nmk_chip = nmk_gpio_populate_chip(np, dev); 1116 if (IS_ERR(nmk_chip)) { 1117 dev_err(&dev->dev, "could not populate nmk chip struct\n"); 1118 return PTR_ERR(nmk_chip); 1119 } 1120 1121 supports_sleepmode = 1122 of_property_read_bool(np, "st,supports-sleepmode"); 1123 1124 /* Correct platform device ID */ 1125 dev->id = nmk_chip->bank; 1126 1127 irq = platform_get_irq(dev, 0); 1128 if (irq < 0) 1129 return irq; 1130 1131 /* 1132 * The virt address in nmk_chip->addr is in the nomadik register space, 1133 * so we can simply convert the resource address, without remapping 1134 */ 1135 nmk_chip->sleepmode = supports_sleepmode; 1136 spin_lock_init(&nmk_chip->lock); 1137 1138 chip = &nmk_chip->chip; 1139 chip->parent = &dev->dev; 1140 chip->request = gpiochip_generic_request; 1141 chip->free = gpiochip_generic_free; 1142 chip->get_direction = nmk_gpio_get_dir; 1143 chip->direction_input = nmk_gpio_make_input; 1144 chip->get = nmk_gpio_get_input; 1145 chip->direction_output = nmk_gpio_make_output; 1146 chip->set = nmk_gpio_set_output; 1147 chip->dbg_show = nmk_gpio_dbg_show; 1148 chip->can_sleep = false; 1149 chip->owner = THIS_MODULE; 1150 1151 girq = &chip->irq; 1152 gpio_irq_chip_set_chip(girq, &nmk_irq_chip); 1153 girq->parent_handler = nmk_gpio_irq_handler; 1154 girq->num_parents = 1; 1155 girq->parents = devm_kcalloc(&dev->dev, 1, 1156 sizeof(*girq->parents), 1157 GFP_KERNEL); 1158 if (!girq->parents) 1159 return -ENOMEM; 1160 girq->parents[0] = irq; 1161 girq->default_type = IRQ_TYPE_NONE; 1162 girq->handler = handle_edge_irq; 1163 1164 clk_enable(nmk_chip->clk); 1165 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); 1166 clk_disable(nmk_chip->clk); 1167 1168 ret = gpiochip_add_data(chip, nmk_chip); 1169 if (ret) 1170 return ret; 1171 1172 platform_set_drvdata(dev, nmk_chip); 1173 1174 dev_info(&dev->dev, "chip registered\n"); 1175 1176 return 0; 1177 } 1178 1179 static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev) 1180 { 1181 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1182 1183 return npct->soc->ngroups; 1184 } 1185 1186 static const char *nmk_get_group_name(struct pinctrl_dev *pctldev, 1187 unsigned selector) 1188 { 1189 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1190 1191 return npct->soc->groups[selector].grp.name; 1192 } 1193 1194 static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, 1195 const unsigned **pins, 1196 unsigned *npins) 1197 { 1198 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1199 1200 *pins = npct->soc->groups[selector].grp.pins; 1201 *npins = npct->soc->groups[selector].grp.npins; 1202 return 0; 1203 } 1204 1205 static struct nmk_gpio_chip *find_nmk_gpio_from_pin(unsigned pin) 1206 { 1207 int i; 1208 struct nmk_gpio_chip *nmk_gpio; 1209 1210 for(i = 0; i < NMK_MAX_BANKS; i++) { 1211 nmk_gpio = nmk_gpio_chips[i]; 1212 if (!nmk_gpio) 1213 continue; 1214 if (pin >= nmk_gpio->chip.base && 1215 pin < nmk_gpio->chip.base + nmk_gpio->chip.ngpio) 1216 return nmk_gpio; 1217 } 1218 return NULL; 1219 } 1220 1221 static struct gpio_chip *find_gc_from_pin(unsigned pin) 1222 { 1223 struct nmk_gpio_chip *nmk_gpio = find_nmk_gpio_from_pin(pin); 1224 1225 if (nmk_gpio) 1226 return &nmk_gpio->chip; 1227 return NULL; 1228 } 1229 1230 static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 1231 unsigned offset) 1232 { 1233 struct gpio_chip *chip = find_gc_from_pin(offset); 1234 1235 if (!chip) { 1236 seq_printf(s, "invalid pin offset"); 1237 return; 1238 } 1239 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset); 1240 } 1241 1242 static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps, 1243 unsigned *num_maps, const char *group, 1244 const char *function) 1245 { 1246 if (*num_maps == *reserved_maps) 1247 return -ENOSPC; 1248 1249 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 1250 (*map)[*num_maps].data.mux.group = group; 1251 (*map)[*num_maps].data.mux.function = function; 1252 (*num_maps)++; 1253 1254 return 0; 1255 } 1256 1257 static int nmk_dt_add_map_configs(struct pinctrl_map **map, 1258 unsigned *reserved_maps, 1259 unsigned *num_maps, const char *group, 1260 unsigned long *configs, unsigned num_configs) 1261 { 1262 unsigned long *dup_configs; 1263 1264 if (*num_maps == *reserved_maps) 1265 return -ENOSPC; 1266 1267 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), 1268 GFP_KERNEL); 1269 if (!dup_configs) 1270 return -ENOMEM; 1271 1272 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN; 1273 1274 (*map)[*num_maps].data.configs.group_or_pin = group; 1275 (*map)[*num_maps].data.configs.configs = dup_configs; 1276 (*map)[*num_maps].data.configs.num_configs = num_configs; 1277 (*num_maps)++; 1278 1279 return 0; 1280 } 1281 1282 #define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, } 1283 #define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \ 1284 .size = ARRAY_SIZE(y), } 1285 1286 static const unsigned long nmk_pin_input_modes[] = { 1287 PIN_INPUT_NOPULL, 1288 PIN_INPUT_PULLUP, 1289 PIN_INPUT_PULLDOWN, 1290 }; 1291 1292 static const unsigned long nmk_pin_output_modes[] = { 1293 PIN_OUTPUT_LOW, 1294 PIN_OUTPUT_HIGH, 1295 PIN_DIR_OUTPUT, 1296 }; 1297 1298 static const unsigned long nmk_pin_sleep_modes[] = { 1299 PIN_SLEEPMODE_DISABLED, 1300 PIN_SLEEPMODE_ENABLED, 1301 }; 1302 1303 static const unsigned long nmk_pin_sleep_input_modes[] = { 1304 PIN_SLPM_INPUT_NOPULL, 1305 PIN_SLPM_INPUT_PULLUP, 1306 PIN_SLPM_INPUT_PULLDOWN, 1307 PIN_SLPM_DIR_INPUT, 1308 }; 1309 1310 static const unsigned long nmk_pin_sleep_output_modes[] = { 1311 PIN_SLPM_OUTPUT_LOW, 1312 PIN_SLPM_OUTPUT_HIGH, 1313 PIN_SLPM_DIR_OUTPUT, 1314 }; 1315 1316 static const unsigned long nmk_pin_sleep_wakeup_modes[] = { 1317 PIN_SLPM_WAKEUP_DISABLE, 1318 PIN_SLPM_WAKEUP_ENABLE, 1319 }; 1320 1321 static const unsigned long nmk_pin_gpio_modes[] = { 1322 PIN_GPIOMODE_DISABLED, 1323 PIN_GPIOMODE_ENABLED, 1324 }; 1325 1326 static const unsigned long nmk_pin_sleep_pdis_modes[] = { 1327 PIN_SLPM_PDIS_DISABLED, 1328 PIN_SLPM_PDIS_ENABLED, 1329 }; 1330 1331 struct nmk_cfg_param { 1332 const char *property; 1333 unsigned long config; 1334 const unsigned long *choice; 1335 int size; 1336 }; 1337 1338 static const struct nmk_cfg_param nmk_cfg_params[] = { 1339 NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes), 1340 NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes), 1341 NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes), 1342 NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes), 1343 NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes), 1344 NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes), 1345 NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes), 1346 NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes), 1347 }; 1348 1349 static int nmk_dt_pin_config(int index, int val, unsigned long *config) 1350 { 1351 if (nmk_cfg_params[index].choice == NULL) 1352 *config = nmk_cfg_params[index].config; 1353 else { 1354 /* test if out of range */ 1355 if (val < nmk_cfg_params[index].size) { 1356 *config = nmk_cfg_params[index].config | 1357 nmk_cfg_params[index].choice[val]; 1358 } 1359 } 1360 return 0; 1361 } 1362 1363 static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name) 1364 { 1365 int i, pin_number; 1366 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1367 1368 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1) 1369 for (i = 0; i < npct->soc->npins; i++) 1370 if (npct->soc->pins[i].number == pin_number) 1371 return npct->soc->pins[i].name; 1372 return NULL; 1373 } 1374 1375 static bool nmk_pinctrl_dt_get_config(struct device_node *np, 1376 unsigned long *configs) 1377 { 1378 bool has_config = 0; 1379 unsigned long cfg = 0; 1380 int i, val, ret; 1381 1382 for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) { 1383 ret = of_property_read_u32(np, 1384 nmk_cfg_params[i].property, &val); 1385 if (ret != -EINVAL) { 1386 if (nmk_dt_pin_config(i, val, &cfg) == 0) { 1387 *configs |= cfg; 1388 has_config = 1; 1389 } 1390 } 1391 } 1392 1393 return has_config; 1394 } 1395 1396 static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 1397 struct device_node *np, 1398 struct pinctrl_map **map, 1399 unsigned *reserved_maps, 1400 unsigned *num_maps) 1401 { 1402 int ret; 1403 const char *function = NULL; 1404 unsigned long configs = 0; 1405 bool has_config = 0; 1406 struct property *prop; 1407 struct device_node *np_config; 1408 1409 ret = of_property_read_string(np, "function", &function); 1410 if (ret >= 0) { 1411 const char *group; 1412 1413 ret = of_property_count_strings(np, "groups"); 1414 if (ret < 0) 1415 goto exit; 1416 1417 ret = pinctrl_utils_reserve_map(pctldev, map, 1418 reserved_maps, 1419 num_maps, ret); 1420 if (ret < 0) 1421 goto exit; 1422 1423 of_property_for_each_string(np, "groups", prop, group) { 1424 ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps, 1425 group, function); 1426 if (ret < 0) 1427 goto exit; 1428 } 1429 } 1430 1431 has_config = nmk_pinctrl_dt_get_config(np, &configs); 1432 np_config = of_parse_phandle(np, "ste,config", 0); 1433 if (np_config) { 1434 has_config |= nmk_pinctrl_dt_get_config(np_config, &configs); 1435 of_node_put(np_config); 1436 } 1437 if (has_config) { 1438 const char *gpio_name; 1439 const char *pin; 1440 1441 ret = of_property_count_strings(np, "pins"); 1442 if (ret < 0) 1443 goto exit; 1444 ret = pinctrl_utils_reserve_map(pctldev, map, 1445 reserved_maps, 1446 num_maps, ret); 1447 if (ret < 0) 1448 goto exit; 1449 1450 of_property_for_each_string(np, "pins", prop, pin) { 1451 gpio_name = nmk_find_pin_name(pctldev, pin); 1452 1453 ret = nmk_dt_add_map_configs(map, reserved_maps, 1454 num_maps, 1455 gpio_name, &configs, 1); 1456 if (ret < 0) 1457 goto exit; 1458 } 1459 } 1460 1461 exit: 1462 return ret; 1463 } 1464 1465 static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 1466 struct device_node *np_config, 1467 struct pinctrl_map **map, unsigned *num_maps) 1468 { 1469 unsigned reserved_maps; 1470 struct device_node *np; 1471 int ret; 1472 1473 reserved_maps = 0; 1474 *map = NULL; 1475 *num_maps = 0; 1476 1477 for_each_child_of_node(np_config, np) { 1478 ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map, 1479 &reserved_maps, num_maps); 1480 if (ret < 0) { 1481 pinctrl_utils_free_map(pctldev, *map, *num_maps); 1482 of_node_put(np); 1483 return ret; 1484 } 1485 } 1486 1487 return 0; 1488 } 1489 1490 static const struct pinctrl_ops nmk_pinctrl_ops = { 1491 .get_groups_count = nmk_get_groups_cnt, 1492 .get_group_name = nmk_get_group_name, 1493 .get_group_pins = nmk_get_group_pins, 1494 .pin_dbg_show = nmk_pin_dbg_show, 1495 .dt_node_to_map = nmk_pinctrl_dt_node_to_map, 1496 .dt_free_map = pinctrl_utils_free_map, 1497 }; 1498 1499 static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 1500 { 1501 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1502 1503 return npct->soc->nfunctions; 1504 } 1505 1506 static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev, 1507 unsigned function) 1508 { 1509 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1510 1511 return npct->soc->functions[function].name; 1512 } 1513 1514 static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev, 1515 unsigned function, 1516 const char * const **groups, 1517 unsigned * const num_groups) 1518 { 1519 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1520 1521 *groups = npct->soc->functions[function].groups; 1522 *num_groups = npct->soc->functions[function].ngroups; 1523 1524 return 0; 1525 } 1526 1527 static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned function, 1528 unsigned group) 1529 { 1530 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1531 const struct nmk_pingroup *g; 1532 static unsigned int slpm[NUM_BANKS]; 1533 unsigned long flags = 0; 1534 bool glitch; 1535 int ret = -EINVAL; 1536 int i; 1537 1538 g = &npct->soc->groups[group]; 1539 1540 if (g->altsetting < 0) 1541 return -EINVAL; 1542 1543 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->grp.name, g->grp.npins); 1544 1545 /* 1546 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1, 1547 * we may pass through an undesired state. In this case we take 1548 * some extra care. 1549 * 1550 * Safe sequence used to switch IOs between GPIO and Alternate-C mode: 1551 * - Save SLPM registers (since we have a shadow register in the 1552 * nmk_chip we're using that as backup) 1553 * - Set SLPM=0 for the IOs you want to switch and others to 1 1554 * - Configure the GPIO registers for the IOs that are being switched 1555 * - Set IOFORCE=1 1556 * - Modify the AFLSA/B registers for the IOs that are being switched 1557 * - Set IOFORCE=0 1558 * - Restore SLPM registers 1559 * - Any spurious wake up event during switch sequence to be ignored 1560 * and cleared 1561 * 1562 * We REALLY need to save ALL slpm registers, because the external 1563 * IOFORCE will switch *all* ports to their sleepmode setting to as 1564 * to avoid glitches. (Not just one port!) 1565 */ 1566 glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C); 1567 1568 if (glitch) { 1569 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 1570 1571 /* Initially don't put any pins to sleep when switching */ 1572 memset(slpm, 0xff, sizeof(slpm)); 1573 1574 /* 1575 * Then mask the pins that need to be sleeping now when we're 1576 * switching to the ALT C function. 1577 */ 1578 for (i = 0; i < g->grp.npins; i++) { 1579 unsigned int bit = g->grp.pins[i] % NMK_GPIO_PER_CHIP; 1580 slpm[g->grp.pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(bit); 1581 } 1582 nmk_gpio_glitch_slpm_init(slpm); 1583 } 1584 1585 for (i = 0; i < g->grp.npins; i++) { 1586 struct nmk_gpio_chip *nmk_chip; 1587 unsigned bit; 1588 1589 nmk_chip = find_nmk_gpio_from_pin(g->grp.pins[i]); 1590 if (!nmk_chip) { 1591 dev_err(npct->dev, 1592 "invalid pin offset %d in group %s at index %d\n", 1593 g->grp.pins[i], g->grp.name, i); 1594 goto out_glitch; 1595 } 1596 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->grp.pins[i], g->altsetting); 1597 1598 clk_enable(nmk_chip->clk); 1599 bit = g->grp.pins[i] % NMK_GPIO_PER_CHIP; 1600 /* 1601 * If the pin is switching to altfunc, and there was an 1602 * interrupt installed on it which has been lazy disabled, 1603 * actually mask the interrupt to prevent spurious interrupts 1604 * that would occur while the pin is under control of the 1605 * peripheral. Only SKE does this. 1606 */ 1607 nmk_gpio_disable_lazy_irq(nmk_chip, bit); 1608 1609 __nmk_gpio_set_mode_safe(nmk_chip, bit, 1610 (g->altsetting & NMK_GPIO_ALT_C), glitch); 1611 clk_disable(nmk_chip->clk); 1612 1613 /* 1614 * Call PRCM GPIOCR config function in case ALTC 1615 * has been selected: 1616 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers 1617 * must be set. 1618 * - If selection is pure ALTC and previous selection was ALTCx, 1619 * then some bits in PRCM GPIOCR registers must be cleared. 1620 */ 1621 if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C) 1622 nmk_prcm_altcx_set_mode(npct, g->grp.pins[i], 1623 g->altsetting >> NMK_GPIO_ALT_CX_SHIFT); 1624 } 1625 1626 /* When all pins are successfully reconfigured we get here */ 1627 ret = 0; 1628 1629 out_glitch: 1630 if (glitch) { 1631 nmk_gpio_glitch_slpm_restore(slpm); 1632 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 1633 } 1634 1635 return ret; 1636 } 1637 1638 static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev, 1639 struct pinctrl_gpio_range *range, 1640 unsigned offset) 1641 { 1642 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1643 struct nmk_gpio_chip *nmk_chip; 1644 struct gpio_chip *chip; 1645 unsigned bit; 1646 1647 if (!range) { 1648 dev_err(npct->dev, "invalid range\n"); 1649 return -EINVAL; 1650 } 1651 if (!range->gc) { 1652 dev_err(npct->dev, "missing GPIO chip in range\n"); 1653 return -EINVAL; 1654 } 1655 chip = range->gc; 1656 nmk_chip = gpiochip_get_data(chip); 1657 1658 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); 1659 1660 clk_enable(nmk_chip->clk); 1661 bit = offset % NMK_GPIO_PER_CHIP; 1662 /* There is no glitch when converting any pin to GPIO */ 1663 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); 1664 clk_disable(nmk_chip->clk); 1665 1666 return 0; 1667 } 1668 1669 static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev, 1670 struct pinctrl_gpio_range *range, 1671 unsigned offset) 1672 { 1673 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1674 1675 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); 1676 /* Set the pin to some default state, GPIO is usually default */ 1677 } 1678 1679 static const struct pinmux_ops nmk_pinmux_ops = { 1680 .get_functions_count = nmk_pmx_get_funcs_cnt, 1681 .get_function_name = nmk_pmx_get_func_name, 1682 .get_function_groups = nmk_pmx_get_func_groups, 1683 .set_mux = nmk_pmx_set, 1684 .gpio_request_enable = nmk_gpio_request_enable, 1685 .gpio_disable_free = nmk_gpio_disable_free, 1686 .strict = true, 1687 }; 1688 1689 static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, 1690 unsigned long *config) 1691 { 1692 /* Not implemented */ 1693 return -EINVAL; 1694 } 1695 1696 static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, 1697 unsigned long *configs, unsigned num_configs) 1698 { 1699 static const char *pullnames[] = { 1700 [NMK_GPIO_PULL_NONE] = "none", 1701 [NMK_GPIO_PULL_UP] = "up", 1702 [NMK_GPIO_PULL_DOWN] = "down", 1703 [3] /* illegal */ = "??" 1704 }; 1705 static const char *slpmnames[] = { 1706 [NMK_GPIO_SLPM_INPUT] = "input/wakeup", 1707 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", 1708 }; 1709 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1710 struct nmk_gpio_chip *nmk_chip; 1711 unsigned bit; 1712 pin_cfg_t cfg; 1713 int pull, slpm, output, val, i; 1714 bool lowemi, gpiomode, sleep; 1715 1716 nmk_chip = find_nmk_gpio_from_pin(pin); 1717 if (!nmk_chip) { 1718 dev_err(npct->dev, 1719 "invalid pin offset %d\n", pin); 1720 return -EINVAL; 1721 } 1722 1723 for (i = 0; i < num_configs; i++) { 1724 /* 1725 * The pin config contains pin number and altfunction fields, 1726 * here we just ignore that part. It's being handled by the 1727 * framework and pinmux callback respectively. 1728 */ 1729 cfg = (pin_cfg_t) configs[i]; 1730 pull = PIN_PULL(cfg); 1731 slpm = PIN_SLPM(cfg); 1732 output = PIN_DIR(cfg); 1733 val = PIN_VAL(cfg); 1734 lowemi = PIN_LOWEMI(cfg); 1735 gpiomode = PIN_GPIOMODE(cfg); 1736 sleep = PIN_SLEEPMODE(cfg); 1737 1738 if (sleep) { 1739 int slpm_pull = PIN_SLPM_PULL(cfg); 1740 int slpm_output = PIN_SLPM_DIR(cfg); 1741 int slpm_val = PIN_SLPM_VAL(cfg); 1742 1743 /* All pins go into GPIO mode at sleep */ 1744 gpiomode = true; 1745 1746 /* 1747 * The SLPM_* values are normal values + 1 to allow zero 1748 * to mean "same as normal". 1749 */ 1750 if (slpm_pull) 1751 pull = slpm_pull - 1; 1752 if (slpm_output) 1753 output = slpm_output - 1; 1754 if (slpm_val) 1755 val = slpm_val - 1; 1756 1757 dev_dbg(nmk_chip->chip.parent, 1758 "pin %d: sleep pull %s, dir %s, val %s\n", 1759 pin, 1760 slpm_pull ? pullnames[pull] : "same", 1761 slpm_output ? (output ? "output" : "input") 1762 : "same", 1763 slpm_val ? (val ? "high" : "low") : "same"); 1764 } 1765 1766 dev_dbg(nmk_chip->chip.parent, 1767 "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n", 1768 pin, cfg, pullnames[pull], slpmnames[slpm], 1769 output ? "output " : "input", 1770 output ? (val ? "high" : "low") : "", 1771 lowemi ? "on" : "off"); 1772 1773 clk_enable(nmk_chip->clk); 1774 bit = pin % NMK_GPIO_PER_CHIP; 1775 if (gpiomode) 1776 /* No glitch when going to GPIO mode */ 1777 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); 1778 if (output) 1779 __nmk_gpio_make_output(nmk_chip, bit, val); 1780 else { 1781 __nmk_gpio_make_input(nmk_chip, bit); 1782 __nmk_gpio_set_pull(nmk_chip, bit, pull); 1783 } 1784 /* TODO: isn't this only applicable on output pins? */ 1785 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi); 1786 1787 __nmk_gpio_set_slpm(nmk_chip, bit, slpm); 1788 clk_disable(nmk_chip->clk); 1789 } /* for each config */ 1790 1791 return 0; 1792 } 1793 1794 static const struct pinconf_ops nmk_pinconf_ops = { 1795 .pin_config_get = nmk_pin_config_get, 1796 .pin_config_set = nmk_pin_config_set, 1797 }; 1798 1799 static struct pinctrl_desc nmk_pinctrl_desc = { 1800 .name = "pinctrl-nomadik", 1801 .pctlops = &nmk_pinctrl_ops, 1802 .pmxops = &nmk_pinmux_ops, 1803 .confops = &nmk_pinconf_ops, 1804 .owner = THIS_MODULE, 1805 }; 1806 1807 static const struct of_device_id nmk_pinctrl_match[] = { 1808 { 1809 .compatible = "stericsson,stn8815-pinctrl", 1810 .data = (void *)PINCTRL_NMK_STN8815, 1811 }, 1812 { 1813 .compatible = "stericsson,db8500-pinctrl", 1814 .data = (void *)PINCTRL_NMK_DB8500, 1815 }, 1816 {}, 1817 }; 1818 1819 #ifdef CONFIG_PM_SLEEP 1820 static int nmk_pinctrl_suspend(struct device *dev) 1821 { 1822 struct nmk_pinctrl *npct; 1823 1824 npct = dev_get_drvdata(dev); 1825 if (!npct) 1826 return -EINVAL; 1827 1828 return pinctrl_force_sleep(npct->pctl); 1829 } 1830 1831 static int nmk_pinctrl_resume(struct device *dev) 1832 { 1833 struct nmk_pinctrl *npct; 1834 1835 npct = dev_get_drvdata(dev); 1836 if (!npct) 1837 return -EINVAL; 1838 1839 return pinctrl_force_default(npct->pctl); 1840 } 1841 #endif 1842 1843 static int nmk_pinctrl_probe(struct platform_device *pdev) 1844 { 1845 struct device_node *np = pdev->dev.of_node; 1846 struct device_node *prcm_np; 1847 struct nmk_pinctrl *npct; 1848 unsigned int version = 0; 1849 int i; 1850 1851 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL); 1852 if (!npct) 1853 return -ENOMEM; 1854 1855 version = (unsigned int)device_get_match_data(&pdev->dev); 1856 1857 /* Poke in other ASIC variants here */ 1858 if (version == PINCTRL_NMK_STN8815) 1859 nmk_pinctrl_stn8815_init(&npct->soc); 1860 if (version == PINCTRL_NMK_DB8500) 1861 nmk_pinctrl_db8500_init(&npct->soc); 1862 1863 /* 1864 * Since we depend on the GPIO chips to provide clock and register base 1865 * for the pin control operations, make sure that we have these 1866 * populated before we continue. Follow the phandles to instantiate 1867 * them. The GPIO portion of the actual hardware may be probed before 1868 * or after this point: it shouldn't matter as the APIs are orthogonal. 1869 */ 1870 for (i = 0; i < NMK_MAX_BANKS; i++) { 1871 struct device_node *gpio_np; 1872 struct nmk_gpio_chip *nmk_chip; 1873 1874 gpio_np = of_parse_phandle(np, "nomadik-gpio-chips", i); 1875 if (gpio_np) { 1876 dev_info(&pdev->dev, 1877 "populate NMK GPIO %d \"%pOFn\"\n", 1878 i, gpio_np); 1879 nmk_chip = nmk_gpio_populate_chip(gpio_np, pdev); 1880 if (IS_ERR(nmk_chip)) 1881 dev_err(&pdev->dev, 1882 "could not populate nmk chip struct " 1883 "- continue anyway\n"); 1884 of_node_put(gpio_np); 1885 } 1886 } 1887 1888 prcm_np = of_parse_phandle(np, "prcm", 0); 1889 if (prcm_np) { 1890 npct->prcm_base = of_iomap(prcm_np, 0); 1891 of_node_put(prcm_np); 1892 } 1893 if (!npct->prcm_base) { 1894 if (version == PINCTRL_NMK_STN8815) { 1895 dev_info(&pdev->dev, 1896 "No PRCM base, " 1897 "assuming no ALT-Cx control is available\n"); 1898 } else { 1899 dev_err(&pdev->dev, "missing PRCM base address\n"); 1900 return -EINVAL; 1901 } 1902 } 1903 1904 nmk_pinctrl_desc.pins = npct->soc->pins; 1905 nmk_pinctrl_desc.npins = npct->soc->npins; 1906 npct->dev = &pdev->dev; 1907 1908 npct->pctl = devm_pinctrl_register(&pdev->dev, &nmk_pinctrl_desc, npct); 1909 if (IS_ERR(npct->pctl)) { 1910 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n"); 1911 return PTR_ERR(npct->pctl); 1912 } 1913 1914 platform_set_drvdata(pdev, npct); 1915 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n"); 1916 1917 return 0; 1918 } 1919 1920 static const struct of_device_id nmk_gpio_match[] = { 1921 { .compatible = "st,nomadik-gpio", }, 1922 {} 1923 }; 1924 1925 static struct platform_driver nmk_gpio_driver = { 1926 .driver = { 1927 .name = "gpio", 1928 .of_match_table = nmk_gpio_match, 1929 }, 1930 .probe = nmk_gpio_probe, 1931 }; 1932 1933 static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops, 1934 nmk_pinctrl_suspend, 1935 nmk_pinctrl_resume); 1936 1937 static struct platform_driver nmk_pinctrl_driver = { 1938 .driver = { 1939 .name = "pinctrl-nomadik", 1940 .of_match_table = nmk_pinctrl_match, 1941 .pm = &nmk_pinctrl_pm_ops, 1942 }, 1943 .probe = nmk_pinctrl_probe, 1944 }; 1945 1946 static int __init nmk_gpio_init(void) 1947 { 1948 return platform_driver_register(&nmk_gpio_driver); 1949 } 1950 subsys_initcall(nmk_gpio_init); 1951 1952 static int __init nmk_pinctrl_init(void) 1953 { 1954 return platform_driver_register(&nmk_pinctrl_driver); 1955 } 1956 core_initcall(nmk_pinctrl_init); 1957