1 /* 2 * Generic GPIO driver for logic cells found in the Nomadik SoC 3 * 4 * Copyright (C) 2008,2009 STMicroelectronics 5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> 6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> 7 * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/init.h> 16 #include <linux/device.h> 17 #include <linux/platform_device.h> 18 #include <linux/io.h> 19 #include <linux/clk.h> 20 #include <linux/err.h> 21 #include <linux/gpio.h> 22 #include <linux/spinlock.h> 23 #include <linux/interrupt.h> 24 #include <linux/slab.h> 25 #include <linux/of_device.h> 26 #include <linux/of_address.h> 27 #include <linux/bitops.h> 28 #include <linux/pinctrl/machine.h> 29 #include <linux/pinctrl/pinctrl.h> 30 #include <linux/pinctrl/pinmux.h> 31 #include <linux/pinctrl/pinconf.h> 32 /* Since we request GPIOs from ourself */ 33 #include <linux/pinctrl/consumer.h> 34 #include "pinctrl-nomadik.h" 35 #include "../core.h" 36 #include "../pinctrl-utils.h" 37 38 /* 39 * The GPIO module in the Nomadik family of Systems-on-Chip is an 40 * AMBA device, managing 32 pins and alternate functions. The logic block 41 * is currently used in the Nomadik and ux500. 42 * 43 * Symbols in this file are called "nmk_gpio" for "nomadik gpio" 44 */ 45 46 /* 47 * pin configurations are represented by 32-bit integers: 48 * 49 * bit 0.. 8 - Pin Number (512 Pins Maximum) 50 * bit 9..10 - Alternate Function Selection 51 * bit 11..12 - Pull up/down state 52 * bit 13 - Sleep mode behaviour 53 * bit 14 - Direction 54 * bit 15 - Value (if output) 55 * bit 16..18 - SLPM pull up/down state 56 * bit 19..20 - SLPM direction 57 * bit 21..22 - SLPM Value (if output) 58 * bit 23..25 - PDIS value (if input) 59 * bit 26 - Gpio mode 60 * bit 27 - Sleep mode 61 * 62 * to facilitate the definition, the following macros are provided 63 * 64 * PIN_CFG_DEFAULT - default config (0): 65 * pull up/down = disabled 66 * sleep mode = input/wakeup 67 * direction = input 68 * value = low 69 * SLPM direction = same as normal 70 * SLPM pull = same as normal 71 * SLPM value = same as normal 72 * 73 * PIN_CFG - default config with alternate function 74 */ 75 76 typedef unsigned long pin_cfg_t; 77 78 #define PIN_NUM_MASK 0x1ff 79 #define PIN_NUM(x) ((x) & PIN_NUM_MASK) 80 81 #define PIN_ALT_SHIFT 9 82 #define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT) 83 #define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT) 84 #define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT) 85 #define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT) 86 #define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT) 87 #define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT) 88 89 #define PIN_PULL_SHIFT 11 90 #define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT) 91 #define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT) 92 #define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT) 93 #define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT) 94 #define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT) 95 96 #define PIN_SLPM_SHIFT 13 97 #define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT) 98 #define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT) 99 #define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT) 100 #define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT) 101 /* These two replace the above in DB8500v2+ */ 102 #define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT) 103 #define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT) 104 #define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE 105 106 #define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */ 107 #define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */ 108 109 #define PIN_DIR_SHIFT 14 110 #define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT) 111 #define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT) 112 #define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT) 113 #define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT) 114 115 #define PIN_VAL_SHIFT 15 116 #define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT) 117 #define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT) 118 #define PIN_VAL_LOW (0 << PIN_VAL_SHIFT) 119 #define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT) 120 121 #define PIN_SLPM_PULL_SHIFT 16 122 #define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT) 123 #define PIN_SLPM_PULL(x) \ 124 (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT) 125 #define PIN_SLPM_PULL_NONE \ 126 ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT) 127 #define PIN_SLPM_PULL_UP \ 128 ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT) 129 #define PIN_SLPM_PULL_DOWN \ 130 ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT) 131 132 #define PIN_SLPM_DIR_SHIFT 19 133 #define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT) 134 #define PIN_SLPM_DIR(x) \ 135 (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT) 136 #define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT) 137 #define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT) 138 139 #define PIN_SLPM_VAL_SHIFT 21 140 #define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT) 141 #define PIN_SLPM_VAL(x) \ 142 (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT) 143 #define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT) 144 #define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT) 145 146 #define PIN_SLPM_PDIS_SHIFT 23 147 #define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT) 148 #define PIN_SLPM_PDIS(x) \ 149 (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT) 150 #define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT) 151 #define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT) 152 #define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT) 153 154 #define PIN_LOWEMI_SHIFT 25 155 #define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT) 156 #define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT) 157 #define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT) 158 #define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT) 159 160 #define PIN_GPIOMODE_SHIFT 26 161 #define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT) 162 #define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT) 163 #define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT) 164 #define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT) 165 166 #define PIN_SLEEPMODE_SHIFT 27 167 #define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT) 168 #define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT) 169 #define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT) 170 #define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT) 171 172 173 /* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */ 174 #define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN) 175 #define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP) 176 #define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE) 177 #define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW) 178 #define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH) 179 180 #define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN) 181 #define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP) 182 #define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE) 183 #define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW) 184 #define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH) 185 186 #define PIN_CFG_DEFAULT (0) 187 188 #define PIN_CFG(num, alt) \ 189 (PIN_CFG_DEFAULT |\ 190 (PIN_NUM(num) | PIN_##alt)) 191 192 #define PIN_CFG_INPUT(num, alt, pull) \ 193 (PIN_CFG_DEFAULT |\ 194 (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull)) 195 196 #define PIN_CFG_OUTPUT(num, alt, val) \ 197 (PIN_CFG_DEFAULT |\ 198 (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val)) 199 200 /* 201 * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving 202 * the "gpio" namespace for generic and cross-machine functions 203 */ 204 205 #define GPIO_BLOCK_SHIFT 5 206 #define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT) 207 #define NMK_MAX_BANKS DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP) 208 209 /* Register in the logic block */ 210 #define NMK_GPIO_DAT 0x00 211 #define NMK_GPIO_DATS 0x04 212 #define NMK_GPIO_DATC 0x08 213 #define NMK_GPIO_PDIS 0x0c 214 #define NMK_GPIO_DIR 0x10 215 #define NMK_GPIO_DIRS 0x14 216 #define NMK_GPIO_DIRC 0x18 217 #define NMK_GPIO_SLPC 0x1c 218 #define NMK_GPIO_AFSLA 0x20 219 #define NMK_GPIO_AFSLB 0x24 220 #define NMK_GPIO_LOWEMI 0x28 221 222 #define NMK_GPIO_RIMSC 0x40 223 #define NMK_GPIO_FIMSC 0x44 224 #define NMK_GPIO_IS 0x48 225 #define NMK_GPIO_IC 0x4c 226 #define NMK_GPIO_RWIMSC 0x50 227 #define NMK_GPIO_FWIMSC 0x54 228 #define NMK_GPIO_WKS 0x58 229 /* These appear in DB8540 and later ASICs */ 230 #define NMK_GPIO_EDGELEVEL 0x5C 231 #define NMK_GPIO_LEVEL 0x60 232 233 234 /* Pull up/down values */ 235 enum nmk_gpio_pull { 236 NMK_GPIO_PULL_NONE, 237 NMK_GPIO_PULL_UP, 238 NMK_GPIO_PULL_DOWN, 239 }; 240 241 /* Sleep mode */ 242 enum nmk_gpio_slpm { 243 NMK_GPIO_SLPM_INPUT, 244 NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT, 245 NMK_GPIO_SLPM_NOCHANGE, 246 NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE, 247 }; 248 249 struct nmk_gpio_chip { 250 struct gpio_chip chip; 251 struct irq_chip irqchip; 252 void __iomem *addr; 253 struct clk *clk; 254 unsigned int bank; 255 unsigned int parent_irq; 256 int latent_parent_irq; 257 u32 (*get_latent_status)(unsigned int bank); 258 void (*set_ioforce)(bool enable); 259 spinlock_t lock; 260 bool sleepmode; 261 /* Keep track of configured edges */ 262 u32 edge_rising; 263 u32 edge_falling; 264 u32 real_wake; 265 u32 rwimsc; 266 u32 fwimsc; 267 u32 rimsc; 268 u32 fimsc; 269 u32 pull_up; 270 u32 lowemi; 271 }; 272 273 /** 274 * struct nmk_pinctrl - state container for the Nomadik pin controller 275 * @dev: containing device pointer 276 * @pctl: corresponding pin controller device 277 * @soc: SoC data for this specific chip 278 * @prcm_base: PRCM register range virtual base 279 */ 280 struct nmk_pinctrl { 281 struct device *dev; 282 struct pinctrl_dev *pctl; 283 const struct nmk_pinctrl_soc_data *soc; 284 void __iomem *prcm_base; 285 }; 286 287 static struct nmk_gpio_chip *nmk_gpio_chips[NMK_MAX_BANKS]; 288 289 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock); 290 291 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips) 292 293 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, 294 unsigned offset, int gpio_mode) 295 { 296 u32 afunc, bfunc; 297 298 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~BIT(offset); 299 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~BIT(offset); 300 if (gpio_mode & NMK_GPIO_ALT_A) 301 afunc |= BIT(offset); 302 if (gpio_mode & NMK_GPIO_ALT_B) 303 bfunc |= BIT(offset); 304 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); 305 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); 306 } 307 308 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, 309 unsigned offset, enum nmk_gpio_slpm mode) 310 { 311 u32 slpm; 312 313 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); 314 if (mode == NMK_GPIO_SLPM_NOCHANGE) 315 slpm |= BIT(offset); 316 else 317 slpm &= ~BIT(offset); 318 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); 319 } 320 321 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, 322 unsigned offset, enum nmk_gpio_pull pull) 323 { 324 u32 pdis; 325 326 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); 327 if (pull == NMK_GPIO_PULL_NONE) { 328 pdis |= BIT(offset); 329 nmk_chip->pull_up &= ~BIT(offset); 330 } else { 331 pdis &= ~BIT(offset); 332 } 333 334 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); 335 336 if (pull == NMK_GPIO_PULL_UP) { 337 nmk_chip->pull_up |= BIT(offset); 338 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS); 339 } else if (pull == NMK_GPIO_PULL_DOWN) { 340 nmk_chip->pull_up &= ~BIT(offset); 341 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC); 342 } 343 } 344 345 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip, 346 unsigned offset, bool lowemi) 347 { 348 bool enabled = nmk_chip->lowemi & BIT(offset); 349 350 if (lowemi == enabled) 351 return; 352 353 if (lowemi) 354 nmk_chip->lowemi |= BIT(offset); 355 else 356 nmk_chip->lowemi &= ~BIT(offset); 357 358 writel_relaxed(nmk_chip->lowemi, 359 nmk_chip->addr + NMK_GPIO_LOWEMI); 360 } 361 362 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, 363 unsigned offset) 364 { 365 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC); 366 } 367 368 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, 369 unsigned offset, int val) 370 { 371 if (val) 372 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS); 373 else 374 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC); 375 } 376 377 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, 378 unsigned offset, int val) 379 { 380 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRS); 381 __nmk_gpio_set_output(nmk_chip, offset, val); 382 } 383 384 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, 385 unsigned offset, int gpio_mode, 386 bool glitch) 387 { 388 u32 rwimsc = nmk_chip->rwimsc; 389 u32 fwimsc = nmk_chip->fwimsc; 390 391 if (glitch && nmk_chip->set_ioforce) { 392 u32 bit = BIT(offset); 393 394 /* Prevent spurious wakeups */ 395 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC); 396 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC); 397 398 nmk_chip->set_ioforce(true); 399 } 400 401 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode); 402 403 if (glitch && nmk_chip->set_ioforce) { 404 nmk_chip->set_ioforce(false); 405 406 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC); 407 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC); 408 } 409 } 410 411 static void 412 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset) 413 { 414 u32 falling = nmk_chip->fimsc & BIT(offset); 415 u32 rising = nmk_chip->rimsc & BIT(offset); 416 int gpio = nmk_chip->chip.base + offset; 417 int irq = irq_find_mapping(nmk_chip->chip.irqdomain, offset); 418 struct irq_data *d = irq_get_irq_data(irq); 419 420 if (!rising && !falling) 421 return; 422 423 if (!d || !irqd_irq_disabled(d)) 424 return; 425 426 if (rising) { 427 nmk_chip->rimsc &= ~BIT(offset); 428 writel_relaxed(nmk_chip->rimsc, 429 nmk_chip->addr + NMK_GPIO_RIMSC); 430 } 431 432 if (falling) { 433 nmk_chip->fimsc &= ~BIT(offset); 434 writel_relaxed(nmk_chip->fimsc, 435 nmk_chip->addr + NMK_GPIO_FIMSC); 436 } 437 438 dev_dbg(nmk_chip->chip.parent, "%d: clearing interrupt mask\n", gpio); 439 } 440 441 static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value) 442 { 443 u32 val; 444 445 val = readl(reg); 446 val = ((val & ~mask) | (value & mask)); 447 writel(val, reg); 448 } 449 450 static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct, 451 unsigned offset, unsigned alt_num) 452 { 453 int i; 454 u16 reg; 455 u8 bit; 456 u8 alt_index; 457 const struct prcm_gpiocr_altcx_pin_desc *pin_desc; 458 const u16 *gpiocr_regs; 459 460 if (!npct->prcm_base) 461 return; 462 463 if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) { 464 dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n", 465 alt_num); 466 return; 467 } 468 469 for (i = 0 ; i < npct->soc->npins_altcx ; i++) { 470 if (npct->soc->altcx_pins[i].pin == offset) 471 break; 472 } 473 if (i == npct->soc->npins_altcx) { 474 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n", 475 offset); 476 return; 477 } 478 479 pin_desc = npct->soc->altcx_pins + i; 480 gpiocr_regs = npct->soc->prcm_gpiocr_registers; 481 482 /* 483 * If alt_num is NULL, just clear current ALTCx selection 484 * to make sure we come back to a pure ALTC selection 485 */ 486 if (!alt_num) { 487 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { 488 if (pin_desc->altcx[i].used == true) { 489 reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; 490 bit = pin_desc->altcx[i].control_bit; 491 if (readl(npct->prcm_base + reg) & BIT(bit)) { 492 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); 493 dev_dbg(npct->dev, 494 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", 495 offset, i+1); 496 } 497 } 498 } 499 return; 500 } 501 502 alt_index = alt_num - 1; 503 if (pin_desc->altcx[alt_index].used == false) { 504 dev_warn(npct->dev, 505 "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n", 506 offset, alt_num); 507 return; 508 } 509 510 /* 511 * Check if any other ALTCx functions are activated on this pin 512 * and disable it first. 513 */ 514 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { 515 if (i == alt_index) 516 continue; 517 if (pin_desc->altcx[i].used == true) { 518 reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; 519 bit = pin_desc->altcx[i].control_bit; 520 if (readl(npct->prcm_base + reg) & BIT(bit)) { 521 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); 522 dev_dbg(npct->dev, 523 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", 524 offset, i+1); 525 } 526 } 527 } 528 529 reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index]; 530 bit = pin_desc->altcx[alt_index].control_bit; 531 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n", 532 offset, alt_index+1); 533 nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit)); 534 } 535 536 /* 537 * Safe sequence used to switch IOs between GPIO and Alternate-C mode: 538 * - Save SLPM registers 539 * - Set SLPM=0 for the IOs you want to switch and others to 1 540 * - Configure the GPIO registers for the IOs that are being switched 541 * - Set IOFORCE=1 542 * - Modify the AFLSA/B registers for the IOs that are being switched 543 * - Set IOFORCE=0 544 * - Restore SLPM registers 545 * - Any spurious wake up event during switch sequence to be ignored and 546 * cleared 547 */ 548 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm) 549 { 550 int i; 551 552 for (i = 0; i < NUM_BANKS; i++) { 553 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 554 unsigned int temp = slpm[i]; 555 556 if (!chip) 557 break; 558 559 clk_enable(chip->clk); 560 561 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC); 562 writel(temp, chip->addr + NMK_GPIO_SLPC); 563 } 564 } 565 566 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm) 567 { 568 int i; 569 570 for (i = 0; i < NUM_BANKS; i++) { 571 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 572 573 if (!chip) 574 break; 575 576 writel(slpm[i], chip->addr + NMK_GPIO_SLPC); 577 578 clk_disable(chip->clk); 579 } 580 } 581 582 static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio) 583 { 584 int i; 585 u16 reg; 586 u8 bit; 587 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 588 const struct prcm_gpiocr_altcx_pin_desc *pin_desc; 589 const u16 *gpiocr_regs; 590 591 if (!npct->prcm_base) 592 return NMK_GPIO_ALT_C; 593 594 for (i = 0; i < npct->soc->npins_altcx; i++) { 595 if (npct->soc->altcx_pins[i].pin == gpio) 596 break; 597 } 598 if (i == npct->soc->npins_altcx) 599 return NMK_GPIO_ALT_C; 600 601 pin_desc = npct->soc->altcx_pins + i; 602 gpiocr_regs = npct->soc->prcm_gpiocr_registers; 603 for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) { 604 if (pin_desc->altcx[i].used == true) { 605 reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; 606 bit = pin_desc->altcx[i].control_bit; 607 if (readl(npct->prcm_base + reg) & BIT(bit)) 608 return NMK_GPIO_ALT_C+i+1; 609 } 610 } 611 return NMK_GPIO_ALT_C; 612 } 613 614 /* IRQ functions */ 615 616 static void nmk_gpio_irq_ack(struct irq_data *d) 617 { 618 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 619 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 620 621 clk_enable(nmk_chip->clk); 622 writel(BIT(d->hwirq), nmk_chip->addr + NMK_GPIO_IC); 623 clk_disable(nmk_chip->clk); 624 } 625 626 enum nmk_gpio_irq_type { 627 NORMAL, 628 WAKE, 629 }; 630 631 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, 632 int offset, enum nmk_gpio_irq_type which, 633 bool enable) 634 { 635 u32 *rimscval; 636 u32 *fimscval; 637 u32 rimscreg; 638 u32 fimscreg; 639 640 if (which == NORMAL) { 641 rimscreg = NMK_GPIO_RIMSC; 642 fimscreg = NMK_GPIO_FIMSC; 643 rimscval = &nmk_chip->rimsc; 644 fimscval = &nmk_chip->fimsc; 645 } else { 646 rimscreg = NMK_GPIO_RWIMSC; 647 fimscreg = NMK_GPIO_FWIMSC; 648 rimscval = &nmk_chip->rwimsc; 649 fimscval = &nmk_chip->fwimsc; 650 } 651 652 /* we must individually set/clear the two edges */ 653 if (nmk_chip->edge_rising & BIT(offset)) { 654 if (enable) 655 *rimscval |= BIT(offset); 656 else 657 *rimscval &= ~BIT(offset); 658 writel(*rimscval, nmk_chip->addr + rimscreg); 659 } 660 if (nmk_chip->edge_falling & BIT(offset)) { 661 if (enable) 662 *fimscval |= BIT(offset); 663 else 664 *fimscval &= ~BIT(offset); 665 writel(*fimscval, nmk_chip->addr + fimscreg); 666 } 667 } 668 669 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, 670 int offset, bool on) 671 { 672 /* 673 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is 674 * disabled, since setting SLPM to 1 increases power consumption, and 675 * wakeup is anyhow controlled by the RIMSC and FIMSC registers. 676 */ 677 if (nmk_chip->sleepmode && on) { 678 __nmk_gpio_set_slpm(nmk_chip, offset, 679 NMK_GPIO_SLPM_WAKEUP_ENABLE); 680 } 681 682 __nmk_gpio_irq_modify(nmk_chip, offset, WAKE, on); 683 } 684 685 static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) 686 { 687 struct nmk_gpio_chip *nmk_chip; 688 unsigned long flags; 689 690 nmk_chip = irq_data_get_irq_chip_data(d); 691 if (!nmk_chip) 692 return -EINVAL; 693 694 clk_enable(nmk_chip->clk); 695 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 696 spin_lock(&nmk_chip->lock); 697 698 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable); 699 700 if (!(nmk_chip->real_wake & BIT(d->hwirq))) 701 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable); 702 703 spin_unlock(&nmk_chip->lock); 704 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 705 clk_disable(nmk_chip->clk); 706 707 return 0; 708 } 709 710 static void nmk_gpio_irq_mask(struct irq_data *d) 711 { 712 nmk_gpio_irq_maskunmask(d, false); 713 } 714 715 static void nmk_gpio_irq_unmask(struct irq_data *d) 716 { 717 nmk_gpio_irq_maskunmask(d, true); 718 } 719 720 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 721 { 722 struct nmk_gpio_chip *nmk_chip; 723 unsigned long flags; 724 725 nmk_chip = irq_data_get_irq_chip_data(d); 726 if (!nmk_chip) 727 return -EINVAL; 728 729 clk_enable(nmk_chip->clk); 730 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 731 spin_lock(&nmk_chip->lock); 732 733 if (irqd_irq_disabled(d)) 734 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on); 735 736 if (on) 737 nmk_chip->real_wake |= BIT(d->hwirq); 738 else 739 nmk_chip->real_wake &= ~BIT(d->hwirq); 740 741 spin_unlock(&nmk_chip->lock); 742 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 743 clk_disable(nmk_chip->clk); 744 745 return 0; 746 } 747 748 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) 749 { 750 bool enabled = !irqd_irq_disabled(d); 751 bool wake = irqd_is_wakeup_set(d); 752 struct nmk_gpio_chip *nmk_chip; 753 unsigned long flags; 754 755 nmk_chip = irq_data_get_irq_chip_data(d); 756 if (!nmk_chip) 757 return -EINVAL; 758 if (type & IRQ_TYPE_LEVEL_HIGH) 759 return -EINVAL; 760 if (type & IRQ_TYPE_LEVEL_LOW) 761 return -EINVAL; 762 763 clk_enable(nmk_chip->clk); 764 spin_lock_irqsave(&nmk_chip->lock, flags); 765 766 if (enabled) 767 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false); 768 769 if (enabled || wake) 770 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false); 771 772 nmk_chip->edge_rising &= ~BIT(d->hwirq); 773 if (type & IRQ_TYPE_EDGE_RISING) 774 nmk_chip->edge_rising |= BIT(d->hwirq); 775 776 nmk_chip->edge_falling &= ~BIT(d->hwirq); 777 if (type & IRQ_TYPE_EDGE_FALLING) 778 nmk_chip->edge_falling |= BIT(d->hwirq); 779 780 if (enabled) 781 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true); 782 783 if (enabled || wake) 784 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true); 785 786 spin_unlock_irqrestore(&nmk_chip->lock, flags); 787 clk_disable(nmk_chip->clk); 788 789 return 0; 790 } 791 792 static unsigned int nmk_gpio_irq_startup(struct irq_data *d) 793 { 794 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); 795 796 clk_enable(nmk_chip->clk); 797 nmk_gpio_irq_unmask(d); 798 return 0; 799 } 800 801 static void nmk_gpio_irq_shutdown(struct irq_data *d) 802 { 803 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); 804 805 nmk_gpio_irq_mask(d); 806 clk_disable(nmk_chip->clk); 807 } 808 809 static void __nmk_gpio_irq_handler(struct irq_desc *desc, u32 status) 810 { 811 struct irq_chip *host_chip = irq_desc_get_chip(desc); 812 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 813 814 chained_irq_enter(host_chip, desc); 815 816 while (status) { 817 int bit = __ffs(status); 818 819 generic_handle_irq(irq_find_mapping(chip->irqdomain, bit)); 820 status &= ~BIT(bit); 821 } 822 823 chained_irq_exit(host_chip, desc); 824 } 825 826 static void nmk_gpio_irq_handler(struct irq_desc *desc) 827 { 828 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 829 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 830 u32 status; 831 832 clk_enable(nmk_chip->clk); 833 status = readl(nmk_chip->addr + NMK_GPIO_IS); 834 clk_disable(nmk_chip->clk); 835 836 __nmk_gpio_irq_handler(desc, status); 837 } 838 839 static void nmk_gpio_latent_irq_handler(struct irq_desc *desc) 840 { 841 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 842 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 843 u32 status = nmk_chip->get_latent_status(nmk_chip->bank); 844 845 __nmk_gpio_irq_handler(desc, status); 846 } 847 848 /* I/O Functions */ 849 850 static int nmk_gpio_get_dir(struct gpio_chip *chip, unsigned offset) 851 { 852 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 853 int dir; 854 855 clk_enable(nmk_chip->clk); 856 857 dir = !(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset)); 858 859 clk_disable(nmk_chip->clk); 860 861 return dir; 862 } 863 864 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) 865 { 866 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 867 868 clk_enable(nmk_chip->clk); 869 870 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC); 871 872 clk_disable(nmk_chip->clk); 873 874 return 0; 875 } 876 877 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset) 878 { 879 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 880 int value; 881 882 clk_enable(nmk_chip->clk); 883 884 value = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset)); 885 886 clk_disable(nmk_chip->clk); 887 888 return value; 889 } 890 891 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset, 892 int val) 893 { 894 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 895 896 clk_enable(nmk_chip->clk); 897 898 __nmk_gpio_set_output(nmk_chip, offset, val); 899 900 clk_disable(nmk_chip->clk); 901 } 902 903 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, 904 int val) 905 { 906 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 907 908 clk_enable(nmk_chip->clk); 909 910 __nmk_gpio_make_output(nmk_chip, offset, val); 911 912 clk_disable(nmk_chip->clk); 913 914 return 0; 915 } 916 917 #ifdef CONFIG_DEBUG_FS 918 static int nmk_gpio_get_mode(struct nmk_gpio_chip *nmk_chip, int offset) 919 { 920 u32 afunc, bfunc; 921 922 clk_enable(nmk_chip->clk); 923 924 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & BIT(offset); 925 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & BIT(offset); 926 927 clk_disable(nmk_chip->clk); 928 929 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0); 930 } 931 932 #include <linux/seq_file.h> 933 934 static void nmk_gpio_dbg_show_one(struct seq_file *s, 935 struct pinctrl_dev *pctldev, struct gpio_chip *chip, 936 unsigned offset, unsigned gpio) 937 { 938 const char *label = gpiochip_is_requested(chip, offset); 939 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 940 int mode; 941 bool is_out; 942 bool data_out; 943 bool pull; 944 const char *modes[] = { 945 [NMK_GPIO_ALT_GPIO] = "gpio", 946 [NMK_GPIO_ALT_A] = "altA", 947 [NMK_GPIO_ALT_B] = "altB", 948 [NMK_GPIO_ALT_C] = "altC", 949 [NMK_GPIO_ALT_C+1] = "altC1", 950 [NMK_GPIO_ALT_C+2] = "altC2", 951 [NMK_GPIO_ALT_C+3] = "altC3", 952 [NMK_GPIO_ALT_C+4] = "altC4", 953 }; 954 const char *pulls[] = { 955 "none ", 956 "pull down", 957 "pull up ", 958 }; 959 960 clk_enable(nmk_chip->clk); 961 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset)); 962 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & BIT(offset)); 963 data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset)); 964 mode = nmk_gpio_get_mode(nmk_chip, offset); 965 if ((mode == NMK_GPIO_ALT_C) && pctldev) 966 mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio); 967 968 if (is_out) { 969 seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s", 970 gpio, 971 label ?: "(none)", 972 data_out ? "hi" : "lo", 973 (mode < 0) ? "unknown" : modes[mode]); 974 } else { 975 int irq = gpio_to_irq(gpio); 976 struct irq_desc *desc = irq_to_desc(irq); 977 int pullidx = 0; 978 int val; 979 980 if (pull) 981 pullidx = data_out ? 2 : 1; 982 983 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s", 984 gpio, 985 label ?: "(none)", 986 pulls[pullidx], 987 (mode < 0) ? "unknown" : modes[mode]); 988 989 val = nmk_gpio_get_input(chip, offset); 990 seq_printf(s, " VAL %d", val); 991 992 /* 993 * This races with request_irq(), set_irq_type(), 994 * and set_irq_wake() ... but those are "rare". 995 */ 996 if (irq > 0 && desc && desc->action) { 997 char *trigger; 998 999 if (nmk_chip->edge_rising & BIT(offset)) 1000 trigger = "edge-rising"; 1001 else if (nmk_chip->edge_falling & BIT(offset)) 1002 trigger = "edge-falling"; 1003 else 1004 trigger = "edge-undefined"; 1005 1006 seq_printf(s, " irq-%d %s%s", 1007 irq, trigger, 1008 irqd_is_wakeup_set(&desc->irq_data) 1009 ? " wakeup" : ""); 1010 } 1011 } 1012 clk_disable(nmk_chip->clk); 1013 } 1014 1015 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 1016 { 1017 unsigned i; 1018 unsigned gpio = chip->base; 1019 1020 for (i = 0; i < chip->ngpio; i++, gpio++) { 1021 nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio); 1022 seq_printf(s, "\n"); 1023 } 1024 } 1025 1026 #else 1027 static inline void nmk_gpio_dbg_show_one(struct seq_file *s, 1028 struct pinctrl_dev *pctldev, 1029 struct gpio_chip *chip, 1030 unsigned offset, unsigned gpio) 1031 { 1032 } 1033 #define nmk_gpio_dbg_show NULL 1034 #endif 1035 1036 /* 1037 * We will allocate memory for the state container using devm* allocators 1038 * binding to the first device reaching this point, it doesn't matter if 1039 * it is the pin controller or GPIO driver. However we need to use the right 1040 * platform device when looking up resources so pay attention to pdev. 1041 */ 1042 static struct nmk_gpio_chip *nmk_gpio_populate_chip(struct device_node *np, 1043 struct platform_device *pdev) 1044 { 1045 struct nmk_gpio_chip *nmk_chip; 1046 struct platform_device *gpio_pdev; 1047 struct gpio_chip *chip; 1048 struct resource *res; 1049 struct clk *clk; 1050 void __iomem *base; 1051 u32 id; 1052 1053 gpio_pdev = of_find_device_by_node(np); 1054 if (!gpio_pdev) { 1055 pr_err("populate \"%s\": device not found\n", np->name); 1056 return ERR_PTR(-ENODEV); 1057 } 1058 if (of_property_read_u32(np, "gpio-bank", &id)) { 1059 dev_err(&pdev->dev, "populate: gpio-bank property not found\n"); 1060 return ERR_PTR(-EINVAL); 1061 } 1062 1063 /* Already populated? */ 1064 nmk_chip = nmk_gpio_chips[id]; 1065 if (nmk_chip) 1066 return nmk_chip; 1067 1068 nmk_chip = devm_kzalloc(&pdev->dev, sizeof(*nmk_chip), GFP_KERNEL); 1069 if (!nmk_chip) 1070 return ERR_PTR(-ENOMEM); 1071 1072 nmk_chip->bank = id; 1073 chip = &nmk_chip->chip; 1074 chip->base = id * NMK_GPIO_PER_CHIP; 1075 chip->ngpio = NMK_GPIO_PER_CHIP; 1076 chip->label = dev_name(&gpio_pdev->dev); 1077 chip->parent = &gpio_pdev->dev; 1078 1079 res = platform_get_resource(gpio_pdev, IORESOURCE_MEM, 0); 1080 base = devm_ioremap_resource(&pdev->dev, res); 1081 if (IS_ERR(base)) 1082 return base; 1083 nmk_chip->addr = base; 1084 1085 clk = clk_get(&gpio_pdev->dev, NULL); 1086 if (IS_ERR(clk)) 1087 return (void *) clk; 1088 clk_prepare(clk); 1089 nmk_chip->clk = clk; 1090 1091 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); 1092 nmk_gpio_chips[id] = nmk_chip; 1093 return nmk_chip; 1094 } 1095 1096 static int nmk_gpio_probe(struct platform_device *dev) 1097 { 1098 struct device_node *np = dev->dev.of_node; 1099 struct nmk_gpio_chip *nmk_chip; 1100 struct gpio_chip *chip; 1101 struct irq_chip *irqchip; 1102 int latent_irq; 1103 bool supports_sleepmode; 1104 int irq; 1105 int ret; 1106 1107 nmk_chip = nmk_gpio_populate_chip(np, dev); 1108 if (IS_ERR(nmk_chip)) { 1109 dev_err(&dev->dev, "could not populate nmk chip struct\n"); 1110 return PTR_ERR(nmk_chip); 1111 } 1112 1113 supports_sleepmode = 1114 of_property_read_bool(np, "st,supports-sleepmode"); 1115 1116 /* Correct platform device ID */ 1117 dev->id = nmk_chip->bank; 1118 1119 irq = platform_get_irq(dev, 0); 1120 if (irq < 0) 1121 return irq; 1122 1123 /* It's OK for this IRQ not to be present */ 1124 latent_irq = platform_get_irq(dev, 1); 1125 1126 /* 1127 * The virt address in nmk_chip->addr is in the nomadik register space, 1128 * so we can simply convert the resource address, without remapping 1129 */ 1130 nmk_chip->parent_irq = irq; 1131 nmk_chip->latent_parent_irq = latent_irq; 1132 nmk_chip->sleepmode = supports_sleepmode; 1133 spin_lock_init(&nmk_chip->lock); 1134 1135 chip = &nmk_chip->chip; 1136 chip->request = gpiochip_generic_request; 1137 chip->free = gpiochip_generic_free; 1138 chip->get_direction = nmk_gpio_get_dir; 1139 chip->direction_input = nmk_gpio_make_input; 1140 chip->get = nmk_gpio_get_input; 1141 chip->direction_output = nmk_gpio_make_output; 1142 chip->set = nmk_gpio_set_output; 1143 chip->dbg_show = nmk_gpio_dbg_show; 1144 chip->can_sleep = false; 1145 chip->owner = THIS_MODULE; 1146 1147 irqchip = &nmk_chip->irqchip; 1148 irqchip->irq_ack = nmk_gpio_irq_ack; 1149 irqchip->irq_mask = nmk_gpio_irq_mask; 1150 irqchip->irq_unmask = nmk_gpio_irq_unmask; 1151 irqchip->irq_set_type = nmk_gpio_irq_set_type; 1152 irqchip->irq_set_wake = nmk_gpio_irq_set_wake; 1153 irqchip->irq_startup = nmk_gpio_irq_startup; 1154 irqchip->irq_shutdown = nmk_gpio_irq_shutdown; 1155 irqchip->flags = IRQCHIP_MASK_ON_SUSPEND; 1156 irqchip->name = kasprintf(GFP_KERNEL, "nmk%u-%u-%u", 1157 dev->id, 1158 chip->base, 1159 chip->base + chip->ngpio - 1); 1160 1161 clk_enable(nmk_chip->clk); 1162 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); 1163 clk_disable(nmk_chip->clk); 1164 chip->of_node = np; 1165 1166 ret = gpiochip_add_data(chip, nmk_chip); 1167 if (ret) 1168 return ret; 1169 1170 platform_set_drvdata(dev, nmk_chip); 1171 1172 /* 1173 * Let the generic code handle this edge IRQ, the the chained 1174 * handler will perform the actual work of handling the parent 1175 * interrupt. 1176 */ 1177 ret = gpiochip_irqchip_add(chip, 1178 irqchip, 1179 0, 1180 handle_edge_irq, 1181 IRQ_TYPE_EDGE_FALLING); 1182 if (ret) { 1183 dev_err(&dev->dev, "could not add irqchip\n"); 1184 gpiochip_remove(&nmk_chip->chip); 1185 return -ENODEV; 1186 } 1187 /* Then register the chain on the parent IRQ */ 1188 gpiochip_set_chained_irqchip(chip, 1189 irqchip, 1190 nmk_chip->parent_irq, 1191 nmk_gpio_irq_handler); 1192 if (nmk_chip->latent_parent_irq > 0) 1193 gpiochip_set_chained_irqchip(chip, 1194 irqchip, 1195 nmk_chip->latent_parent_irq, 1196 nmk_gpio_latent_irq_handler); 1197 1198 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr); 1199 1200 return 0; 1201 } 1202 1203 static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev) 1204 { 1205 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1206 1207 return npct->soc->ngroups; 1208 } 1209 1210 static const char *nmk_get_group_name(struct pinctrl_dev *pctldev, 1211 unsigned selector) 1212 { 1213 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1214 1215 return npct->soc->groups[selector].name; 1216 } 1217 1218 static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, 1219 const unsigned **pins, 1220 unsigned *num_pins) 1221 { 1222 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1223 1224 *pins = npct->soc->groups[selector].pins; 1225 *num_pins = npct->soc->groups[selector].npins; 1226 return 0; 1227 } 1228 1229 static struct nmk_gpio_chip *find_nmk_gpio_from_pin(unsigned pin) 1230 { 1231 int i; 1232 struct nmk_gpio_chip *nmk_gpio; 1233 1234 for(i = 0; i < NMK_MAX_BANKS; i++) { 1235 nmk_gpio = nmk_gpio_chips[i]; 1236 if (!nmk_gpio) 1237 continue; 1238 if (pin >= nmk_gpio->chip.base && 1239 pin < nmk_gpio->chip.base + nmk_gpio->chip.ngpio) 1240 return nmk_gpio; 1241 } 1242 return NULL; 1243 } 1244 1245 static struct gpio_chip *find_gc_from_pin(unsigned pin) 1246 { 1247 struct nmk_gpio_chip *nmk_gpio = find_nmk_gpio_from_pin(pin); 1248 1249 if (nmk_gpio) 1250 return &nmk_gpio->chip; 1251 return NULL; 1252 } 1253 1254 static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 1255 unsigned offset) 1256 { 1257 struct gpio_chip *chip = find_gc_from_pin(offset); 1258 1259 if (!chip) { 1260 seq_printf(s, "invalid pin offset"); 1261 return; 1262 } 1263 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset); 1264 } 1265 1266 static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps, 1267 unsigned *num_maps, const char *group, 1268 const char *function) 1269 { 1270 if (*num_maps == *reserved_maps) 1271 return -ENOSPC; 1272 1273 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 1274 (*map)[*num_maps].data.mux.group = group; 1275 (*map)[*num_maps].data.mux.function = function; 1276 (*num_maps)++; 1277 1278 return 0; 1279 } 1280 1281 static int nmk_dt_add_map_configs(struct pinctrl_map **map, 1282 unsigned *reserved_maps, 1283 unsigned *num_maps, const char *group, 1284 unsigned long *configs, unsigned num_configs) 1285 { 1286 unsigned long *dup_configs; 1287 1288 if (*num_maps == *reserved_maps) 1289 return -ENOSPC; 1290 1291 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), 1292 GFP_KERNEL); 1293 if (!dup_configs) 1294 return -ENOMEM; 1295 1296 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN; 1297 1298 (*map)[*num_maps].data.configs.group_or_pin = group; 1299 (*map)[*num_maps].data.configs.configs = dup_configs; 1300 (*map)[*num_maps].data.configs.num_configs = num_configs; 1301 (*num_maps)++; 1302 1303 return 0; 1304 } 1305 1306 #define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, } 1307 #define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \ 1308 .size = ARRAY_SIZE(y), } 1309 1310 static const unsigned long nmk_pin_input_modes[] = { 1311 PIN_INPUT_NOPULL, 1312 PIN_INPUT_PULLUP, 1313 PIN_INPUT_PULLDOWN, 1314 }; 1315 1316 static const unsigned long nmk_pin_output_modes[] = { 1317 PIN_OUTPUT_LOW, 1318 PIN_OUTPUT_HIGH, 1319 PIN_DIR_OUTPUT, 1320 }; 1321 1322 static const unsigned long nmk_pin_sleep_modes[] = { 1323 PIN_SLEEPMODE_DISABLED, 1324 PIN_SLEEPMODE_ENABLED, 1325 }; 1326 1327 static const unsigned long nmk_pin_sleep_input_modes[] = { 1328 PIN_SLPM_INPUT_NOPULL, 1329 PIN_SLPM_INPUT_PULLUP, 1330 PIN_SLPM_INPUT_PULLDOWN, 1331 PIN_SLPM_DIR_INPUT, 1332 }; 1333 1334 static const unsigned long nmk_pin_sleep_output_modes[] = { 1335 PIN_SLPM_OUTPUT_LOW, 1336 PIN_SLPM_OUTPUT_HIGH, 1337 PIN_SLPM_DIR_OUTPUT, 1338 }; 1339 1340 static const unsigned long nmk_pin_sleep_wakeup_modes[] = { 1341 PIN_SLPM_WAKEUP_DISABLE, 1342 PIN_SLPM_WAKEUP_ENABLE, 1343 }; 1344 1345 static const unsigned long nmk_pin_gpio_modes[] = { 1346 PIN_GPIOMODE_DISABLED, 1347 PIN_GPIOMODE_ENABLED, 1348 }; 1349 1350 static const unsigned long nmk_pin_sleep_pdis_modes[] = { 1351 PIN_SLPM_PDIS_DISABLED, 1352 PIN_SLPM_PDIS_ENABLED, 1353 }; 1354 1355 struct nmk_cfg_param { 1356 const char *property; 1357 unsigned long config; 1358 const unsigned long *choice; 1359 int size; 1360 }; 1361 1362 static const struct nmk_cfg_param nmk_cfg_params[] = { 1363 NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes), 1364 NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes), 1365 NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes), 1366 NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes), 1367 NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes), 1368 NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes), 1369 NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes), 1370 NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes), 1371 }; 1372 1373 static int nmk_dt_pin_config(int index, int val, unsigned long *config) 1374 { 1375 int ret = 0; 1376 1377 if (nmk_cfg_params[index].choice == NULL) 1378 *config = nmk_cfg_params[index].config; 1379 else { 1380 /* test if out of range */ 1381 if (val < nmk_cfg_params[index].size) { 1382 *config = nmk_cfg_params[index].config | 1383 nmk_cfg_params[index].choice[val]; 1384 } 1385 } 1386 return ret; 1387 } 1388 1389 static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name) 1390 { 1391 int i, pin_number; 1392 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1393 1394 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1) 1395 for (i = 0; i < npct->soc->npins; i++) 1396 if (npct->soc->pins[i].number == pin_number) 1397 return npct->soc->pins[i].name; 1398 return NULL; 1399 } 1400 1401 static bool nmk_pinctrl_dt_get_config(struct device_node *np, 1402 unsigned long *configs) 1403 { 1404 bool has_config = 0; 1405 unsigned long cfg = 0; 1406 int i, val, ret; 1407 1408 for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) { 1409 ret = of_property_read_u32(np, 1410 nmk_cfg_params[i].property, &val); 1411 if (ret != -EINVAL) { 1412 if (nmk_dt_pin_config(i, val, &cfg) == 0) { 1413 *configs |= cfg; 1414 has_config = 1; 1415 } 1416 } 1417 } 1418 1419 return has_config; 1420 } 1421 1422 static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 1423 struct device_node *np, 1424 struct pinctrl_map **map, 1425 unsigned *reserved_maps, 1426 unsigned *num_maps) 1427 { 1428 int ret; 1429 const char *function = NULL; 1430 unsigned long configs = 0; 1431 bool has_config = 0; 1432 struct property *prop; 1433 struct device_node *np_config; 1434 1435 ret = of_property_read_string(np, "function", &function); 1436 if (ret >= 0) { 1437 const char *group; 1438 1439 ret = of_property_count_strings(np, "groups"); 1440 if (ret < 0) 1441 goto exit; 1442 1443 ret = pinctrl_utils_reserve_map(pctldev, map, 1444 reserved_maps, 1445 num_maps, ret); 1446 if (ret < 0) 1447 goto exit; 1448 1449 of_property_for_each_string(np, "groups", prop, group) { 1450 ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps, 1451 group, function); 1452 if (ret < 0) 1453 goto exit; 1454 } 1455 } 1456 1457 has_config = nmk_pinctrl_dt_get_config(np, &configs); 1458 np_config = of_parse_phandle(np, "ste,config", 0); 1459 if (np_config) 1460 has_config |= nmk_pinctrl_dt_get_config(np_config, &configs); 1461 if (has_config) { 1462 const char *gpio_name; 1463 const char *pin; 1464 1465 ret = of_property_count_strings(np, "pins"); 1466 if (ret < 0) 1467 goto exit; 1468 ret = pinctrl_utils_reserve_map(pctldev, map, 1469 reserved_maps, 1470 num_maps, ret); 1471 if (ret < 0) 1472 goto exit; 1473 1474 of_property_for_each_string(np, "pins", prop, pin) { 1475 gpio_name = nmk_find_pin_name(pctldev, pin); 1476 1477 ret = nmk_dt_add_map_configs(map, reserved_maps, 1478 num_maps, 1479 gpio_name, &configs, 1); 1480 if (ret < 0) 1481 goto exit; 1482 } 1483 } 1484 1485 exit: 1486 return ret; 1487 } 1488 1489 static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 1490 struct device_node *np_config, 1491 struct pinctrl_map **map, unsigned *num_maps) 1492 { 1493 unsigned reserved_maps; 1494 struct device_node *np; 1495 int ret; 1496 1497 reserved_maps = 0; 1498 *map = NULL; 1499 *num_maps = 0; 1500 1501 for_each_child_of_node(np_config, np) { 1502 ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map, 1503 &reserved_maps, num_maps); 1504 if (ret < 0) { 1505 pinctrl_utils_free_map(pctldev, *map, *num_maps); 1506 return ret; 1507 } 1508 } 1509 1510 return 0; 1511 } 1512 1513 static const struct pinctrl_ops nmk_pinctrl_ops = { 1514 .get_groups_count = nmk_get_groups_cnt, 1515 .get_group_name = nmk_get_group_name, 1516 .get_group_pins = nmk_get_group_pins, 1517 .pin_dbg_show = nmk_pin_dbg_show, 1518 .dt_node_to_map = nmk_pinctrl_dt_node_to_map, 1519 .dt_free_map = pinctrl_utils_free_map, 1520 }; 1521 1522 static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 1523 { 1524 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1525 1526 return npct->soc->nfunctions; 1527 } 1528 1529 static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev, 1530 unsigned function) 1531 { 1532 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1533 1534 return npct->soc->functions[function].name; 1535 } 1536 1537 static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev, 1538 unsigned function, 1539 const char * const **groups, 1540 unsigned * const num_groups) 1541 { 1542 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1543 1544 *groups = npct->soc->functions[function].groups; 1545 *num_groups = npct->soc->functions[function].ngroups; 1546 1547 return 0; 1548 } 1549 1550 static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned function, 1551 unsigned group) 1552 { 1553 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1554 const struct nmk_pingroup *g; 1555 static unsigned int slpm[NUM_BANKS]; 1556 unsigned long flags = 0; 1557 bool glitch; 1558 int ret = -EINVAL; 1559 int i; 1560 1561 g = &npct->soc->groups[group]; 1562 1563 if (g->altsetting < 0) 1564 return -EINVAL; 1565 1566 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins); 1567 1568 /* 1569 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1, 1570 * we may pass through an undesired state. In this case we take 1571 * some extra care. 1572 * 1573 * Safe sequence used to switch IOs between GPIO and Alternate-C mode: 1574 * - Save SLPM registers (since we have a shadow register in the 1575 * nmk_chip we're using that as backup) 1576 * - Set SLPM=0 for the IOs you want to switch and others to 1 1577 * - Configure the GPIO registers for the IOs that are being switched 1578 * - Set IOFORCE=1 1579 * - Modify the AFLSA/B registers for the IOs that are being switched 1580 * - Set IOFORCE=0 1581 * - Restore SLPM registers 1582 * - Any spurious wake up event during switch sequence to be ignored 1583 * and cleared 1584 * 1585 * We REALLY need to save ALL slpm registers, because the external 1586 * IOFORCE will switch *all* ports to their sleepmode setting to as 1587 * to avoid glitches. (Not just one port!) 1588 */ 1589 glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C); 1590 1591 if (glitch) { 1592 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 1593 1594 /* Initially don't put any pins to sleep when switching */ 1595 memset(slpm, 0xff, sizeof(slpm)); 1596 1597 /* 1598 * Then mask the pins that need to be sleeping now when we're 1599 * switching to the ALT C function. 1600 */ 1601 for (i = 0; i < g->npins; i++) 1602 slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]); 1603 nmk_gpio_glitch_slpm_init(slpm); 1604 } 1605 1606 for (i = 0; i < g->npins; i++) { 1607 struct nmk_gpio_chip *nmk_chip; 1608 unsigned bit; 1609 1610 nmk_chip = find_nmk_gpio_from_pin(g->pins[i]); 1611 if (!nmk_chip) { 1612 dev_err(npct->dev, 1613 "invalid pin offset %d in group %s at index %d\n", 1614 g->pins[i], g->name, i); 1615 goto out_glitch; 1616 } 1617 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting); 1618 1619 clk_enable(nmk_chip->clk); 1620 bit = g->pins[i] % NMK_GPIO_PER_CHIP; 1621 /* 1622 * If the pin is switching to altfunc, and there was an 1623 * interrupt installed on it which has been lazy disabled, 1624 * actually mask the interrupt to prevent spurious interrupts 1625 * that would occur while the pin is under control of the 1626 * peripheral. Only SKE does this. 1627 */ 1628 nmk_gpio_disable_lazy_irq(nmk_chip, bit); 1629 1630 __nmk_gpio_set_mode_safe(nmk_chip, bit, 1631 (g->altsetting & NMK_GPIO_ALT_C), glitch); 1632 clk_disable(nmk_chip->clk); 1633 1634 /* 1635 * Call PRCM GPIOCR config function in case ALTC 1636 * has been selected: 1637 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers 1638 * must be set. 1639 * - If selection is pure ALTC and previous selection was ALTCx, 1640 * then some bits in PRCM GPIOCR registers must be cleared. 1641 */ 1642 if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C) 1643 nmk_prcm_altcx_set_mode(npct, g->pins[i], 1644 g->altsetting >> NMK_GPIO_ALT_CX_SHIFT); 1645 } 1646 1647 /* When all pins are successfully reconfigured we get here */ 1648 ret = 0; 1649 1650 out_glitch: 1651 if (glitch) { 1652 nmk_gpio_glitch_slpm_restore(slpm); 1653 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 1654 } 1655 1656 return ret; 1657 } 1658 1659 static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev, 1660 struct pinctrl_gpio_range *range, 1661 unsigned offset) 1662 { 1663 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1664 struct nmk_gpio_chip *nmk_chip; 1665 struct gpio_chip *chip; 1666 unsigned bit; 1667 1668 if (!range) { 1669 dev_err(npct->dev, "invalid range\n"); 1670 return -EINVAL; 1671 } 1672 if (!range->gc) { 1673 dev_err(npct->dev, "missing GPIO chip in range\n"); 1674 return -EINVAL; 1675 } 1676 chip = range->gc; 1677 nmk_chip = gpiochip_get_data(chip); 1678 1679 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); 1680 1681 clk_enable(nmk_chip->clk); 1682 bit = offset % NMK_GPIO_PER_CHIP; 1683 /* There is no glitch when converting any pin to GPIO */ 1684 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); 1685 clk_disable(nmk_chip->clk); 1686 1687 return 0; 1688 } 1689 1690 static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev, 1691 struct pinctrl_gpio_range *range, 1692 unsigned offset) 1693 { 1694 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1695 1696 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); 1697 /* Set the pin to some default state, GPIO is usually default */ 1698 } 1699 1700 static const struct pinmux_ops nmk_pinmux_ops = { 1701 .get_functions_count = nmk_pmx_get_funcs_cnt, 1702 .get_function_name = nmk_pmx_get_func_name, 1703 .get_function_groups = nmk_pmx_get_func_groups, 1704 .set_mux = nmk_pmx_set, 1705 .gpio_request_enable = nmk_gpio_request_enable, 1706 .gpio_disable_free = nmk_gpio_disable_free, 1707 .strict = true, 1708 }; 1709 1710 static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, 1711 unsigned long *config) 1712 { 1713 /* Not implemented */ 1714 return -EINVAL; 1715 } 1716 1717 static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, 1718 unsigned long *configs, unsigned num_configs) 1719 { 1720 static const char *pullnames[] = { 1721 [NMK_GPIO_PULL_NONE] = "none", 1722 [NMK_GPIO_PULL_UP] = "up", 1723 [NMK_GPIO_PULL_DOWN] = "down", 1724 [3] /* illegal */ = "??" 1725 }; 1726 static const char *slpmnames[] = { 1727 [NMK_GPIO_SLPM_INPUT] = "input/wakeup", 1728 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", 1729 }; 1730 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1731 struct nmk_gpio_chip *nmk_chip; 1732 unsigned bit; 1733 pin_cfg_t cfg; 1734 int pull, slpm, output, val, i; 1735 bool lowemi, gpiomode, sleep; 1736 1737 nmk_chip = find_nmk_gpio_from_pin(pin); 1738 if (!nmk_chip) { 1739 dev_err(npct->dev, 1740 "invalid pin offset %d\n", pin); 1741 return -EINVAL; 1742 } 1743 1744 for (i = 0; i < num_configs; i++) { 1745 /* 1746 * The pin config contains pin number and altfunction fields, 1747 * here we just ignore that part. It's being handled by the 1748 * framework and pinmux callback respectively. 1749 */ 1750 cfg = (pin_cfg_t) configs[i]; 1751 pull = PIN_PULL(cfg); 1752 slpm = PIN_SLPM(cfg); 1753 output = PIN_DIR(cfg); 1754 val = PIN_VAL(cfg); 1755 lowemi = PIN_LOWEMI(cfg); 1756 gpiomode = PIN_GPIOMODE(cfg); 1757 sleep = PIN_SLEEPMODE(cfg); 1758 1759 if (sleep) { 1760 int slpm_pull = PIN_SLPM_PULL(cfg); 1761 int slpm_output = PIN_SLPM_DIR(cfg); 1762 int slpm_val = PIN_SLPM_VAL(cfg); 1763 1764 /* All pins go into GPIO mode at sleep */ 1765 gpiomode = true; 1766 1767 /* 1768 * The SLPM_* values are normal values + 1 to allow zero 1769 * to mean "same as normal". 1770 */ 1771 if (slpm_pull) 1772 pull = slpm_pull - 1; 1773 if (slpm_output) 1774 output = slpm_output - 1; 1775 if (slpm_val) 1776 val = slpm_val - 1; 1777 1778 dev_dbg(nmk_chip->chip.parent, 1779 "pin %d: sleep pull %s, dir %s, val %s\n", 1780 pin, 1781 slpm_pull ? pullnames[pull] : "same", 1782 slpm_output ? (output ? "output" : "input") 1783 : "same", 1784 slpm_val ? (val ? "high" : "low") : "same"); 1785 } 1786 1787 dev_dbg(nmk_chip->chip.parent, 1788 "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n", 1789 pin, cfg, pullnames[pull], slpmnames[slpm], 1790 output ? "output " : "input", 1791 output ? (val ? "high" : "low") : "", 1792 lowemi ? "on" : "off"); 1793 1794 clk_enable(nmk_chip->clk); 1795 bit = pin % NMK_GPIO_PER_CHIP; 1796 if (gpiomode) 1797 /* No glitch when going to GPIO mode */ 1798 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); 1799 if (output) 1800 __nmk_gpio_make_output(nmk_chip, bit, val); 1801 else { 1802 __nmk_gpio_make_input(nmk_chip, bit); 1803 __nmk_gpio_set_pull(nmk_chip, bit, pull); 1804 } 1805 /* TODO: isn't this only applicable on output pins? */ 1806 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi); 1807 1808 __nmk_gpio_set_slpm(nmk_chip, bit, slpm); 1809 clk_disable(nmk_chip->clk); 1810 } /* for each config */ 1811 1812 return 0; 1813 } 1814 1815 static const struct pinconf_ops nmk_pinconf_ops = { 1816 .pin_config_get = nmk_pin_config_get, 1817 .pin_config_set = nmk_pin_config_set, 1818 }; 1819 1820 static struct pinctrl_desc nmk_pinctrl_desc = { 1821 .name = "pinctrl-nomadik", 1822 .pctlops = &nmk_pinctrl_ops, 1823 .pmxops = &nmk_pinmux_ops, 1824 .confops = &nmk_pinconf_ops, 1825 .owner = THIS_MODULE, 1826 }; 1827 1828 static const struct of_device_id nmk_pinctrl_match[] = { 1829 { 1830 .compatible = "stericsson,stn8815-pinctrl", 1831 .data = (void *)PINCTRL_NMK_STN8815, 1832 }, 1833 { 1834 .compatible = "stericsson,db8500-pinctrl", 1835 .data = (void *)PINCTRL_NMK_DB8500, 1836 }, 1837 { 1838 .compatible = "stericsson,db8540-pinctrl", 1839 .data = (void *)PINCTRL_NMK_DB8540, 1840 }, 1841 {}, 1842 }; 1843 1844 #ifdef CONFIG_PM_SLEEP 1845 static int nmk_pinctrl_suspend(struct device *dev) 1846 { 1847 struct nmk_pinctrl *npct; 1848 1849 npct = dev_get_drvdata(dev); 1850 if (!npct) 1851 return -EINVAL; 1852 1853 return pinctrl_force_sleep(npct->pctl); 1854 } 1855 1856 static int nmk_pinctrl_resume(struct device *dev) 1857 { 1858 struct nmk_pinctrl *npct; 1859 1860 npct = dev_get_drvdata(dev); 1861 if (!npct) 1862 return -EINVAL; 1863 1864 return pinctrl_force_default(npct->pctl); 1865 } 1866 #endif 1867 1868 static int nmk_pinctrl_probe(struct platform_device *pdev) 1869 { 1870 const struct of_device_id *match; 1871 struct device_node *np = pdev->dev.of_node; 1872 struct device_node *prcm_np; 1873 struct nmk_pinctrl *npct; 1874 unsigned int version = 0; 1875 int i; 1876 1877 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL); 1878 if (!npct) 1879 return -ENOMEM; 1880 1881 match = of_match_device(nmk_pinctrl_match, &pdev->dev); 1882 if (!match) 1883 return -ENODEV; 1884 version = (unsigned int) match->data; 1885 1886 /* Poke in other ASIC variants here */ 1887 if (version == PINCTRL_NMK_STN8815) 1888 nmk_pinctrl_stn8815_init(&npct->soc); 1889 if (version == PINCTRL_NMK_DB8500) 1890 nmk_pinctrl_db8500_init(&npct->soc); 1891 if (version == PINCTRL_NMK_DB8540) 1892 nmk_pinctrl_db8540_init(&npct->soc); 1893 1894 /* 1895 * Since we depend on the GPIO chips to provide clock and register base 1896 * for the pin control operations, make sure that we have these 1897 * populated before we continue. Follow the phandles to instantiate 1898 * them. The GPIO portion of the actual hardware may be probed before 1899 * or after this point: it shouldn't matter as the APIs are orthogonal. 1900 */ 1901 for (i = 0; i < NMK_MAX_BANKS; i++) { 1902 struct device_node *gpio_np; 1903 struct nmk_gpio_chip *nmk_chip; 1904 1905 gpio_np = of_parse_phandle(np, "nomadik-gpio-chips", i); 1906 if (gpio_np) { 1907 dev_info(&pdev->dev, 1908 "populate NMK GPIO %d \"%s\"\n", 1909 i, gpio_np->name); 1910 nmk_chip = nmk_gpio_populate_chip(gpio_np, pdev); 1911 if (IS_ERR(nmk_chip)) 1912 dev_err(&pdev->dev, 1913 "could not populate nmk chip struct " 1914 "- continue anyway\n"); 1915 of_node_put(gpio_np); 1916 } 1917 } 1918 1919 prcm_np = of_parse_phandle(np, "prcm", 0); 1920 if (prcm_np) 1921 npct->prcm_base = of_iomap(prcm_np, 0); 1922 if (!npct->prcm_base) { 1923 if (version == PINCTRL_NMK_STN8815) { 1924 dev_info(&pdev->dev, 1925 "No PRCM base, " 1926 "assuming no ALT-Cx control is available\n"); 1927 } else { 1928 dev_err(&pdev->dev, "missing PRCM base address\n"); 1929 return -EINVAL; 1930 } 1931 } 1932 1933 nmk_pinctrl_desc.pins = npct->soc->pins; 1934 nmk_pinctrl_desc.npins = npct->soc->npins; 1935 npct->dev = &pdev->dev; 1936 1937 npct->pctl = devm_pinctrl_register(&pdev->dev, &nmk_pinctrl_desc, npct); 1938 if (IS_ERR(npct->pctl)) { 1939 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n"); 1940 return PTR_ERR(npct->pctl); 1941 } 1942 1943 platform_set_drvdata(pdev, npct); 1944 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n"); 1945 1946 return 0; 1947 } 1948 1949 static const struct of_device_id nmk_gpio_match[] = { 1950 { .compatible = "st,nomadik-gpio", }, 1951 {} 1952 }; 1953 1954 static struct platform_driver nmk_gpio_driver = { 1955 .driver = { 1956 .name = "gpio", 1957 .of_match_table = nmk_gpio_match, 1958 }, 1959 .probe = nmk_gpio_probe, 1960 }; 1961 1962 static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops, 1963 nmk_pinctrl_suspend, 1964 nmk_pinctrl_resume); 1965 1966 static struct platform_driver nmk_pinctrl_driver = { 1967 .driver = { 1968 .name = "pinctrl-nomadik", 1969 .of_match_table = nmk_pinctrl_match, 1970 .pm = &nmk_pinctrl_pm_ops, 1971 }, 1972 .probe = nmk_pinctrl_probe, 1973 }; 1974 1975 static int __init nmk_gpio_init(void) 1976 { 1977 return platform_driver_register(&nmk_gpio_driver); 1978 } 1979 subsys_initcall(nmk_gpio_init); 1980 1981 static int __init nmk_pinctrl_init(void) 1982 { 1983 return platform_driver_register(&nmk_pinctrl_driver); 1984 } 1985 core_initcall(nmk_pinctrl_init); 1986 1987 MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini"); 1988 MODULE_DESCRIPTION("Nomadik GPIO Driver"); 1989 MODULE_LICENSE("GPL"); 1990