13a198059SLinus Walleij /* 23a198059SLinus Walleij * Generic GPIO driver for logic cells found in the Nomadik SoC 33a198059SLinus Walleij * 43a198059SLinus Walleij * Copyright (C) 2008,2009 STMicroelectronics 53a198059SLinus Walleij * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> 63a198059SLinus Walleij * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> 73a198059SLinus Walleij * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org> 83a198059SLinus Walleij * 93a198059SLinus Walleij * This program is free software; you can redistribute it and/or modify 103a198059SLinus Walleij * it under the terms of the GNU General Public License version 2 as 113a198059SLinus Walleij * published by the Free Software Foundation. 123a198059SLinus Walleij */ 133a198059SLinus Walleij #include <linux/kernel.h> 143a198059SLinus Walleij #include <linux/init.h> 153a198059SLinus Walleij #include <linux/device.h> 163a198059SLinus Walleij #include <linux/platform_device.h> 173a198059SLinus Walleij #include <linux/io.h> 183a198059SLinus Walleij #include <linux/clk.h> 193a198059SLinus Walleij #include <linux/err.h> 203a198059SLinus Walleij #include <linux/gpio.h> 213a198059SLinus Walleij #include <linux/spinlock.h> 223a198059SLinus Walleij #include <linux/interrupt.h> 233a198059SLinus Walleij #include <linux/slab.h> 243a198059SLinus Walleij #include <linux/of_device.h> 253a198059SLinus Walleij #include <linux/of_address.h> 265e81e0a0SLinus Walleij #include <linux/bitops.h> 273a198059SLinus Walleij #include <linux/pinctrl/machine.h> 283a198059SLinus Walleij #include <linux/pinctrl/pinctrl.h> 293a198059SLinus Walleij #include <linux/pinctrl/pinmux.h> 303a198059SLinus Walleij #include <linux/pinctrl/pinconf.h> 313a198059SLinus Walleij /* Since we request GPIOs from ourself */ 323a198059SLinus Walleij #include <linux/pinctrl/consumer.h> 333a198059SLinus Walleij #include "pinctrl-nomadik.h" 343a198059SLinus Walleij #include "../core.h" 35ba388294SLinus Walleij #include "../pinctrl-utils.h" 363a198059SLinus Walleij 373a198059SLinus Walleij /* 383a198059SLinus Walleij * The GPIO module in the Nomadik family of Systems-on-Chip is an 393a198059SLinus Walleij * AMBA device, managing 32 pins and alternate functions. The logic block 403a198059SLinus Walleij * is currently used in the Nomadik and ux500. 413a198059SLinus Walleij * 423a198059SLinus Walleij * Symbols in this file are called "nmk_gpio" for "nomadik gpio" 433a198059SLinus Walleij */ 443a198059SLinus Walleij 453a198059SLinus Walleij /* 463a198059SLinus Walleij * pin configurations are represented by 32-bit integers: 473a198059SLinus Walleij * 483a198059SLinus Walleij * bit 0.. 8 - Pin Number (512 Pins Maximum) 493a198059SLinus Walleij * bit 9..10 - Alternate Function Selection 503a198059SLinus Walleij * bit 11..12 - Pull up/down state 513a198059SLinus Walleij * bit 13 - Sleep mode behaviour 523a198059SLinus Walleij * bit 14 - Direction 533a198059SLinus Walleij * bit 15 - Value (if output) 543a198059SLinus Walleij * bit 16..18 - SLPM pull up/down state 553a198059SLinus Walleij * bit 19..20 - SLPM direction 563a198059SLinus Walleij * bit 21..22 - SLPM Value (if output) 573a198059SLinus Walleij * bit 23..25 - PDIS value (if input) 583a198059SLinus Walleij * bit 26 - Gpio mode 593a198059SLinus Walleij * bit 27 - Sleep mode 603a198059SLinus Walleij * 613a198059SLinus Walleij * to facilitate the definition, the following macros are provided 623a198059SLinus Walleij * 633a198059SLinus Walleij * PIN_CFG_DEFAULT - default config (0): 643a198059SLinus Walleij * pull up/down = disabled 653a198059SLinus Walleij * sleep mode = input/wakeup 663a198059SLinus Walleij * direction = input 673a198059SLinus Walleij * value = low 683a198059SLinus Walleij * SLPM direction = same as normal 693a198059SLinus Walleij * SLPM pull = same as normal 703a198059SLinus Walleij * SLPM value = same as normal 713a198059SLinus Walleij * 723a198059SLinus Walleij * PIN_CFG - default config with alternate function 733a198059SLinus Walleij */ 743a198059SLinus Walleij 753a198059SLinus Walleij typedef unsigned long pin_cfg_t; 763a198059SLinus Walleij 773a198059SLinus Walleij #define PIN_NUM_MASK 0x1ff 783a198059SLinus Walleij #define PIN_NUM(x) ((x) & PIN_NUM_MASK) 793a198059SLinus Walleij 803a198059SLinus Walleij #define PIN_ALT_SHIFT 9 813a198059SLinus Walleij #define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT) 823a198059SLinus Walleij #define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT) 833a198059SLinus Walleij #define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT) 843a198059SLinus Walleij #define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT) 853a198059SLinus Walleij #define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT) 863a198059SLinus Walleij #define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT) 873a198059SLinus Walleij 883a198059SLinus Walleij #define PIN_PULL_SHIFT 11 893a198059SLinus Walleij #define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT) 903a198059SLinus Walleij #define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT) 913a198059SLinus Walleij #define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT) 923a198059SLinus Walleij #define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT) 933a198059SLinus Walleij #define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT) 943a198059SLinus Walleij 953a198059SLinus Walleij #define PIN_SLPM_SHIFT 13 963a198059SLinus Walleij #define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT) 973a198059SLinus Walleij #define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT) 983a198059SLinus Walleij #define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT) 993a198059SLinus Walleij #define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT) 1003a198059SLinus Walleij /* These two replace the above in DB8500v2+ */ 1013a198059SLinus Walleij #define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT) 1023a198059SLinus Walleij #define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT) 1033a198059SLinus Walleij #define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE 1043a198059SLinus Walleij 1053a198059SLinus Walleij #define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */ 1063a198059SLinus Walleij #define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */ 1073a198059SLinus Walleij 1083a198059SLinus Walleij #define PIN_DIR_SHIFT 14 1093a198059SLinus Walleij #define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT) 1103a198059SLinus Walleij #define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT) 1113a198059SLinus Walleij #define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT) 1123a198059SLinus Walleij #define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT) 1133a198059SLinus Walleij 1143a198059SLinus Walleij #define PIN_VAL_SHIFT 15 1153a198059SLinus Walleij #define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT) 1163a198059SLinus Walleij #define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT) 1173a198059SLinus Walleij #define PIN_VAL_LOW (0 << PIN_VAL_SHIFT) 1183a198059SLinus Walleij #define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT) 1193a198059SLinus Walleij 1203a198059SLinus Walleij #define PIN_SLPM_PULL_SHIFT 16 1213a198059SLinus Walleij #define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT) 1223a198059SLinus Walleij #define PIN_SLPM_PULL(x) \ 1233a198059SLinus Walleij (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT) 1243a198059SLinus Walleij #define PIN_SLPM_PULL_NONE \ 1253a198059SLinus Walleij ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT) 1263a198059SLinus Walleij #define PIN_SLPM_PULL_UP \ 1273a198059SLinus Walleij ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT) 1283a198059SLinus Walleij #define PIN_SLPM_PULL_DOWN \ 1293a198059SLinus Walleij ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT) 1303a198059SLinus Walleij 1313a198059SLinus Walleij #define PIN_SLPM_DIR_SHIFT 19 1323a198059SLinus Walleij #define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT) 1333a198059SLinus Walleij #define PIN_SLPM_DIR(x) \ 1343a198059SLinus Walleij (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT) 1353a198059SLinus Walleij #define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT) 1363a198059SLinus Walleij #define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT) 1373a198059SLinus Walleij 1383a198059SLinus Walleij #define PIN_SLPM_VAL_SHIFT 21 1393a198059SLinus Walleij #define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT) 1403a198059SLinus Walleij #define PIN_SLPM_VAL(x) \ 1413a198059SLinus Walleij (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT) 1423a198059SLinus Walleij #define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT) 1433a198059SLinus Walleij #define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT) 1443a198059SLinus Walleij 1453a198059SLinus Walleij #define PIN_SLPM_PDIS_SHIFT 23 1463a198059SLinus Walleij #define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT) 1473a198059SLinus Walleij #define PIN_SLPM_PDIS(x) \ 1483a198059SLinus Walleij (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT) 1493a198059SLinus Walleij #define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT) 1503a198059SLinus Walleij #define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT) 1513a198059SLinus Walleij #define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT) 1523a198059SLinus Walleij 1533a198059SLinus Walleij #define PIN_LOWEMI_SHIFT 25 1543a198059SLinus Walleij #define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT) 1553a198059SLinus Walleij #define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT) 1563a198059SLinus Walleij #define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT) 1573a198059SLinus Walleij #define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT) 1583a198059SLinus Walleij 1593a198059SLinus Walleij #define PIN_GPIOMODE_SHIFT 26 1603a198059SLinus Walleij #define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT) 1613a198059SLinus Walleij #define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT) 1623a198059SLinus Walleij #define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT) 1633a198059SLinus Walleij #define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT) 1643a198059SLinus Walleij 1653a198059SLinus Walleij #define PIN_SLEEPMODE_SHIFT 27 1663a198059SLinus Walleij #define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT) 1673a198059SLinus Walleij #define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT) 1683a198059SLinus Walleij #define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT) 1693a198059SLinus Walleij #define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT) 1703a198059SLinus Walleij 1713a198059SLinus Walleij 1723a198059SLinus Walleij /* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */ 1733a198059SLinus Walleij #define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN) 1743a198059SLinus Walleij #define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP) 1753a198059SLinus Walleij #define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE) 1763a198059SLinus Walleij #define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW) 1773a198059SLinus Walleij #define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH) 1783a198059SLinus Walleij 1793a198059SLinus Walleij #define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN) 1803a198059SLinus Walleij #define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP) 1813a198059SLinus Walleij #define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE) 1823a198059SLinus Walleij #define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW) 1833a198059SLinus Walleij #define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH) 1843a198059SLinus Walleij 1853a198059SLinus Walleij #define PIN_CFG_DEFAULT (0) 1863a198059SLinus Walleij 1873a198059SLinus Walleij #define PIN_CFG(num, alt) \ 1883a198059SLinus Walleij (PIN_CFG_DEFAULT |\ 1893a198059SLinus Walleij (PIN_NUM(num) | PIN_##alt)) 1903a198059SLinus Walleij 1913a198059SLinus Walleij #define PIN_CFG_INPUT(num, alt, pull) \ 1923a198059SLinus Walleij (PIN_CFG_DEFAULT |\ 1933a198059SLinus Walleij (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull)) 1943a198059SLinus Walleij 1953a198059SLinus Walleij #define PIN_CFG_OUTPUT(num, alt, val) \ 1963a198059SLinus Walleij (PIN_CFG_DEFAULT |\ 1973a198059SLinus Walleij (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val)) 1983a198059SLinus Walleij 1993a198059SLinus Walleij /* 2003a198059SLinus Walleij * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving 2013a198059SLinus Walleij * the "gpio" namespace for generic and cross-machine functions 2023a198059SLinus Walleij */ 2033a198059SLinus Walleij 2043a198059SLinus Walleij #define GPIO_BLOCK_SHIFT 5 2053a198059SLinus Walleij #define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT) 206bc222ef4SLinus Walleij #define NMK_MAX_BANKS DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP) 2073a198059SLinus Walleij 2083a198059SLinus Walleij /* Register in the logic block */ 2093a198059SLinus Walleij #define NMK_GPIO_DAT 0x00 2103a198059SLinus Walleij #define NMK_GPIO_DATS 0x04 2113a198059SLinus Walleij #define NMK_GPIO_DATC 0x08 2123a198059SLinus Walleij #define NMK_GPIO_PDIS 0x0c 2133a198059SLinus Walleij #define NMK_GPIO_DIR 0x10 2143a198059SLinus Walleij #define NMK_GPIO_DIRS 0x14 2153a198059SLinus Walleij #define NMK_GPIO_DIRC 0x18 2163a198059SLinus Walleij #define NMK_GPIO_SLPC 0x1c 2173a198059SLinus Walleij #define NMK_GPIO_AFSLA 0x20 2183a198059SLinus Walleij #define NMK_GPIO_AFSLB 0x24 2193a198059SLinus Walleij #define NMK_GPIO_LOWEMI 0x28 2203a198059SLinus Walleij 2213a198059SLinus Walleij #define NMK_GPIO_RIMSC 0x40 2223a198059SLinus Walleij #define NMK_GPIO_FIMSC 0x44 2233a198059SLinus Walleij #define NMK_GPIO_IS 0x48 2243a198059SLinus Walleij #define NMK_GPIO_IC 0x4c 2253a198059SLinus Walleij #define NMK_GPIO_RWIMSC 0x50 2263a198059SLinus Walleij #define NMK_GPIO_FWIMSC 0x54 2273a198059SLinus Walleij #define NMK_GPIO_WKS 0x58 2283a198059SLinus Walleij /* These appear in DB8540 and later ASICs */ 2293a198059SLinus Walleij #define NMK_GPIO_EDGELEVEL 0x5C 2303a198059SLinus Walleij #define NMK_GPIO_LEVEL 0x60 2313a198059SLinus Walleij 2323a198059SLinus Walleij 2333a198059SLinus Walleij /* Pull up/down values */ 2343a198059SLinus Walleij enum nmk_gpio_pull { 2353a198059SLinus Walleij NMK_GPIO_PULL_NONE, 2363a198059SLinus Walleij NMK_GPIO_PULL_UP, 2373a198059SLinus Walleij NMK_GPIO_PULL_DOWN, 2383a198059SLinus Walleij }; 2393a198059SLinus Walleij 2403a198059SLinus Walleij /* Sleep mode */ 2413a198059SLinus Walleij enum nmk_gpio_slpm { 2423a198059SLinus Walleij NMK_GPIO_SLPM_INPUT, 2433a198059SLinus Walleij NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT, 2443a198059SLinus Walleij NMK_GPIO_SLPM_NOCHANGE, 2453a198059SLinus Walleij NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE, 2463a198059SLinus Walleij }; 2473a198059SLinus Walleij 2483a198059SLinus Walleij struct nmk_gpio_chip { 2493a198059SLinus Walleij struct gpio_chip chip; 2503007d941SLinus Walleij struct irq_chip irqchip; 2513a198059SLinus Walleij void __iomem *addr; 2523a198059SLinus Walleij struct clk *clk; 2533a198059SLinus Walleij unsigned int bank; 2543a198059SLinus Walleij unsigned int parent_irq; 2553a198059SLinus Walleij int latent_parent_irq; 2563a198059SLinus Walleij u32 (*get_latent_status)(unsigned int bank); 2573a198059SLinus Walleij void (*set_ioforce)(bool enable); 2583a198059SLinus Walleij spinlock_t lock; 2593a198059SLinus Walleij bool sleepmode; 2603a198059SLinus Walleij /* Keep track of configured edges */ 2613a198059SLinus Walleij u32 edge_rising; 2623a198059SLinus Walleij u32 edge_falling; 2633a198059SLinus Walleij u32 real_wake; 2643a198059SLinus Walleij u32 rwimsc; 2653a198059SLinus Walleij u32 fwimsc; 2663a198059SLinus Walleij u32 rimsc; 2673a198059SLinus Walleij u32 fimsc; 2683a198059SLinus Walleij u32 pull_up; 2693a198059SLinus Walleij u32 lowemi; 2703a198059SLinus Walleij }; 2713a198059SLinus Walleij 2723a198059SLinus Walleij /** 2733a198059SLinus Walleij * struct nmk_pinctrl - state container for the Nomadik pin controller 2743a198059SLinus Walleij * @dev: containing device pointer 2753a198059SLinus Walleij * @pctl: corresponding pin controller device 2763a198059SLinus Walleij * @soc: SoC data for this specific chip 2773a198059SLinus Walleij * @prcm_base: PRCM register range virtual base 2783a198059SLinus Walleij */ 2793a198059SLinus Walleij struct nmk_pinctrl { 2803a198059SLinus Walleij struct device *dev; 2813a198059SLinus Walleij struct pinctrl_dev *pctl; 2823a198059SLinus Walleij const struct nmk_pinctrl_soc_data *soc; 2833a198059SLinus Walleij void __iomem *prcm_base; 2843a198059SLinus Walleij }; 2853a198059SLinus Walleij 286bc222ef4SLinus Walleij static struct nmk_gpio_chip *nmk_gpio_chips[NMK_MAX_BANKS]; 2873a198059SLinus Walleij 2883a198059SLinus Walleij static DEFINE_SPINLOCK(nmk_gpio_slpm_lock); 2893a198059SLinus Walleij 2903a198059SLinus Walleij #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips) 2913a198059SLinus Walleij 2923a198059SLinus Walleij static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, 2933a198059SLinus Walleij unsigned offset, int gpio_mode) 2943a198059SLinus Walleij { 2953a198059SLinus Walleij u32 afunc, bfunc; 2963a198059SLinus Walleij 2975e81e0a0SLinus Walleij afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~BIT(offset); 2985e81e0a0SLinus Walleij bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~BIT(offset); 2993a198059SLinus Walleij if (gpio_mode & NMK_GPIO_ALT_A) 3005e81e0a0SLinus Walleij afunc |= BIT(offset); 3013a198059SLinus Walleij if (gpio_mode & NMK_GPIO_ALT_B) 3025e81e0a0SLinus Walleij bfunc |= BIT(offset); 3033a198059SLinus Walleij writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); 3043a198059SLinus Walleij writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); 3053a198059SLinus Walleij } 3063a198059SLinus Walleij 3073a198059SLinus Walleij static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, 3083a198059SLinus Walleij unsigned offset, enum nmk_gpio_slpm mode) 3093a198059SLinus Walleij { 3103a198059SLinus Walleij u32 slpm; 3113a198059SLinus Walleij 3123a198059SLinus Walleij slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); 3133a198059SLinus Walleij if (mode == NMK_GPIO_SLPM_NOCHANGE) 3145e81e0a0SLinus Walleij slpm |= BIT(offset); 3153a198059SLinus Walleij else 3165e81e0a0SLinus Walleij slpm &= ~BIT(offset); 3173a198059SLinus Walleij writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); 3183a198059SLinus Walleij } 3193a198059SLinus Walleij 3203a198059SLinus Walleij static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, 3213a198059SLinus Walleij unsigned offset, enum nmk_gpio_pull pull) 3223a198059SLinus Walleij { 3233a198059SLinus Walleij u32 pdis; 3243a198059SLinus Walleij 3253a198059SLinus Walleij pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); 3263a198059SLinus Walleij if (pull == NMK_GPIO_PULL_NONE) { 3275e81e0a0SLinus Walleij pdis |= BIT(offset); 3285e81e0a0SLinus Walleij nmk_chip->pull_up &= ~BIT(offset); 3293a198059SLinus Walleij } else { 3305e81e0a0SLinus Walleij pdis &= ~BIT(offset); 3313a198059SLinus Walleij } 3323a198059SLinus Walleij 3333a198059SLinus Walleij writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); 3343a198059SLinus Walleij 3353a198059SLinus Walleij if (pull == NMK_GPIO_PULL_UP) { 3365e81e0a0SLinus Walleij nmk_chip->pull_up |= BIT(offset); 3375e81e0a0SLinus Walleij writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS); 3383a198059SLinus Walleij } else if (pull == NMK_GPIO_PULL_DOWN) { 3395e81e0a0SLinus Walleij nmk_chip->pull_up &= ~BIT(offset); 3405e81e0a0SLinus Walleij writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC); 3413a198059SLinus Walleij } 3423a198059SLinus Walleij } 3433a198059SLinus Walleij 3443a198059SLinus Walleij static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip, 3453a198059SLinus Walleij unsigned offset, bool lowemi) 3463a198059SLinus Walleij { 3475e81e0a0SLinus Walleij bool enabled = nmk_chip->lowemi & BIT(offset); 3483a198059SLinus Walleij 3493a198059SLinus Walleij if (lowemi == enabled) 3503a198059SLinus Walleij return; 3513a198059SLinus Walleij 3523a198059SLinus Walleij if (lowemi) 3535e81e0a0SLinus Walleij nmk_chip->lowemi |= BIT(offset); 3543a198059SLinus Walleij else 3555e81e0a0SLinus Walleij nmk_chip->lowemi &= ~BIT(offset); 3563a198059SLinus Walleij 3573a198059SLinus Walleij writel_relaxed(nmk_chip->lowemi, 3583a198059SLinus Walleij nmk_chip->addr + NMK_GPIO_LOWEMI); 3593a198059SLinus Walleij } 3603a198059SLinus Walleij 3613a198059SLinus Walleij static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, 3623a198059SLinus Walleij unsigned offset) 3633a198059SLinus Walleij { 3645e81e0a0SLinus Walleij writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC); 3653a198059SLinus Walleij } 3663a198059SLinus Walleij 3673a198059SLinus Walleij static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, 3683a198059SLinus Walleij unsigned offset, int val) 3693a198059SLinus Walleij { 3703a198059SLinus Walleij if (val) 3715e81e0a0SLinus Walleij writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS); 3723a198059SLinus Walleij else 3735e81e0a0SLinus Walleij writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC); 3743a198059SLinus Walleij } 3753a198059SLinus Walleij 3763a198059SLinus Walleij static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, 3773a198059SLinus Walleij unsigned offset, int val) 3783a198059SLinus Walleij { 3795e81e0a0SLinus Walleij writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRS); 3803a198059SLinus Walleij __nmk_gpio_set_output(nmk_chip, offset, val); 3813a198059SLinus Walleij } 3823a198059SLinus Walleij 3833a198059SLinus Walleij static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, 3843a198059SLinus Walleij unsigned offset, int gpio_mode, 3853a198059SLinus Walleij bool glitch) 3863a198059SLinus Walleij { 3873a198059SLinus Walleij u32 rwimsc = nmk_chip->rwimsc; 3883a198059SLinus Walleij u32 fwimsc = nmk_chip->fwimsc; 3893a198059SLinus Walleij 3903a198059SLinus Walleij if (glitch && nmk_chip->set_ioforce) { 3913a198059SLinus Walleij u32 bit = BIT(offset); 3923a198059SLinus Walleij 3933a198059SLinus Walleij /* Prevent spurious wakeups */ 3943a198059SLinus Walleij writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC); 3953a198059SLinus Walleij writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC); 3963a198059SLinus Walleij 3973a198059SLinus Walleij nmk_chip->set_ioforce(true); 3983a198059SLinus Walleij } 3993a198059SLinus Walleij 4003a198059SLinus Walleij __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode); 4013a198059SLinus Walleij 4023a198059SLinus Walleij if (glitch && nmk_chip->set_ioforce) { 4033a198059SLinus Walleij nmk_chip->set_ioforce(false); 4043a198059SLinus Walleij 4053a198059SLinus Walleij writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC); 4063a198059SLinus Walleij writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC); 4073a198059SLinus Walleij } 4083a198059SLinus Walleij } 4093a198059SLinus Walleij 4103a198059SLinus Walleij static void 4113a198059SLinus Walleij nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset) 4123a198059SLinus Walleij { 4133a198059SLinus Walleij u32 falling = nmk_chip->fimsc & BIT(offset); 4143a198059SLinus Walleij u32 rising = nmk_chip->rimsc & BIT(offset); 4153a198059SLinus Walleij int gpio = nmk_chip->chip.base + offset; 416f0fbe7bcSThierry Reding int irq = irq_find_mapping(nmk_chip->chip.irq.domain, offset); 4173a198059SLinus Walleij struct irq_data *d = irq_get_irq_data(irq); 4183a198059SLinus Walleij 4193a198059SLinus Walleij if (!rising && !falling) 4203a198059SLinus Walleij return; 4213a198059SLinus Walleij 4223a198059SLinus Walleij if (!d || !irqd_irq_disabled(d)) 4233a198059SLinus Walleij return; 4243a198059SLinus Walleij 4253a198059SLinus Walleij if (rising) { 4263a198059SLinus Walleij nmk_chip->rimsc &= ~BIT(offset); 4273a198059SLinus Walleij writel_relaxed(nmk_chip->rimsc, 4283a198059SLinus Walleij nmk_chip->addr + NMK_GPIO_RIMSC); 4293a198059SLinus Walleij } 4303a198059SLinus Walleij 4313a198059SLinus Walleij if (falling) { 4323a198059SLinus Walleij nmk_chip->fimsc &= ~BIT(offset); 4333a198059SLinus Walleij writel_relaxed(nmk_chip->fimsc, 4343a198059SLinus Walleij nmk_chip->addr + NMK_GPIO_FIMSC); 4353a198059SLinus Walleij } 4363a198059SLinus Walleij 43758383c78SLinus Walleij dev_dbg(nmk_chip->chip.parent, "%d: clearing interrupt mask\n", gpio); 4383a198059SLinus Walleij } 4393a198059SLinus Walleij 4403a198059SLinus Walleij static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value) 4413a198059SLinus Walleij { 4423a198059SLinus Walleij u32 val; 4433a198059SLinus Walleij 4443a198059SLinus Walleij val = readl(reg); 4453a198059SLinus Walleij val = ((val & ~mask) | (value & mask)); 4463a198059SLinus Walleij writel(val, reg); 4473a198059SLinus Walleij } 4483a198059SLinus Walleij 4493a198059SLinus Walleij static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct, 4503a198059SLinus Walleij unsigned offset, unsigned alt_num) 4513a198059SLinus Walleij { 4523a198059SLinus Walleij int i; 4533a198059SLinus Walleij u16 reg; 4543a198059SLinus Walleij u8 bit; 4553a198059SLinus Walleij u8 alt_index; 4563a198059SLinus Walleij const struct prcm_gpiocr_altcx_pin_desc *pin_desc; 4573a198059SLinus Walleij const u16 *gpiocr_regs; 4583a198059SLinus Walleij 4593a198059SLinus Walleij if (!npct->prcm_base) 4603a198059SLinus Walleij return; 4613a198059SLinus Walleij 4623a198059SLinus Walleij if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) { 4633a198059SLinus Walleij dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n", 4643a198059SLinus Walleij alt_num); 4653a198059SLinus Walleij return; 4663a198059SLinus Walleij } 4673a198059SLinus Walleij 4683a198059SLinus Walleij for (i = 0 ; i < npct->soc->npins_altcx ; i++) { 4693a198059SLinus Walleij if (npct->soc->altcx_pins[i].pin == offset) 4703a198059SLinus Walleij break; 4713a198059SLinus Walleij } 4723a198059SLinus Walleij if (i == npct->soc->npins_altcx) { 4733a198059SLinus Walleij dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n", 4743a198059SLinus Walleij offset); 4753a198059SLinus Walleij return; 4763a198059SLinus Walleij } 4773a198059SLinus Walleij 4783a198059SLinus Walleij pin_desc = npct->soc->altcx_pins + i; 4793a198059SLinus Walleij gpiocr_regs = npct->soc->prcm_gpiocr_registers; 4803a198059SLinus Walleij 4813a198059SLinus Walleij /* 4823a198059SLinus Walleij * If alt_num is NULL, just clear current ALTCx selection 4833a198059SLinus Walleij * to make sure we come back to a pure ALTC selection 4843a198059SLinus Walleij */ 4853a198059SLinus Walleij if (!alt_num) { 4863a198059SLinus Walleij for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { 4873a198059SLinus Walleij if (pin_desc->altcx[i].used == true) { 4883a198059SLinus Walleij reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; 4893a198059SLinus Walleij bit = pin_desc->altcx[i].control_bit; 4903a198059SLinus Walleij if (readl(npct->prcm_base + reg) & BIT(bit)) { 4913a198059SLinus Walleij nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); 4923a198059SLinus Walleij dev_dbg(npct->dev, 4933a198059SLinus Walleij "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", 4943a198059SLinus Walleij offset, i+1); 4953a198059SLinus Walleij } 4963a198059SLinus Walleij } 4973a198059SLinus Walleij } 4983a198059SLinus Walleij return; 4993a198059SLinus Walleij } 5003a198059SLinus Walleij 5013a198059SLinus Walleij alt_index = alt_num - 1; 5023a198059SLinus Walleij if (pin_desc->altcx[alt_index].used == false) { 5033a198059SLinus Walleij dev_warn(npct->dev, 5043a198059SLinus Walleij "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n", 5053a198059SLinus Walleij offset, alt_num); 5063a198059SLinus Walleij return; 5073a198059SLinus Walleij } 5083a198059SLinus Walleij 5093a198059SLinus Walleij /* 5103a198059SLinus Walleij * Check if any other ALTCx functions are activated on this pin 5113a198059SLinus Walleij * and disable it first. 5123a198059SLinus Walleij */ 5133a198059SLinus Walleij for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { 5143a198059SLinus Walleij if (i == alt_index) 5153a198059SLinus Walleij continue; 5163a198059SLinus Walleij if (pin_desc->altcx[i].used == true) { 5173a198059SLinus Walleij reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; 5183a198059SLinus Walleij bit = pin_desc->altcx[i].control_bit; 5193a198059SLinus Walleij if (readl(npct->prcm_base + reg) & BIT(bit)) { 5203a198059SLinus Walleij nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); 5213a198059SLinus Walleij dev_dbg(npct->dev, 5223a198059SLinus Walleij "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", 5233a198059SLinus Walleij offset, i+1); 5243a198059SLinus Walleij } 5253a198059SLinus Walleij } 5263a198059SLinus Walleij } 5273a198059SLinus Walleij 5283a198059SLinus Walleij reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index]; 5293a198059SLinus Walleij bit = pin_desc->altcx[alt_index].control_bit; 5303a198059SLinus Walleij dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n", 5313a198059SLinus Walleij offset, alt_index+1); 5323a198059SLinus Walleij nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit)); 5333a198059SLinus Walleij } 5343a198059SLinus Walleij 5353a198059SLinus Walleij /* 5363a198059SLinus Walleij * Safe sequence used to switch IOs between GPIO and Alternate-C mode: 5373a198059SLinus Walleij * - Save SLPM registers 5383a198059SLinus Walleij * - Set SLPM=0 for the IOs you want to switch and others to 1 5393a198059SLinus Walleij * - Configure the GPIO registers for the IOs that are being switched 5403a198059SLinus Walleij * - Set IOFORCE=1 5413a198059SLinus Walleij * - Modify the AFLSA/B registers for the IOs that are being switched 5423a198059SLinus Walleij * - Set IOFORCE=0 5433a198059SLinus Walleij * - Restore SLPM registers 5443a198059SLinus Walleij * - Any spurious wake up event during switch sequence to be ignored and 5453a198059SLinus Walleij * cleared 5463a198059SLinus Walleij */ 5473a198059SLinus Walleij static void nmk_gpio_glitch_slpm_init(unsigned int *slpm) 5483a198059SLinus Walleij { 5493a198059SLinus Walleij int i; 5503a198059SLinus Walleij 5513a198059SLinus Walleij for (i = 0; i < NUM_BANKS; i++) { 5523a198059SLinus Walleij struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 5533a198059SLinus Walleij unsigned int temp = slpm[i]; 5543a198059SLinus Walleij 5553a198059SLinus Walleij if (!chip) 5563a198059SLinus Walleij break; 5573a198059SLinus Walleij 5583a198059SLinus Walleij clk_enable(chip->clk); 5593a198059SLinus Walleij 5603a198059SLinus Walleij slpm[i] = readl(chip->addr + NMK_GPIO_SLPC); 5613a198059SLinus Walleij writel(temp, chip->addr + NMK_GPIO_SLPC); 5623a198059SLinus Walleij } 5633a198059SLinus Walleij } 5643a198059SLinus Walleij 5653a198059SLinus Walleij static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm) 5663a198059SLinus Walleij { 5673a198059SLinus Walleij int i; 5683a198059SLinus Walleij 5693a198059SLinus Walleij for (i = 0; i < NUM_BANKS; i++) { 5703a198059SLinus Walleij struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 5713a198059SLinus Walleij 5723a198059SLinus Walleij if (!chip) 5733a198059SLinus Walleij break; 5743a198059SLinus Walleij 5753a198059SLinus Walleij writel(slpm[i], chip->addr + NMK_GPIO_SLPC); 5763a198059SLinus Walleij 5773a198059SLinus Walleij clk_disable(chip->clk); 5783a198059SLinus Walleij } 5793a198059SLinus Walleij } 5803a198059SLinus Walleij 5813a198059SLinus Walleij static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio) 5823a198059SLinus Walleij { 5833a198059SLinus Walleij int i; 5843a198059SLinus Walleij u16 reg; 5853a198059SLinus Walleij u8 bit; 5863a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 5873a198059SLinus Walleij const struct prcm_gpiocr_altcx_pin_desc *pin_desc; 5883a198059SLinus Walleij const u16 *gpiocr_regs; 5893a198059SLinus Walleij 5903a198059SLinus Walleij if (!npct->prcm_base) 5913a198059SLinus Walleij return NMK_GPIO_ALT_C; 5923a198059SLinus Walleij 5933a198059SLinus Walleij for (i = 0; i < npct->soc->npins_altcx; i++) { 5943a198059SLinus Walleij if (npct->soc->altcx_pins[i].pin == gpio) 5953a198059SLinus Walleij break; 5963a198059SLinus Walleij } 5973a198059SLinus Walleij if (i == npct->soc->npins_altcx) 5983a198059SLinus Walleij return NMK_GPIO_ALT_C; 5993a198059SLinus Walleij 6003a198059SLinus Walleij pin_desc = npct->soc->altcx_pins + i; 6013a198059SLinus Walleij gpiocr_regs = npct->soc->prcm_gpiocr_registers; 6023a198059SLinus Walleij for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) { 6033a198059SLinus Walleij if (pin_desc->altcx[i].used == true) { 6043a198059SLinus Walleij reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; 6053a198059SLinus Walleij bit = pin_desc->altcx[i].control_bit; 6063a198059SLinus Walleij if (readl(npct->prcm_base + reg) & BIT(bit)) 6073a198059SLinus Walleij return NMK_GPIO_ALT_C+i+1; 6083a198059SLinus Walleij } 6093a198059SLinus Walleij } 6103a198059SLinus Walleij return NMK_GPIO_ALT_C; 6113a198059SLinus Walleij } 6123a198059SLinus Walleij 6133a198059SLinus Walleij /* IRQ functions */ 6143a198059SLinus Walleij 6153a198059SLinus Walleij static void nmk_gpio_irq_ack(struct irq_data *d) 6163a198059SLinus Walleij { 6173a198059SLinus Walleij struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 61868ab0126SLinus Walleij struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 6193a198059SLinus Walleij 6203a198059SLinus Walleij clk_enable(nmk_chip->clk); 6215e81e0a0SLinus Walleij writel(BIT(d->hwirq), nmk_chip->addr + NMK_GPIO_IC); 6223a198059SLinus Walleij clk_disable(nmk_chip->clk); 6233a198059SLinus Walleij } 6243a198059SLinus Walleij 6253a198059SLinus Walleij enum nmk_gpio_irq_type { 6263a198059SLinus Walleij NORMAL, 6273a198059SLinus Walleij WAKE, 6283a198059SLinus Walleij }; 6293a198059SLinus Walleij 6303a198059SLinus Walleij static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, 6315e81e0a0SLinus Walleij int offset, enum nmk_gpio_irq_type which, 6323a198059SLinus Walleij bool enable) 6333a198059SLinus Walleij { 6343a198059SLinus Walleij u32 *rimscval; 6353a198059SLinus Walleij u32 *fimscval; 6363a198059SLinus Walleij u32 rimscreg; 6373a198059SLinus Walleij u32 fimscreg; 6383a198059SLinus Walleij 6393a198059SLinus Walleij if (which == NORMAL) { 6403a198059SLinus Walleij rimscreg = NMK_GPIO_RIMSC; 6413a198059SLinus Walleij fimscreg = NMK_GPIO_FIMSC; 6423a198059SLinus Walleij rimscval = &nmk_chip->rimsc; 6433a198059SLinus Walleij fimscval = &nmk_chip->fimsc; 6443a198059SLinus Walleij } else { 6453a198059SLinus Walleij rimscreg = NMK_GPIO_RWIMSC; 6463a198059SLinus Walleij fimscreg = NMK_GPIO_FWIMSC; 6473a198059SLinus Walleij rimscval = &nmk_chip->rwimsc; 6483a198059SLinus Walleij fimscval = &nmk_chip->fwimsc; 6493a198059SLinus Walleij } 6503a198059SLinus Walleij 6513a198059SLinus Walleij /* we must individually set/clear the two edges */ 6525e81e0a0SLinus Walleij if (nmk_chip->edge_rising & BIT(offset)) { 6533a198059SLinus Walleij if (enable) 6545e81e0a0SLinus Walleij *rimscval |= BIT(offset); 6553a198059SLinus Walleij else 6565e81e0a0SLinus Walleij *rimscval &= ~BIT(offset); 6573a198059SLinus Walleij writel(*rimscval, nmk_chip->addr + rimscreg); 6583a198059SLinus Walleij } 6595e81e0a0SLinus Walleij if (nmk_chip->edge_falling & BIT(offset)) { 6603a198059SLinus Walleij if (enable) 6615e81e0a0SLinus Walleij *fimscval |= BIT(offset); 6623a198059SLinus Walleij else 6635e81e0a0SLinus Walleij *fimscval &= ~BIT(offset); 6643a198059SLinus Walleij writel(*fimscval, nmk_chip->addr + fimscreg); 6653a198059SLinus Walleij } 6663a198059SLinus Walleij } 6673a198059SLinus Walleij 6683a198059SLinus Walleij static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, 6695e81e0a0SLinus Walleij int offset, bool on) 6703a198059SLinus Walleij { 6713a198059SLinus Walleij /* 6723a198059SLinus Walleij * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is 6733a198059SLinus Walleij * disabled, since setting SLPM to 1 increases power consumption, and 6743a198059SLinus Walleij * wakeup is anyhow controlled by the RIMSC and FIMSC registers. 6753a198059SLinus Walleij */ 6763a198059SLinus Walleij if (nmk_chip->sleepmode && on) { 6775e81e0a0SLinus Walleij __nmk_gpio_set_slpm(nmk_chip, offset, 6783a198059SLinus Walleij NMK_GPIO_SLPM_WAKEUP_ENABLE); 6793a198059SLinus Walleij } 6803a198059SLinus Walleij 6815e81e0a0SLinus Walleij __nmk_gpio_irq_modify(nmk_chip, offset, WAKE, on); 6823a198059SLinus Walleij } 6833a198059SLinus Walleij 6843a198059SLinus Walleij static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) 6853a198059SLinus Walleij { 6863a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip; 6873a198059SLinus Walleij unsigned long flags; 6883a198059SLinus Walleij 6893a198059SLinus Walleij nmk_chip = irq_data_get_irq_chip_data(d); 6903a198059SLinus Walleij if (!nmk_chip) 6913a198059SLinus Walleij return -EINVAL; 6923a198059SLinus Walleij 6933a198059SLinus Walleij clk_enable(nmk_chip->clk); 6943a198059SLinus Walleij spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 6953a198059SLinus Walleij spin_lock(&nmk_chip->lock); 6963a198059SLinus Walleij 6973a198059SLinus Walleij __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable); 6983a198059SLinus Walleij 6995e81e0a0SLinus Walleij if (!(nmk_chip->real_wake & BIT(d->hwirq))) 7003a198059SLinus Walleij __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable); 7013a198059SLinus Walleij 7023a198059SLinus Walleij spin_unlock(&nmk_chip->lock); 7033a198059SLinus Walleij spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 7043a198059SLinus Walleij clk_disable(nmk_chip->clk); 7053a198059SLinus Walleij 7063a198059SLinus Walleij return 0; 7073a198059SLinus Walleij } 7083a198059SLinus Walleij 7093a198059SLinus Walleij static void nmk_gpio_irq_mask(struct irq_data *d) 7103a198059SLinus Walleij { 7113a198059SLinus Walleij nmk_gpio_irq_maskunmask(d, false); 7123a198059SLinus Walleij } 7133a198059SLinus Walleij 7143a198059SLinus Walleij static void nmk_gpio_irq_unmask(struct irq_data *d) 7153a198059SLinus Walleij { 7163a198059SLinus Walleij nmk_gpio_irq_maskunmask(d, true); 7173a198059SLinus Walleij } 7183a198059SLinus Walleij 7193a198059SLinus Walleij static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 7203a198059SLinus Walleij { 7213a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip; 7223a198059SLinus Walleij unsigned long flags; 7233a198059SLinus Walleij 7243a198059SLinus Walleij nmk_chip = irq_data_get_irq_chip_data(d); 7253a198059SLinus Walleij if (!nmk_chip) 7263a198059SLinus Walleij return -EINVAL; 7273a198059SLinus Walleij 7283a198059SLinus Walleij clk_enable(nmk_chip->clk); 7293a198059SLinus Walleij spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 7303a198059SLinus Walleij spin_lock(&nmk_chip->lock); 7313a198059SLinus Walleij 7323a198059SLinus Walleij if (irqd_irq_disabled(d)) 7333a198059SLinus Walleij __nmk_gpio_set_wake(nmk_chip, d->hwirq, on); 7343a198059SLinus Walleij 7353a198059SLinus Walleij if (on) 7365e81e0a0SLinus Walleij nmk_chip->real_wake |= BIT(d->hwirq); 7373a198059SLinus Walleij else 7385e81e0a0SLinus Walleij nmk_chip->real_wake &= ~BIT(d->hwirq); 7393a198059SLinus Walleij 7403a198059SLinus Walleij spin_unlock(&nmk_chip->lock); 7413a198059SLinus Walleij spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 7423a198059SLinus Walleij clk_disable(nmk_chip->clk); 7433a198059SLinus Walleij 7443a198059SLinus Walleij return 0; 7453a198059SLinus Walleij } 7463a198059SLinus Walleij 7473a198059SLinus Walleij static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) 7483a198059SLinus Walleij { 7493a198059SLinus Walleij bool enabled = !irqd_irq_disabled(d); 7503a198059SLinus Walleij bool wake = irqd_is_wakeup_set(d); 7513a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip; 7523a198059SLinus Walleij unsigned long flags; 7533a198059SLinus Walleij 7543a198059SLinus Walleij nmk_chip = irq_data_get_irq_chip_data(d); 7553a198059SLinus Walleij if (!nmk_chip) 7563a198059SLinus Walleij return -EINVAL; 7573a198059SLinus Walleij if (type & IRQ_TYPE_LEVEL_HIGH) 7583a198059SLinus Walleij return -EINVAL; 7593a198059SLinus Walleij if (type & IRQ_TYPE_LEVEL_LOW) 7603a198059SLinus Walleij return -EINVAL; 7613a198059SLinus Walleij 7623a198059SLinus Walleij clk_enable(nmk_chip->clk); 7633a198059SLinus Walleij spin_lock_irqsave(&nmk_chip->lock, flags); 7643a198059SLinus Walleij 7653a198059SLinus Walleij if (enabled) 7663a198059SLinus Walleij __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false); 7673a198059SLinus Walleij 7683a198059SLinus Walleij if (enabled || wake) 7693a198059SLinus Walleij __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false); 7703a198059SLinus Walleij 7715e81e0a0SLinus Walleij nmk_chip->edge_rising &= ~BIT(d->hwirq); 7723a198059SLinus Walleij if (type & IRQ_TYPE_EDGE_RISING) 7735e81e0a0SLinus Walleij nmk_chip->edge_rising |= BIT(d->hwirq); 7743a198059SLinus Walleij 7755e81e0a0SLinus Walleij nmk_chip->edge_falling &= ~BIT(d->hwirq); 7763a198059SLinus Walleij if (type & IRQ_TYPE_EDGE_FALLING) 7775e81e0a0SLinus Walleij nmk_chip->edge_falling |= BIT(d->hwirq); 7783a198059SLinus Walleij 7793a198059SLinus Walleij if (enabled) 7803a198059SLinus Walleij __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true); 7813a198059SLinus Walleij 7823a198059SLinus Walleij if (enabled || wake) 7833a198059SLinus Walleij __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true); 7843a198059SLinus Walleij 7853a198059SLinus Walleij spin_unlock_irqrestore(&nmk_chip->lock, flags); 7863a198059SLinus Walleij clk_disable(nmk_chip->clk); 7873a198059SLinus Walleij 7883a198059SLinus Walleij return 0; 7893a198059SLinus Walleij } 7903a198059SLinus Walleij 7913a198059SLinus Walleij static unsigned int nmk_gpio_irq_startup(struct irq_data *d) 7923a198059SLinus Walleij { 7933a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); 7943a198059SLinus Walleij 7953a198059SLinus Walleij clk_enable(nmk_chip->clk); 7963a198059SLinus Walleij nmk_gpio_irq_unmask(d); 7973a198059SLinus Walleij return 0; 7983a198059SLinus Walleij } 7993a198059SLinus Walleij 8003a198059SLinus Walleij static void nmk_gpio_irq_shutdown(struct irq_data *d) 8013a198059SLinus Walleij { 8023a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); 8033a198059SLinus Walleij 8043a198059SLinus Walleij nmk_gpio_irq_mask(d); 8053a198059SLinus Walleij clk_disable(nmk_chip->clk); 8063a198059SLinus Walleij } 8073a198059SLinus Walleij 8085663bb27SJiang Liu static void __nmk_gpio_irq_handler(struct irq_desc *desc, u32 status) 8093a198059SLinus Walleij { 8105663bb27SJiang Liu struct irq_chip *host_chip = irq_desc_get_chip(desc); 8113a198059SLinus Walleij struct gpio_chip *chip = irq_desc_get_handler_data(desc); 8123a198059SLinus Walleij 8133a198059SLinus Walleij chained_irq_enter(host_chip, desc); 8143a198059SLinus Walleij 8153a198059SLinus Walleij while (status) { 8163a198059SLinus Walleij int bit = __ffs(status); 8173a198059SLinus Walleij 818f0fbe7bcSThierry Reding generic_handle_irq(irq_find_mapping(chip->irq.domain, bit)); 8193a198059SLinus Walleij status &= ~BIT(bit); 8203a198059SLinus Walleij } 8213a198059SLinus Walleij 8223a198059SLinus Walleij chained_irq_exit(host_chip, desc); 8233a198059SLinus Walleij } 8243a198059SLinus Walleij 825bd0b9ac4SThomas Gleixner static void nmk_gpio_irq_handler(struct irq_desc *desc) 8263a198059SLinus Walleij { 8273a198059SLinus Walleij struct gpio_chip *chip = irq_desc_get_handler_data(desc); 82868ab0126SLinus Walleij struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 8293a198059SLinus Walleij u32 status; 8303a198059SLinus Walleij 8313a198059SLinus Walleij clk_enable(nmk_chip->clk); 8323a198059SLinus Walleij status = readl(nmk_chip->addr + NMK_GPIO_IS); 8333a198059SLinus Walleij clk_disable(nmk_chip->clk); 8343a198059SLinus Walleij 8355663bb27SJiang Liu __nmk_gpio_irq_handler(desc, status); 8363a198059SLinus Walleij } 8373a198059SLinus Walleij 838bd0b9ac4SThomas Gleixner static void nmk_gpio_latent_irq_handler(struct irq_desc *desc) 8393a198059SLinus Walleij { 8403a198059SLinus Walleij struct gpio_chip *chip = irq_desc_get_handler_data(desc); 84168ab0126SLinus Walleij struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 8423a198059SLinus Walleij u32 status = nmk_chip->get_latent_status(nmk_chip->bank); 8433a198059SLinus Walleij 8445663bb27SJiang Liu __nmk_gpio_irq_handler(desc, status); 8453a198059SLinus Walleij } 8463a198059SLinus Walleij 8473a198059SLinus Walleij /* I/O Functions */ 8483a198059SLinus Walleij 84967668a57SLinus Walleij static int nmk_gpio_get_dir(struct gpio_chip *chip, unsigned offset) 85067668a57SLinus Walleij { 85167668a57SLinus Walleij struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 85267668a57SLinus Walleij int dir; 85367668a57SLinus Walleij 85467668a57SLinus Walleij clk_enable(nmk_chip->clk); 85567668a57SLinus Walleij 8566b1a7c9eSLinus Walleij dir = !(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset)); 85767668a57SLinus Walleij 85867668a57SLinus Walleij clk_disable(nmk_chip->clk); 85967668a57SLinus Walleij 86067668a57SLinus Walleij return dir; 86167668a57SLinus Walleij } 86267668a57SLinus Walleij 8633a198059SLinus Walleij static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) 8643a198059SLinus Walleij { 86568ab0126SLinus Walleij struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 8663a198059SLinus Walleij 8673a198059SLinus Walleij clk_enable(nmk_chip->clk); 8683a198059SLinus Walleij 8695e81e0a0SLinus Walleij writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC); 8703a198059SLinus Walleij 8713a198059SLinus Walleij clk_disable(nmk_chip->clk); 8723a198059SLinus Walleij 8733a198059SLinus Walleij return 0; 8743a198059SLinus Walleij } 8753a198059SLinus Walleij 8763a198059SLinus Walleij static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset) 8773a198059SLinus Walleij { 87868ab0126SLinus Walleij struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 8793a198059SLinus Walleij int value; 8803a198059SLinus Walleij 8813a198059SLinus Walleij clk_enable(nmk_chip->clk); 8823a198059SLinus Walleij 8835e81e0a0SLinus Walleij value = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset)); 8843a198059SLinus Walleij 8853a198059SLinus Walleij clk_disable(nmk_chip->clk); 8863a198059SLinus Walleij 8873a198059SLinus Walleij return value; 8883a198059SLinus Walleij } 8893a198059SLinus Walleij 8903a198059SLinus Walleij static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset, 8913a198059SLinus Walleij int val) 8923a198059SLinus Walleij { 89368ab0126SLinus Walleij struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 8943a198059SLinus Walleij 8953a198059SLinus Walleij clk_enable(nmk_chip->clk); 8963a198059SLinus Walleij 8973a198059SLinus Walleij __nmk_gpio_set_output(nmk_chip, offset, val); 8983a198059SLinus Walleij 8993a198059SLinus Walleij clk_disable(nmk_chip->clk); 9003a198059SLinus Walleij } 9013a198059SLinus Walleij 9023a198059SLinus Walleij static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, 9033a198059SLinus Walleij int val) 9043a198059SLinus Walleij { 90568ab0126SLinus Walleij struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 9063a198059SLinus Walleij 9073a198059SLinus Walleij clk_enable(nmk_chip->clk); 9083a198059SLinus Walleij 9093a198059SLinus Walleij __nmk_gpio_make_output(nmk_chip, offset, val); 9103a198059SLinus Walleij 9113a198059SLinus Walleij clk_disable(nmk_chip->clk); 9123a198059SLinus Walleij 9133a198059SLinus Walleij return 0; 9143a198059SLinus Walleij } 9153a198059SLinus Walleij 9163a198059SLinus Walleij #ifdef CONFIG_DEBUG_FS 917caee57ecSArnd Bergmann static int nmk_gpio_get_mode(struct nmk_gpio_chip *nmk_chip, int offset) 918caee57ecSArnd Bergmann { 919caee57ecSArnd Bergmann u32 afunc, bfunc; 920caee57ecSArnd Bergmann 921caee57ecSArnd Bergmann clk_enable(nmk_chip->clk); 922caee57ecSArnd Bergmann 923caee57ecSArnd Bergmann afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & BIT(offset); 924caee57ecSArnd Bergmann bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & BIT(offset); 925caee57ecSArnd Bergmann 926caee57ecSArnd Bergmann clk_disable(nmk_chip->clk); 927caee57ecSArnd Bergmann 928caee57ecSArnd Bergmann return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0); 929caee57ecSArnd Bergmann } 9303a198059SLinus Walleij 9313a198059SLinus Walleij #include <linux/seq_file.h> 9323a198059SLinus Walleij 9333a198059SLinus Walleij static void nmk_gpio_dbg_show_one(struct seq_file *s, 9343a198059SLinus Walleij struct pinctrl_dev *pctldev, struct gpio_chip *chip, 9353a198059SLinus Walleij unsigned offset, unsigned gpio) 9363a198059SLinus Walleij { 9373a198059SLinus Walleij const char *label = gpiochip_is_requested(chip, offset); 93868ab0126SLinus Walleij struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 9393a198059SLinus Walleij int mode; 9403a198059SLinus Walleij bool is_out; 9418f1774a2SLinus Walleij bool data_out; 9423a198059SLinus Walleij bool pull; 9433a198059SLinus Walleij const char *modes[] = { 9443a198059SLinus Walleij [NMK_GPIO_ALT_GPIO] = "gpio", 9453a198059SLinus Walleij [NMK_GPIO_ALT_A] = "altA", 9463a198059SLinus Walleij [NMK_GPIO_ALT_B] = "altB", 9473a198059SLinus Walleij [NMK_GPIO_ALT_C] = "altC", 9483a198059SLinus Walleij [NMK_GPIO_ALT_C+1] = "altC1", 9493a198059SLinus Walleij [NMK_GPIO_ALT_C+2] = "altC2", 9503a198059SLinus Walleij [NMK_GPIO_ALT_C+3] = "altC3", 9513a198059SLinus Walleij [NMK_GPIO_ALT_C+4] = "altC4", 9523a198059SLinus Walleij }; 9538f1774a2SLinus Walleij const char *pulls[] = { 9548f1774a2SLinus Walleij "none ", 9558f1774a2SLinus Walleij "pull down", 9568f1774a2SLinus Walleij "pull up ", 9578f1774a2SLinus Walleij }; 9583a198059SLinus Walleij 9593a198059SLinus Walleij clk_enable(nmk_chip->clk); 9605e81e0a0SLinus Walleij is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset)); 9615e81e0a0SLinus Walleij pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & BIT(offset)); 9625e81e0a0SLinus Walleij data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset)); 9635e81e0a0SLinus Walleij mode = nmk_gpio_get_mode(nmk_chip, offset); 9643a198059SLinus Walleij if ((mode == NMK_GPIO_ALT_C) && pctldev) 9653a198059SLinus Walleij mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio); 9663a198059SLinus Walleij 9678f1774a2SLinus Walleij if (is_out) { 9688f1774a2SLinus Walleij seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s", 9698f1774a2SLinus Walleij gpio, 9708f1774a2SLinus Walleij label ?: "(none)", 9718f1774a2SLinus Walleij data_out ? "hi" : "lo", 9728f1774a2SLinus Walleij (mode < 0) ? "unknown" : modes[mode]); 9738f1774a2SLinus Walleij } else { 9743a198059SLinus Walleij int irq = gpio_to_irq(gpio); 9753a198059SLinus Walleij struct irq_desc *desc = irq_to_desc(irq); 9768f1774a2SLinus Walleij int pullidx = 0; 977d7f005e8SLinus Walleij int val; 9783a198059SLinus Walleij 9798f1774a2SLinus Walleij if (pull) 9806ee33455SLinus Walleij pullidx = data_out ? 2 : 1; 9818f1774a2SLinus Walleij 9828f1774a2SLinus Walleij seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s", 9838f1774a2SLinus Walleij gpio, 9848f1774a2SLinus Walleij label ?: "(none)", 9858f1774a2SLinus Walleij pulls[pullidx], 9868f1774a2SLinus Walleij (mode < 0) ? "unknown" : modes[mode]); 987d7f005e8SLinus Walleij 988d7f005e8SLinus Walleij val = nmk_gpio_get_input(chip, offset); 989d7f005e8SLinus Walleij seq_printf(s, " VAL %d", val); 990d7f005e8SLinus Walleij 9918f1774a2SLinus Walleij /* 9928f1774a2SLinus Walleij * This races with request_irq(), set_irq_type(), 9933a198059SLinus Walleij * and set_irq_wake() ... but those are "rare". 9943a198059SLinus Walleij */ 9953a198059SLinus Walleij if (irq > 0 && desc && desc->action) { 9963a198059SLinus Walleij char *trigger; 9973a198059SLinus Walleij 9985e81e0a0SLinus Walleij if (nmk_chip->edge_rising & BIT(offset)) 9993a198059SLinus Walleij trigger = "edge-rising"; 10005e81e0a0SLinus Walleij else if (nmk_chip->edge_falling & BIT(offset)) 10013a198059SLinus Walleij trigger = "edge-falling"; 10023a198059SLinus Walleij else 10033a198059SLinus Walleij trigger = "edge-undefined"; 10043a198059SLinus Walleij 10053a198059SLinus Walleij seq_printf(s, " irq-%d %s%s", 10063a198059SLinus Walleij irq, trigger, 10073a198059SLinus Walleij irqd_is_wakeup_set(&desc->irq_data) 10083a198059SLinus Walleij ? " wakeup" : ""); 10093a198059SLinus Walleij } 10103a198059SLinus Walleij } 10113a198059SLinus Walleij clk_disable(nmk_chip->clk); 10123a198059SLinus Walleij } 10133a198059SLinus Walleij 10143a198059SLinus Walleij static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 10153a198059SLinus Walleij { 10163a198059SLinus Walleij unsigned i; 10173a198059SLinus Walleij unsigned gpio = chip->base; 10183a198059SLinus Walleij 10193a198059SLinus Walleij for (i = 0; i < chip->ngpio; i++, gpio++) { 10203a198059SLinus Walleij nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio); 10213a198059SLinus Walleij seq_printf(s, "\n"); 10223a198059SLinus Walleij } 10233a198059SLinus Walleij } 10243a198059SLinus Walleij 10253a198059SLinus Walleij #else 10263a198059SLinus Walleij static inline void nmk_gpio_dbg_show_one(struct seq_file *s, 10273a198059SLinus Walleij struct pinctrl_dev *pctldev, 10283a198059SLinus Walleij struct gpio_chip *chip, 10293a198059SLinus Walleij unsigned offset, unsigned gpio) 10303a198059SLinus Walleij { 10313a198059SLinus Walleij } 10323a198059SLinus Walleij #define nmk_gpio_dbg_show NULL 10333a198059SLinus Walleij #endif 10343a198059SLinus Walleij 1035bc222ef4SLinus Walleij /* 1036bc222ef4SLinus Walleij * We will allocate memory for the state container using devm* allocators 1037bc222ef4SLinus Walleij * binding to the first device reaching this point, it doesn't matter if 1038bc222ef4SLinus Walleij * it is the pin controller or GPIO driver. However we need to use the right 1039bc222ef4SLinus Walleij * platform device when looking up resources so pay attention to pdev. 1040bc222ef4SLinus Walleij */ 1041bc222ef4SLinus Walleij static struct nmk_gpio_chip *nmk_gpio_populate_chip(struct device_node *np, 1042bc222ef4SLinus Walleij struct platform_device *pdev) 1043bc222ef4SLinus Walleij { 1044bc222ef4SLinus Walleij struct nmk_gpio_chip *nmk_chip; 1045bc222ef4SLinus Walleij struct platform_device *gpio_pdev; 1046bc222ef4SLinus Walleij struct gpio_chip *chip; 1047bc222ef4SLinus Walleij struct resource *res; 1048bc222ef4SLinus Walleij struct clk *clk; 1049bc222ef4SLinus Walleij void __iomem *base; 1050bc222ef4SLinus Walleij u32 id; 1051bc222ef4SLinus Walleij 1052bc222ef4SLinus Walleij gpio_pdev = of_find_device_by_node(np); 1053bc222ef4SLinus Walleij if (!gpio_pdev) { 1054bc222ef4SLinus Walleij pr_err("populate \"%s\": device not found\n", np->name); 1055bc222ef4SLinus Walleij return ERR_PTR(-ENODEV); 1056bc222ef4SLinus Walleij } 1057bc222ef4SLinus Walleij if (of_property_read_u32(np, "gpio-bank", &id)) { 1058bc222ef4SLinus Walleij dev_err(&pdev->dev, "populate: gpio-bank property not found\n"); 1059bc222ef4SLinus Walleij return ERR_PTR(-EINVAL); 1060bc222ef4SLinus Walleij } 1061bc222ef4SLinus Walleij 1062bc222ef4SLinus Walleij /* Already populated? */ 1063bc222ef4SLinus Walleij nmk_chip = nmk_gpio_chips[id]; 1064bc222ef4SLinus Walleij if (nmk_chip) 1065bc222ef4SLinus Walleij return nmk_chip; 1066bc222ef4SLinus Walleij 1067bc222ef4SLinus Walleij nmk_chip = devm_kzalloc(&pdev->dev, sizeof(*nmk_chip), GFP_KERNEL); 1068bc222ef4SLinus Walleij if (!nmk_chip) 1069bc222ef4SLinus Walleij return ERR_PTR(-ENOMEM); 1070bc222ef4SLinus Walleij 1071bc222ef4SLinus Walleij nmk_chip->bank = id; 1072bc222ef4SLinus Walleij chip = &nmk_chip->chip; 1073bc222ef4SLinus Walleij chip->base = id * NMK_GPIO_PER_CHIP; 1074bc222ef4SLinus Walleij chip->ngpio = NMK_GPIO_PER_CHIP; 1075bc222ef4SLinus Walleij chip->label = dev_name(&gpio_pdev->dev); 107658383c78SLinus Walleij chip->parent = &gpio_pdev->dev; 1077bc222ef4SLinus Walleij 1078bc222ef4SLinus Walleij res = platform_get_resource(gpio_pdev, IORESOURCE_MEM, 0); 1079bc222ef4SLinus Walleij base = devm_ioremap_resource(&pdev->dev, res); 1080bc222ef4SLinus Walleij if (IS_ERR(base)) 1081376c7a75SMasahiro Yamada return ERR_CAST(base); 1082bc222ef4SLinus Walleij nmk_chip->addr = base; 1083bc222ef4SLinus Walleij 1084bc222ef4SLinus Walleij clk = clk_get(&gpio_pdev->dev, NULL); 1085bc222ef4SLinus Walleij if (IS_ERR(clk)) 1086bc222ef4SLinus Walleij return (void *) clk; 1087bc222ef4SLinus Walleij clk_prepare(clk); 1088bc222ef4SLinus Walleij nmk_chip->clk = clk; 1089bc222ef4SLinus Walleij 1090bc222ef4SLinus Walleij BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); 1091bc222ef4SLinus Walleij nmk_gpio_chips[id] = nmk_chip; 1092bc222ef4SLinus Walleij return nmk_chip; 1093bc222ef4SLinus Walleij } 1094bc222ef4SLinus Walleij 10953a198059SLinus Walleij static int nmk_gpio_probe(struct platform_device *dev) 10963a198059SLinus Walleij { 10973a198059SLinus Walleij struct device_node *np = dev->dev.of_node; 10983a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip; 10993a198059SLinus Walleij struct gpio_chip *chip; 11003007d941SLinus Walleij struct irq_chip *irqchip; 11013a198059SLinus Walleij int latent_irq; 11023a198059SLinus Walleij bool supports_sleepmode; 11033a198059SLinus Walleij int irq; 11043a198059SLinus Walleij int ret; 11053a198059SLinus Walleij 1106bc222ef4SLinus Walleij nmk_chip = nmk_gpio_populate_chip(np, dev); 1107bc222ef4SLinus Walleij if (IS_ERR(nmk_chip)) { 1108bc222ef4SLinus Walleij dev_err(&dev->dev, "could not populate nmk chip struct\n"); 1109bc222ef4SLinus Walleij return PTR_ERR(nmk_chip); 1110bc222ef4SLinus Walleij } 1111bc222ef4SLinus Walleij 11120f9d85b7SJulia Lawall supports_sleepmode = 11130f9d85b7SJulia Lawall of_property_read_bool(np, "st,supports-sleepmode"); 11143a198059SLinus Walleij 1115bc222ef4SLinus Walleij /* Correct platform device ID */ 1116bc222ef4SLinus Walleij dev->id = nmk_chip->bank; 11173a198059SLinus Walleij 11183a198059SLinus Walleij irq = platform_get_irq(dev, 0); 11193a198059SLinus Walleij if (irq < 0) 11203a198059SLinus Walleij return irq; 11213a198059SLinus Walleij 11223a198059SLinus Walleij /* It's OK for this IRQ not to be present */ 11233a198059SLinus Walleij latent_irq = platform_get_irq(dev, 1); 11243a198059SLinus Walleij 11253a198059SLinus Walleij /* 11263a198059SLinus Walleij * The virt address in nmk_chip->addr is in the nomadik register space, 11273a198059SLinus Walleij * so we can simply convert the resource address, without remapping 11283a198059SLinus Walleij */ 11293a198059SLinus Walleij nmk_chip->parent_irq = irq; 11303a198059SLinus Walleij nmk_chip->latent_parent_irq = latent_irq; 11313a198059SLinus Walleij nmk_chip->sleepmode = supports_sleepmode; 11323a198059SLinus Walleij spin_lock_init(&nmk_chip->lock); 11333a198059SLinus Walleij 11343a198059SLinus Walleij chip = &nmk_chip->chip; 113598c85d58SJonas Gorski chip->request = gpiochip_generic_request; 113698c85d58SJonas Gorski chip->free = gpiochip_generic_free; 113767668a57SLinus Walleij chip->get_direction = nmk_gpio_get_dir; 11383007d941SLinus Walleij chip->direction_input = nmk_gpio_make_input; 11393007d941SLinus Walleij chip->get = nmk_gpio_get_input; 11403007d941SLinus Walleij chip->direction_output = nmk_gpio_make_output; 11413007d941SLinus Walleij chip->set = nmk_gpio_set_output; 11423007d941SLinus Walleij chip->dbg_show = nmk_gpio_dbg_show; 11433007d941SLinus Walleij chip->can_sleep = false; 11443a198059SLinus Walleij chip->owner = THIS_MODULE; 11453a198059SLinus Walleij 11463007d941SLinus Walleij irqchip = &nmk_chip->irqchip; 11473007d941SLinus Walleij irqchip->irq_ack = nmk_gpio_irq_ack; 11483007d941SLinus Walleij irqchip->irq_mask = nmk_gpio_irq_mask; 11493007d941SLinus Walleij irqchip->irq_unmask = nmk_gpio_irq_unmask; 11503007d941SLinus Walleij irqchip->irq_set_type = nmk_gpio_irq_set_type; 11513007d941SLinus Walleij irqchip->irq_set_wake = nmk_gpio_irq_set_wake; 11523007d941SLinus Walleij irqchip->irq_startup = nmk_gpio_irq_startup; 11533007d941SLinus Walleij irqchip->irq_shutdown = nmk_gpio_irq_shutdown; 11543007d941SLinus Walleij irqchip->flags = IRQCHIP_MASK_ON_SUSPEND; 11553007d941SLinus Walleij irqchip->name = kasprintf(GFP_KERNEL, "nmk%u-%u-%u", 11563007d941SLinus Walleij dev->id, 11573007d941SLinus Walleij chip->base, 11583007d941SLinus Walleij chip->base + chip->ngpio - 1); 11593007d941SLinus Walleij 11603a198059SLinus Walleij clk_enable(nmk_chip->clk); 11613a198059SLinus Walleij nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); 11623a198059SLinus Walleij clk_disable(nmk_chip->clk); 11633a198059SLinus Walleij chip->of_node = np; 11643a198059SLinus Walleij 116568ab0126SLinus Walleij ret = gpiochip_add_data(chip, nmk_chip); 11663a198059SLinus Walleij if (ret) 11673a198059SLinus Walleij return ret; 11683a198059SLinus Walleij 11693a198059SLinus Walleij platform_set_drvdata(dev, nmk_chip); 11703a198059SLinus Walleij 11713a198059SLinus Walleij /* 11723a198059SLinus Walleij * Let the generic code handle this edge IRQ, the the chained 11733a198059SLinus Walleij * handler will perform the actual work of handling the parent 11743a198059SLinus Walleij * interrupt. 11753a198059SLinus Walleij */ 11763007d941SLinus Walleij ret = gpiochip_irqchip_add(chip, 11773007d941SLinus Walleij irqchip, 11783a198059SLinus Walleij 0, 11793a198059SLinus Walleij handle_edge_irq, 118031ebe86dSLinus Walleij IRQ_TYPE_NONE); 11813a198059SLinus Walleij if (ret) { 11823a198059SLinus Walleij dev_err(&dev->dev, "could not add irqchip\n"); 11832fcea6ceSLinus Walleij gpiochip_remove(&nmk_chip->chip); 11843a198059SLinus Walleij return -ENODEV; 11853a198059SLinus Walleij } 11863a198059SLinus Walleij /* Then register the chain on the parent IRQ */ 11873007d941SLinus Walleij gpiochip_set_chained_irqchip(chip, 11883007d941SLinus Walleij irqchip, 11893a198059SLinus Walleij nmk_chip->parent_irq, 11903a198059SLinus Walleij nmk_gpio_irq_handler); 11913a198059SLinus Walleij if (nmk_chip->latent_parent_irq > 0) 11923007d941SLinus Walleij gpiochip_set_chained_irqchip(chip, 11933007d941SLinus Walleij irqchip, 11943a198059SLinus Walleij nmk_chip->latent_parent_irq, 11953a198059SLinus Walleij nmk_gpio_latent_irq_handler); 11963a198059SLinus Walleij 11973a198059SLinus Walleij dev_info(&dev->dev, "at address %p\n", nmk_chip->addr); 11983a198059SLinus Walleij 11993a198059SLinus Walleij return 0; 12003a198059SLinus Walleij } 12013a198059SLinus Walleij 12023a198059SLinus Walleij static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev) 12033a198059SLinus Walleij { 12043a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 12053a198059SLinus Walleij 12063a198059SLinus Walleij return npct->soc->ngroups; 12073a198059SLinus Walleij } 12083a198059SLinus Walleij 12093a198059SLinus Walleij static const char *nmk_get_group_name(struct pinctrl_dev *pctldev, 12103a198059SLinus Walleij unsigned selector) 12113a198059SLinus Walleij { 12123a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 12133a198059SLinus Walleij 12143a198059SLinus Walleij return npct->soc->groups[selector].name; 12153a198059SLinus Walleij } 12163a198059SLinus Walleij 12173a198059SLinus Walleij static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, 12183a198059SLinus Walleij const unsigned **pins, 12193a198059SLinus Walleij unsigned *num_pins) 12203a198059SLinus Walleij { 12213a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 12223a198059SLinus Walleij 12233a198059SLinus Walleij *pins = npct->soc->groups[selector].pins; 12243a198059SLinus Walleij *num_pins = npct->soc->groups[selector].npins; 12253a198059SLinus Walleij return 0; 12263a198059SLinus Walleij } 12273a198059SLinus Walleij 12286ca7d2e3SLinus Walleij static struct nmk_gpio_chip *find_nmk_gpio_from_pin(unsigned pin) 12293a198059SLinus Walleij { 12303a198059SLinus Walleij int i; 12316ca7d2e3SLinus Walleij struct nmk_gpio_chip *nmk_gpio; 12323a198059SLinus Walleij 12336ca7d2e3SLinus Walleij for(i = 0; i < NMK_MAX_BANKS; i++) { 12346ca7d2e3SLinus Walleij nmk_gpio = nmk_gpio_chips[i]; 12356ca7d2e3SLinus Walleij if (!nmk_gpio) 12366ca7d2e3SLinus Walleij continue; 12376ca7d2e3SLinus Walleij if (pin >= nmk_gpio->chip.base && 12386ca7d2e3SLinus Walleij pin < nmk_gpio->chip.base + nmk_gpio->chip.ngpio) 12396ca7d2e3SLinus Walleij return nmk_gpio; 12403a198059SLinus Walleij } 12413a198059SLinus Walleij return NULL; 12423a198059SLinus Walleij } 12433a198059SLinus Walleij 12446ca7d2e3SLinus Walleij static struct gpio_chip *find_gc_from_pin(unsigned pin) 12456ca7d2e3SLinus Walleij { 12466ca7d2e3SLinus Walleij struct nmk_gpio_chip *nmk_gpio = find_nmk_gpio_from_pin(pin); 12476ca7d2e3SLinus Walleij 12486ca7d2e3SLinus Walleij if (nmk_gpio) 12496ca7d2e3SLinus Walleij return &nmk_gpio->chip; 12506ca7d2e3SLinus Walleij return NULL; 12516ca7d2e3SLinus Walleij } 12526ca7d2e3SLinus Walleij 12533a198059SLinus Walleij static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 12543a198059SLinus Walleij unsigned offset) 12553a198059SLinus Walleij { 12566ca7d2e3SLinus Walleij struct gpio_chip *chip = find_gc_from_pin(offset); 12573a198059SLinus Walleij 12586ca7d2e3SLinus Walleij if (!chip) { 12593a198059SLinus Walleij seq_printf(s, "invalid pin offset"); 12603a198059SLinus Walleij return; 12613a198059SLinus Walleij } 12623a198059SLinus Walleij nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset); 12633a198059SLinus Walleij } 12643a198059SLinus Walleij 12653a198059SLinus Walleij static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps, 12663a198059SLinus Walleij unsigned *num_maps, const char *group, 12673a198059SLinus Walleij const char *function) 12683a198059SLinus Walleij { 12693a198059SLinus Walleij if (*num_maps == *reserved_maps) 12703a198059SLinus Walleij return -ENOSPC; 12713a198059SLinus Walleij 12723a198059SLinus Walleij (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 12733a198059SLinus Walleij (*map)[*num_maps].data.mux.group = group; 12743a198059SLinus Walleij (*map)[*num_maps].data.mux.function = function; 12753a198059SLinus Walleij (*num_maps)++; 12763a198059SLinus Walleij 12773a198059SLinus Walleij return 0; 12783a198059SLinus Walleij } 12793a198059SLinus Walleij 12803a198059SLinus Walleij static int nmk_dt_add_map_configs(struct pinctrl_map **map, 12813a198059SLinus Walleij unsigned *reserved_maps, 12823a198059SLinus Walleij unsigned *num_maps, const char *group, 12833a198059SLinus Walleij unsigned long *configs, unsigned num_configs) 12843a198059SLinus Walleij { 12853a198059SLinus Walleij unsigned long *dup_configs; 12863a198059SLinus Walleij 12873a198059SLinus Walleij if (*num_maps == *reserved_maps) 12883a198059SLinus Walleij return -ENOSPC; 12893a198059SLinus Walleij 12903a198059SLinus Walleij dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), 12913a198059SLinus Walleij GFP_KERNEL); 12923a198059SLinus Walleij if (!dup_configs) 12933a198059SLinus Walleij return -ENOMEM; 12943a198059SLinus Walleij 12953a198059SLinus Walleij (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN; 12963a198059SLinus Walleij 12973a198059SLinus Walleij (*map)[*num_maps].data.configs.group_or_pin = group; 12983a198059SLinus Walleij (*map)[*num_maps].data.configs.configs = dup_configs; 12993a198059SLinus Walleij (*map)[*num_maps].data.configs.num_configs = num_configs; 13003a198059SLinus Walleij (*num_maps)++; 13013a198059SLinus Walleij 13023a198059SLinus Walleij return 0; 13033a198059SLinus Walleij } 13043a198059SLinus Walleij 13053a198059SLinus Walleij #define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, } 13063a198059SLinus Walleij #define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \ 13073a198059SLinus Walleij .size = ARRAY_SIZE(y), } 13083a198059SLinus Walleij 13093a198059SLinus Walleij static const unsigned long nmk_pin_input_modes[] = { 13103a198059SLinus Walleij PIN_INPUT_NOPULL, 13113a198059SLinus Walleij PIN_INPUT_PULLUP, 13123a198059SLinus Walleij PIN_INPUT_PULLDOWN, 13133a198059SLinus Walleij }; 13143a198059SLinus Walleij 13153a198059SLinus Walleij static const unsigned long nmk_pin_output_modes[] = { 13163a198059SLinus Walleij PIN_OUTPUT_LOW, 13173a198059SLinus Walleij PIN_OUTPUT_HIGH, 13183a198059SLinus Walleij PIN_DIR_OUTPUT, 13193a198059SLinus Walleij }; 13203a198059SLinus Walleij 13213a198059SLinus Walleij static const unsigned long nmk_pin_sleep_modes[] = { 13223a198059SLinus Walleij PIN_SLEEPMODE_DISABLED, 13233a198059SLinus Walleij PIN_SLEEPMODE_ENABLED, 13243a198059SLinus Walleij }; 13253a198059SLinus Walleij 13263a198059SLinus Walleij static const unsigned long nmk_pin_sleep_input_modes[] = { 13273a198059SLinus Walleij PIN_SLPM_INPUT_NOPULL, 13283a198059SLinus Walleij PIN_SLPM_INPUT_PULLUP, 13293a198059SLinus Walleij PIN_SLPM_INPUT_PULLDOWN, 13303a198059SLinus Walleij PIN_SLPM_DIR_INPUT, 13313a198059SLinus Walleij }; 13323a198059SLinus Walleij 13333a198059SLinus Walleij static const unsigned long nmk_pin_sleep_output_modes[] = { 13343a198059SLinus Walleij PIN_SLPM_OUTPUT_LOW, 13353a198059SLinus Walleij PIN_SLPM_OUTPUT_HIGH, 13363a198059SLinus Walleij PIN_SLPM_DIR_OUTPUT, 13373a198059SLinus Walleij }; 13383a198059SLinus Walleij 13393a198059SLinus Walleij static const unsigned long nmk_pin_sleep_wakeup_modes[] = { 13403a198059SLinus Walleij PIN_SLPM_WAKEUP_DISABLE, 13413a198059SLinus Walleij PIN_SLPM_WAKEUP_ENABLE, 13423a198059SLinus Walleij }; 13433a198059SLinus Walleij 13443a198059SLinus Walleij static const unsigned long nmk_pin_gpio_modes[] = { 13453a198059SLinus Walleij PIN_GPIOMODE_DISABLED, 13463a198059SLinus Walleij PIN_GPIOMODE_ENABLED, 13473a198059SLinus Walleij }; 13483a198059SLinus Walleij 13493a198059SLinus Walleij static const unsigned long nmk_pin_sleep_pdis_modes[] = { 13503a198059SLinus Walleij PIN_SLPM_PDIS_DISABLED, 13513a198059SLinus Walleij PIN_SLPM_PDIS_ENABLED, 13523a198059SLinus Walleij }; 13533a198059SLinus Walleij 13543a198059SLinus Walleij struct nmk_cfg_param { 13553a198059SLinus Walleij const char *property; 13563a198059SLinus Walleij unsigned long config; 13573a198059SLinus Walleij const unsigned long *choice; 13583a198059SLinus Walleij int size; 13593a198059SLinus Walleij }; 13603a198059SLinus Walleij 13613a198059SLinus Walleij static const struct nmk_cfg_param nmk_cfg_params[] = { 13623a198059SLinus Walleij NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes), 13633a198059SLinus Walleij NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes), 13643a198059SLinus Walleij NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes), 13653a198059SLinus Walleij NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes), 13663a198059SLinus Walleij NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes), 13673a198059SLinus Walleij NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes), 13683a198059SLinus Walleij NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes), 13693a198059SLinus Walleij NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes), 13703a198059SLinus Walleij }; 13713a198059SLinus Walleij 13723a198059SLinus Walleij static int nmk_dt_pin_config(int index, int val, unsigned long *config) 13733a198059SLinus Walleij { 13743a198059SLinus Walleij int ret = 0; 13753a198059SLinus Walleij 13763a198059SLinus Walleij if (nmk_cfg_params[index].choice == NULL) 13773a198059SLinus Walleij *config = nmk_cfg_params[index].config; 13783a198059SLinus Walleij else { 13793a198059SLinus Walleij /* test if out of range */ 13803a198059SLinus Walleij if (val < nmk_cfg_params[index].size) { 13813a198059SLinus Walleij *config = nmk_cfg_params[index].config | 13823a198059SLinus Walleij nmk_cfg_params[index].choice[val]; 13833a198059SLinus Walleij } 13843a198059SLinus Walleij } 13853a198059SLinus Walleij return ret; 13863a198059SLinus Walleij } 13873a198059SLinus Walleij 13883a198059SLinus Walleij static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name) 13893a198059SLinus Walleij { 13903a198059SLinus Walleij int i, pin_number; 13913a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 13923a198059SLinus Walleij 13933a198059SLinus Walleij if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1) 13943a198059SLinus Walleij for (i = 0; i < npct->soc->npins; i++) 13953a198059SLinus Walleij if (npct->soc->pins[i].number == pin_number) 13963a198059SLinus Walleij return npct->soc->pins[i].name; 13973a198059SLinus Walleij return NULL; 13983a198059SLinus Walleij } 13993a198059SLinus Walleij 14003a198059SLinus Walleij static bool nmk_pinctrl_dt_get_config(struct device_node *np, 14013a198059SLinus Walleij unsigned long *configs) 14023a198059SLinus Walleij { 14033a198059SLinus Walleij bool has_config = 0; 14043a198059SLinus Walleij unsigned long cfg = 0; 14053a198059SLinus Walleij int i, val, ret; 14063a198059SLinus Walleij 14073a198059SLinus Walleij for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) { 14083a198059SLinus Walleij ret = of_property_read_u32(np, 14093a198059SLinus Walleij nmk_cfg_params[i].property, &val); 14103a198059SLinus Walleij if (ret != -EINVAL) { 14113a198059SLinus Walleij if (nmk_dt_pin_config(i, val, &cfg) == 0) { 14123a198059SLinus Walleij *configs |= cfg; 14133a198059SLinus Walleij has_config = 1; 14143a198059SLinus Walleij } 14153a198059SLinus Walleij } 14163a198059SLinus Walleij } 14173a198059SLinus Walleij 14183a198059SLinus Walleij return has_config; 14193a198059SLinus Walleij } 14203a198059SLinus Walleij 14213a198059SLinus Walleij static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 14223a198059SLinus Walleij struct device_node *np, 14233a198059SLinus Walleij struct pinctrl_map **map, 14243a198059SLinus Walleij unsigned *reserved_maps, 14253a198059SLinus Walleij unsigned *num_maps) 14263a198059SLinus Walleij { 14273a198059SLinus Walleij int ret; 14283a198059SLinus Walleij const char *function = NULL; 14293a198059SLinus Walleij unsigned long configs = 0; 14303a198059SLinus Walleij bool has_config = 0; 14313a198059SLinus Walleij struct property *prop; 14323a198059SLinus Walleij struct device_node *np_config; 14333a198059SLinus Walleij 143468d41f23SLinus Walleij ret = of_property_read_string(np, "function", &function); 1435c2f6d059SLinus Walleij if (ret >= 0) { 143668d41f23SLinus Walleij const char *group; 143768d41f23SLinus Walleij 143868d41f23SLinus Walleij ret = of_property_count_strings(np, "groups"); 14393a198059SLinus Walleij if (ret < 0) 14403a198059SLinus Walleij goto exit; 14413a198059SLinus Walleij 1442c2f6d059SLinus Walleij ret = pinctrl_utils_reserve_map(pctldev, map, 1443c2f6d059SLinus Walleij reserved_maps, 1444c2f6d059SLinus Walleij num_maps, ret); 14453a198059SLinus Walleij if (ret < 0) 14463a198059SLinus Walleij goto exit; 14473a198059SLinus Walleij 144868d41f23SLinus Walleij of_property_for_each_string(np, "groups", prop, group) { 14493a198059SLinus Walleij ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps, 14503a198059SLinus Walleij group, function); 14513a198059SLinus Walleij if (ret < 0) 14523a198059SLinus Walleij goto exit; 14533a198059SLinus Walleij } 1454c2f6d059SLinus Walleij } 1455c2f6d059SLinus Walleij 1456c2f6d059SLinus Walleij has_config = nmk_pinctrl_dt_get_config(np, &configs); 1457c2f6d059SLinus Walleij np_config = of_parse_phandle(np, "ste,config", 0); 1458c2f6d059SLinus Walleij if (np_config) 1459c2f6d059SLinus Walleij has_config |= nmk_pinctrl_dt_get_config(np_config, &configs); 14603a198059SLinus Walleij if (has_config) { 146168d41f23SLinus Walleij const char *gpio_name; 146268d41f23SLinus Walleij const char *pin; 146368d41f23SLinus Walleij 14641637d480SLinus Walleij ret = of_property_count_strings(np, "pins"); 1465c2f6d059SLinus Walleij if (ret < 0) 1466c2f6d059SLinus Walleij goto exit; 1467c2f6d059SLinus Walleij ret = pinctrl_utils_reserve_map(pctldev, map, 1468c2f6d059SLinus Walleij reserved_maps, 1469c2f6d059SLinus Walleij num_maps, ret); 1470c2f6d059SLinus Walleij if (ret < 0) 1471c2f6d059SLinus Walleij goto exit; 1472c2f6d059SLinus Walleij 14731637d480SLinus Walleij of_property_for_each_string(np, "pins", prop, pin) { 147468d41f23SLinus Walleij gpio_name = nmk_find_pin_name(pctldev, pin); 14753a198059SLinus Walleij 1476c2f6d059SLinus Walleij ret = nmk_dt_add_map_configs(map, reserved_maps, 1477c2f6d059SLinus Walleij num_maps, 14783a198059SLinus Walleij gpio_name, &configs, 1); 14793a198059SLinus Walleij if (ret < 0) 14803a198059SLinus Walleij goto exit; 14813a198059SLinus Walleij } 14823a198059SLinus Walleij } 1483c2f6d059SLinus Walleij 14843a198059SLinus Walleij exit: 14853a198059SLinus Walleij return ret; 14863a198059SLinus Walleij } 14873a198059SLinus Walleij 14883a198059SLinus Walleij static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 14893a198059SLinus Walleij struct device_node *np_config, 14903a198059SLinus Walleij struct pinctrl_map **map, unsigned *num_maps) 14913a198059SLinus Walleij { 14923a198059SLinus Walleij unsigned reserved_maps; 14933a198059SLinus Walleij struct device_node *np; 14943a198059SLinus Walleij int ret; 14953a198059SLinus Walleij 14963a198059SLinus Walleij reserved_maps = 0; 14973a198059SLinus Walleij *map = NULL; 14983a198059SLinus Walleij *num_maps = 0; 14993a198059SLinus Walleij 15003a198059SLinus Walleij for_each_child_of_node(np_config, np) { 15013a198059SLinus Walleij ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map, 15023a198059SLinus Walleij &reserved_maps, num_maps); 15033a198059SLinus Walleij if (ret < 0) { 1504d32f7fd3SIrina Tirdea pinctrl_utils_free_map(pctldev, *map, *num_maps); 15053a198059SLinus Walleij return ret; 15063a198059SLinus Walleij } 15073a198059SLinus Walleij } 15083a198059SLinus Walleij 15093a198059SLinus Walleij return 0; 15103a198059SLinus Walleij } 15113a198059SLinus Walleij 15123a198059SLinus Walleij static const struct pinctrl_ops nmk_pinctrl_ops = { 15133a198059SLinus Walleij .get_groups_count = nmk_get_groups_cnt, 15143a198059SLinus Walleij .get_group_name = nmk_get_group_name, 15153a198059SLinus Walleij .get_group_pins = nmk_get_group_pins, 15163a198059SLinus Walleij .pin_dbg_show = nmk_pin_dbg_show, 15173a198059SLinus Walleij .dt_node_to_map = nmk_pinctrl_dt_node_to_map, 1518d32f7fd3SIrina Tirdea .dt_free_map = pinctrl_utils_free_map, 15193a198059SLinus Walleij }; 15203a198059SLinus Walleij 15213a198059SLinus Walleij static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 15223a198059SLinus Walleij { 15233a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 15243a198059SLinus Walleij 15253a198059SLinus Walleij return npct->soc->nfunctions; 15263a198059SLinus Walleij } 15273a198059SLinus Walleij 15283a198059SLinus Walleij static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev, 15293a198059SLinus Walleij unsigned function) 15303a198059SLinus Walleij { 15313a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 15323a198059SLinus Walleij 15333a198059SLinus Walleij return npct->soc->functions[function].name; 15343a198059SLinus Walleij } 15353a198059SLinus Walleij 15363a198059SLinus Walleij static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev, 15373a198059SLinus Walleij unsigned function, 15383a198059SLinus Walleij const char * const **groups, 15393a198059SLinus Walleij unsigned * const num_groups) 15403a198059SLinus Walleij { 15413a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 15423a198059SLinus Walleij 15433a198059SLinus Walleij *groups = npct->soc->functions[function].groups; 15443a198059SLinus Walleij *num_groups = npct->soc->functions[function].ngroups; 15453a198059SLinus Walleij 15463a198059SLinus Walleij return 0; 15473a198059SLinus Walleij } 15483a198059SLinus Walleij 154903e9f0caSLinus Walleij static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned function, 15503a198059SLinus Walleij unsigned group) 15513a198059SLinus Walleij { 15523a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 15533a198059SLinus Walleij const struct nmk_pingroup *g; 15543a198059SLinus Walleij static unsigned int slpm[NUM_BANKS]; 15553a198059SLinus Walleij unsigned long flags = 0; 15563a198059SLinus Walleij bool glitch; 15573a198059SLinus Walleij int ret = -EINVAL; 15583a198059SLinus Walleij int i; 15593a198059SLinus Walleij 15603a198059SLinus Walleij g = &npct->soc->groups[group]; 15613a198059SLinus Walleij 15623a198059SLinus Walleij if (g->altsetting < 0) 15633a198059SLinus Walleij return -EINVAL; 15643a198059SLinus Walleij 15653a198059SLinus Walleij dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins); 15663a198059SLinus Walleij 15673a198059SLinus Walleij /* 15683a198059SLinus Walleij * If we're setting altfunc C by setting both AFSLA and AFSLB to 1, 15693a198059SLinus Walleij * we may pass through an undesired state. In this case we take 15703a198059SLinus Walleij * some extra care. 15713a198059SLinus Walleij * 15723a198059SLinus Walleij * Safe sequence used to switch IOs between GPIO and Alternate-C mode: 15733a198059SLinus Walleij * - Save SLPM registers (since we have a shadow register in the 15743a198059SLinus Walleij * nmk_chip we're using that as backup) 15753a198059SLinus Walleij * - Set SLPM=0 for the IOs you want to switch and others to 1 15763a198059SLinus Walleij * - Configure the GPIO registers for the IOs that are being switched 15773a198059SLinus Walleij * - Set IOFORCE=1 15783a198059SLinus Walleij * - Modify the AFLSA/B registers for the IOs that are being switched 15793a198059SLinus Walleij * - Set IOFORCE=0 15803a198059SLinus Walleij * - Restore SLPM registers 15813a198059SLinus Walleij * - Any spurious wake up event during switch sequence to be ignored 15823a198059SLinus Walleij * and cleared 15833a198059SLinus Walleij * 15843a198059SLinus Walleij * We REALLY need to save ALL slpm registers, because the external 15853a198059SLinus Walleij * IOFORCE will switch *all* ports to their sleepmode setting to as 15863a198059SLinus Walleij * to avoid glitches. (Not just one port!) 15873a198059SLinus Walleij */ 15883a198059SLinus Walleij glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C); 15893a198059SLinus Walleij 15903a198059SLinus Walleij if (glitch) { 15913a198059SLinus Walleij spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 15923a198059SLinus Walleij 15933a198059SLinus Walleij /* Initially don't put any pins to sleep when switching */ 15943a198059SLinus Walleij memset(slpm, 0xff, sizeof(slpm)); 15953a198059SLinus Walleij 15963a198059SLinus Walleij /* 15973a198059SLinus Walleij * Then mask the pins that need to be sleeping now when we're 15983a198059SLinus Walleij * switching to the ALT C function. 15993a198059SLinus Walleij */ 16003a198059SLinus Walleij for (i = 0; i < g->npins; i++) 16013a198059SLinus Walleij slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]); 16023a198059SLinus Walleij nmk_gpio_glitch_slpm_init(slpm); 16033a198059SLinus Walleij } 16043a198059SLinus Walleij 16053a198059SLinus Walleij for (i = 0; i < g->npins; i++) { 16063a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip; 16073a198059SLinus Walleij unsigned bit; 16083a198059SLinus Walleij 16096ca7d2e3SLinus Walleij nmk_chip = find_nmk_gpio_from_pin(g->pins[i]); 16106ca7d2e3SLinus Walleij if (!nmk_chip) { 16113a198059SLinus Walleij dev_err(npct->dev, 16123a198059SLinus Walleij "invalid pin offset %d in group %s at index %d\n", 16133a198059SLinus Walleij g->pins[i], g->name, i); 16143a198059SLinus Walleij goto out_glitch; 16153a198059SLinus Walleij } 16163a198059SLinus Walleij dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting); 16173a198059SLinus Walleij 16183a198059SLinus Walleij clk_enable(nmk_chip->clk); 16193a198059SLinus Walleij bit = g->pins[i] % NMK_GPIO_PER_CHIP; 16203a198059SLinus Walleij /* 16213a198059SLinus Walleij * If the pin is switching to altfunc, and there was an 16223a198059SLinus Walleij * interrupt installed on it which has been lazy disabled, 16233a198059SLinus Walleij * actually mask the interrupt to prevent spurious interrupts 16243a198059SLinus Walleij * that would occur while the pin is under control of the 16253a198059SLinus Walleij * peripheral. Only SKE does this. 16263a198059SLinus Walleij */ 16273a198059SLinus Walleij nmk_gpio_disable_lazy_irq(nmk_chip, bit); 16283a198059SLinus Walleij 16293a198059SLinus Walleij __nmk_gpio_set_mode_safe(nmk_chip, bit, 16303a198059SLinus Walleij (g->altsetting & NMK_GPIO_ALT_C), glitch); 16313a198059SLinus Walleij clk_disable(nmk_chip->clk); 16323a198059SLinus Walleij 16333a198059SLinus Walleij /* 16343a198059SLinus Walleij * Call PRCM GPIOCR config function in case ALTC 16353a198059SLinus Walleij * has been selected: 16363a198059SLinus Walleij * - If selection is a ALTCx, some bits in PRCM GPIOCR registers 16373a198059SLinus Walleij * must be set. 16383a198059SLinus Walleij * - If selection is pure ALTC and previous selection was ALTCx, 16393a198059SLinus Walleij * then some bits in PRCM GPIOCR registers must be cleared. 16403a198059SLinus Walleij */ 16413a198059SLinus Walleij if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C) 16423a198059SLinus Walleij nmk_prcm_altcx_set_mode(npct, g->pins[i], 16433a198059SLinus Walleij g->altsetting >> NMK_GPIO_ALT_CX_SHIFT); 16443a198059SLinus Walleij } 16453a198059SLinus Walleij 16463a198059SLinus Walleij /* When all pins are successfully reconfigured we get here */ 16473a198059SLinus Walleij ret = 0; 16483a198059SLinus Walleij 16493a198059SLinus Walleij out_glitch: 16503a198059SLinus Walleij if (glitch) { 16513a198059SLinus Walleij nmk_gpio_glitch_slpm_restore(slpm); 16523a198059SLinus Walleij spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 16533a198059SLinus Walleij } 16543a198059SLinus Walleij 16553a198059SLinus Walleij return ret; 16563a198059SLinus Walleij } 16573a198059SLinus Walleij 16583a198059SLinus Walleij static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev, 16593a198059SLinus Walleij struct pinctrl_gpio_range *range, 16603a198059SLinus Walleij unsigned offset) 16613a198059SLinus Walleij { 16623a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 16633a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip; 16643a198059SLinus Walleij struct gpio_chip *chip; 16653a198059SLinus Walleij unsigned bit; 16663a198059SLinus Walleij 16673a198059SLinus Walleij if (!range) { 16683a198059SLinus Walleij dev_err(npct->dev, "invalid range\n"); 16693a198059SLinus Walleij return -EINVAL; 16703a198059SLinus Walleij } 16713a198059SLinus Walleij if (!range->gc) { 16723a198059SLinus Walleij dev_err(npct->dev, "missing GPIO chip in range\n"); 16733a198059SLinus Walleij return -EINVAL; 16743a198059SLinus Walleij } 16753a198059SLinus Walleij chip = range->gc; 167668ab0126SLinus Walleij nmk_chip = gpiochip_get_data(chip); 16773a198059SLinus Walleij 16783a198059SLinus Walleij dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); 16793a198059SLinus Walleij 16803a198059SLinus Walleij clk_enable(nmk_chip->clk); 16813a198059SLinus Walleij bit = offset % NMK_GPIO_PER_CHIP; 16823a198059SLinus Walleij /* There is no glitch when converting any pin to GPIO */ 16833a198059SLinus Walleij __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); 16843a198059SLinus Walleij clk_disable(nmk_chip->clk); 16853a198059SLinus Walleij 16863a198059SLinus Walleij return 0; 16873a198059SLinus Walleij } 16883a198059SLinus Walleij 16893a198059SLinus Walleij static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev, 16903a198059SLinus Walleij struct pinctrl_gpio_range *range, 16913a198059SLinus Walleij unsigned offset) 16923a198059SLinus Walleij { 16933a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 16943a198059SLinus Walleij 16953a198059SLinus Walleij dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); 16963a198059SLinus Walleij /* Set the pin to some default state, GPIO is usually default */ 16973a198059SLinus Walleij } 16983a198059SLinus Walleij 16993a198059SLinus Walleij static const struct pinmux_ops nmk_pinmux_ops = { 17003a198059SLinus Walleij .get_functions_count = nmk_pmx_get_funcs_cnt, 17013a198059SLinus Walleij .get_function_name = nmk_pmx_get_func_name, 17023a198059SLinus Walleij .get_function_groups = nmk_pmx_get_func_groups, 170303e9f0caSLinus Walleij .set_mux = nmk_pmx_set, 17043a198059SLinus Walleij .gpio_request_enable = nmk_gpio_request_enable, 17053a198059SLinus Walleij .gpio_disable_free = nmk_gpio_disable_free, 1706a21763a0SLinus Walleij .strict = true, 17073a198059SLinus Walleij }; 17083a198059SLinus Walleij 17093a198059SLinus Walleij static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, 17103a198059SLinus Walleij unsigned long *config) 17113a198059SLinus Walleij { 17123a198059SLinus Walleij /* Not implemented */ 17133a198059SLinus Walleij return -EINVAL; 17143a198059SLinus Walleij } 17153a198059SLinus Walleij 17163a198059SLinus Walleij static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, 17173a198059SLinus Walleij unsigned long *configs, unsigned num_configs) 17183a198059SLinus Walleij { 17193a198059SLinus Walleij static const char *pullnames[] = { 17203a198059SLinus Walleij [NMK_GPIO_PULL_NONE] = "none", 17213a198059SLinus Walleij [NMK_GPIO_PULL_UP] = "up", 17223a198059SLinus Walleij [NMK_GPIO_PULL_DOWN] = "down", 17233a198059SLinus Walleij [3] /* illegal */ = "??" 17243a198059SLinus Walleij }; 17253a198059SLinus Walleij static const char *slpmnames[] = { 17263a198059SLinus Walleij [NMK_GPIO_SLPM_INPUT] = "input/wakeup", 17273a198059SLinus Walleij [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", 17283a198059SLinus Walleij }; 17293a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 17303a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip; 17313a198059SLinus Walleij unsigned bit; 17323a198059SLinus Walleij pin_cfg_t cfg; 17333a198059SLinus Walleij int pull, slpm, output, val, i; 17343a198059SLinus Walleij bool lowemi, gpiomode, sleep; 17353a198059SLinus Walleij 17366ca7d2e3SLinus Walleij nmk_chip = find_nmk_gpio_from_pin(pin); 17376ca7d2e3SLinus Walleij if (!nmk_chip) { 17386ca7d2e3SLinus Walleij dev_err(npct->dev, 17396ca7d2e3SLinus Walleij "invalid pin offset %d\n", pin); 17403a198059SLinus Walleij return -EINVAL; 17413a198059SLinus Walleij } 17423a198059SLinus Walleij 17433a198059SLinus Walleij for (i = 0; i < num_configs; i++) { 17443a198059SLinus Walleij /* 17453a198059SLinus Walleij * The pin config contains pin number and altfunction fields, 17463a198059SLinus Walleij * here we just ignore that part. It's being handled by the 17473a198059SLinus Walleij * framework and pinmux callback respectively. 17483a198059SLinus Walleij */ 17493a198059SLinus Walleij cfg = (pin_cfg_t) configs[i]; 17503a198059SLinus Walleij pull = PIN_PULL(cfg); 17513a198059SLinus Walleij slpm = PIN_SLPM(cfg); 17523a198059SLinus Walleij output = PIN_DIR(cfg); 17533a198059SLinus Walleij val = PIN_VAL(cfg); 17543a198059SLinus Walleij lowemi = PIN_LOWEMI(cfg); 17553a198059SLinus Walleij gpiomode = PIN_GPIOMODE(cfg); 17563a198059SLinus Walleij sleep = PIN_SLEEPMODE(cfg); 17573a198059SLinus Walleij 17583a198059SLinus Walleij if (sleep) { 17593a198059SLinus Walleij int slpm_pull = PIN_SLPM_PULL(cfg); 17603a198059SLinus Walleij int slpm_output = PIN_SLPM_DIR(cfg); 17613a198059SLinus Walleij int slpm_val = PIN_SLPM_VAL(cfg); 17623a198059SLinus Walleij 17633a198059SLinus Walleij /* All pins go into GPIO mode at sleep */ 17643a198059SLinus Walleij gpiomode = true; 17653a198059SLinus Walleij 17663a198059SLinus Walleij /* 17673a198059SLinus Walleij * The SLPM_* values are normal values + 1 to allow zero 17683a198059SLinus Walleij * to mean "same as normal". 17693a198059SLinus Walleij */ 17703a198059SLinus Walleij if (slpm_pull) 17713a198059SLinus Walleij pull = slpm_pull - 1; 17723a198059SLinus Walleij if (slpm_output) 17733a198059SLinus Walleij output = slpm_output - 1; 17743a198059SLinus Walleij if (slpm_val) 17753a198059SLinus Walleij val = slpm_val - 1; 17763a198059SLinus Walleij 177758383c78SLinus Walleij dev_dbg(nmk_chip->chip.parent, 17783a198059SLinus Walleij "pin %d: sleep pull %s, dir %s, val %s\n", 17793a198059SLinus Walleij pin, 17803a198059SLinus Walleij slpm_pull ? pullnames[pull] : "same", 17813a198059SLinus Walleij slpm_output ? (output ? "output" : "input") 17823a198059SLinus Walleij : "same", 17833a198059SLinus Walleij slpm_val ? (val ? "high" : "low") : "same"); 17843a198059SLinus Walleij } 17853a198059SLinus Walleij 178658383c78SLinus Walleij dev_dbg(nmk_chip->chip.parent, 17873a198059SLinus Walleij "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n", 17883a198059SLinus Walleij pin, cfg, pullnames[pull], slpmnames[slpm], 17893a198059SLinus Walleij output ? "output " : "input", 17903a198059SLinus Walleij output ? (val ? "high" : "low") : "", 17913a198059SLinus Walleij lowemi ? "on" : "off"); 17923a198059SLinus Walleij 17933a198059SLinus Walleij clk_enable(nmk_chip->clk); 17943a198059SLinus Walleij bit = pin % NMK_GPIO_PER_CHIP; 17953a198059SLinus Walleij if (gpiomode) 17963a198059SLinus Walleij /* No glitch when going to GPIO mode */ 17973a198059SLinus Walleij __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); 17983a198059SLinus Walleij if (output) 17993a198059SLinus Walleij __nmk_gpio_make_output(nmk_chip, bit, val); 18003a198059SLinus Walleij else { 18013a198059SLinus Walleij __nmk_gpio_make_input(nmk_chip, bit); 18023a198059SLinus Walleij __nmk_gpio_set_pull(nmk_chip, bit, pull); 18033a198059SLinus Walleij } 18043a198059SLinus Walleij /* TODO: isn't this only applicable on output pins? */ 18053a198059SLinus Walleij __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi); 18063a198059SLinus Walleij 18073a198059SLinus Walleij __nmk_gpio_set_slpm(nmk_chip, bit, slpm); 18083a198059SLinus Walleij clk_disable(nmk_chip->clk); 18093a198059SLinus Walleij } /* for each config */ 18103a198059SLinus Walleij 18113a198059SLinus Walleij return 0; 18123a198059SLinus Walleij } 18133a198059SLinus Walleij 18143a198059SLinus Walleij static const struct pinconf_ops nmk_pinconf_ops = { 18153a198059SLinus Walleij .pin_config_get = nmk_pin_config_get, 18163a198059SLinus Walleij .pin_config_set = nmk_pin_config_set, 18173a198059SLinus Walleij }; 18183a198059SLinus Walleij 18193a198059SLinus Walleij static struct pinctrl_desc nmk_pinctrl_desc = { 18203a198059SLinus Walleij .name = "pinctrl-nomadik", 18213a198059SLinus Walleij .pctlops = &nmk_pinctrl_ops, 18223a198059SLinus Walleij .pmxops = &nmk_pinmux_ops, 18233a198059SLinus Walleij .confops = &nmk_pinconf_ops, 18243a198059SLinus Walleij .owner = THIS_MODULE, 18253a198059SLinus Walleij }; 18263a198059SLinus Walleij 18273a198059SLinus Walleij static const struct of_device_id nmk_pinctrl_match[] = { 18283a198059SLinus Walleij { 18293a198059SLinus Walleij .compatible = "stericsson,stn8815-pinctrl", 18303a198059SLinus Walleij .data = (void *)PINCTRL_NMK_STN8815, 18313a198059SLinus Walleij }, 18323a198059SLinus Walleij { 18333a198059SLinus Walleij .compatible = "stericsson,db8500-pinctrl", 18343a198059SLinus Walleij .data = (void *)PINCTRL_NMK_DB8500, 18353a198059SLinus Walleij }, 18363a198059SLinus Walleij { 18373a198059SLinus Walleij .compatible = "stericsson,db8540-pinctrl", 18383a198059SLinus Walleij .data = (void *)PINCTRL_NMK_DB8540, 18393a198059SLinus Walleij }, 18403a198059SLinus Walleij {}, 18413a198059SLinus Walleij }; 18423a198059SLinus Walleij 18433a198059SLinus Walleij #ifdef CONFIG_PM_SLEEP 18443a198059SLinus Walleij static int nmk_pinctrl_suspend(struct device *dev) 18453a198059SLinus Walleij { 18463a198059SLinus Walleij struct nmk_pinctrl *npct; 18473a198059SLinus Walleij 18483a198059SLinus Walleij npct = dev_get_drvdata(dev); 18493a198059SLinus Walleij if (!npct) 18503a198059SLinus Walleij return -EINVAL; 18513a198059SLinus Walleij 18523a198059SLinus Walleij return pinctrl_force_sleep(npct->pctl); 18533a198059SLinus Walleij } 18543a198059SLinus Walleij 18553a198059SLinus Walleij static int nmk_pinctrl_resume(struct device *dev) 18563a198059SLinus Walleij { 18573a198059SLinus Walleij struct nmk_pinctrl *npct; 18583a198059SLinus Walleij 18593a198059SLinus Walleij npct = dev_get_drvdata(dev); 18603a198059SLinus Walleij if (!npct) 18613a198059SLinus Walleij return -EINVAL; 18623a198059SLinus Walleij 18633a198059SLinus Walleij return pinctrl_force_default(npct->pctl); 18643a198059SLinus Walleij } 18653a198059SLinus Walleij #endif 18663a198059SLinus Walleij 18673a198059SLinus Walleij static int nmk_pinctrl_probe(struct platform_device *pdev) 18683a198059SLinus Walleij { 18693a198059SLinus Walleij const struct of_device_id *match; 18703a198059SLinus Walleij struct device_node *np = pdev->dev.of_node; 18713a198059SLinus Walleij struct device_node *prcm_np; 18723a198059SLinus Walleij struct nmk_pinctrl *npct; 18733a198059SLinus Walleij unsigned int version = 0; 18743a198059SLinus Walleij int i; 18753a198059SLinus Walleij 18763a198059SLinus Walleij npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL); 18773a198059SLinus Walleij if (!npct) 18783a198059SLinus Walleij return -ENOMEM; 18793a198059SLinus Walleij 18803a198059SLinus Walleij match = of_match_device(nmk_pinctrl_match, &pdev->dev); 18813a198059SLinus Walleij if (!match) 18823a198059SLinus Walleij return -ENODEV; 18833a198059SLinus Walleij version = (unsigned int) match->data; 18843a198059SLinus Walleij 18853a198059SLinus Walleij /* Poke in other ASIC variants here */ 18863a198059SLinus Walleij if (version == PINCTRL_NMK_STN8815) 18873a198059SLinus Walleij nmk_pinctrl_stn8815_init(&npct->soc); 18883a198059SLinus Walleij if (version == PINCTRL_NMK_DB8500) 18893a198059SLinus Walleij nmk_pinctrl_db8500_init(&npct->soc); 18903a198059SLinus Walleij if (version == PINCTRL_NMK_DB8540) 18913a198059SLinus Walleij nmk_pinctrl_db8540_init(&npct->soc); 18923a198059SLinus Walleij 1893ab4a9362SLinus Walleij /* 1894ab4a9362SLinus Walleij * Since we depend on the GPIO chips to provide clock and register base 1895ab4a9362SLinus Walleij * for the pin control operations, make sure that we have these 1896ab4a9362SLinus Walleij * populated before we continue. Follow the phandles to instantiate 1897ab4a9362SLinus Walleij * them. The GPIO portion of the actual hardware may be probed before 1898ab4a9362SLinus Walleij * or after this point: it shouldn't matter as the APIs are orthogonal. 1899ab4a9362SLinus Walleij */ 1900ab4a9362SLinus Walleij for (i = 0; i < NMK_MAX_BANKS; i++) { 1901ab4a9362SLinus Walleij struct device_node *gpio_np; 1902ab4a9362SLinus Walleij struct nmk_gpio_chip *nmk_chip; 1903ab4a9362SLinus Walleij 1904ab4a9362SLinus Walleij gpio_np = of_parse_phandle(np, "nomadik-gpio-chips", i); 1905ab4a9362SLinus Walleij if (gpio_np) { 1906ab4a9362SLinus Walleij dev_info(&pdev->dev, 1907ab4a9362SLinus Walleij "populate NMK GPIO %d \"%s\"\n", 1908ab4a9362SLinus Walleij i, gpio_np->name); 1909ab4a9362SLinus Walleij nmk_chip = nmk_gpio_populate_chip(gpio_np, pdev); 1910ab4a9362SLinus Walleij if (IS_ERR(nmk_chip)) 1911ab4a9362SLinus Walleij dev_err(&pdev->dev, 1912ab4a9362SLinus Walleij "could not populate nmk chip struct " 1913ab4a9362SLinus Walleij "- continue anyway\n"); 1914ab4a9362SLinus Walleij of_node_put(gpio_np); 1915ab4a9362SLinus Walleij } 1916ab4a9362SLinus Walleij } 1917ab4a9362SLinus Walleij 19183a198059SLinus Walleij prcm_np = of_parse_phandle(np, "prcm", 0); 19193a198059SLinus Walleij if (prcm_np) 19203a198059SLinus Walleij npct->prcm_base = of_iomap(prcm_np, 0); 19213a198059SLinus Walleij if (!npct->prcm_base) { 19223a198059SLinus Walleij if (version == PINCTRL_NMK_STN8815) { 19233a198059SLinus Walleij dev_info(&pdev->dev, 19243a198059SLinus Walleij "No PRCM base, " 19253a198059SLinus Walleij "assuming no ALT-Cx control is available\n"); 19263a198059SLinus Walleij } else { 19273a198059SLinus Walleij dev_err(&pdev->dev, "missing PRCM base address\n"); 19283a198059SLinus Walleij return -EINVAL; 19293a198059SLinus Walleij } 19303a198059SLinus Walleij } 19313a198059SLinus Walleij 19323a198059SLinus Walleij nmk_pinctrl_desc.pins = npct->soc->pins; 19333a198059SLinus Walleij nmk_pinctrl_desc.npins = npct->soc->npins; 19343a198059SLinus Walleij npct->dev = &pdev->dev; 19353a198059SLinus Walleij 19360ee60110SLaxman Dewangan npct->pctl = devm_pinctrl_register(&pdev->dev, &nmk_pinctrl_desc, npct); 1937323de9efSMasahiro Yamada if (IS_ERR(npct->pctl)) { 19383a198059SLinus Walleij dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n"); 1939323de9efSMasahiro Yamada return PTR_ERR(npct->pctl); 19403a198059SLinus Walleij } 19413a198059SLinus Walleij 19423a198059SLinus Walleij platform_set_drvdata(pdev, npct); 19433a198059SLinus Walleij dev_info(&pdev->dev, "initialized Nomadik pin control driver\n"); 19443a198059SLinus Walleij 19453a198059SLinus Walleij return 0; 19463a198059SLinus Walleij } 19473a198059SLinus Walleij 19483a198059SLinus Walleij static const struct of_device_id nmk_gpio_match[] = { 19493a198059SLinus Walleij { .compatible = "st,nomadik-gpio", }, 19503a198059SLinus Walleij {} 19513a198059SLinus Walleij }; 19523a198059SLinus Walleij 19533a198059SLinus Walleij static struct platform_driver nmk_gpio_driver = { 19543a198059SLinus Walleij .driver = { 19553a198059SLinus Walleij .name = "gpio", 19563a198059SLinus Walleij .of_match_table = nmk_gpio_match, 19573a198059SLinus Walleij }, 19583a198059SLinus Walleij .probe = nmk_gpio_probe, 19593a198059SLinus Walleij }; 19603a198059SLinus Walleij 19613a198059SLinus Walleij static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops, 19623a198059SLinus Walleij nmk_pinctrl_suspend, 19633a198059SLinus Walleij nmk_pinctrl_resume); 19643a198059SLinus Walleij 19653a198059SLinus Walleij static struct platform_driver nmk_pinctrl_driver = { 19663a198059SLinus Walleij .driver = { 19673a198059SLinus Walleij .name = "pinctrl-nomadik", 19683a198059SLinus Walleij .of_match_table = nmk_pinctrl_match, 19693a198059SLinus Walleij .pm = &nmk_pinctrl_pm_ops, 19703a198059SLinus Walleij }, 19713a198059SLinus Walleij .probe = nmk_pinctrl_probe, 19723a198059SLinus Walleij }; 19733a198059SLinus Walleij 19743a198059SLinus Walleij static int __init nmk_gpio_init(void) 19753a198059SLinus Walleij { 1976802bb9b6SLinus Walleij return platform_driver_register(&nmk_gpio_driver); 1977802bb9b6SLinus Walleij } 1978802bb9b6SLinus Walleij subsys_initcall(nmk_gpio_init); 19793a198059SLinus Walleij 1980802bb9b6SLinus Walleij static int __init nmk_pinctrl_init(void) 1981802bb9b6SLinus Walleij { 19823a198059SLinus Walleij return platform_driver_register(&nmk_pinctrl_driver); 19833a198059SLinus Walleij } 1984802bb9b6SLinus Walleij core_initcall(nmk_pinctrl_init); 1985