13a198059SLinus Walleij /* 23a198059SLinus Walleij * Generic GPIO driver for logic cells found in the Nomadik SoC 33a198059SLinus Walleij * 43a198059SLinus Walleij * Copyright (C) 2008,2009 STMicroelectronics 53a198059SLinus Walleij * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> 63a198059SLinus Walleij * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> 73a198059SLinus Walleij * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org> 83a198059SLinus Walleij * 93a198059SLinus Walleij * This program is free software; you can redistribute it and/or modify 103a198059SLinus Walleij * it under the terms of the GNU General Public License version 2 as 113a198059SLinus Walleij * published by the Free Software Foundation. 123a198059SLinus Walleij */ 133a198059SLinus Walleij #include <linux/kernel.h> 143a198059SLinus Walleij #include <linux/module.h> 153a198059SLinus Walleij #include <linux/init.h> 163a198059SLinus Walleij #include <linux/device.h> 173a198059SLinus Walleij #include <linux/platform_device.h> 183a198059SLinus Walleij #include <linux/io.h> 193a198059SLinus Walleij #include <linux/clk.h> 203a198059SLinus Walleij #include <linux/err.h> 213a198059SLinus Walleij #include <linux/gpio.h> 223a198059SLinus Walleij #include <linux/spinlock.h> 233a198059SLinus Walleij #include <linux/interrupt.h> 243a198059SLinus Walleij #include <linux/slab.h> 253a198059SLinus Walleij #include <linux/of_device.h> 263a198059SLinus Walleij #include <linux/of_address.h> 273a198059SLinus Walleij #include <linux/pinctrl/machine.h> 283a198059SLinus Walleij #include <linux/pinctrl/pinctrl.h> 293a198059SLinus Walleij #include <linux/pinctrl/pinmux.h> 303a198059SLinus Walleij #include <linux/pinctrl/pinconf.h> 313a198059SLinus Walleij /* Since we request GPIOs from ourself */ 323a198059SLinus Walleij #include <linux/pinctrl/consumer.h> 333a198059SLinus Walleij #include "pinctrl-nomadik.h" 343a198059SLinus Walleij #include "../core.h" 35ba388294SLinus Walleij #include "../pinctrl-utils.h" 363a198059SLinus Walleij 373a198059SLinus Walleij /* 383a198059SLinus Walleij * The GPIO module in the Nomadik family of Systems-on-Chip is an 393a198059SLinus Walleij * AMBA device, managing 32 pins and alternate functions. The logic block 403a198059SLinus Walleij * is currently used in the Nomadik and ux500. 413a198059SLinus Walleij * 423a198059SLinus Walleij * Symbols in this file are called "nmk_gpio" for "nomadik gpio" 433a198059SLinus Walleij */ 443a198059SLinus Walleij 453a198059SLinus Walleij /* 463a198059SLinus Walleij * pin configurations are represented by 32-bit integers: 473a198059SLinus Walleij * 483a198059SLinus Walleij * bit 0.. 8 - Pin Number (512 Pins Maximum) 493a198059SLinus Walleij * bit 9..10 - Alternate Function Selection 503a198059SLinus Walleij * bit 11..12 - Pull up/down state 513a198059SLinus Walleij * bit 13 - Sleep mode behaviour 523a198059SLinus Walleij * bit 14 - Direction 533a198059SLinus Walleij * bit 15 - Value (if output) 543a198059SLinus Walleij * bit 16..18 - SLPM pull up/down state 553a198059SLinus Walleij * bit 19..20 - SLPM direction 563a198059SLinus Walleij * bit 21..22 - SLPM Value (if output) 573a198059SLinus Walleij * bit 23..25 - PDIS value (if input) 583a198059SLinus Walleij * bit 26 - Gpio mode 593a198059SLinus Walleij * bit 27 - Sleep mode 603a198059SLinus Walleij * 613a198059SLinus Walleij * to facilitate the definition, the following macros are provided 623a198059SLinus Walleij * 633a198059SLinus Walleij * PIN_CFG_DEFAULT - default config (0): 643a198059SLinus Walleij * pull up/down = disabled 653a198059SLinus Walleij * sleep mode = input/wakeup 663a198059SLinus Walleij * direction = input 673a198059SLinus Walleij * value = low 683a198059SLinus Walleij * SLPM direction = same as normal 693a198059SLinus Walleij * SLPM pull = same as normal 703a198059SLinus Walleij * SLPM value = same as normal 713a198059SLinus Walleij * 723a198059SLinus Walleij * PIN_CFG - default config with alternate function 733a198059SLinus Walleij */ 743a198059SLinus Walleij 753a198059SLinus Walleij typedef unsigned long pin_cfg_t; 763a198059SLinus Walleij 773a198059SLinus Walleij #define PIN_NUM_MASK 0x1ff 783a198059SLinus Walleij #define PIN_NUM(x) ((x) & PIN_NUM_MASK) 793a198059SLinus Walleij 803a198059SLinus Walleij #define PIN_ALT_SHIFT 9 813a198059SLinus Walleij #define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT) 823a198059SLinus Walleij #define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT) 833a198059SLinus Walleij #define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT) 843a198059SLinus Walleij #define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT) 853a198059SLinus Walleij #define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT) 863a198059SLinus Walleij #define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT) 873a198059SLinus Walleij 883a198059SLinus Walleij #define PIN_PULL_SHIFT 11 893a198059SLinus Walleij #define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT) 903a198059SLinus Walleij #define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT) 913a198059SLinus Walleij #define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT) 923a198059SLinus Walleij #define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT) 933a198059SLinus Walleij #define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT) 943a198059SLinus Walleij 953a198059SLinus Walleij #define PIN_SLPM_SHIFT 13 963a198059SLinus Walleij #define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT) 973a198059SLinus Walleij #define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT) 983a198059SLinus Walleij #define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT) 993a198059SLinus Walleij #define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT) 1003a198059SLinus Walleij /* These two replace the above in DB8500v2+ */ 1013a198059SLinus Walleij #define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT) 1023a198059SLinus Walleij #define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT) 1033a198059SLinus Walleij #define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE 1043a198059SLinus Walleij 1053a198059SLinus Walleij #define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */ 1063a198059SLinus Walleij #define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */ 1073a198059SLinus Walleij 1083a198059SLinus Walleij #define PIN_DIR_SHIFT 14 1093a198059SLinus Walleij #define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT) 1103a198059SLinus Walleij #define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT) 1113a198059SLinus Walleij #define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT) 1123a198059SLinus Walleij #define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT) 1133a198059SLinus Walleij 1143a198059SLinus Walleij #define PIN_VAL_SHIFT 15 1153a198059SLinus Walleij #define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT) 1163a198059SLinus Walleij #define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT) 1173a198059SLinus Walleij #define PIN_VAL_LOW (0 << PIN_VAL_SHIFT) 1183a198059SLinus Walleij #define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT) 1193a198059SLinus Walleij 1203a198059SLinus Walleij #define PIN_SLPM_PULL_SHIFT 16 1213a198059SLinus Walleij #define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT) 1223a198059SLinus Walleij #define PIN_SLPM_PULL(x) \ 1233a198059SLinus Walleij (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT) 1243a198059SLinus Walleij #define PIN_SLPM_PULL_NONE \ 1253a198059SLinus Walleij ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT) 1263a198059SLinus Walleij #define PIN_SLPM_PULL_UP \ 1273a198059SLinus Walleij ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT) 1283a198059SLinus Walleij #define PIN_SLPM_PULL_DOWN \ 1293a198059SLinus Walleij ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT) 1303a198059SLinus Walleij 1313a198059SLinus Walleij #define PIN_SLPM_DIR_SHIFT 19 1323a198059SLinus Walleij #define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT) 1333a198059SLinus Walleij #define PIN_SLPM_DIR(x) \ 1343a198059SLinus Walleij (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT) 1353a198059SLinus Walleij #define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT) 1363a198059SLinus Walleij #define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT) 1373a198059SLinus Walleij 1383a198059SLinus Walleij #define PIN_SLPM_VAL_SHIFT 21 1393a198059SLinus Walleij #define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT) 1403a198059SLinus Walleij #define PIN_SLPM_VAL(x) \ 1413a198059SLinus Walleij (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT) 1423a198059SLinus Walleij #define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT) 1433a198059SLinus Walleij #define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT) 1443a198059SLinus Walleij 1453a198059SLinus Walleij #define PIN_SLPM_PDIS_SHIFT 23 1463a198059SLinus Walleij #define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT) 1473a198059SLinus Walleij #define PIN_SLPM_PDIS(x) \ 1483a198059SLinus Walleij (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT) 1493a198059SLinus Walleij #define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT) 1503a198059SLinus Walleij #define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT) 1513a198059SLinus Walleij #define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT) 1523a198059SLinus Walleij 1533a198059SLinus Walleij #define PIN_LOWEMI_SHIFT 25 1543a198059SLinus Walleij #define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT) 1553a198059SLinus Walleij #define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT) 1563a198059SLinus Walleij #define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT) 1573a198059SLinus Walleij #define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT) 1583a198059SLinus Walleij 1593a198059SLinus Walleij #define PIN_GPIOMODE_SHIFT 26 1603a198059SLinus Walleij #define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT) 1613a198059SLinus Walleij #define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT) 1623a198059SLinus Walleij #define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT) 1633a198059SLinus Walleij #define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT) 1643a198059SLinus Walleij 1653a198059SLinus Walleij #define PIN_SLEEPMODE_SHIFT 27 1663a198059SLinus Walleij #define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT) 1673a198059SLinus Walleij #define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT) 1683a198059SLinus Walleij #define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT) 1693a198059SLinus Walleij #define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT) 1703a198059SLinus Walleij 1713a198059SLinus Walleij 1723a198059SLinus Walleij /* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */ 1733a198059SLinus Walleij #define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN) 1743a198059SLinus Walleij #define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP) 1753a198059SLinus Walleij #define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE) 1763a198059SLinus Walleij #define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW) 1773a198059SLinus Walleij #define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH) 1783a198059SLinus Walleij 1793a198059SLinus Walleij #define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN) 1803a198059SLinus Walleij #define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP) 1813a198059SLinus Walleij #define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE) 1823a198059SLinus Walleij #define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW) 1833a198059SLinus Walleij #define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH) 1843a198059SLinus Walleij 1853a198059SLinus Walleij #define PIN_CFG_DEFAULT (0) 1863a198059SLinus Walleij 1873a198059SLinus Walleij #define PIN_CFG(num, alt) \ 1883a198059SLinus Walleij (PIN_CFG_DEFAULT |\ 1893a198059SLinus Walleij (PIN_NUM(num) | PIN_##alt)) 1903a198059SLinus Walleij 1913a198059SLinus Walleij #define PIN_CFG_INPUT(num, alt, pull) \ 1923a198059SLinus Walleij (PIN_CFG_DEFAULT |\ 1933a198059SLinus Walleij (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull)) 1943a198059SLinus Walleij 1953a198059SLinus Walleij #define PIN_CFG_OUTPUT(num, alt, val) \ 1963a198059SLinus Walleij (PIN_CFG_DEFAULT |\ 1973a198059SLinus Walleij (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val)) 1983a198059SLinus Walleij 1993a198059SLinus Walleij /* 2003a198059SLinus Walleij * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving 2013a198059SLinus Walleij * the "gpio" namespace for generic and cross-machine functions 2023a198059SLinus Walleij */ 2033a198059SLinus Walleij 2043a198059SLinus Walleij #define GPIO_BLOCK_SHIFT 5 2053a198059SLinus Walleij #define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT) 206bc222ef4SLinus Walleij #define NMK_MAX_BANKS DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP) 2073a198059SLinus Walleij 2083a198059SLinus Walleij /* Register in the logic block */ 2093a198059SLinus Walleij #define NMK_GPIO_DAT 0x00 2103a198059SLinus Walleij #define NMK_GPIO_DATS 0x04 2113a198059SLinus Walleij #define NMK_GPIO_DATC 0x08 2123a198059SLinus Walleij #define NMK_GPIO_PDIS 0x0c 2133a198059SLinus Walleij #define NMK_GPIO_DIR 0x10 2143a198059SLinus Walleij #define NMK_GPIO_DIRS 0x14 2153a198059SLinus Walleij #define NMK_GPIO_DIRC 0x18 2163a198059SLinus Walleij #define NMK_GPIO_SLPC 0x1c 2173a198059SLinus Walleij #define NMK_GPIO_AFSLA 0x20 2183a198059SLinus Walleij #define NMK_GPIO_AFSLB 0x24 2193a198059SLinus Walleij #define NMK_GPIO_LOWEMI 0x28 2203a198059SLinus Walleij 2213a198059SLinus Walleij #define NMK_GPIO_RIMSC 0x40 2223a198059SLinus Walleij #define NMK_GPIO_FIMSC 0x44 2233a198059SLinus Walleij #define NMK_GPIO_IS 0x48 2243a198059SLinus Walleij #define NMK_GPIO_IC 0x4c 2253a198059SLinus Walleij #define NMK_GPIO_RWIMSC 0x50 2263a198059SLinus Walleij #define NMK_GPIO_FWIMSC 0x54 2273a198059SLinus Walleij #define NMK_GPIO_WKS 0x58 2283a198059SLinus Walleij /* These appear in DB8540 and later ASICs */ 2293a198059SLinus Walleij #define NMK_GPIO_EDGELEVEL 0x5C 2303a198059SLinus Walleij #define NMK_GPIO_LEVEL 0x60 2313a198059SLinus Walleij 2323a198059SLinus Walleij 2333a198059SLinus Walleij /* Pull up/down values */ 2343a198059SLinus Walleij enum nmk_gpio_pull { 2353a198059SLinus Walleij NMK_GPIO_PULL_NONE, 2363a198059SLinus Walleij NMK_GPIO_PULL_UP, 2373a198059SLinus Walleij NMK_GPIO_PULL_DOWN, 2383a198059SLinus Walleij }; 2393a198059SLinus Walleij 2403a198059SLinus Walleij /* Sleep mode */ 2413a198059SLinus Walleij enum nmk_gpio_slpm { 2423a198059SLinus Walleij NMK_GPIO_SLPM_INPUT, 2433a198059SLinus Walleij NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT, 2443a198059SLinus Walleij NMK_GPIO_SLPM_NOCHANGE, 2453a198059SLinus Walleij NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE, 2463a198059SLinus Walleij }; 2473a198059SLinus Walleij 2483a198059SLinus Walleij struct nmk_gpio_chip { 2493a198059SLinus Walleij struct gpio_chip chip; 2503007d941SLinus Walleij struct irq_chip irqchip; 2513a198059SLinus Walleij void __iomem *addr; 2523a198059SLinus Walleij struct clk *clk; 2533a198059SLinus Walleij unsigned int bank; 2543a198059SLinus Walleij unsigned int parent_irq; 2553a198059SLinus Walleij int latent_parent_irq; 2563a198059SLinus Walleij u32 (*get_latent_status)(unsigned int bank); 2573a198059SLinus Walleij void (*set_ioforce)(bool enable); 2583a198059SLinus Walleij spinlock_t lock; 2593a198059SLinus Walleij bool sleepmode; 2603a198059SLinus Walleij /* Keep track of configured edges */ 2613a198059SLinus Walleij u32 edge_rising; 2623a198059SLinus Walleij u32 edge_falling; 2633a198059SLinus Walleij u32 real_wake; 2643a198059SLinus Walleij u32 rwimsc; 2653a198059SLinus Walleij u32 fwimsc; 2663a198059SLinus Walleij u32 rimsc; 2673a198059SLinus Walleij u32 fimsc; 2683a198059SLinus Walleij u32 pull_up; 2693a198059SLinus Walleij u32 lowemi; 2703a198059SLinus Walleij }; 2713a198059SLinus Walleij 2723a198059SLinus Walleij /** 2733a198059SLinus Walleij * struct nmk_pinctrl - state container for the Nomadik pin controller 2743a198059SLinus Walleij * @dev: containing device pointer 2753a198059SLinus Walleij * @pctl: corresponding pin controller device 2763a198059SLinus Walleij * @soc: SoC data for this specific chip 2773a198059SLinus Walleij * @prcm_base: PRCM register range virtual base 2783a198059SLinus Walleij */ 2793a198059SLinus Walleij struct nmk_pinctrl { 2803a198059SLinus Walleij struct device *dev; 2813a198059SLinus Walleij struct pinctrl_dev *pctl; 2823a198059SLinus Walleij const struct nmk_pinctrl_soc_data *soc; 2833a198059SLinus Walleij void __iomem *prcm_base; 2843a198059SLinus Walleij }; 2853a198059SLinus Walleij 286bc222ef4SLinus Walleij static struct nmk_gpio_chip *nmk_gpio_chips[NMK_MAX_BANKS]; 2873a198059SLinus Walleij 2883a198059SLinus Walleij static DEFINE_SPINLOCK(nmk_gpio_slpm_lock); 2893a198059SLinus Walleij 2903a198059SLinus Walleij #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips) 2913a198059SLinus Walleij 2923a198059SLinus Walleij static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, 2933a198059SLinus Walleij unsigned offset, int gpio_mode) 2943a198059SLinus Walleij { 2953a198059SLinus Walleij u32 bit = 1 << offset; 2963a198059SLinus Walleij u32 afunc, bfunc; 2973a198059SLinus Walleij 2983a198059SLinus Walleij afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit; 2993a198059SLinus Walleij bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit; 3003a198059SLinus Walleij if (gpio_mode & NMK_GPIO_ALT_A) 3013a198059SLinus Walleij afunc |= bit; 3023a198059SLinus Walleij if (gpio_mode & NMK_GPIO_ALT_B) 3033a198059SLinus Walleij bfunc |= bit; 3043a198059SLinus Walleij writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); 3053a198059SLinus Walleij writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); 3063a198059SLinus Walleij } 3073a198059SLinus Walleij 3083a198059SLinus Walleij static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, 3093a198059SLinus Walleij unsigned offset, enum nmk_gpio_slpm mode) 3103a198059SLinus Walleij { 3113a198059SLinus Walleij u32 bit = 1 << offset; 3123a198059SLinus Walleij u32 slpm; 3133a198059SLinus Walleij 3143a198059SLinus Walleij slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); 3153a198059SLinus Walleij if (mode == NMK_GPIO_SLPM_NOCHANGE) 3163a198059SLinus Walleij slpm |= bit; 3173a198059SLinus Walleij else 3183a198059SLinus Walleij slpm &= ~bit; 3193a198059SLinus Walleij writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); 3203a198059SLinus Walleij } 3213a198059SLinus Walleij 3223a198059SLinus Walleij static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, 3233a198059SLinus Walleij unsigned offset, enum nmk_gpio_pull pull) 3243a198059SLinus Walleij { 3253a198059SLinus Walleij u32 bit = 1 << offset; 3263a198059SLinus Walleij u32 pdis; 3273a198059SLinus Walleij 3283a198059SLinus Walleij pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); 3293a198059SLinus Walleij if (pull == NMK_GPIO_PULL_NONE) { 3303a198059SLinus Walleij pdis |= bit; 3313a198059SLinus Walleij nmk_chip->pull_up &= ~bit; 3323a198059SLinus Walleij } else { 3333a198059SLinus Walleij pdis &= ~bit; 3343a198059SLinus Walleij } 3353a198059SLinus Walleij 3363a198059SLinus Walleij writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); 3373a198059SLinus Walleij 3383a198059SLinus Walleij if (pull == NMK_GPIO_PULL_UP) { 3393a198059SLinus Walleij nmk_chip->pull_up |= bit; 3403a198059SLinus Walleij writel(bit, nmk_chip->addr + NMK_GPIO_DATS); 3413a198059SLinus Walleij } else if (pull == NMK_GPIO_PULL_DOWN) { 3423a198059SLinus Walleij nmk_chip->pull_up &= ~bit; 3433a198059SLinus Walleij writel(bit, nmk_chip->addr + NMK_GPIO_DATC); 3443a198059SLinus Walleij } 3453a198059SLinus Walleij } 3463a198059SLinus Walleij 3473a198059SLinus Walleij static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip, 3483a198059SLinus Walleij unsigned offset, bool lowemi) 3493a198059SLinus Walleij { 3503a198059SLinus Walleij u32 bit = BIT(offset); 3513a198059SLinus Walleij bool enabled = nmk_chip->lowemi & bit; 3523a198059SLinus Walleij 3533a198059SLinus Walleij if (lowemi == enabled) 3543a198059SLinus Walleij return; 3553a198059SLinus Walleij 3563a198059SLinus Walleij if (lowemi) 3573a198059SLinus Walleij nmk_chip->lowemi |= bit; 3583a198059SLinus Walleij else 3593a198059SLinus Walleij nmk_chip->lowemi &= ~bit; 3603a198059SLinus Walleij 3613a198059SLinus Walleij writel_relaxed(nmk_chip->lowemi, 3623a198059SLinus Walleij nmk_chip->addr + NMK_GPIO_LOWEMI); 3633a198059SLinus Walleij } 3643a198059SLinus Walleij 3653a198059SLinus Walleij static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, 3663a198059SLinus Walleij unsigned offset) 3673a198059SLinus Walleij { 3683a198059SLinus Walleij writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); 3693a198059SLinus Walleij } 3703a198059SLinus Walleij 3713a198059SLinus Walleij static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, 3723a198059SLinus Walleij unsigned offset, int val) 3733a198059SLinus Walleij { 3743a198059SLinus Walleij if (val) 3753a198059SLinus Walleij writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS); 3763a198059SLinus Walleij else 3773a198059SLinus Walleij writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC); 3783a198059SLinus Walleij } 3793a198059SLinus Walleij 3803a198059SLinus Walleij static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, 3813a198059SLinus Walleij unsigned offset, int val) 3823a198059SLinus Walleij { 3833a198059SLinus Walleij writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS); 3843a198059SLinus Walleij __nmk_gpio_set_output(nmk_chip, offset, val); 3853a198059SLinus Walleij } 3863a198059SLinus Walleij 3873a198059SLinus Walleij static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, 3883a198059SLinus Walleij unsigned offset, int gpio_mode, 3893a198059SLinus Walleij bool glitch) 3903a198059SLinus Walleij { 3913a198059SLinus Walleij u32 rwimsc = nmk_chip->rwimsc; 3923a198059SLinus Walleij u32 fwimsc = nmk_chip->fwimsc; 3933a198059SLinus Walleij 3943a198059SLinus Walleij if (glitch && nmk_chip->set_ioforce) { 3953a198059SLinus Walleij u32 bit = BIT(offset); 3963a198059SLinus Walleij 3973a198059SLinus Walleij /* Prevent spurious wakeups */ 3983a198059SLinus Walleij writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC); 3993a198059SLinus Walleij writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC); 4003a198059SLinus Walleij 4013a198059SLinus Walleij nmk_chip->set_ioforce(true); 4023a198059SLinus Walleij } 4033a198059SLinus Walleij 4043a198059SLinus Walleij __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode); 4053a198059SLinus Walleij 4063a198059SLinus Walleij if (glitch && nmk_chip->set_ioforce) { 4073a198059SLinus Walleij nmk_chip->set_ioforce(false); 4083a198059SLinus Walleij 4093a198059SLinus Walleij writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC); 4103a198059SLinus Walleij writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC); 4113a198059SLinus Walleij } 4123a198059SLinus Walleij } 4133a198059SLinus Walleij 4143a198059SLinus Walleij static void 4153a198059SLinus Walleij nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset) 4163a198059SLinus Walleij { 4173a198059SLinus Walleij u32 falling = nmk_chip->fimsc & BIT(offset); 4183a198059SLinus Walleij u32 rising = nmk_chip->rimsc & BIT(offset); 4193a198059SLinus Walleij int gpio = nmk_chip->chip.base + offset; 4203a198059SLinus Walleij int irq = irq_find_mapping(nmk_chip->chip.irqdomain, offset); 4213a198059SLinus Walleij struct irq_data *d = irq_get_irq_data(irq); 4223a198059SLinus Walleij 4233a198059SLinus Walleij if (!rising && !falling) 4243a198059SLinus Walleij return; 4253a198059SLinus Walleij 4263a198059SLinus Walleij if (!d || !irqd_irq_disabled(d)) 4273a198059SLinus Walleij return; 4283a198059SLinus Walleij 4293a198059SLinus Walleij if (rising) { 4303a198059SLinus Walleij nmk_chip->rimsc &= ~BIT(offset); 4313a198059SLinus Walleij writel_relaxed(nmk_chip->rimsc, 4323a198059SLinus Walleij nmk_chip->addr + NMK_GPIO_RIMSC); 4333a198059SLinus Walleij } 4343a198059SLinus Walleij 4353a198059SLinus Walleij if (falling) { 4363a198059SLinus Walleij nmk_chip->fimsc &= ~BIT(offset); 4373a198059SLinus Walleij writel_relaxed(nmk_chip->fimsc, 4383a198059SLinus Walleij nmk_chip->addr + NMK_GPIO_FIMSC); 4393a198059SLinus Walleij } 4403a198059SLinus Walleij 4413a198059SLinus Walleij dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio); 4423a198059SLinus Walleij } 4433a198059SLinus Walleij 4443a198059SLinus Walleij static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value) 4453a198059SLinus Walleij { 4463a198059SLinus Walleij u32 val; 4473a198059SLinus Walleij 4483a198059SLinus Walleij val = readl(reg); 4493a198059SLinus Walleij val = ((val & ~mask) | (value & mask)); 4503a198059SLinus Walleij writel(val, reg); 4513a198059SLinus Walleij } 4523a198059SLinus Walleij 4533a198059SLinus Walleij static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct, 4543a198059SLinus Walleij unsigned offset, unsigned alt_num) 4553a198059SLinus Walleij { 4563a198059SLinus Walleij int i; 4573a198059SLinus Walleij u16 reg; 4583a198059SLinus Walleij u8 bit; 4593a198059SLinus Walleij u8 alt_index; 4603a198059SLinus Walleij const struct prcm_gpiocr_altcx_pin_desc *pin_desc; 4613a198059SLinus Walleij const u16 *gpiocr_regs; 4623a198059SLinus Walleij 4633a198059SLinus Walleij if (!npct->prcm_base) 4643a198059SLinus Walleij return; 4653a198059SLinus Walleij 4663a198059SLinus Walleij if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) { 4673a198059SLinus Walleij dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n", 4683a198059SLinus Walleij alt_num); 4693a198059SLinus Walleij return; 4703a198059SLinus Walleij } 4713a198059SLinus Walleij 4723a198059SLinus Walleij for (i = 0 ; i < npct->soc->npins_altcx ; i++) { 4733a198059SLinus Walleij if (npct->soc->altcx_pins[i].pin == offset) 4743a198059SLinus Walleij break; 4753a198059SLinus Walleij } 4763a198059SLinus Walleij if (i == npct->soc->npins_altcx) { 4773a198059SLinus Walleij dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n", 4783a198059SLinus Walleij offset); 4793a198059SLinus Walleij return; 4803a198059SLinus Walleij } 4813a198059SLinus Walleij 4823a198059SLinus Walleij pin_desc = npct->soc->altcx_pins + i; 4833a198059SLinus Walleij gpiocr_regs = npct->soc->prcm_gpiocr_registers; 4843a198059SLinus Walleij 4853a198059SLinus Walleij /* 4863a198059SLinus Walleij * If alt_num is NULL, just clear current ALTCx selection 4873a198059SLinus Walleij * to make sure we come back to a pure ALTC selection 4883a198059SLinus Walleij */ 4893a198059SLinus Walleij if (!alt_num) { 4903a198059SLinus Walleij for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { 4913a198059SLinus Walleij if (pin_desc->altcx[i].used == true) { 4923a198059SLinus Walleij reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; 4933a198059SLinus Walleij bit = pin_desc->altcx[i].control_bit; 4943a198059SLinus Walleij if (readl(npct->prcm_base + reg) & BIT(bit)) { 4953a198059SLinus Walleij nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); 4963a198059SLinus Walleij dev_dbg(npct->dev, 4973a198059SLinus Walleij "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", 4983a198059SLinus Walleij offset, i+1); 4993a198059SLinus Walleij } 5003a198059SLinus Walleij } 5013a198059SLinus Walleij } 5023a198059SLinus Walleij return; 5033a198059SLinus Walleij } 5043a198059SLinus Walleij 5053a198059SLinus Walleij alt_index = alt_num - 1; 5063a198059SLinus Walleij if (pin_desc->altcx[alt_index].used == false) { 5073a198059SLinus Walleij dev_warn(npct->dev, 5083a198059SLinus Walleij "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n", 5093a198059SLinus Walleij offset, alt_num); 5103a198059SLinus Walleij return; 5113a198059SLinus Walleij } 5123a198059SLinus Walleij 5133a198059SLinus Walleij /* 5143a198059SLinus Walleij * Check if any other ALTCx functions are activated on this pin 5153a198059SLinus Walleij * and disable it first. 5163a198059SLinus Walleij */ 5173a198059SLinus Walleij for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { 5183a198059SLinus Walleij if (i == alt_index) 5193a198059SLinus Walleij continue; 5203a198059SLinus Walleij if (pin_desc->altcx[i].used == true) { 5213a198059SLinus Walleij reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; 5223a198059SLinus Walleij bit = pin_desc->altcx[i].control_bit; 5233a198059SLinus Walleij if (readl(npct->prcm_base + reg) & BIT(bit)) { 5243a198059SLinus Walleij nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); 5253a198059SLinus Walleij dev_dbg(npct->dev, 5263a198059SLinus Walleij "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", 5273a198059SLinus Walleij offset, i+1); 5283a198059SLinus Walleij } 5293a198059SLinus Walleij } 5303a198059SLinus Walleij } 5313a198059SLinus Walleij 5323a198059SLinus Walleij reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index]; 5333a198059SLinus Walleij bit = pin_desc->altcx[alt_index].control_bit; 5343a198059SLinus Walleij dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n", 5353a198059SLinus Walleij offset, alt_index+1); 5363a198059SLinus Walleij nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit)); 5373a198059SLinus Walleij } 5383a198059SLinus Walleij 5393a198059SLinus Walleij /* 5403a198059SLinus Walleij * Safe sequence used to switch IOs between GPIO and Alternate-C mode: 5413a198059SLinus Walleij * - Save SLPM registers 5423a198059SLinus Walleij * - Set SLPM=0 for the IOs you want to switch and others to 1 5433a198059SLinus Walleij * - Configure the GPIO registers for the IOs that are being switched 5443a198059SLinus Walleij * - Set IOFORCE=1 5453a198059SLinus Walleij * - Modify the AFLSA/B registers for the IOs that are being switched 5463a198059SLinus Walleij * - Set IOFORCE=0 5473a198059SLinus Walleij * - Restore SLPM registers 5483a198059SLinus Walleij * - Any spurious wake up event during switch sequence to be ignored and 5493a198059SLinus Walleij * cleared 5503a198059SLinus Walleij */ 5513a198059SLinus Walleij static void nmk_gpio_glitch_slpm_init(unsigned int *slpm) 5523a198059SLinus Walleij { 5533a198059SLinus Walleij int i; 5543a198059SLinus Walleij 5553a198059SLinus Walleij for (i = 0; i < NUM_BANKS; i++) { 5563a198059SLinus Walleij struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 5573a198059SLinus Walleij unsigned int temp = slpm[i]; 5583a198059SLinus Walleij 5593a198059SLinus Walleij if (!chip) 5603a198059SLinus Walleij break; 5613a198059SLinus Walleij 5623a198059SLinus Walleij clk_enable(chip->clk); 5633a198059SLinus Walleij 5643a198059SLinus Walleij slpm[i] = readl(chip->addr + NMK_GPIO_SLPC); 5653a198059SLinus Walleij writel(temp, chip->addr + NMK_GPIO_SLPC); 5663a198059SLinus Walleij } 5673a198059SLinus Walleij } 5683a198059SLinus Walleij 5693a198059SLinus Walleij static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm) 5703a198059SLinus Walleij { 5713a198059SLinus Walleij int i; 5723a198059SLinus Walleij 5733a198059SLinus Walleij for (i = 0; i < NUM_BANKS; i++) { 5743a198059SLinus Walleij struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 5753a198059SLinus Walleij 5763a198059SLinus Walleij if (!chip) 5773a198059SLinus Walleij break; 5783a198059SLinus Walleij 5793a198059SLinus Walleij writel(slpm[i], chip->addr + NMK_GPIO_SLPC); 5803a198059SLinus Walleij 5813a198059SLinus Walleij clk_disable(chip->clk); 5823a198059SLinus Walleij } 5833a198059SLinus Walleij } 5843a198059SLinus Walleij 5853a198059SLinus Walleij static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio) 5863a198059SLinus Walleij { 5873a198059SLinus Walleij int i; 5883a198059SLinus Walleij u16 reg; 5893a198059SLinus Walleij u8 bit; 5903a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 5913a198059SLinus Walleij const struct prcm_gpiocr_altcx_pin_desc *pin_desc; 5923a198059SLinus Walleij const u16 *gpiocr_regs; 5933a198059SLinus Walleij 5943a198059SLinus Walleij if (!npct->prcm_base) 5953a198059SLinus Walleij return NMK_GPIO_ALT_C; 5963a198059SLinus Walleij 5973a198059SLinus Walleij for (i = 0; i < npct->soc->npins_altcx; i++) { 5983a198059SLinus Walleij if (npct->soc->altcx_pins[i].pin == gpio) 5993a198059SLinus Walleij break; 6003a198059SLinus Walleij } 6013a198059SLinus Walleij if (i == npct->soc->npins_altcx) 6023a198059SLinus Walleij return NMK_GPIO_ALT_C; 6033a198059SLinus Walleij 6043a198059SLinus Walleij pin_desc = npct->soc->altcx_pins + i; 6053a198059SLinus Walleij gpiocr_regs = npct->soc->prcm_gpiocr_registers; 6063a198059SLinus Walleij for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) { 6073a198059SLinus Walleij if (pin_desc->altcx[i].used == true) { 6083a198059SLinus Walleij reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; 6093a198059SLinus Walleij bit = pin_desc->altcx[i].control_bit; 6103a198059SLinus Walleij if (readl(npct->prcm_base + reg) & BIT(bit)) 6113a198059SLinus Walleij return NMK_GPIO_ALT_C+i+1; 6123a198059SLinus Walleij } 6133a198059SLinus Walleij } 6143a198059SLinus Walleij return NMK_GPIO_ALT_C; 6153a198059SLinus Walleij } 6163a198059SLinus Walleij 6173a198059SLinus Walleij int nmk_gpio_get_mode(int gpio) 6183a198059SLinus Walleij { 6193a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip; 6203a198059SLinus Walleij u32 afunc, bfunc, bit; 6213a198059SLinus Walleij 6223a198059SLinus Walleij nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; 6233a198059SLinus Walleij if (!nmk_chip) 6243a198059SLinus Walleij return -EINVAL; 6253a198059SLinus Walleij 6263a198059SLinus Walleij bit = 1 << (gpio % NMK_GPIO_PER_CHIP); 6273a198059SLinus Walleij 6283a198059SLinus Walleij clk_enable(nmk_chip->clk); 6293a198059SLinus Walleij 6303a198059SLinus Walleij afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit; 6313a198059SLinus Walleij bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit; 6323a198059SLinus Walleij 6333a198059SLinus Walleij clk_disable(nmk_chip->clk); 6343a198059SLinus Walleij 6353a198059SLinus Walleij return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0); 6363a198059SLinus Walleij } 6373a198059SLinus Walleij EXPORT_SYMBOL(nmk_gpio_get_mode); 6383a198059SLinus Walleij 6393a198059SLinus Walleij 6403a198059SLinus Walleij /* IRQ functions */ 6413a198059SLinus Walleij static inline int nmk_gpio_get_bitmask(int gpio) 6423a198059SLinus Walleij { 6433a198059SLinus Walleij return 1 << (gpio % NMK_GPIO_PER_CHIP); 6443a198059SLinus Walleij } 6453a198059SLinus Walleij 6463a198059SLinus Walleij static void nmk_gpio_irq_ack(struct irq_data *d) 6473a198059SLinus Walleij { 6483a198059SLinus Walleij struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 6493a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); 6503a198059SLinus Walleij 6513a198059SLinus Walleij clk_enable(nmk_chip->clk); 6523a198059SLinus Walleij writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC); 6533a198059SLinus Walleij clk_disable(nmk_chip->clk); 6543a198059SLinus Walleij } 6553a198059SLinus Walleij 6563a198059SLinus Walleij enum nmk_gpio_irq_type { 6573a198059SLinus Walleij NORMAL, 6583a198059SLinus Walleij WAKE, 6593a198059SLinus Walleij }; 6603a198059SLinus Walleij 6613a198059SLinus Walleij static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, 6623a198059SLinus Walleij int gpio, enum nmk_gpio_irq_type which, 6633a198059SLinus Walleij bool enable) 6643a198059SLinus Walleij { 6653a198059SLinus Walleij u32 bitmask = nmk_gpio_get_bitmask(gpio); 6663a198059SLinus Walleij u32 *rimscval; 6673a198059SLinus Walleij u32 *fimscval; 6683a198059SLinus Walleij u32 rimscreg; 6693a198059SLinus Walleij u32 fimscreg; 6703a198059SLinus Walleij 6713a198059SLinus Walleij if (which == NORMAL) { 6723a198059SLinus Walleij rimscreg = NMK_GPIO_RIMSC; 6733a198059SLinus Walleij fimscreg = NMK_GPIO_FIMSC; 6743a198059SLinus Walleij rimscval = &nmk_chip->rimsc; 6753a198059SLinus Walleij fimscval = &nmk_chip->fimsc; 6763a198059SLinus Walleij } else { 6773a198059SLinus Walleij rimscreg = NMK_GPIO_RWIMSC; 6783a198059SLinus Walleij fimscreg = NMK_GPIO_FWIMSC; 6793a198059SLinus Walleij rimscval = &nmk_chip->rwimsc; 6803a198059SLinus Walleij fimscval = &nmk_chip->fwimsc; 6813a198059SLinus Walleij } 6823a198059SLinus Walleij 6833a198059SLinus Walleij /* we must individually set/clear the two edges */ 6843a198059SLinus Walleij if (nmk_chip->edge_rising & bitmask) { 6853a198059SLinus Walleij if (enable) 6863a198059SLinus Walleij *rimscval |= bitmask; 6873a198059SLinus Walleij else 6883a198059SLinus Walleij *rimscval &= ~bitmask; 6893a198059SLinus Walleij writel(*rimscval, nmk_chip->addr + rimscreg); 6903a198059SLinus Walleij } 6913a198059SLinus Walleij if (nmk_chip->edge_falling & bitmask) { 6923a198059SLinus Walleij if (enable) 6933a198059SLinus Walleij *fimscval |= bitmask; 6943a198059SLinus Walleij else 6953a198059SLinus Walleij *fimscval &= ~bitmask; 6963a198059SLinus Walleij writel(*fimscval, nmk_chip->addr + fimscreg); 6973a198059SLinus Walleij } 6983a198059SLinus Walleij } 6993a198059SLinus Walleij 7003a198059SLinus Walleij static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, 7013a198059SLinus Walleij int gpio, bool on) 7023a198059SLinus Walleij { 7033a198059SLinus Walleij /* 7043a198059SLinus Walleij * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is 7053a198059SLinus Walleij * disabled, since setting SLPM to 1 increases power consumption, and 7063a198059SLinus Walleij * wakeup is anyhow controlled by the RIMSC and FIMSC registers. 7073a198059SLinus Walleij */ 7083a198059SLinus Walleij if (nmk_chip->sleepmode && on) { 7093a198059SLinus Walleij __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, 7103a198059SLinus Walleij NMK_GPIO_SLPM_WAKEUP_ENABLE); 7113a198059SLinus Walleij } 7123a198059SLinus Walleij 7133a198059SLinus Walleij __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); 7143a198059SLinus Walleij } 7153a198059SLinus Walleij 7163a198059SLinus Walleij static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) 7173a198059SLinus Walleij { 7183a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip; 7193a198059SLinus Walleij unsigned long flags; 7203a198059SLinus Walleij u32 bitmask; 7213a198059SLinus Walleij 7223a198059SLinus Walleij nmk_chip = irq_data_get_irq_chip_data(d); 7233a198059SLinus Walleij bitmask = nmk_gpio_get_bitmask(d->hwirq); 7243a198059SLinus Walleij if (!nmk_chip) 7253a198059SLinus Walleij return -EINVAL; 7263a198059SLinus Walleij 7273a198059SLinus Walleij clk_enable(nmk_chip->clk); 7283a198059SLinus Walleij spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 7293a198059SLinus Walleij spin_lock(&nmk_chip->lock); 7303a198059SLinus Walleij 7313a198059SLinus Walleij __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable); 7323a198059SLinus Walleij 7333a198059SLinus Walleij if (!(nmk_chip->real_wake & bitmask)) 7343a198059SLinus Walleij __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable); 7353a198059SLinus Walleij 7363a198059SLinus Walleij spin_unlock(&nmk_chip->lock); 7373a198059SLinus Walleij spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 7383a198059SLinus Walleij clk_disable(nmk_chip->clk); 7393a198059SLinus Walleij 7403a198059SLinus Walleij return 0; 7413a198059SLinus Walleij } 7423a198059SLinus Walleij 7433a198059SLinus Walleij static void nmk_gpio_irq_mask(struct irq_data *d) 7443a198059SLinus Walleij { 7453a198059SLinus Walleij nmk_gpio_irq_maskunmask(d, false); 7463a198059SLinus Walleij } 7473a198059SLinus Walleij 7483a198059SLinus Walleij static void nmk_gpio_irq_unmask(struct irq_data *d) 7493a198059SLinus Walleij { 7503a198059SLinus Walleij nmk_gpio_irq_maskunmask(d, true); 7513a198059SLinus Walleij } 7523a198059SLinus Walleij 7533a198059SLinus Walleij static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 7543a198059SLinus Walleij { 7553a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip; 7563a198059SLinus Walleij unsigned long flags; 7573a198059SLinus Walleij u32 bitmask; 7583a198059SLinus Walleij 7593a198059SLinus Walleij nmk_chip = irq_data_get_irq_chip_data(d); 7603a198059SLinus Walleij if (!nmk_chip) 7613a198059SLinus Walleij return -EINVAL; 7623a198059SLinus Walleij bitmask = nmk_gpio_get_bitmask(d->hwirq); 7633a198059SLinus Walleij 7643a198059SLinus Walleij clk_enable(nmk_chip->clk); 7653a198059SLinus Walleij spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 7663a198059SLinus Walleij spin_lock(&nmk_chip->lock); 7673a198059SLinus Walleij 7683a198059SLinus Walleij if (irqd_irq_disabled(d)) 7693a198059SLinus Walleij __nmk_gpio_set_wake(nmk_chip, d->hwirq, on); 7703a198059SLinus Walleij 7713a198059SLinus Walleij if (on) 7723a198059SLinus Walleij nmk_chip->real_wake |= bitmask; 7733a198059SLinus Walleij else 7743a198059SLinus Walleij nmk_chip->real_wake &= ~bitmask; 7753a198059SLinus Walleij 7763a198059SLinus Walleij spin_unlock(&nmk_chip->lock); 7773a198059SLinus Walleij spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 7783a198059SLinus Walleij clk_disable(nmk_chip->clk); 7793a198059SLinus Walleij 7803a198059SLinus Walleij return 0; 7813a198059SLinus Walleij } 7823a198059SLinus Walleij 7833a198059SLinus Walleij static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) 7843a198059SLinus Walleij { 7853a198059SLinus Walleij bool enabled = !irqd_irq_disabled(d); 7863a198059SLinus Walleij bool wake = irqd_is_wakeup_set(d); 7873a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip; 7883a198059SLinus Walleij unsigned long flags; 7893a198059SLinus Walleij u32 bitmask; 7903a198059SLinus Walleij 7913a198059SLinus Walleij nmk_chip = irq_data_get_irq_chip_data(d); 7923a198059SLinus Walleij bitmask = nmk_gpio_get_bitmask(d->hwirq); 7933a198059SLinus Walleij if (!nmk_chip) 7943a198059SLinus Walleij return -EINVAL; 7953a198059SLinus Walleij if (type & IRQ_TYPE_LEVEL_HIGH) 7963a198059SLinus Walleij return -EINVAL; 7973a198059SLinus Walleij if (type & IRQ_TYPE_LEVEL_LOW) 7983a198059SLinus Walleij return -EINVAL; 7993a198059SLinus Walleij 8003a198059SLinus Walleij clk_enable(nmk_chip->clk); 8013a198059SLinus Walleij spin_lock_irqsave(&nmk_chip->lock, flags); 8023a198059SLinus Walleij 8033a198059SLinus Walleij if (enabled) 8043a198059SLinus Walleij __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false); 8053a198059SLinus Walleij 8063a198059SLinus Walleij if (enabled || wake) 8073a198059SLinus Walleij __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false); 8083a198059SLinus Walleij 8093a198059SLinus Walleij nmk_chip->edge_rising &= ~bitmask; 8103a198059SLinus Walleij if (type & IRQ_TYPE_EDGE_RISING) 8113a198059SLinus Walleij nmk_chip->edge_rising |= bitmask; 8123a198059SLinus Walleij 8133a198059SLinus Walleij nmk_chip->edge_falling &= ~bitmask; 8143a198059SLinus Walleij if (type & IRQ_TYPE_EDGE_FALLING) 8153a198059SLinus Walleij nmk_chip->edge_falling |= bitmask; 8163a198059SLinus Walleij 8173a198059SLinus Walleij if (enabled) 8183a198059SLinus Walleij __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true); 8193a198059SLinus Walleij 8203a198059SLinus Walleij if (enabled || wake) 8213a198059SLinus Walleij __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true); 8223a198059SLinus Walleij 8233a198059SLinus Walleij spin_unlock_irqrestore(&nmk_chip->lock, flags); 8243a198059SLinus Walleij clk_disable(nmk_chip->clk); 8253a198059SLinus Walleij 8263a198059SLinus Walleij return 0; 8273a198059SLinus Walleij } 8283a198059SLinus Walleij 8293a198059SLinus Walleij static unsigned int nmk_gpio_irq_startup(struct irq_data *d) 8303a198059SLinus Walleij { 8313a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); 8323a198059SLinus Walleij 8333a198059SLinus Walleij clk_enable(nmk_chip->clk); 8343a198059SLinus Walleij nmk_gpio_irq_unmask(d); 8353a198059SLinus Walleij return 0; 8363a198059SLinus Walleij } 8373a198059SLinus Walleij 8383a198059SLinus Walleij static void nmk_gpio_irq_shutdown(struct irq_data *d) 8393a198059SLinus Walleij { 8403a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); 8413a198059SLinus Walleij 8423a198059SLinus Walleij nmk_gpio_irq_mask(d); 8433a198059SLinus Walleij clk_disable(nmk_chip->clk); 8443a198059SLinus Walleij } 8453a198059SLinus Walleij 8465663bb27SJiang Liu static void __nmk_gpio_irq_handler(struct irq_desc *desc, u32 status) 8473a198059SLinus Walleij { 8485663bb27SJiang Liu struct irq_chip *host_chip = irq_desc_get_chip(desc); 8493a198059SLinus Walleij struct gpio_chip *chip = irq_desc_get_handler_data(desc); 8503a198059SLinus Walleij 8513a198059SLinus Walleij chained_irq_enter(host_chip, desc); 8523a198059SLinus Walleij 8533a198059SLinus Walleij while (status) { 8543a198059SLinus Walleij int bit = __ffs(status); 8553a198059SLinus Walleij 8563a198059SLinus Walleij generic_handle_irq(irq_find_mapping(chip->irqdomain, bit)); 8573a198059SLinus Walleij status &= ~BIT(bit); 8583a198059SLinus Walleij } 8593a198059SLinus Walleij 8603a198059SLinus Walleij chained_irq_exit(host_chip, desc); 8613a198059SLinus Walleij } 8623a198059SLinus Walleij 863bd0b9ac4SThomas Gleixner static void nmk_gpio_irq_handler(struct irq_desc *desc) 8643a198059SLinus Walleij { 8653a198059SLinus Walleij struct gpio_chip *chip = irq_desc_get_handler_data(desc); 8663a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); 8673a198059SLinus Walleij u32 status; 8683a198059SLinus Walleij 8693a198059SLinus Walleij clk_enable(nmk_chip->clk); 8703a198059SLinus Walleij status = readl(nmk_chip->addr + NMK_GPIO_IS); 8713a198059SLinus Walleij clk_disable(nmk_chip->clk); 8723a198059SLinus Walleij 8735663bb27SJiang Liu __nmk_gpio_irq_handler(desc, status); 8743a198059SLinus Walleij } 8753a198059SLinus Walleij 876bd0b9ac4SThomas Gleixner static void nmk_gpio_latent_irq_handler(struct irq_desc *desc) 8773a198059SLinus Walleij { 8783a198059SLinus Walleij struct gpio_chip *chip = irq_desc_get_handler_data(desc); 8793a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); 8803a198059SLinus Walleij u32 status = nmk_chip->get_latent_status(nmk_chip->bank); 8813a198059SLinus Walleij 8825663bb27SJiang Liu __nmk_gpio_irq_handler(desc, status); 8833a198059SLinus Walleij } 8843a198059SLinus Walleij 8853a198059SLinus Walleij /* I/O Functions */ 8863a198059SLinus Walleij 8873a198059SLinus Walleij static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) 8883a198059SLinus Walleij { 8893a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip = 8903a198059SLinus Walleij container_of(chip, struct nmk_gpio_chip, chip); 8913a198059SLinus Walleij 8923a198059SLinus Walleij clk_enable(nmk_chip->clk); 8933a198059SLinus Walleij 8943a198059SLinus Walleij writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); 8953a198059SLinus Walleij 8963a198059SLinus Walleij clk_disable(nmk_chip->clk); 8973a198059SLinus Walleij 8983a198059SLinus Walleij return 0; 8993a198059SLinus Walleij } 9003a198059SLinus Walleij 9013a198059SLinus Walleij static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset) 9023a198059SLinus Walleij { 9033a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip = 9043a198059SLinus Walleij container_of(chip, struct nmk_gpio_chip, chip); 9053a198059SLinus Walleij u32 bit = 1 << offset; 9063a198059SLinus Walleij int value; 9073a198059SLinus Walleij 9083a198059SLinus Walleij clk_enable(nmk_chip->clk); 9093a198059SLinus Walleij 9103a198059SLinus Walleij value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0; 9113a198059SLinus Walleij 9123a198059SLinus Walleij clk_disable(nmk_chip->clk); 9133a198059SLinus Walleij 9143a198059SLinus Walleij return value; 9153a198059SLinus Walleij } 9163a198059SLinus Walleij 9173a198059SLinus Walleij static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset, 9183a198059SLinus Walleij int val) 9193a198059SLinus Walleij { 9203a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip = 9213a198059SLinus Walleij container_of(chip, struct nmk_gpio_chip, chip); 9223a198059SLinus Walleij 9233a198059SLinus Walleij clk_enable(nmk_chip->clk); 9243a198059SLinus Walleij 9253a198059SLinus Walleij __nmk_gpio_set_output(nmk_chip, offset, val); 9263a198059SLinus Walleij 9273a198059SLinus Walleij clk_disable(nmk_chip->clk); 9283a198059SLinus Walleij } 9293a198059SLinus Walleij 9303a198059SLinus Walleij static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, 9313a198059SLinus Walleij int val) 9323a198059SLinus Walleij { 9333a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip = 9343a198059SLinus Walleij container_of(chip, struct nmk_gpio_chip, chip); 9353a198059SLinus Walleij 9363a198059SLinus Walleij clk_enable(nmk_chip->clk); 9373a198059SLinus Walleij 9383a198059SLinus Walleij __nmk_gpio_make_output(nmk_chip, offset, val); 9393a198059SLinus Walleij 9403a198059SLinus Walleij clk_disable(nmk_chip->clk); 9413a198059SLinus Walleij 9423a198059SLinus Walleij return 0; 9433a198059SLinus Walleij } 9443a198059SLinus Walleij 9453a198059SLinus Walleij #ifdef CONFIG_DEBUG_FS 9463a198059SLinus Walleij 9473a198059SLinus Walleij #include <linux/seq_file.h> 9483a198059SLinus Walleij 9493a198059SLinus Walleij static void nmk_gpio_dbg_show_one(struct seq_file *s, 9503a198059SLinus Walleij struct pinctrl_dev *pctldev, struct gpio_chip *chip, 9513a198059SLinus Walleij unsigned offset, unsigned gpio) 9523a198059SLinus Walleij { 9533a198059SLinus Walleij const char *label = gpiochip_is_requested(chip, offset); 9543a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip = 9553a198059SLinus Walleij container_of(chip, struct nmk_gpio_chip, chip); 9563a198059SLinus Walleij int mode; 9573a198059SLinus Walleij bool is_out; 9588f1774a2SLinus Walleij bool data_out; 9593a198059SLinus Walleij bool pull; 9603a198059SLinus Walleij u32 bit = 1 << offset; 9613a198059SLinus Walleij const char *modes[] = { 9623a198059SLinus Walleij [NMK_GPIO_ALT_GPIO] = "gpio", 9633a198059SLinus Walleij [NMK_GPIO_ALT_A] = "altA", 9643a198059SLinus Walleij [NMK_GPIO_ALT_B] = "altB", 9653a198059SLinus Walleij [NMK_GPIO_ALT_C] = "altC", 9663a198059SLinus Walleij [NMK_GPIO_ALT_C+1] = "altC1", 9673a198059SLinus Walleij [NMK_GPIO_ALT_C+2] = "altC2", 9683a198059SLinus Walleij [NMK_GPIO_ALT_C+3] = "altC3", 9693a198059SLinus Walleij [NMK_GPIO_ALT_C+4] = "altC4", 9703a198059SLinus Walleij }; 9718f1774a2SLinus Walleij const char *pulls[] = { 9728f1774a2SLinus Walleij "none ", 9738f1774a2SLinus Walleij "pull down", 9748f1774a2SLinus Walleij "pull up ", 9758f1774a2SLinus Walleij }; 9763a198059SLinus Walleij 9773a198059SLinus Walleij clk_enable(nmk_chip->clk); 9783a198059SLinus Walleij is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit); 9793a198059SLinus Walleij pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); 9808f1774a2SLinus Walleij data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & bit); 9813a198059SLinus Walleij mode = nmk_gpio_get_mode(gpio); 9823a198059SLinus Walleij if ((mode == NMK_GPIO_ALT_C) && pctldev) 9833a198059SLinus Walleij mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio); 9843a198059SLinus Walleij 9858f1774a2SLinus Walleij if (is_out) { 9868f1774a2SLinus Walleij seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s", 9878f1774a2SLinus Walleij gpio, 9888f1774a2SLinus Walleij label ?: "(none)", 9898f1774a2SLinus Walleij data_out ? "hi" : "lo", 9908f1774a2SLinus Walleij (mode < 0) ? "unknown" : modes[mode]); 9918f1774a2SLinus Walleij } else { 9923a198059SLinus Walleij int irq = gpio_to_irq(gpio); 9933a198059SLinus Walleij struct irq_desc *desc = irq_to_desc(irq); 9948f1774a2SLinus Walleij int pullidx = 0; 995d7f005e8SLinus Walleij int val; 9963a198059SLinus Walleij 9978f1774a2SLinus Walleij if (pull) 9988f1774a2SLinus Walleij pullidx = data_out ? 1 : 2; 9998f1774a2SLinus Walleij 10008f1774a2SLinus Walleij seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s", 10018f1774a2SLinus Walleij gpio, 10028f1774a2SLinus Walleij label ?: "(none)", 10038f1774a2SLinus Walleij pulls[pullidx], 10048f1774a2SLinus Walleij (mode < 0) ? "unknown" : modes[mode]); 1005d7f005e8SLinus Walleij 1006d7f005e8SLinus Walleij val = nmk_gpio_get_input(chip, offset); 1007d7f005e8SLinus Walleij seq_printf(s, " VAL %d", val); 1008d7f005e8SLinus Walleij 10098f1774a2SLinus Walleij /* 10108f1774a2SLinus Walleij * This races with request_irq(), set_irq_type(), 10113a198059SLinus Walleij * and set_irq_wake() ... but those are "rare". 10123a198059SLinus Walleij */ 10133a198059SLinus Walleij if (irq > 0 && desc && desc->action) { 10143a198059SLinus Walleij char *trigger; 10153a198059SLinus Walleij u32 bitmask = nmk_gpio_get_bitmask(gpio); 10163a198059SLinus Walleij 10173a198059SLinus Walleij if (nmk_chip->edge_rising & bitmask) 10183a198059SLinus Walleij trigger = "edge-rising"; 10193a198059SLinus Walleij else if (nmk_chip->edge_falling & bitmask) 10203a198059SLinus Walleij trigger = "edge-falling"; 10213a198059SLinus Walleij else 10223a198059SLinus Walleij trigger = "edge-undefined"; 10233a198059SLinus Walleij 10243a198059SLinus Walleij seq_printf(s, " irq-%d %s%s", 10253a198059SLinus Walleij irq, trigger, 10263a198059SLinus Walleij irqd_is_wakeup_set(&desc->irq_data) 10273a198059SLinus Walleij ? " wakeup" : ""); 10283a198059SLinus Walleij } 10293a198059SLinus Walleij } 10303a198059SLinus Walleij clk_disable(nmk_chip->clk); 10313a198059SLinus Walleij } 10323a198059SLinus Walleij 10333a198059SLinus Walleij static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 10343a198059SLinus Walleij { 10353a198059SLinus Walleij unsigned i; 10363a198059SLinus Walleij unsigned gpio = chip->base; 10373a198059SLinus Walleij 10383a198059SLinus Walleij for (i = 0; i < chip->ngpio; i++, gpio++) { 10393a198059SLinus Walleij nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio); 10403a198059SLinus Walleij seq_printf(s, "\n"); 10413a198059SLinus Walleij } 10423a198059SLinus Walleij } 10433a198059SLinus Walleij 10443a198059SLinus Walleij #else 10453a198059SLinus Walleij static inline void nmk_gpio_dbg_show_one(struct seq_file *s, 10463a198059SLinus Walleij struct pinctrl_dev *pctldev, 10473a198059SLinus Walleij struct gpio_chip *chip, 10483a198059SLinus Walleij unsigned offset, unsigned gpio) 10493a198059SLinus Walleij { 10503a198059SLinus Walleij } 10513a198059SLinus Walleij #define nmk_gpio_dbg_show NULL 10523a198059SLinus Walleij #endif 10533a198059SLinus Walleij 10543a198059SLinus Walleij void nmk_gpio_clocks_enable(void) 10553a198059SLinus Walleij { 10563a198059SLinus Walleij int i; 10573a198059SLinus Walleij 10583a198059SLinus Walleij for (i = 0; i < NUM_BANKS; i++) { 10593a198059SLinus Walleij struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 10603a198059SLinus Walleij 10613a198059SLinus Walleij if (!chip) 10623a198059SLinus Walleij continue; 10633a198059SLinus Walleij 10643a198059SLinus Walleij clk_enable(chip->clk); 10653a198059SLinus Walleij } 10663a198059SLinus Walleij } 10673a198059SLinus Walleij 10683a198059SLinus Walleij void nmk_gpio_clocks_disable(void) 10693a198059SLinus Walleij { 10703a198059SLinus Walleij int i; 10713a198059SLinus Walleij 10723a198059SLinus Walleij for (i = 0; i < NUM_BANKS; i++) { 10733a198059SLinus Walleij struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 10743a198059SLinus Walleij 10753a198059SLinus Walleij if (!chip) 10763a198059SLinus Walleij continue; 10773a198059SLinus Walleij 10783a198059SLinus Walleij clk_disable(chip->clk); 10793a198059SLinus Walleij } 10803a198059SLinus Walleij } 10813a198059SLinus Walleij 10823a198059SLinus Walleij /* 10833a198059SLinus Walleij * Called from the suspend/resume path to only keep the real wakeup interrupts 10843a198059SLinus Walleij * (those that have had set_irq_wake() called on them) as wakeup interrupts, 10853a198059SLinus Walleij * and not the rest of the interrupts which we needed to have as wakeups for 10863a198059SLinus Walleij * cpuidle. 10873a198059SLinus Walleij * 10883a198059SLinus Walleij * PM ops are not used since this needs to be done at the end, after all the 10893a198059SLinus Walleij * other drivers are done with their suspend callbacks. 10903a198059SLinus Walleij */ 10913a198059SLinus Walleij void nmk_gpio_wakeups_suspend(void) 10923a198059SLinus Walleij { 10933a198059SLinus Walleij int i; 10943a198059SLinus Walleij 10953a198059SLinus Walleij for (i = 0; i < NUM_BANKS; i++) { 10963a198059SLinus Walleij struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 10973a198059SLinus Walleij 10983a198059SLinus Walleij if (!chip) 10993a198059SLinus Walleij break; 11003a198059SLinus Walleij 11013a198059SLinus Walleij clk_enable(chip->clk); 11023a198059SLinus Walleij 11033a198059SLinus Walleij writel(chip->rwimsc & chip->real_wake, 11043a198059SLinus Walleij chip->addr + NMK_GPIO_RWIMSC); 11053a198059SLinus Walleij writel(chip->fwimsc & chip->real_wake, 11063a198059SLinus Walleij chip->addr + NMK_GPIO_FWIMSC); 11073a198059SLinus Walleij 11083a198059SLinus Walleij clk_disable(chip->clk); 11093a198059SLinus Walleij } 11103a198059SLinus Walleij } 11113a198059SLinus Walleij 11123a198059SLinus Walleij void nmk_gpio_wakeups_resume(void) 11133a198059SLinus Walleij { 11143a198059SLinus Walleij int i; 11153a198059SLinus Walleij 11163a198059SLinus Walleij for (i = 0; i < NUM_BANKS; i++) { 11173a198059SLinus Walleij struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 11183a198059SLinus Walleij 11193a198059SLinus Walleij if (!chip) 11203a198059SLinus Walleij break; 11213a198059SLinus Walleij 11223a198059SLinus Walleij clk_enable(chip->clk); 11233a198059SLinus Walleij 11243a198059SLinus Walleij writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC); 11253a198059SLinus Walleij writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC); 11263a198059SLinus Walleij 11273a198059SLinus Walleij clk_disable(chip->clk); 11283a198059SLinus Walleij } 11293a198059SLinus Walleij } 11303a198059SLinus Walleij 11313a198059SLinus Walleij /* 11323a198059SLinus Walleij * Read the pull up/pull down status. 11333a198059SLinus Walleij * A bit set in 'pull_up' means that pull up 11343a198059SLinus Walleij * is selected if pull is enabled in PDIS register. 11353a198059SLinus Walleij * Note: only pull up/down set via this driver can 11363a198059SLinus Walleij * be detected due to HW limitations. 11373a198059SLinus Walleij */ 11383a198059SLinus Walleij void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up) 11393a198059SLinus Walleij { 11403a198059SLinus Walleij if (gpio_bank < NUM_BANKS) { 11413a198059SLinus Walleij struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank]; 11423a198059SLinus Walleij 11433a198059SLinus Walleij if (!chip) 11443a198059SLinus Walleij return; 11453a198059SLinus Walleij 11463a198059SLinus Walleij *pull_up = chip->pull_up; 11473a198059SLinus Walleij } 11483a198059SLinus Walleij } 11493a198059SLinus Walleij 1150bc222ef4SLinus Walleij /* 1151bc222ef4SLinus Walleij * We will allocate memory for the state container using devm* allocators 1152bc222ef4SLinus Walleij * binding to the first device reaching this point, it doesn't matter if 1153bc222ef4SLinus Walleij * it is the pin controller or GPIO driver. However we need to use the right 1154bc222ef4SLinus Walleij * platform device when looking up resources so pay attention to pdev. 1155bc222ef4SLinus Walleij */ 1156bc222ef4SLinus Walleij static struct nmk_gpio_chip *nmk_gpio_populate_chip(struct device_node *np, 1157bc222ef4SLinus Walleij struct platform_device *pdev) 1158bc222ef4SLinus Walleij { 1159bc222ef4SLinus Walleij struct nmk_gpio_chip *nmk_chip; 1160bc222ef4SLinus Walleij struct platform_device *gpio_pdev; 1161bc222ef4SLinus Walleij struct gpio_chip *chip; 1162bc222ef4SLinus Walleij struct resource *res; 1163bc222ef4SLinus Walleij struct clk *clk; 1164bc222ef4SLinus Walleij void __iomem *base; 1165bc222ef4SLinus Walleij u32 id; 1166bc222ef4SLinus Walleij 1167bc222ef4SLinus Walleij gpio_pdev = of_find_device_by_node(np); 1168bc222ef4SLinus Walleij if (!gpio_pdev) { 1169bc222ef4SLinus Walleij pr_err("populate \"%s\": device not found\n", np->name); 1170bc222ef4SLinus Walleij return ERR_PTR(-ENODEV); 1171bc222ef4SLinus Walleij } 1172bc222ef4SLinus Walleij if (of_property_read_u32(np, "gpio-bank", &id)) { 1173bc222ef4SLinus Walleij dev_err(&pdev->dev, "populate: gpio-bank property not found\n"); 1174bc222ef4SLinus Walleij return ERR_PTR(-EINVAL); 1175bc222ef4SLinus Walleij } 1176bc222ef4SLinus Walleij 1177bc222ef4SLinus Walleij /* Already populated? */ 1178bc222ef4SLinus Walleij nmk_chip = nmk_gpio_chips[id]; 1179bc222ef4SLinus Walleij if (nmk_chip) 1180bc222ef4SLinus Walleij return nmk_chip; 1181bc222ef4SLinus Walleij 1182bc222ef4SLinus Walleij nmk_chip = devm_kzalloc(&pdev->dev, sizeof(*nmk_chip), GFP_KERNEL); 1183bc222ef4SLinus Walleij if (!nmk_chip) 1184bc222ef4SLinus Walleij return ERR_PTR(-ENOMEM); 1185bc222ef4SLinus Walleij 1186bc222ef4SLinus Walleij nmk_chip->bank = id; 1187bc222ef4SLinus Walleij chip = &nmk_chip->chip; 1188bc222ef4SLinus Walleij chip->base = id * NMK_GPIO_PER_CHIP; 1189bc222ef4SLinus Walleij chip->ngpio = NMK_GPIO_PER_CHIP; 1190bc222ef4SLinus Walleij chip->label = dev_name(&gpio_pdev->dev); 1191bc222ef4SLinus Walleij chip->dev = &gpio_pdev->dev; 1192bc222ef4SLinus Walleij 1193bc222ef4SLinus Walleij res = platform_get_resource(gpio_pdev, IORESOURCE_MEM, 0); 1194bc222ef4SLinus Walleij base = devm_ioremap_resource(&pdev->dev, res); 1195bc222ef4SLinus Walleij if (IS_ERR(base)) 1196bc222ef4SLinus Walleij return base; 1197bc222ef4SLinus Walleij nmk_chip->addr = base; 1198bc222ef4SLinus Walleij 1199bc222ef4SLinus Walleij clk = clk_get(&gpio_pdev->dev, NULL); 1200bc222ef4SLinus Walleij if (IS_ERR(clk)) 1201bc222ef4SLinus Walleij return (void *) clk; 1202bc222ef4SLinus Walleij clk_prepare(clk); 1203bc222ef4SLinus Walleij nmk_chip->clk = clk; 1204bc222ef4SLinus Walleij 1205bc222ef4SLinus Walleij BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); 1206bc222ef4SLinus Walleij nmk_gpio_chips[id] = nmk_chip; 1207bc222ef4SLinus Walleij return nmk_chip; 1208bc222ef4SLinus Walleij } 1209bc222ef4SLinus Walleij 12103a198059SLinus Walleij static int nmk_gpio_probe(struct platform_device *dev) 12113a198059SLinus Walleij { 12123a198059SLinus Walleij struct device_node *np = dev->dev.of_node; 12133a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip; 12143a198059SLinus Walleij struct gpio_chip *chip; 12153007d941SLinus Walleij struct irq_chip *irqchip; 12163a198059SLinus Walleij int latent_irq; 12173a198059SLinus Walleij bool supports_sleepmode; 12183a198059SLinus Walleij int irq; 12193a198059SLinus Walleij int ret; 12203a198059SLinus Walleij 1221bc222ef4SLinus Walleij nmk_chip = nmk_gpio_populate_chip(np, dev); 1222bc222ef4SLinus Walleij if (IS_ERR(nmk_chip)) { 1223bc222ef4SLinus Walleij dev_err(&dev->dev, "could not populate nmk chip struct\n"); 1224bc222ef4SLinus Walleij return PTR_ERR(nmk_chip); 1225bc222ef4SLinus Walleij } 1226bc222ef4SLinus Walleij 12273a198059SLinus Walleij if (of_get_property(np, "st,supports-sleepmode", NULL)) 12283a198059SLinus Walleij supports_sleepmode = true; 12293a198059SLinus Walleij else 12303a198059SLinus Walleij supports_sleepmode = false; 12313a198059SLinus Walleij 1232bc222ef4SLinus Walleij /* Correct platform device ID */ 1233bc222ef4SLinus Walleij dev->id = nmk_chip->bank; 12343a198059SLinus Walleij 12353a198059SLinus Walleij irq = platform_get_irq(dev, 0); 12363a198059SLinus Walleij if (irq < 0) 12373a198059SLinus Walleij return irq; 12383a198059SLinus Walleij 12393a198059SLinus Walleij /* It's OK for this IRQ not to be present */ 12403a198059SLinus Walleij latent_irq = platform_get_irq(dev, 1); 12413a198059SLinus Walleij 12423a198059SLinus Walleij /* 12433a198059SLinus Walleij * The virt address in nmk_chip->addr is in the nomadik register space, 12443a198059SLinus Walleij * so we can simply convert the resource address, without remapping 12453a198059SLinus Walleij */ 12463a198059SLinus Walleij nmk_chip->parent_irq = irq; 12473a198059SLinus Walleij nmk_chip->latent_parent_irq = latent_irq; 12483a198059SLinus Walleij nmk_chip->sleepmode = supports_sleepmode; 12493a198059SLinus Walleij spin_lock_init(&nmk_chip->lock); 12503a198059SLinus Walleij 12513a198059SLinus Walleij chip = &nmk_chip->chip; 125298c85d58SJonas Gorski chip->request = gpiochip_generic_request; 125398c85d58SJonas Gorski chip->free = gpiochip_generic_free; 12543007d941SLinus Walleij chip->direction_input = nmk_gpio_make_input; 12553007d941SLinus Walleij chip->get = nmk_gpio_get_input; 12563007d941SLinus Walleij chip->direction_output = nmk_gpio_make_output; 12573007d941SLinus Walleij chip->set = nmk_gpio_set_output; 12583007d941SLinus Walleij chip->dbg_show = nmk_gpio_dbg_show; 12593007d941SLinus Walleij chip->can_sleep = false; 12603a198059SLinus Walleij chip->owner = THIS_MODULE; 12613a198059SLinus Walleij 12623007d941SLinus Walleij irqchip = &nmk_chip->irqchip; 12633007d941SLinus Walleij irqchip->irq_ack = nmk_gpio_irq_ack; 12643007d941SLinus Walleij irqchip->irq_mask = nmk_gpio_irq_mask; 12653007d941SLinus Walleij irqchip->irq_unmask = nmk_gpio_irq_unmask; 12663007d941SLinus Walleij irqchip->irq_set_type = nmk_gpio_irq_set_type; 12673007d941SLinus Walleij irqchip->irq_set_wake = nmk_gpio_irq_set_wake; 12683007d941SLinus Walleij irqchip->irq_startup = nmk_gpio_irq_startup; 12693007d941SLinus Walleij irqchip->irq_shutdown = nmk_gpio_irq_shutdown; 12703007d941SLinus Walleij irqchip->flags = IRQCHIP_MASK_ON_SUSPEND; 12713007d941SLinus Walleij irqchip->name = kasprintf(GFP_KERNEL, "nmk%u-%u-%u", 12723007d941SLinus Walleij dev->id, 12733007d941SLinus Walleij chip->base, 12743007d941SLinus Walleij chip->base + chip->ngpio - 1); 12753007d941SLinus Walleij 12763a198059SLinus Walleij clk_enable(nmk_chip->clk); 12773a198059SLinus Walleij nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); 12783a198059SLinus Walleij clk_disable(nmk_chip->clk); 12793a198059SLinus Walleij chip->of_node = np; 12803a198059SLinus Walleij 1281bc222ef4SLinus Walleij ret = gpiochip_add(chip); 12823a198059SLinus Walleij if (ret) 12833a198059SLinus Walleij return ret; 12843a198059SLinus Walleij 12853a198059SLinus Walleij platform_set_drvdata(dev, nmk_chip); 12863a198059SLinus Walleij 12873a198059SLinus Walleij /* 12883a198059SLinus Walleij * Let the generic code handle this edge IRQ, the the chained 12893a198059SLinus Walleij * handler will perform the actual work of handling the parent 12903a198059SLinus Walleij * interrupt. 12913a198059SLinus Walleij */ 12923007d941SLinus Walleij ret = gpiochip_irqchip_add(chip, 12933007d941SLinus Walleij irqchip, 12943a198059SLinus Walleij 0, 12953a198059SLinus Walleij handle_edge_irq, 12963a198059SLinus Walleij IRQ_TYPE_EDGE_FALLING); 12973a198059SLinus Walleij if (ret) { 12983a198059SLinus Walleij dev_err(&dev->dev, "could not add irqchip\n"); 12992fcea6ceSLinus Walleij gpiochip_remove(&nmk_chip->chip); 13003a198059SLinus Walleij return -ENODEV; 13013a198059SLinus Walleij } 13023a198059SLinus Walleij /* Then register the chain on the parent IRQ */ 13033007d941SLinus Walleij gpiochip_set_chained_irqchip(chip, 13043007d941SLinus Walleij irqchip, 13053a198059SLinus Walleij nmk_chip->parent_irq, 13063a198059SLinus Walleij nmk_gpio_irq_handler); 13073a198059SLinus Walleij if (nmk_chip->latent_parent_irq > 0) 13083007d941SLinus Walleij gpiochip_set_chained_irqchip(chip, 13093007d941SLinus Walleij irqchip, 13103a198059SLinus Walleij nmk_chip->latent_parent_irq, 13113a198059SLinus Walleij nmk_gpio_latent_irq_handler); 13123a198059SLinus Walleij 13133a198059SLinus Walleij dev_info(&dev->dev, "at address %p\n", nmk_chip->addr); 13143a198059SLinus Walleij 13153a198059SLinus Walleij return 0; 13163a198059SLinus Walleij } 13173a198059SLinus Walleij 13183a198059SLinus Walleij static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev) 13193a198059SLinus Walleij { 13203a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 13213a198059SLinus Walleij 13223a198059SLinus Walleij return npct->soc->ngroups; 13233a198059SLinus Walleij } 13243a198059SLinus Walleij 13253a198059SLinus Walleij static const char *nmk_get_group_name(struct pinctrl_dev *pctldev, 13263a198059SLinus Walleij unsigned selector) 13273a198059SLinus Walleij { 13283a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 13293a198059SLinus Walleij 13303a198059SLinus Walleij return npct->soc->groups[selector].name; 13313a198059SLinus Walleij } 13323a198059SLinus Walleij 13333a198059SLinus Walleij static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, 13343a198059SLinus Walleij const unsigned **pins, 13353a198059SLinus Walleij unsigned *num_pins) 13363a198059SLinus Walleij { 13373a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 13383a198059SLinus Walleij 13393a198059SLinus Walleij *pins = npct->soc->groups[selector].pins; 13403a198059SLinus Walleij *num_pins = npct->soc->groups[selector].npins; 13413a198059SLinus Walleij return 0; 13423a198059SLinus Walleij } 13433a198059SLinus Walleij 13446ca7d2e3SLinus Walleij static struct nmk_gpio_chip *find_nmk_gpio_from_pin(unsigned pin) 13453a198059SLinus Walleij { 13463a198059SLinus Walleij int i; 13476ca7d2e3SLinus Walleij struct nmk_gpio_chip *nmk_gpio; 13483a198059SLinus Walleij 13496ca7d2e3SLinus Walleij for(i = 0; i < NMK_MAX_BANKS; i++) { 13506ca7d2e3SLinus Walleij nmk_gpio = nmk_gpio_chips[i]; 13516ca7d2e3SLinus Walleij if (!nmk_gpio) 13526ca7d2e3SLinus Walleij continue; 13536ca7d2e3SLinus Walleij if (pin >= nmk_gpio->chip.base && 13546ca7d2e3SLinus Walleij pin < nmk_gpio->chip.base + nmk_gpio->chip.ngpio) 13556ca7d2e3SLinus Walleij return nmk_gpio; 13563a198059SLinus Walleij } 13573a198059SLinus Walleij return NULL; 13583a198059SLinus Walleij } 13593a198059SLinus Walleij 13606ca7d2e3SLinus Walleij static struct gpio_chip *find_gc_from_pin(unsigned pin) 13616ca7d2e3SLinus Walleij { 13626ca7d2e3SLinus Walleij struct nmk_gpio_chip *nmk_gpio = find_nmk_gpio_from_pin(pin); 13636ca7d2e3SLinus Walleij 13646ca7d2e3SLinus Walleij if (nmk_gpio) 13656ca7d2e3SLinus Walleij return &nmk_gpio->chip; 13666ca7d2e3SLinus Walleij return NULL; 13676ca7d2e3SLinus Walleij } 13686ca7d2e3SLinus Walleij 13693a198059SLinus Walleij static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 13703a198059SLinus Walleij unsigned offset) 13713a198059SLinus Walleij { 13726ca7d2e3SLinus Walleij struct gpio_chip *chip = find_gc_from_pin(offset); 13733a198059SLinus Walleij 13746ca7d2e3SLinus Walleij if (!chip) { 13753a198059SLinus Walleij seq_printf(s, "invalid pin offset"); 13763a198059SLinus Walleij return; 13773a198059SLinus Walleij } 13783a198059SLinus Walleij nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset); 13793a198059SLinus Walleij } 13803a198059SLinus Walleij 13813a198059SLinus Walleij static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps, 13823a198059SLinus Walleij unsigned *num_maps, const char *group, 13833a198059SLinus Walleij const char *function) 13843a198059SLinus Walleij { 13853a198059SLinus Walleij if (*num_maps == *reserved_maps) 13863a198059SLinus Walleij return -ENOSPC; 13873a198059SLinus Walleij 13883a198059SLinus Walleij (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 13893a198059SLinus Walleij (*map)[*num_maps].data.mux.group = group; 13903a198059SLinus Walleij (*map)[*num_maps].data.mux.function = function; 13913a198059SLinus Walleij (*num_maps)++; 13923a198059SLinus Walleij 13933a198059SLinus Walleij return 0; 13943a198059SLinus Walleij } 13953a198059SLinus Walleij 13963a198059SLinus Walleij static int nmk_dt_add_map_configs(struct pinctrl_map **map, 13973a198059SLinus Walleij unsigned *reserved_maps, 13983a198059SLinus Walleij unsigned *num_maps, const char *group, 13993a198059SLinus Walleij unsigned long *configs, unsigned num_configs) 14003a198059SLinus Walleij { 14013a198059SLinus Walleij unsigned long *dup_configs; 14023a198059SLinus Walleij 14033a198059SLinus Walleij if (*num_maps == *reserved_maps) 14043a198059SLinus Walleij return -ENOSPC; 14053a198059SLinus Walleij 14063a198059SLinus Walleij dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), 14073a198059SLinus Walleij GFP_KERNEL); 14083a198059SLinus Walleij if (!dup_configs) 14093a198059SLinus Walleij return -ENOMEM; 14103a198059SLinus Walleij 14113a198059SLinus Walleij (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN; 14123a198059SLinus Walleij 14133a198059SLinus Walleij (*map)[*num_maps].data.configs.group_or_pin = group; 14143a198059SLinus Walleij (*map)[*num_maps].data.configs.configs = dup_configs; 14153a198059SLinus Walleij (*map)[*num_maps].data.configs.num_configs = num_configs; 14163a198059SLinus Walleij (*num_maps)++; 14173a198059SLinus Walleij 14183a198059SLinus Walleij return 0; 14193a198059SLinus Walleij } 14203a198059SLinus Walleij 14213a198059SLinus Walleij #define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, } 14223a198059SLinus Walleij #define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \ 14233a198059SLinus Walleij .size = ARRAY_SIZE(y), } 14243a198059SLinus Walleij 14253a198059SLinus Walleij static const unsigned long nmk_pin_input_modes[] = { 14263a198059SLinus Walleij PIN_INPUT_NOPULL, 14273a198059SLinus Walleij PIN_INPUT_PULLUP, 14283a198059SLinus Walleij PIN_INPUT_PULLDOWN, 14293a198059SLinus Walleij }; 14303a198059SLinus Walleij 14313a198059SLinus Walleij static const unsigned long nmk_pin_output_modes[] = { 14323a198059SLinus Walleij PIN_OUTPUT_LOW, 14333a198059SLinus Walleij PIN_OUTPUT_HIGH, 14343a198059SLinus Walleij PIN_DIR_OUTPUT, 14353a198059SLinus Walleij }; 14363a198059SLinus Walleij 14373a198059SLinus Walleij static const unsigned long nmk_pin_sleep_modes[] = { 14383a198059SLinus Walleij PIN_SLEEPMODE_DISABLED, 14393a198059SLinus Walleij PIN_SLEEPMODE_ENABLED, 14403a198059SLinus Walleij }; 14413a198059SLinus Walleij 14423a198059SLinus Walleij static const unsigned long nmk_pin_sleep_input_modes[] = { 14433a198059SLinus Walleij PIN_SLPM_INPUT_NOPULL, 14443a198059SLinus Walleij PIN_SLPM_INPUT_PULLUP, 14453a198059SLinus Walleij PIN_SLPM_INPUT_PULLDOWN, 14463a198059SLinus Walleij PIN_SLPM_DIR_INPUT, 14473a198059SLinus Walleij }; 14483a198059SLinus Walleij 14493a198059SLinus Walleij static const unsigned long nmk_pin_sleep_output_modes[] = { 14503a198059SLinus Walleij PIN_SLPM_OUTPUT_LOW, 14513a198059SLinus Walleij PIN_SLPM_OUTPUT_HIGH, 14523a198059SLinus Walleij PIN_SLPM_DIR_OUTPUT, 14533a198059SLinus Walleij }; 14543a198059SLinus Walleij 14553a198059SLinus Walleij static const unsigned long nmk_pin_sleep_wakeup_modes[] = { 14563a198059SLinus Walleij PIN_SLPM_WAKEUP_DISABLE, 14573a198059SLinus Walleij PIN_SLPM_WAKEUP_ENABLE, 14583a198059SLinus Walleij }; 14593a198059SLinus Walleij 14603a198059SLinus Walleij static const unsigned long nmk_pin_gpio_modes[] = { 14613a198059SLinus Walleij PIN_GPIOMODE_DISABLED, 14623a198059SLinus Walleij PIN_GPIOMODE_ENABLED, 14633a198059SLinus Walleij }; 14643a198059SLinus Walleij 14653a198059SLinus Walleij static const unsigned long nmk_pin_sleep_pdis_modes[] = { 14663a198059SLinus Walleij PIN_SLPM_PDIS_DISABLED, 14673a198059SLinus Walleij PIN_SLPM_PDIS_ENABLED, 14683a198059SLinus Walleij }; 14693a198059SLinus Walleij 14703a198059SLinus Walleij struct nmk_cfg_param { 14713a198059SLinus Walleij const char *property; 14723a198059SLinus Walleij unsigned long config; 14733a198059SLinus Walleij const unsigned long *choice; 14743a198059SLinus Walleij int size; 14753a198059SLinus Walleij }; 14763a198059SLinus Walleij 14773a198059SLinus Walleij static const struct nmk_cfg_param nmk_cfg_params[] = { 14783a198059SLinus Walleij NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes), 14793a198059SLinus Walleij NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes), 14803a198059SLinus Walleij NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes), 14813a198059SLinus Walleij NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes), 14823a198059SLinus Walleij NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes), 14833a198059SLinus Walleij NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes), 14843a198059SLinus Walleij NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes), 14853a198059SLinus Walleij NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes), 14863a198059SLinus Walleij }; 14873a198059SLinus Walleij 14883a198059SLinus Walleij static int nmk_dt_pin_config(int index, int val, unsigned long *config) 14893a198059SLinus Walleij { 14903a198059SLinus Walleij int ret = 0; 14913a198059SLinus Walleij 14923a198059SLinus Walleij if (nmk_cfg_params[index].choice == NULL) 14933a198059SLinus Walleij *config = nmk_cfg_params[index].config; 14943a198059SLinus Walleij else { 14953a198059SLinus Walleij /* test if out of range */ 14963a198059SLinus Walleij if (val < nmk_cfg_params[index].size) { 14973a198059SLinus Walleij *config = nmk_cfg_params[index].config | 14983a198059SLinus Walleij nmk_cfg_params[index].choice[val]; 14993a198059SLinus Walleij } 15003a198059SLinus Walleij } 15013a198059SLinus Walleij return ret; 15023a198059SLinus Walleij } 15033a198059SLinus Walleij 15043a198059SLinus Walleij static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name) 15053a198059SLinus Walleij { 15063a198059SLinus Walleij int i, pin_number; 15073a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 15083a198059SLinus Walleij 15093a198059SLinus Walleij if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1) 15103a198059SLinus Walleij for (i = 0; i < npct->soc->npins; i++) 15113a198059SLinus Walleij if (npct->soc->pins[i].number == pin_number) 15123a198059SLinus Walleij return npct->soc->pins[i].name; 15133a198059SLinus Walleij return NULL; 15143a198059SLinus Walleij } 15153a198059SLinus Walleij 15163a198059SLinus Walleij static bool nmk_pinctrl_dt_get_config(struct device_node *np, 15173a198059SLinus Walleij unsigned long *configs) 15183a198059SLinus Walleij { 15193a198059SLinus Walleij bool has_config = 0; 15203a198059SLinus Walleij unsigned long cfg = 0; 15213a198059SLinus Walleij int i, val, ret; 15223a198059SLinus Walleij 15233a198059SLinus Walleij for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) { 15243a198059SLinus Walleij ret = of_property_read_u32(np, 15253a198059SLinus Walleij nmk_cfg_params[i].property, &val); 15263a198059SLinus Walleij if (ret != -EINVAL) { 15273a198059SLinus Walleij if (nmk_dt_pin_config(i, val, &cfg) == 0) { 15283a198059SLinus Walleij *configs |= cfg; 15293a198059SLinus Walleij has_config = 1; 15303a198059SLinus Walleij } 15313a198059SLinus Walleij } 15323a198059SLinus Walleij } 15333a198059SLinus Walleij 15343a198059SLinus Walleij return has_config; 15353a198059SLinus Walleij } 15363a198059SLinus Walleij 15373a198059SLinus Walleij static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 15383a198059SLinus Walleij struct device_node *np, 15393a198059SLinus Walleij struct pinctrl_map **map, 15403a198059SLinus Walleij unsigned *reserved_maps, 15413a198059SLinus Walleij unsigned *num_maps) 15423a198059SLinus Walleij { 15433a198059SLinus Walleij int ret; 15443a198059SLinus Walleij const char *function = NULL; 15453a198059SLinus Walleij unsigned long configs = 0; 15463a198059SLinus Walleij bool has_config = 0; 15473a198059SLinus Walleij struct property *prop; 15483a198059SLinus Walleij struct device_node *np_config; 15493a198059SLinus Walleij 155068d41f23SLinus Walleij ret = of_property_read_string(np, "function", &function); 1551c2f6d059SLinus Walleij if (ret >= 0) { 155268d41f23SLinus Walleij const char *group; 155368d41f23SLinus Walleij 155468d41f23SLinus Walleij ret = of_property_count_strings(np, "groups"); 15553a198059SLinus Walleij if (ret < 0) 15563a198059SLinus Walleij goto exit; 15573a198059SLinus Walleij 1558c2f6d059SLinus Walleij ret = pinctrl_utils_reserve_map(pctldev, map, 1559c2f6d059SLinus Walleij reserved_maps, 1560c2f6d059SLinus Walleij num_maps, ret); 15613a198059SLinus Walleij if (ret < 0) 15623a198059SLinus Walleij goto exit; 15633a198059SLinus Walleij 156468d41f23SLinus Walleij of_property_for_each_string(np, "groups", prop, group) { 15653a198059SLinus Walleij ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps, 15663a198059SLinus Walleij group, function); 15673a198059SLinus Walleij if (ret < 0) 15683a198059SLinus Walleij goto exit; 15693a198059SLinus Walleij } 1570c2f6d059SLinus Walleij } 1571c2f6d059SLinus Walleij 1572c2f6d059SLinus Walleij has_config = nmk_pinctrl_dt_get_config(np, &configs); 1573c2f6d059SLinus Walleij np_config = of_parse_phandle(np, "ste,config", 0); 1574c2f6d059SLinus Walleij if (np_config) 1575c2f6d059SLinus Walleij has_config |= nmk_pinctrl_dt_get_config(np_config, &configs); 15763a198059SLinus Walleij if (has_config) { 157768d41f23SLinus Walleij const char *gpio_name; 157868d41f23SLinus Walleij const char *pin; 157968d41f23SLinus Walleij 15801637d480SLinus Walleij ret = of_property_count_strings(np, "pins"); 1581c2f6d059SLinus Walleij if (ret < 0) 1582c2f6d059SLinus Walleij goto exit; 1583c2f6d059SLinus Walleij ret = pinctrl_utils_reserve_map(pctldev, map, 1584c2f6d059SLinus Walleij reserved_maps, 1585c2f6d059SLinus Walleij num_maps, ret); 1586c2f6d059SLinus Walleij if (ret < 0) 1587c2f6d059SLinus Walleij goto exit; 1588c2f6d059SLinus Walleij 15891637d480SLinus Walleij of_property_for_each_string(np, "pins", prop, pin) { 159068d41f23SLinus Walleij gpio_name = nmk_find_pin_name(pctldev, pin); 15913a198059SLinus Walleij 1592c2f6d059SLinus Walleij ret = nmk_dt_add_map_configs(map, reserved_maps, 1593c2f6d059SLinus Walleij num_maps, 15943a198059SLinus Walleij gpio_name, &configs, 1); 15953a198059SLinus Walleij if (ret < 0) 15963a198059SLinus Walleij goto exit; 15973a198059SLinus Walleij } 15983a198059SLinus Walleij } 1599c2f6d059SLinus Walleij 16003a198059SLinus Walleij exit: 16013a198059SLinus Walleij return ret; 16023a198059SLinus Walleij } 16033a198059SLinus Walleij 16043a198059SLinus Walleij static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 16053a198059SLinus Walleij struct device_node *np_config, 16063a198059SLinus Walleij struct pinctrl_map **map, unsigned *num_maps) 16073a198059SLinus Walleij { 16083a198059SLinus Walleij unsigned reserved_maps; 16093a198059SLinus Walleij struct device_node *np; 16103a198059SLinus Walleij int ret; 16113a198059SLinus Walleij 16123a198059SLinus Walleij reserved_maps = 0; 16133a198059SLinus Walleij *map = NULL; 16143a198059SLinus Walleij *num_maps = 0; 16153a198059SLinus Walleij 16163a198059SLinus Walleij for_each_child_of_node(np_config, np) { 16173a198059SLinus Walleij ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map, 16183a198059SLinus Walleij &reserved_maps, num_maps); 16193a198059SLinus Walleij if (ret < 0) { 16206e9b1c35SLinus Walleij pinctrl_utils_dt_free_map(pctldev, *map, *num_maps); 16213a198059SLinus Walleij return ret; 16223a198059SLinus Walleij } 16233a198059SLinus Walleij } 16243a198059SLinus Walleij 16253a198059SLinus Walleij return 0; 16263a198059SLinus Walleij } 16273a198059SLinus Walleij 16283a198059SLinus Walleij static const struct pinctrl_ops nmk_pinctrl_ops = { 16293a198059SLinus Walleij .get_groups_count = nmk_get_groups_cnt, 16303a198059SLinus Walleij .get_group_name = nmk_get_group_name, 16313a198059SLinus Walleij .get_group_pins = nmk_get_group_pins, 16323a198059SLinus Walleij .pin_dbg_show = nmk_pin_dbg_show, 16333a198059SLinus Walleij .dt_node_to_map = nmk_pinctrl_dt_node_to_map, 16346e9b1c35SLinus Walleij .dt_free_map = pinctrl_utils_dt_free_map, 16353a198059SLinus Walleij }; 16363a198059SLinus Walleij 16373a198059SLinus Walleij static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 16383a198059SLinus Walleij { 16393a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 16403a198059SLinus Walleij 16413a198059SLinus Walleij return npct->soc->nfunctions; 16423a198059SLinus Walleij } 16433a198059SLinus Walleij 16443a198059SLinus Walleij static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev, 16453a198059SLinus Walleij unsigned function) 16463a198059SLinus Walleij { 16473a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 16483a198059SLinus Walleij 16493a198059SLinus Walleij return npct->soc->functions[function].name; 16503a198059SLinus Walleij } 16513a198059SLinus Walleij 16523a198059SLinus Walleij static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev, 16533a198059SLinus Walleij unsigned function, 16543a198059SLinus Walleij const char * const **groups, 16553a198059SLinus Walleij unsigned * const num_groups) 16563a198059SLinus Walleij { 16573a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 16583a198059SLinus Walleij 16593a198059SLinus Walleij *groups = npct->soc->functions[function].groups; 16603a198059SLinus Walleij *num_groups = npct->soc->functions[function].ngroups; 16613a198059SLinus Walleij 16623a198059SLinus Walleij return 0; 16633a198059SLinus Walleij } 16643a198059SLinus Walleij 166503e9f0caSLinus Walleij static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned function, 16663a198059SLinus Walleij unsigned group) 16673a198059SLinus Walleij { 16683a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 16693a198059SLinus Walleij const struct nmk_pingroup *g; 16703a198059SLinus Walleij static unsigned int slpm[NUM_BANKS]; 16713a198059SLinus Walleij unsigned long flags = 0; 16723a198059SLinus Walleij bool glitch; 16733a198059SLinus Walleij int ret = -EINVAL; 16743a198059SLinus Walleij int i; 16753a198059SLinus Walleij 16763a198059SLinus Walleij g = &npct->soc->groups[group]; 16773a198059SLinus Walleij 16783a198059SLinus Walleij if (g->altsetting < 0) 16793a198059SLinus Walleij return -EINVAL; 16803a198059SLinus Walleij 16813a198059SLinus Walleij dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins); 16823a198059SLinus Walleij 16833a198059SLinus Walleij /* 16843a198059SLinus Walleij * If we're setting altfunc C by setting both AFSLA and AFSLB to 1, 16853a198059SLinus Walleij * we may pass through an undesired state. In this case we take 16863a198059SLinus Walleij * some extra care. 16873a198059SLinus Walleij * 16883a198059SLinus Walleij * Safe sequence used to switch IOs between GPIO and Alternate-C mode: 16893a198059SLinus Walleij * - Save SLPM registers (since we have a shadow register in the 16903a198059SLinus Walleij * nmk_chip we're using that as backup) 16913a198059SLinus Walleij * - Set SLPM=0 for the IOs you want to switch and others to 1 16923a198059SLinus Walleij * - Configure the GPIO registers for the IOs that are being switched 16933a198059SLinus Walleij * - Set IOFORCE=1 16943a198059SLinus Walleij * - Modify the AFLSA/B registers for the IOs that are being switched 16953a198059SLinus Walleij * - Set IOFORCE=0 16963a198059SLinus Walleij * - Restore SLPM registers 16973a198059SLinus Walleij * - Any spurious wake up event during switch sequence to be ignored 16983a198059SLinus Walleij * and cleared 16993a198059SLinus Walleij * 17003a198059SLinus Walleij * We REALLY need to save ALL slpm registers, because the external 17013a198059SLinus Walleij * IOFORCE will switch *all* ports to their sleepmode setting to as 17023a198059SLinus Walleij * to avoid glitches. (Not just one port!) 17033a198059SLinus Walleij */ 17043a198059SLinus Walleij glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C); 17053a198059SLinus Walleij 17063a198059SLinus Walleij if (glitch) { 17073a198059SLinus Walleij spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 17083a198059SLinus Walleij 17093a198059SLinus Walleij /* Initially don't put any pins to sleep when switching */ 17103a198059SLinus Walleij memset(slpm, 0xff, sizeof(slpm)); 17113a198059SLinus Walleij 17123a198059SLinus Walleij /* 17133a198059SLinus Walleij * Then mask the pins that need to be sleeping now when we're 17143a198059SLinus Walleij * switching to the ALT C function. 17153a198059SLinus Walleij */ 17163a198059SLinus Walleij for (i = 0; i < g->npins; i++) 17173a198059SLinus Walleij slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]); 17183a198059SLinus Walleij nmk_gpio_glitch_slpm_init(slpm); 17193a198059SLinus Walleij } 17203a198059SLinus Walleij 17213a198059SLinus Walleij for (i = 0; i < g->npins; i++) { 17223a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip; 17233a198059SLinus Walleij unsigned bit; 17243a198059SLinus Walleij 17256ca7d2e3SLinus Walleij nmk_chip = find_nmk_gpio_from_pin(g->pins[i]); 17266ca7d2e3SLinus Walleij if (!nmk_chip) { 17273a198059SLinus Walleij dev_err(npct->dev, 17283a198059SLinus Walleij "invalid pin offset %d in group %s at index %d\n", 17293a198059SLinus Walleij g->pins[i], g->name, i); 17303a198059SLinus Walleij goto out_glitch; 17313a198059SLinus Walleij } 17323a198059SLinus Walleij dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting); 17333a198059SLinus Walleij 17343a198059SLinus Walleij clk_enable(nmk_chip->clk); 17353a198059SLinus Walleij bit = g->pins[i] % NMK_GPIO_PER_CHIP; 17363a198059SLinus Walleij /* 17373a198059SLinus Walleij * If the pin is switching to altfunc, and there was an 17383a198059SLinus Walleij * interrupt installed on it which has been lazy disabled, 17393a198059SLinus Walleij * actually mask the interrupt to prevent spurious interrupts 17403a198059SLinus Walleij * that would occur while the pin is under control of the 17413a198059SLinus Walleij * peripheral. Only SKE does this. 17423a198059SLinus Walleij */ 17433a198059SLinus Walleij nmk_gpio_disable_lazy_irq(nmk_chip, bit); 17443a198059SLinus Walleij 17453a198059SLinus Walleij __nmk_gpio_set_mode_safe(nmk_chip, bit, 17463a198059SLinus Walleij (g->altsetting & NMK_GPIO_ALT_C), glitch); 17473a198059SLinus Walleij clk_disable(nmk_chip->clk); 17483a198059SLinus Walleij 17493a198059SLinus Walleij /* 17503a198059SLinus Walleij * Call PRCM GPIOCR config function in case ALTC 17513a198059SLinus Walleij * has been selected: 17523a198059SLinus Walleij * - If selection is a ALTCx, some bits in PRCM GPIOCR registers 17533a198059SLinus Walleij * must be set. 17543a198059SLinus Walleij * - If selection is pure ALTC and previous selection was ALTCx, 17553a198059SLinus Walleij * then some bits in PRCM GPIOCR registers must be cleared. 17563a198059SLinus Walleij */ 17573a198059SLinus Walleij if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C) 17583a198059SLinus Walleij nmk_prcm_altcx_set_mode(npct, g->pins[i], 17593a198059SLinus Walleij g->altsetting >> NMK_GPIO_ALT_CX_SHIFT); 17603a198059SLinus Walleij } 17613a198059SLinus Walleij 17623a198059SLinus Walleij /* When all pins are successfully reconfigured we get here */ 17633a198059SLinus Walleij ret = 0; 17643a198059SLinus Walleij 17653a198059SLinus Walleij out_glitch: 17663a198059SLinus Walleij if (glitch) { 17673a198059SLinus Walleij nmk_gpio_glitch_slpm_restore(slpm); 17683a198059SLinus Walleij spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 17693a198059SLinus Walleij } 17703a198059SLinus Walleij 17713a198059SLinus Walleij return ret; 17723a198059SLinus Walleij } 17733a198059SLinus Walleij 17743a198059SLinus Walleij static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev, 17753a198059SLinus Walleij struct pinctrl_gpio_range *range, 17763a198059SLinus Walleij unsigned offset) 17773a198059SLinus Walleij { 17783a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 17793a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip; 17803a198059SLinus Walleij struct gpio_chip *chip; 17813a198059SLinus Walleij unsigned bit; 17823a198059SLinus Walleij 17833a198059SLinus Walleij if (!range) { 17843a198059SLinus Walleij dev_err(npct->dev, "invalid range\n"); 17853a198059SLinus Walleij return -EINVAL; 17863a198059SLinus Walleij } 17873a198059SLinus Walleij if (!range->gc) { 17883a198059SLinus Walleij dev_err(npct->dev, "missing GPIO chip in range\n"); 17893a198059SLinus Walleij return -EINVAL; 17903a198059SLinus Walleij } 17913a198059SLinus Walleij chip = range->gc; 17923a198059SLinus Walleij nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); 17933a198059SLinus Walleij 17943a198059SLinus Walleij dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); 17953a198059SLinus Walleij 17963a198059SLinus Walleij clk_enable(nmk_chip->clk); 17973a198059SLinus Walleij bit = offset % NMK_GPIO_PER_CHIP; 17983a198059SLinus Walleij /* There is no glitch when converting any pin to GPIO */ 17993a198059SLinus Walleij __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); 18003a198059SLinus Walleij clk_disable(nmk_chip->clk); 18013a198059SLinus Walleij 18023a198059SLinus Walleij return 0; 18033a198059SLinus Walleij } 18043a198059SLinus Walleij 18053a198059SLinus Walleij static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev, 18063a198059SLinus Walleij struct pinctrl_gpio_range *range, 18073a198059SLinus Walleij unsigned offset) 18083a198059SLinus Walleij { 18093a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 18103a198059SLinus Walleij 18113a198059SLinus Walleij dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); 18123a198059SLinus Walleij /* Set the pin to some default state, GPIO is usually default */ 18133a198059SLinus Walleij } 18143a198059SLinus Walleij 18153a198059SLinus Walleij static const struct pinmux_ops nmk_pinmux_ops = { 18163a198059SLinus Walleij .get_functions_count = nmk_pmx_get_funcs_cnt, 18173a198059SLinus Walleij .get_function_name = nmk_pmx_get_func_name, 18183a198059SLinus Walleij .get_function_groups = nmk_pmx_get_func_groups, 181903e9f0caSLinus Walleij .set_mux = nmk_pmx_set, 18203a198059SLinus Walleij .gpio_request_enable = nmk_gpio_request_enable, 18213a198059SLinus Walleij .gpio_disable_free = nmk_gpio_disable_free, 1822a21763a0SLinus Walleij .strict = true, 18233a198059SLinus Walleij }; 18243a198059SLinus Walleij 18253a198059SLinus Walleij static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, 18263a198059SLinus Walleij unsigned long *config) 18273a198059SLinus Walleij { 18283a198059SLinus Walleij /* Not implemented */ 18293a198059SLinus Walleij return -EINVAL; 18303a198059SLinus Walleij } 18313a198059SLinus Walleij 18323a198059SLinus Walleij static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, 18333a198059SLinus Walleij unsigned long *configs, unsigned num_configs) 18343a198059SLinus Walleij { 18353a198059SLinus Walleij static const char *pullnames[] = { 18363a198059SLinus Walleij [NMK_GPIO_PULL_NONE] = "none", 18373a198059SLinus Walleij [NMK_GPIO_PULL_UP] = "up", 18383a198059SLinus Walleij [NMK_GPIO_PULL_DOWN] = "down", 18393a198059SLinus Walleij [3] /* illegal */ = "??" 18403a198059SLinus Walleij }; 18413a198059SLinus Walleij static const char *slpmnames[] = { 18423a198059SLinus Walleij [NMK_GPIO_SLPM_INPUT] = "input/wakeup", 18433a198059SLinus Walleij [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", 18443a198059SLinus Walleij }; 18453a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 18463a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip; 18473a198059SLinus Walleij unsigned bit; 18483a198059SLinus Walleij pin_cfg_t cfg; 18493a198059SLinus Walleij int pull, slpm, output, val, i; 18503a198059SLinus Walleij bool lowemi, gpiomode, sleep; 18513a198059SLinus Walleij 18526ca7d2e3SLinus Walleij nmk_chip = find_nmk_gpio_from_pin(pin); 18536ca7d2e3SLinus Walleij if (!nmk_chip) { 18546ca7d2e3SLinus Walleij dev_err(npct->dev, 18556ca7d2e3SLinus Walleij "invalid pin offset %d\n", pin); 18563a198059SLinus Walleij return -EINVAL; 18573a198059SLinus Walleij } 18583a198059SLinus Walleij 18593a198059SLinus Walleij for (i = 0; i < num_configs; i++) { 18603a198059SLinus Walleij /* 18613a198059SLinus Walleij * The pin config contains pin number and altfunction fields, 18623a198059SLinus Walleij * here we just ignore that part. It's being handled by the 18633a198059SLinus Walleij * framework and pinmux callback respectively. 18643a198059SLinus Walleij */ 18653a198059SLinus Walleij cfg = (pin_cfg_t) configs[i]; 18663a198059SLinus Walleij pull = PIN_PULL(cfg); 18673a198059SLinus Walleij slpm = PIN_SLPM(cfg); 18683a198059SLinus Walleij output = PIN_DIR(cfg); 18693a198059SLinus Walleij val = PIN_VAL(cfg); 18703a198059SLinus Walleij lowemi = PIN_LOWEMI(cfg); 18713a198059SLinus Walleij gpiomode = PIN_GPIOMODE(cfg); 18723a198059SLinus Walleij sleep = PIN_SLEEPMODE(cfg); 18733a198059SLinus Walleij 18743a198059SLinus Walleij if (sleep) { 18753a198059SLinus Walleij int slpm_pull = PIN_SLPM_PULL(cfg); 18763a198059SLinus Walleij int slpm_output = PIN_SLPM_DIR(cfg); 18773a198059SLinus Walleij int slpm_val = PIN_SLPM_VAL(cfg); 18783a198059SLinus Walleij 18793a198059SLinus Walleij /* All pins go into GPIO mode at sleep */ 18803a198059SLinus Walleij gpiomode = true; 18813a198059SLinus Walleij 18823a198059SLinus Walleij /* 18833a198059SLinus Walleij * The SLPM_* values are normal values + 1 to allow zero 18843a198059SLinus Walleij * to mean "same as normal". 18853a198059SLinus Walleij */ 18863a198059SLinus Walleij if (slpm_pull) 18873a198059SLinus Walleij pull = slpm_pull - 1; 18883a198059SLinus Walleij if (slpm_output) 18893a198059SLinus Walleij output = slpm_output - 1; 18903a198059SLinus Walleij if (slpm_val) 18913a198059SLinus Walleij val = slpm_val - 1; 18923a198059SLinus Walleij 18933a198059SLinus Walleij dev_dbg(nmk_chip->chip.dev, 18943a198059SLinus Walleij "pin %d: sleep pull %s, dir %s, val %s\n", 18953a198059SLinus Walleij pin, 18963a198059SLinus Walleij slpm_pull ? pullnames[pull] : "same", 18973a198059SLinus Walleij slpm_output ? (output ? "output" : "input") 18983a198059SLinus Walleij : "same", 18993a198059SLinus Walleij slpm_val ? (val ? "high" : "low") : "same"); 19003a198059SLinus Walleij } 19013a198059SLinus Walleij 19023a198059SLinus Walleij dev_dbg(nmk_chip->chip.dev, 19033a198059SLinus Walleij "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n", 19043a198059SLinus Walleij pin, cfg, pullnames[pull], slpmnames[slpm], 19053a198059SLinus Walleij output ? "output " : "input", 19063a198059SLinus Walleij output ? (val ? "high" : "low") : "", 19073a198059SLinus Walleij lowemi ? "on" : "off"); 19083a198059SLinus Walleij 19093a198059SLinus Walleij clk_enable(nmk_chip->clk); 19103a198059SLinus Walleij bit = pin % NMK_GPIO_PER_CHIP; 19113a198059SLinus Walleij if (gpiomode) 19123a198059SLinus Walleij /* No glitch when going to GPIO mode */ 19133a198059SLinus Walleij __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); 19143a198059SLinus Walleij if (output) 19153a198059SLinus Walleij __nmk_gpio_make_output(nmk_chip, bit, val); 19163a198059SLinus Walleij else { 19173a198059SLinus Walleij __nmk_gpio_make_input(nmk_chip, bit); 19183a198059SLinus Walleij __nmk_gpio_set_pull(nmk_chip, bit, pull); 19193a198059SLinus Walleij } 19203a198059SLinus Walleij /* TODO: isn't this only applicable on output pins? */ 19213a198059SLinus Walleij __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi); 19223a198059SLinus Walleij 19233a198059SLinus Walleij __nmk_gpio_set_slpm(nmk_chip, bit, slpm); 19243a198059SLinus Walleij clk_disable(nmk_chip->clk); 19253a198059SLinus Walleij } /* for each config */ 19263a198059SLinus Walleij 19273a198059SLinus Walleij return 0; 19283a198059SLinus Walleij } 19293a198059SLinus Walleij 19303a198059SLinus Walleij static const struct pinconf_ops nmk_pinconf_ops = { 19313a198059SLinus Walleij .pin_config_get = nmk_pin_config_get, 19323a198059SLinus Walleij .pin_config_set = nmk_pin_config_set, 19333a198059SLinus Walleij }; 19343a198059SLinus Walleij 19353a198059SLinus Walleij static struct pinctrl_desc nmk_pinctrl_desc = { 19363a198059SLinus Walleij .name = "pinctrl-nomadik", 19373a198059SLinus Walleij .pctlops = &nmk_pinctrl_ops, 19383a198059SLinus Walleij .pmxops = &nmk_pinmux_ops, 19393a198059SLinus Walleij .confops = &nmk_pinconf_ops, 19403a198059SLinus Walleij .owner = THIS_MODULE, 19413a198059SLinus Walleij }; 19423a198059SLinus Walleij 19433a198059SLinus Walleij static const struct of_device_id nmk_pinctrl_match[] = { 19443a198059SLinus Walleij { 19453a198059SLinus Walleij .compatible = "stericsson,stn8815-pinctrl", 19463a198059SLinus Walleij .data = (void *)PINCTRL_NMK_STN8815, 19473a198059SLinus Walleij }, 19483a198059SLinus Walleij { 19493a198059SLinus Walleij .compatible = "stericsson,db8500-pinctrl", 19503a198059SLinus Walleij .data = (void *)PINCTRL_NMK_DB8500, 19513a198059SLinus Walleij }, 19523a198059SLinus Walleij { 19533a198059SLinus Walleij .compatible = "stericsson,db8540-pinctrl", 19543a198059SLinus Walleij .data = (void *)PINCTRL_NMK_DB8540, 19553a198059SLinus Walleij }, 19563a198059SLinus Walleij {}, 19573a198059SLinus Walleij }; 19583a198059SLinus Walleij 19593a198059SLinus Walleij #ifdef CONFIG_PM_SLEEP 19603a198059SLinus Walleij static int nmk_pinctrl_suspend(struct device *dev) 19613a198059SLinus Walleij { 19623a198059SLinus Walleij struct nmk_pinctrl *npct; 19633a198059SLinus Walleij 19643a198059SLinus Walleij npct = dev_get_drvdata(dev); 19653a198059SLinus Walleij if (!npct) 19663a198059SLinus Walleij return -EINVAL; 19673a198059SLinus Walleij 19683a198059SLinus Walleij return pinctrl_force_sleep(npct->pctl); 19693a198059SLinus Walleij } 19703a198059SLinus Walleij 19713a198059SLinus Walleij static int nmk_pinctrl_resume(struct device *dev) 19723a198059SLinus Walleij { 19733a198059SLinus Walleij struct nmk_pinctrl *npct; 19743a198059SLinus Walleij 19753a198059SLinus Walleij npct = dev_get_drvdata(dev); 19763a198059SLinus Walleij if (!npct) 19773a198059SLinus Walleij return -EINVAL; 19783a198059SLinus Walleij 19793a198059SLinus Walleij return pinctrl_force_default(npct->pctl); 19803a198059SLinus Walleij } 19813a198059SLinus Walleij #endif 19823a198059SLinus Walleij 19833a198059SLinus Walleij static int nmk_pinctrl_probe(struct platform_device *pdev) 19843a198059SLinus Walleij { 19853a198059SLinus Walleij const struct of_device_id *match; 19863a198059SLinus Walleij struct device_node *np = pdev->dev.of_node; 19873a198059SLinus Walleij struct device_node *prcm_np; 19883a198059SLinus Walleij struct nmk_pinctrl *npct; 19893a198059SLinus Walleij unsigned int version = 0; 19903a198059SLinus Walleij int i; 19913a198059SLinus Walleij 19923a198059SLinus Walleij npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL); 19933a198059SLinus Walleij if (!npct) 19943a198059SLinus Walleij return -ENOMEM; 19953a198059SLinus Walleij 19963a198059SLinus Walleij match = of_match_device(nmk_pinctrl_match, &pdev->dev); 19973a198059SLinus Walleij if (!match) 19983a198059SLinus Walleij return -ENODEV; 19993a198059SLinus Walleij version = (unsigned int) match->data; 20003a198059SLinus Walleij 20013a198059SLinus Walleij /* Poke in other ASIC variants here */ 20023a198059SLinus Walleij if (version == PINCTRL_NMK_STN8815) 20033a198059SLinus Walleij nmk_pinctrl_stn8815_init(&npct->soc); 20043a198059SLinus Walleij if (version == PINCTRL_NMK_DB8500) 20053a198059SLinus Walleij nmk_pinctrl_db8500_init(&npct->soc); 20063a198059SLinus Walleij if (version == PINCTRL_NMK_DB8540) 20073a198059SLinus Walleij nmk_pinctrl_db8540_init(&npct->soc); 20083a198059SLinus Walleij 2009ab4a9362SLinus Walleij /* 2010ab4a9362SLinus Walleij * Since we depend on the GPIO chips to provide clock and register base 2011ab4a9362SLinus Walleij * for the pin control operations, make sure that we have these 2012ab4a9362SLinus Walleij * populated before we continue. Follow the phandles to instantiate 2013ab4a9362SLinus Walleij * them. The GPIO portion of the actual hardware may be probed before 2014ab4a9362SLinus Walleij * or after this point: it shouldn't matter as the APIs are orthogonal. 2015ab4a9362SLinus Walleij */ 2016ab4a9362SLinus Walleij for (i = 0; i < NMK_MAX_BANKS; i++) { 2017ab4a9362SLinus Walleij struct device_node *gpio_np; 2018ab4a9362SLinus Walleij struct nmk_gpio_chip *nmk_chip; 2019ab4a9362SLinus Walleij 2020ab4a9362SLinus Walleij gpio_np = of_parse_phandle(np, "nomadik-gpio-chips", i); 2021ab4a9362SLinus Walleij if (gpio_np) { 2022ab4a9362SLinus Walleij dev_info(&pdev->dev, 2023ab4a9362SLinus Walleij "populate NMK GPIO %d \"%s\"\n", 2024ab4a9362SLinus Walleij i, gpio_np->name); 2025ab4a9362SLinus Walleij nmk_chip = nmk_gpio_populate_chip(gpio_np, pdev); 2026ab4a9362SLinus Walleij if (IS_ERR(nmk_chip)) 2027ab4a9362SLinus Walleij dev_err(&pdev->dev, 2028ab4a9362SLinus Walleij "could not populate nmk chip struct " 2029ab4a9362SLinus Walleij "- continue anyway\n"); 2030ab4a9362SLinus Walleij of_node_put(gpio_np); 2031ab4a9362SLinus Walleij } 2032ab4a9362SLinus Walleij } 2033ab4a9362SLinus Walleij 20343a198059SLinus Walleij prcm_np = of_parse_phandle(np, "prcm", 0); 20353a198059SLinus Walleij if (prcm_np) 20363a198059SLinus Walleij npct->prcm_base = of_iomap(prcm_np, 0); 20373a198059SLinus Walleij if (!npct->prcm_base) { 20383a198059SLinus Walleij if (version == PINCTRL_NMK_STN8815) { 20393a198059SLinus Walleij dev_info(&pdev->dev, 20403a198059SLinus Walleij "No PRCM base, " 20413a198059SLinus Walleij "assuming no ALT-Cx control is available\n"); 20423a198059SLinus Walleij } else { 20433a198059SLinus Walleij dev_err(&pdev->dev, "missing PRCM base address\n"); 20443a198059SLinus Walleij return -EINVAL; 20453a198059SLinus Walleij } 20463a198059SLinus Walleij } 20473a198059SLinus Walleij 20483a198059SLinus Walleij nmk_pinctrl_desc.pins = npct->soc->pins; 20493a198059SLinus Walleij nmk_pinctrl_desc.npins = npct->soc->npins; 20503a198059SLinus Walleij npct->dev = &pdev->dev; 20513a198059SLinus Walleij 20523a198059SLinus Walleij npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct); 2053323de9efSMasahiro Yamada if (IS_ERR(npct->pctl)) { 20543a198059SLinus Walleij dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n"); 2055323de9efSMasahiro Yamada return PTR_ERR(npct->pctl); 20563a198059SLinus Walleij } 20573a198059SLinus Walleij 20583a198059SLinus Walleij platform_set_drvdata(pdev, npct); 20593a198059SLinus Walleij dev_info(&pdev->dev, "initialized Nomadik pin control driver\n"); 20603a198059SLinus Walleij 20613a198059SLinus Walleij return 0; 20623a198059SLinus Walleij } 20633a198059SLinus Walleij 20643a198059SLinus Walleij static const struct of_device_id nmk_gpio_match[] = { 20653a198059SLinus Walleij { .compatible = "st,nomadik-gpio", }, 20663a198059SLinus Walleij {} 20673a198059SLinus Walleij }; 20683a198059SLinus Walleij 20693a198059SLinus Walleij static struct platform_driver nmk_gpio_driver = { 20703a198059SLinus Walleij .driver = { 20713a198059SLinus Walleij .name = "gpio", 20723a198059SLinus Walleij .of_match_table = nmk_gpio_match, 20733a198059SLinus Walleij }, 20743a198059SLinus Walleij .probe = nmk_gpio_probe, 20753a198059SLinus Walleij }; 20763a198059SLinus Walleij 20773a198059SLinus Walleij static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops, 20783a198059SLinus Walleij nmk_pinctrl_suspend, 20793a198059SLinus Walleij nmk_pinctrl_resume); 20803a198059SLinus Walleij 20813a198059SLinus Walleij static struct platform_driver nmk_pinctrl_driver = { 20823a198059SLinus Walleij .driver = { 20833a198059SLinus Walleij .name = "pinctrl-nomadik", 20843a198059SLinus Walleij .of_match_table = nmk_pinctrl_match, 20853a198059SLinus Walleij .pm = &nmk_pinctrl_pm_ops, 20863a198059SLinus Walleij }, 20873a198059SLinus Walleij .probe = nmk_pinctrl_probe, 20883a198059SLinus Walleij }; 20893a198059SLinus Walleij 20903a198059SLinus Walleij static int __init nmk_gpio_init(void) 20913a198059SLinus Walleij { 2092802bb9b6SLinus Walleij return platform_driver_register(&nmk_gpio_driver); 2093802bb9b6SLinus Walleij } 2094802bb9b6SLinus Walleij subsys_initcall(nmk_gpio_init); 20953a198059SLinus Walleij 2096802bb9b6SLinus Walleij static int __init nmk_pinctrl_init(void) 2097802bb9b6SLinus Walleij { 20983a198059SLinus Walleij return platform_driver_register(&nmk_pinctrl_driver); 20993a198059SLinus Walleij } 2100802bb9b6SLinus Walleij core_initcall(nmk_pinctrl_init); 21013a198059SLinus Walleij 21023a198059SLinus Walleij MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini"); 21033a198059SLinus Walleij MODULE_DESCRIPTION("Nomadik GPIO Driver"); 21043a198059SLinus Walleij MODULE_LICENSE("GPL"); 2105