13a198059SLinus Walleij /* 23a198059SLinus Walleij * Generic GPIO driver for logic cells found in the Nomadik SoC 33a198059SLinus Walleij * 43a198059SLinus Walleij * Copyright (C) 2008,2009 STMicroelectronics 53a198059SLinus Walleij * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> 63a198059SLinus Walleij * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> 73a198059SLinus Walleij * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org> 83a198059SLinus Walleij * 93a198059SLinus Walleij * This program is free software; you can redistribute it and/or modify 103a198059SLinus Walleij * it under the terms of the GNU General Public License version 2 as 113a198059SLinus Walleij * published by the Free Software Foundation. 123a198059SLinus Walleij */ 133a198059SLinus Walleij #include <linux/kernel.h> 143a198059SLinus Walleij #include <linux/module.h> 153a198059SLinus Walleij #include <linux/init.h> 163a198059SLinus Walleij #include <linux/device.h> 173a198059SLinus Walleij #include <linux/platform_device.h> 183a198059SLinus Walleij #include <linux/io.h> 193a198059SLinus Walleij #include <linux/clk.h> 203a198059SLinus Walleij #include <linux/err.h> 213a198059SLinus Walleij #include <linux/gpio.h> 223a198059SLinus Walleij #include <linux/spinlock.h> 233a198059SLinus Walleij #include <linux/interrupt.h> 243a198059SLinus Walleij #include <linux/slab.h> 253a198059SLinus Walleij #include <linux/of_device.h> 263a198059SLinus Walleij #include <linux/of_address.h> 273a198059SLinus Walleij #include <linux/pinctrl/machine.h> 283a198059SLinus Walleij #include <linux/pinctrl/pinctrl.h> 293a198059SLinus Walleij #include <linux/pinctrl/pinmux.h> 303a198059SLinus Walleij #include <linux/pinctrl/pinconf.h> 313a198059SLinus Walleij /* Since we request GPIOs from ourself */ 323a198059SLinus Walleij #include <linux/pinctrl/consumer.h> 333a198059SLinus Walleij #include "pinctrl-nomadik.h" 343a198059SLinus Walleij #include "../core.h" 35ba388294SLinus Walleij #include "../pinctrl-utils.h" 363a198059SLinus Walleij 373a198059SLinus Walleij /* 383a198059SLinus Walleij * The GPIO module in the Nomadik family of Systems-on-Chip is an 393a198059SLinus Walleij * AMBA device, managing 32 pins and alternate functions. The logic block 403a198059SLinus Walleij * is currently used in the Nomadik and ux500. 413a198059SLinus Walleij * 423a198059SLinus Walleij * Symbols in this file are called "nmk_gpio" for "nomadik gpio" 433a198059SLinus Walleij */ 443a198059SLinus Walleij 453a198059SLinus Walleij /* 463a198059SLinus Walleij * pin configurations are represented by 32-bit integers: 473a198059SLinus Walleij * 483a198059SLinus Walleij * bit 0.. 8 - Pin Number (512 Pins Maximum) 493a198059SLinus Walleij * bit 9..10 - Alternate Function Selection 503a198059SLinus Walleij * bit 11..12 - Pull up/down state 513a198059SLinus Walleij * bit 13 - Sleep mode behaviour 523a198059SLinus Walleij * bit 14 - Direction 533a198059SLinus Walleij * bit 15 - Value (if output) 543a198059SLinus Walleij * bit 16..18 - SLPM pull up/down state 553a198059SLinus Walleij * bit 19..20 - SLPM direction 563a198059SLinus Walleij * bit 21..22 - SLPM Value (if output) 573a198059SLinus Walleij * bit 23..25 - PDIS value (if input) 583a198059SLinus Walleij * bit 26 - Gpio mode 593a198059SLinus Walleij * bit 27 - Sleep mode 603a198059SLinus Walleij * 613a198059SLinus Walleij * to facilitate the definition, the following macros are provided 623a198059SLinus Walleij * 633a198059SLinus Walleij * PIN_CFG_DEFAULT - default config (0): 643a198059SLinus Walleij * pull up/down = disabled 653a198059SLinus Walleij * sleep mode = input/wakeup 663a198059SLinus Walleij * direction = input 673a198059SLinus Walleij * value = low 683a198059SLinus Walleij * SLPM direction = same as normal 693a198059SLinus Walleij * SLPM pull = same as normal 703a198059SLinus Walleij * SLPM value = same as normal 713a198059SLinus Walleij * 723a198059SLinus Walleij * PIN_CFG - default config with alternate function 733a198059SLinus Walleij */ 743a198059SLinus Walleij 753a198059SLinus Walleij typedef unsigned long pin_cfg_t; 763a198059SLinus Walleij 773a198059SLinus Walleij #define PIN_NUM_MASK 0x1ff 783a198059SLinus Walleij #define PIN_NUM(x) ((x) & PIN_NUM_MASK) 793a198059SLinus Walleij 803a198059SLinus Walleij #define PIN_ALT_SHIFT 9 813a198059SLinus Walleij #define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT) 823a198059SLinus Walleij #define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT) 833a198059SLinus Walleij #define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT) 843a198059SLinus Walleij #define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT) 853a198059SLinus Walleij #define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT) 863a198059SLinus Walleij #define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT) 873a198059SLinus Walleij 883a198059SLinus Walleij #define PIN_PULL_SHIFT 11 893a198059SLinus Walleij #define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT) 903a198059SLinus Walleij #define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT) 913a198059SLinus Walleij #define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT) 923a198059SLinus Walleij #define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT) 933a198059SLinus Walleij #define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT) 943a198059SLinus Walleij 953a198059SLinus Walleij #define PIN_SLPM_SHIFT 13 963a198059SLinus Walleij #define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT) 973a198059SLinus Walleij #define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT) 983a198059SLinus Walleij #define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT) 993a198059SLinus Walleij #define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT) 1003a198059SLinus Walleij /* These two replace the above in DB8500v2+ */ 1013a198059SLinus Walleij #define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT) 1023a198059SLinus Walleij #define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT) 1033a198059SLinus Walleij #define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE 1043a198059SLinus Walleij 1053a198059SLinus Walleij #define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */ 1063a198059SLinus Walleij #define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */ 1073a198059SLinus Walleij 1083a198059SLinus Walleij #define PIN_DIR_SHIFT 14 1093a198059SLinus Walleij #define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT) 1103a198059SLinus Walleij #define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT) 1113a198059SLinus Walleij #define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT) 1123a198059SLinus Walleij #define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT) 1133a198059SLinus Walleij 1143a198059SLinus Walleij #define PIN_VAL_SHIFT 15 1153a198059SLinus Walleij #define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT) 1163a198059SLinus Walleij #define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT) 1173a198059SLinus Walleij #define PIN_VAL_LOW (0 << PIN_VAL_SHIFT) 1183a198059SLinus Walleij #define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT) 1193a198059SLinus Walleij 1203a198059SLinus Walleij #define PIN_SLPM_PULL_SHIFT 16 1213a198059SLinus Walleij #define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT) 1223a198059SLinus Walleij #define PIN_SLPM_PULL(x) \ 1233a198059SLinus Walleij (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT) 1243a198059SLinus Walleij #define PIN_SLPM_PULL_NONE \ 1253a198059SLinus Walleij ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT) 1263a198059SLinus Walleij #define PIN_SLPM_PULL_UP \ 1273a198059SLinus Walleij ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT) 1283a198059SLinus Walleij #define PIN_SLPM_PULL_DOWN \ 1293a198059SLinus Walleij ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT) 1303a198059SLinus Walleij 1313a198059SLinus Walleij #define PIN_SLPM_DIR_SHIFT 19 1323a198059SLinus Walleij #define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT) 1333a198059SLinus Walleij #define PIN_SLPM_DIR(x) \ 1343a198059SLinus Walleij (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT) 1353a198059SLinus Walleij #define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT) 1363a198059SLinus Walleij #define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT) 1373a198059SLinus Walleij 1383a198059SLinus Walleij #define PIN_SLPM_VAL_SHIFT 21 1393a198059SLinus Walleij #define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT) 1403a198059SLinus Walleij #define PIN_SLPM_VAL(x) \ 1413a198059SLinus Walleij (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT) 1423a198059SLinus Walleij #define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT) 1433a198059SLinus Walleij #define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT) 1443a198059SLinus Walleij 1453a198059SLinus Walleij #define PIN_SLPM_PDIS_SHIFT 23 1463a198059SLinus Walleij #define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT) 1473a198059SLinus Walleij #define PIN_SLPM_PDIS(x) \ 1483a198059SLinus Walleij (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT) 1493a198059SLinus Walleij #define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT) 1503a198059SLinus Walleij #define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT) 1513a198059SLinus Walleij #define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT) 1523a198059SLinus Walleij 1533a198059SLinus Walleij #define PIN_LOWEMI_SHIFT 25 1543a198059SLinus Walleij #define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT) 1553a198059SLinus Walleij #define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT) 1563a198059SLinus Walleij #define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT) 1573a198059SLinus Walleij #define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT) 1583a198059SLinus Walleij 1593a198059SLinus Walleij #define PIN_GPIOMODE_SHIFT 26 1603a198059SLinus Walleij #define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT) 1613a198059SLinus Walleij #define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT) 1623a198059SLinus Walleij #define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT) 1633a198059SLinus Walleij #define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT) 1643a198059SLinus Walleij 1653a198059SLinus Walleij #define PIN_SLEEPMODE_SHIFT 27 1663a198059SLinus Walleij #define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT) 1673a198059SLinus Walleij #define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT) 1683a198059SLinus Walleij #define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT) 1693a198059SLinus Walleij #define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT) 1703a198059SLinus Walleij 1713a198059SLinus Walleij 1723a198059SLinus Walleij /* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */ 1733a198059SLinus Walleij #define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN) 1743a198059SLinus Walleij #define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP) 1753a198059SLinus Walleij #define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE) 1763a198059SLinus Walleij #define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW) 1773a198059SLinus Walleij #define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH) 1783a198059SLinus Walleij 1793a198059SLinus Walleij #define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN) 1803a198059SLinus Walleij #define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP) 1813a198059SLinus Walleij #define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE) 1823a198059SLinus Walleij #define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW) 1833a198059SLinus Walleij #define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH) 1843a198059SLinus Walleij 1853a198059SLinus Walleij #define PIN_CFG_DEFAULT (0) 1863a198059SLinus Walleij 1873a198059SLinus Walleij #define PIN_CFG(num, alt) \ 1883a198059SLinus Walleij (PIN_CFG_DEFAULT |\ 1893a198059SLinus Walleij (PIN_NUM(num) | PIN_##alt)) 1903a198059SLinus Walleij 1913a198059SLinus Walleij #define PIN_CFG_INPUT(num, alt, pull) \ 1923a198059SLinus Walleij (PIN_CFG_DEFAULT |\ 1933a198059SLinus Walleij (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull)) 1943a198059SLinus Walleij 1953a198059SLinus Walleij #define PIN_CFG_OUTPUT(num, alt, val) \ 1963a198059SLinus Walleij (PIN_CFG_DEFAULT |\ 1973a198059SLinus Walleij (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val)) 1983a198059SLinus Walleij 1993a198059SLinus Walleij /* 2003a198059SLinus Walleij * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving 2013a198059SLinus Walleij * the "gpio" namespace for generic and cross-machine functions 2023a198059SLinus Walleij */ 2033a198059SLinus Walleij 2043a198059SLinus Walleij #define GPIO_BLOCK_SHIFT 5 2053a198059SLinus Walleij #define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT) 2063a198059SLinus Walleij 2073a198059SLinus Walleij /* Register in the logic block */ 2083a198059SLinus Walleij #define NMK_GPIO_DAT 0x00 2093a198059SLinus Walleij #define NMK_GPIO_DATS 0x04 2103a198059SLinus Walleij #define NMK_GPIO_DATC 0x08 2113a198059SLinus Walleij #define NMK_GPIO_PDIS 0x0c 2123a198059SLinus Walleij #define NMK_GPIO_DIR 0x10 2133a198059SLinus Walleij #define NMK_GPIO_DIRS 0x14 2143a198059SLinus Walleij #define NMK_GPIO_DIRC 0x18 2153a198059SLinus Walleij #define NMK_GPIO_SLPC 0x1c 2163a198059SLinus Walleij #define NMK_GPIO_AFSLA 0x20 2173a198059SLinus Walleij #define NMK_GPIO_AFSLB 0x24 2183a198059SLinus Walleij #define NMK_GPIO_LOWEMI 0x28 2193a198059SLinus Walleij 2203a198059SLinus Walleij #define NMK_GPIO_RIMSC 0x40 2213a198059SLinus Walleij #define NMK_GPIO_FIMSC 0x44 2223a198059SLinus Walleij #define NMK_GPIO_IS 0x48 2233a198059SLinus Walleij #define NMK_GPIO_IC 0x4c 2243a198059SLinus Walleij #define NMK_GPIO_RWIMSC 0x50 2253a198059SLinus Walleij #define NMK_GPIO_FWIMSC 0x54 2263a198059SLinus Walleij #define NMK_GPIO_WKS 0x58 2273a198059SLinus Walleij /* These appear in DB8540 and later ASICs */ 2283a198059SLinus Walleij #define NMK_GPIO_EDGELEVEL 0x5C 2293a198059SLinus Walleij #define NMK_GPIO_LEVEL 0x60 2303a198059SLinus Walleij 2313a198059SLinus Walleij 2323a198059SLinus Walleij /* Pull up/down values */ 2333a198059SLinus Walleij enum nmk_gpio_pull { 2343a198059SLinus Walleij NMK_GPIO_PULL_NONE, 2353a198059SLinus Walleij NMK_GPIO_PULL_UP, 2363a198059SLinus Walleij NMK_GPIO_PULL_DOWN, 2373a198059SLinus Walleij }; 2383a198059SLinus Walleij 2393a198059SLinus Walleij /* Sleep mode */ 2403a198059SLinus Walleij enum nmk_gpio_slpm { 2413a198059SLinus Walleij NMK_GPIO_SLPM_INPUT, 2423a198059SLinus Walleij NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT, 2433a198059SLinus Walleij NMK_GPIO_SLPM_NOCHANGE, 2443a198059SLinus Walleij NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE, 2453a198059SLinus Walleij }; 2463a198059SLinus Walleij 2473a198059SLinus Walleij struct nmk_gpio_chip { 2483a198059SLinus Walleij struct gpio_chip chip; 2493a198059SLinus Walleij void __iomem *addr; 2503a198059SLinus Walleij struct clk *clk; 2513a198059SLinus Walleij unsigned int bank; 2523a198059SLinus Walleij unsigned int parent_irq; 2533a198059SLinus Walleij int latent_parent_irq; 2543a198059SLinus Walleij u32 (*get_latent_status)(unsigned int bank); 2553a198059SLinus Walleij void (*set_ioforce)(bool enable); 2563a198059SLinus Walleij spinlock_t lock; 2573a198059SLinus Walleij bool sleepmode; 2583a198059SLinus Walleij /* Keep track of configured edges */ 2593a198059SLinus Walleij u32 edge_rising; 2603a198059SLinus Walleij u32 edge_falling; 2613a198059SLinus Walleij u32 real_wake; 2623a198059SLinus Walleij u32 rwimsc; 2633a198059SLinus Walleij u32 fwimsc; 2643a198059SLinus Walleij u32 rimsc; 2653a198059SLinus Walleij u32 fimsc; 2663a198059SLinus Walleij u32 pull_up; 2673a198059SLinus Walleij u32 lowemi; 2683a198059SLinus Walleij }; 2693a198059SLinus Walleij 2703a198059SLinus Walleij /** 2713a198059SLinus Walleij * struct nmk_pinctrl - state container for the Nomadik pin controller 2723a198059SLinus Walleij * @dev: containing device pointer 2733a198059SLinus Walleij * @pctl: corresponding pin controller device 2743a198059SLinus Walleij * @soc: SoC data for this specific chip 2753a198059SLinus Walleij * @prcm_base: PRCM register range virtual base 2763a198059SLinus Walleij */ 2773a198059SLinus Walleij struct nmk_pinctrl { 2783a198059SLinus Walleij struct device *dev; 2793a198059SLinus Walleij struct pinctrl_dev *pctl; 2803a198059SLinus Walleij const struct nmk_pinctrl_soc_data *soc; 2813a198059SLinus Walleij void __iomem *prcm_base; 2823a198059SLinus Walleij }; 2833a198059SLinus Walleij 2843a198059SLinus Walleij static struct nmk_gpio_chip * 2853a198059SLinus Walleij nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)]; 2863a198059SLinus Walleij 2873a198059SLinus Walleij static DEFINE_SPINLOCK(nmk_gpio_slpm_lock); 2883a198059SLinus Walleij 2893a198059SLinus Walleij #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips) 2903a198059SLinus Walleij 2913a198059SLinus Walleij static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, 2923a198059SLinus Walleij unsigned offset, int gpio_mode) 2933a198059SLinus Walleij { 2943a198059SLinus Walleij u32 bit = 1 << offset; 2953a198059SLinus Walleij u32 afunc, bfunc; 2963a198059SLinus Walleij 2973a198059SLinus Walleij afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit; 2983a198059SLinus Walleij bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit; 2993a198059SLinus Walleij if (gpio_mode & NMK_GPIO_ALT_A) 3003a198059SLinus Walleij afunc |= bit; 3013a198059SLinus Walleij if (gpio_mode & NMK_GPIO_ALT_B) 3023a198059SLinus Walleij bfunc |= bit; 3033a198059SLinus Walleij writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); 3043a198059SLinus Walleij writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); 3053a198059SLinus Walleij } 3063a198059SLinus Walleij 3073a198059SLinus Walleij static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, 3083a198059SLinus Walleij unsigned offset, enum nmk_gpio_slpm mode) 3093a198059SLinus Walleij { 3103a198059SLinus Walleij u32 bit = 1 << offset; 3113a198059SLinus Walleij u32 slpm; 3123a198059SLinus Walleij 3133a198059SLinus Walleij slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); 3143a198059SLinus Walleij if (mode == NMK_GPIO_SLPM_NOCHANGE) 3153a198059SLinus Walleij slpm |= bit; 3163a198059SLinus Walleij else 3173a198059SLinus Walleij slpm &= ~bit; 3183a198059SLinus Walleij writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); 3193a198059SLinus Walleij } 3203a198059SLinus Walleij 3213a198059SLinus Walleij static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, 3223a198059SLinus Walleij unsigned offset, enum nmk_gpio_pull pull) 3233a198059SLinus Walleij { 3243a198059SLinus Walleij u32 bit = 1 << offset; 3253a198059SLinus Walleij u32 pdis; 3263a198059SLinus Walleij 3273a198059SLinus Walleij pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); 3283a198059SLinus Walleij if (pull == NMK_GPIO_PULL_NONE) { 3293a198059SLinus Walleij pdis |= bit; 3303a198059SLinus Walleij nmk_chip->pull_up &= ~bit; 3313a198059SLinus Walleij } else { 3323a198059SLinus Walleij pdis &= ~bit; 3333a198059SLinus Walleij } 3343a198059SLinus Walleij 3353a198059SLinus Walleij writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); 3363a198059SLinus Walleij 3373a198059SLinus Walleij if (pull == NMK_GPIO_PULL_UP) { 3383a198059SLinus Walleij nmk_chip->pull_up |= bit; 3393a198059SLinus Walleij writel(bit, nmk_chip->addr + NMK_GPIO_DATS); 3403a198059SLinus Walleij } else if (pull == NMK_GPIO_PULL_DOWN) { 3413a198059SLinus Walleij nmk_chip->pull_up &= ~bit; 3423a198059SLinus Walleij writel(bit, nmk_chip->addr + NMK_GPIO_DATC); 3433a198059SLinus Walleij } 3443a198059SLinus Walleij } 3453a198059SLinus Walleij 3463a198059SLinus Walleij static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip, 3473a198059SLinus Walleij unsigned offset, bool lowemi) 3483a198059SLinus Walleij { 3493a198059SLinus Walleij u32 bit = BIT(offset); 3503a198059SLinus Walleij bool enabled = nmk_chip->lowemi & bit; 3513a198059SLinus Walleij 3523a198059SLinus Walleij if (lowemi == enabled) 3533a198059SLinus Walleij return; 3543a198059SLinus Walleij 3553a198059SLinus Walleij if (lowemi) 3563a198059SLinus Walleij nmk_chip->lowemi |= bit; 3573a198059SLinus Walleij else 3583a198059SLinus Walleij nmk_chip->lowemi &= ~bit; 3593a198059SLinus Walleij 3603a198059SLinus Walleij writel_relaxed(nmk_chip->lowemi, 3613a198059SLinus Walleij nmk_chip->addr + NMK_GPIO_LOWEMI); 3623a198059SLinus Walleij } 3633a198059SLinus Walleij 3643a198059SLinus Walleij static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, 3653a198059SLinus Walleij unsigned offset) 3663a198059SLinus Walleij { 3673a198059SLinus Walleij writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); 3683a198059SLinus Walleij } 3693a198059SLinus Walleij 3703a198059SLinus Walleij static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, 3713a198059SLinus Walleij unsigned offset, int val) 3723a198059SLinus Walleij { 3733a198059SLinus Walleij if (val) 3743a198059SLinus Walleij writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS); 3753a198059SLinus Walleij else 3763a198059SLinus Walleij writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC); 3773a198059SLinus Walleij } 3783a198059SLinus Walleij 3793a198059SLinus Walleij static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, 3803a198059SLinus Walleij unsigned offset, int val) 3813a198059SLinus Walleij { 3823a198059SLinus Walleij writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS); 3833a198059SLinus Walleij __nmk_gpio_set_output(nmk_chip, offset, val); 3843a198059SLinus Walleij } 3853a198059SLinus Walleij 3863a198059SLinus Walleij static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, 3873a198059SLinus Walleij unsigned offset, int gpio_mode, 3883a198059SLinus Walleij bool glitch) 3893a198059SLinus Walleij { 3903a198059SLinus Walleij u32 rwimsc = nmk_chip->rwimsc; 3913a198059SLinus Walleij u32 fwimsc = nmk_chip->fwimsc; 3923a198059SLinus Walleij 3933a198059SLinus Walleij if (glitch && nmk_chip->set_ioforce) { 3943a198059SLinus Walleij u32 bit = BIT(offset); 3953a198059SLinus Walleij 3963a198059SLinus Walleij /* Prevent spurious wakeups */ 3973a198059SLinus Walleij writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC); 3983a198059SLinus Walleij writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC); 3993a198059SLinus Walleij 4003a198059SLinus Walleij nmk_chip->set_ioforce(true); 4013a198059SLinus Walleij } 4023a198059SLinus Walleij 4033a198059SLinus Walleij __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode); 4043a198059SLinus Walleij 4053a198059SLinus Walleij if (glitch && nmk_chip->set_ioforce) { 4063a198059SLinus Walleij nmk_chip->set_ioforce(false); 4073a198059SLinus Walleij 4083a198059SLinus Walleij writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC); 4093a198059SLinus Walleij writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC); 4103a198059SLinus Walleij } 4113a198059SLinus Walleij } 4123a198059SLinus Walleij 4133a198059SLinus Walleij static void 4143a198059SLinus Walleij nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset) 4153a198059SLinus Walleij { 4163a198059SLinus Walleij u32 falling = nmk_chip->fimsc & BIT(offset); 4173a198059SLinus Walleij u32 rising = nmk_chip->rimsc & BIT(offset); 4183a198059SLinus Walleij int gpio = nmk_chip->chip.base + offset; 4193a198059SLinus Walleij int irq = irq_find_mapping(nmk_chip->chip.irqdomain, offset); 4203a198059SLinus Walleij struct irq_data *d = irq_get_irq_data(irq); 4213a198059SLinus Walleij 4223a198059SLinus Walleij if (!rising && !falling) 4233a198059SLinus Walleij return; 4243a198059SLinus Walleij 4253a198059SLinus Walleij if (!d || !irqd_irq_disabled(d)) 4263a198059SLinus Walleij return; 4273a198059SLinus Walleij 4283a198059SLinus Walleij if (rising) { 4293a198059SLinus Walleij nmk_chip->rimsc &= ~BIT(offset); 4303a198059SLinus Walleij writel_relaxed(nmk_chip->rimsc, 4313a198059SLinus Walleij nmk_chip->addr + NMK_GPIO_RIMSC); 4323a198059SLinus Walleij } 4333a198059SLinus Walleij 4343a198059SLinus Walleij if (falling) { 4353a198059SLinus Walleij nmk_chip->fimsc &= ~BIT(offset); 4363a198059SLinus Walleij writel_relaxed(nmk_chip->fimsc, 4373a198059SLinus Walleij nmk_chip->addr + NMK_GPIO_FIMSC); 4383a198059SLinus Walleij } 4393a198059SLinus Walleij 4403a198059SLinus Walleij dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio); 4413a198059SLinus Walleij } 4423a198059SLinus Walleij 4433a198059SLinus Walleij static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value) 4443a198059SLinus Walleij { 4453a198059SLinus Walleij u32 val; 4463a198059SLinus Walleij 4473a198059SLinus Walleij val = readl(reg); 4483a198059SLinus Walleij val = ((val & ~mask) | (value & mask)); 4493a198059SLinus Walleij writel(val, reg); 4503a198059SLinus Walleij } 4513a198059SLinus Walleij 4523a198059SLinus Walleij static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct, 4533a198059SLinus Walleij unsigned offset, unsigned alt_num) 4543a198059SLinus Walleij { 4553a198059SLinus Walleij int i; 4563a198059SLinus Walleij u16 reg; 4573a198059SLinus Walleij u8 bit; 4583a198059SLinus Walleij u8 alt_index; 4593a198059SLinus Walleij const struct prcm_gpiocr_altcx_pin_desc *pin_desc; 4603a198059SLinus Walleij const u16 *gpiocr_regs; 4613a198059SLinus Walleij 4623a198059SLinus Walleij if (!npct->prcm_base) 4633a198059SLinus Walleij return; 4643a198059SLinus Walleij 4653a198059SLinus Walleij if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) { 4663a198059SLinus Walleij dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n", 4673a198059SLinus Walleij alt_num); 4683a198059SLinus Walleij return; 4693a198059SLinus Walleij } 4703a198059SLinus Walleij 4713a198059SLinus Walleij for (i = 0 ; i < npct->soc->npins_altcx ; i++) { 4723a198059SLinus Walleij if (npct->soc->altcx_pins[i].pin == offset) 4733a198059SLinus Walleij break; 4743a198059SLinus Walleij } 4753a198059SLinus Walleij if (i == npct->soc->npins_altcx) { 4763a198059SLinus Walleij dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n", 4773a198059SLinus Walleij offset); 4783a198059SLinus Walleij return; 4793a198059SLinus Walleij } 4803a198059SLinus Walleij 4813a198059SLinus Walleij pin_desc = npct->soc->altcx_pins + i; 4823a198059SLinus Walleij gpiocr_regs = npct->soc->prcm_gpiocr_registers; 4833a198059SLinus Walleij 4843a198059SLinus Walleij /* 4853a198059SLinus Walleij * If alt_num is NULL, just clear current ALTCx selection 4863a198059SLinus Walleij * to make sure we come back to a pure ALTC selection 4873a198059SLinus Walleij */ 4883a198059SLinus Walleij if (!alt_num) { 4893a198059SLinus Walleij for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { 4903a198059SLinus Walleij if (pin_desc->altcx[i].used == true) { 4913a198059SLinus Walleij reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; 4923a198059SLinus Walleij bit = pin_desc->altcx[i].control_bit; 4933a198059SLinus Walleij if (readl(npct->prcm_base + reg) & BIT(bit)) { 4943a198059SLinus Walleij nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); 4953a198059SLinus Walleij dev_dbg(npct->dev, 4963a198059SLinus Walleij "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", 4973a198059SLinus Walleij offset, i+1); 4983a198059SLinus Walleij } 4993a198059SLinus Walleij } 5003a198059SLinus Walleij } 5013a198059SLinus Walleij return; 5023a198059SLinus Walleij } 5033a198059SLinus Walleij 5043a198059SLinus Walleij alt_index = alt_num - 1; 5053a198059SLinus Walleij if (pin_desc->altcx[alt_index].used == false) { 5063a198059SLinus Walleij dev_warn(npct->dev, 5073a198059SLinus Walleij "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n", 5083a198059SLinus Walleij offset, alt_num); 5093a198059SLinus Walleij return; 5103a198059SLinus Walleij } 5113a198059SLinus Walleij 5123a198059SLinus Walleij /* 5133a198059SLinus Walleij * Check if any other ALTCx functions are activated on this pin 5143a198059SLinus Walleij * and disable it first. 5153a198059SLinus Walleij */ 5163a198059SLinus Walleij for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { 5173a198059SLinus Walleij if (i == alt_index) 5183a198059SLinus Walleij continue; 5193a198059SLinus Walleij if (pin_desc->altcx[i].used == true) { 5203a198059SLinus Walleij reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; 5213a198059SLinus Walleij bit = pin_desc->altcx[i].control_bit; 5223a198059SLinus Walleij if (readl(npct->prcm_base + reg) & BIT(bit)) { 5233a198059SLinus Walleij nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); 5243a198059SLinus Walleij dev_dbg(npct->dev, 5253a198059SLinus Walleij "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", 5263a198059SLinus Walleij offset, i+1); 5273a198059SLinus Walleij } 5283a198059SLinus Walleij } 5293a198059SLinus Walleij } 5303a198059SLinus Walleij 5313a198059SLinus Walleij reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index]; 5323a198059SLinus Walleij bit = pin_desc->altcx[alt_index].control_bit; 5333a198059SLinus Walleij dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n", 5343a198059SLinus Walleij offset, alt_index+1); 5353a198059SLinus Walleij nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit)); 5363a198059SLinus Walleij } 5373a198059SLinus Walleij 5383a198059SLinus Walleij /* 5393a198059SLinus Walleij * Safe sequence used to switch IOs between GPIO and Alternate-C mode: 5403a198059SLinus Walleij * - Save SLPM registers 5413a198059SLinus Walleij * - Set SLPM=0 for the IOs you want to switch and others to 1 5423a198059SLinus Walleij * - Configure the GPIO registers for the IOs that are being switched 5433a198059SLinus Walleij * - Set IOFORCE=1 5443a198059SLinus Walleij * - Modify the AFLSA/B registers for the IOs that are being switched 5453a198059SLinus Walleij * - Set IOFORCE=0 5463a198059SLinus Walleij * - Restore SLPM registers 5473a198059SLinus Walleij * - Any spurious wake up event during switch sequence to be ignored and 5483a198059SLinus Walleij * cleared 5493a198059SLinus Walleij */ 5503a198059SLinus Walleij static void nmk_gpio_glitch_slpm_init(unsigned int *slpm) 5513a198059SLinus Walleij { 5523a198059SLinus Walleij int i; 5533a198059SLinus Walleij 5543a198059SLinus Walleij for (i = 0; i < NUM_BANKS; i++) { 5553a198059SLinus Walleij struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 5563a198059SLinus Walleij unsigned int temp = slpm[i]; 5573a198059SLinus Walleij 5583a198059SLinus Walleij if (!chip) 5593a198059SLinus Walleij break; 5603a198059SLinus Walleij 5613a198059SLinus Walleij clk_enable(chip->clk); 5623a198059SLinus Walleij 5633a198059SLinus Walleij slpm[i] = readl(chip->addr + NMK_GPIO_SLPC); 5643a198059SLinus Walleij writel(temp, chip->addr + NMK_GPIO_SLPC); 5653a198059SLinus Walleij } 5663a198059SLinus Walleij } 5673a198059SLinus Walleij 5683a198059SLinus Walleij static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm) 5693a198059SLinus Walleij { 5703a198059SLinus Walleij int i; 5713a198059SLinus Walleij 5723a198059SLinus Walleij for (i = 0; i < NUM_BANKS; i++) { 5733a198059SLinus Walleij struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 5743a198059SLinus Walleij 5753a198059SLinus Walleij if (!chip) 5763a198059SLinus Walleij break; 5773a198059SLinus Walleij 5783a198059SLinus Walleij writel(slpm[i], chip->addr + NMK_GPIO_SLPC); 5793a198059SLinus Walleij 5803a198059SLinus Walleij clk_disable(chip->clk); 5813a198059SLinus Walleij } 5823a198059SLinus Walleij } 5833a198059SLinus Walleij 5843a198059SLinus Walleij static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio) 5853a198059SLinus Walleij { 5863a198059SLinus Walleij int i; 5873a198059SLinus Walleij u16 reg; 5883a198059SLinus Walleij u8 bit; 5893a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 5903a198059SLinus Walleij const struct prcm_gpiocr_altcx_pin_desc *pin_desc; 5913a198059SLinus Walleij const u16 *gpiocr_regs; 5923a198059SLinus Walleij 5933a198059SLinus Walleij if (!npct->prcm_base) 5943a198059SLinus Walleij return NMK_GPIO_ALT_C; 5953a198059SLinus Walleij 5963a198059SLinus Walleij for (i = 0; i < npct->soc->npins_altcx; i++) { 5973a198059SLinus Walleij if (npct->soc->altcx_pins[i].pin == gpio) 5983a198059SLinus Walleij break; 5993a198059SLinus Walleij } 6003a198059SLinus Walleij if (i == npct->soc->npins_altcx) 6013a198059SLinus Walleij return NMK_GPIO_ALT_C; 6023a198059SLinus Walleij 6033a198059SLinus Walleij pin_desc = npct->soc->altcx_pins + i; 6043a198059SLinus Walleij gpiocr_regs = npct->soc->prcm_gpiocr_registers; 6053a198059SLinus Walleij for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) { 6063a198059SLinus Walleij if (pin_desc->altcx[i].used == true) { 6073a198059SLinus Walleij reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; 6083a198059SLinus Walleij bit = pin_desc->altcx[i].control_bit; 6093a198059SLinus Walleij if (readl(npct->prcm_base + reg) & BIT(bit)) 6103a198059SLinus Walleij return NMK_GPIO_ALT_C+i+1; 6113a198059SLinus Walleij } 6123a198059SLinus Walleij } 6133a198059SLinus Walleij return NMK_GPIO_ALT_C; 6143a198059SLinus Walleij } 6153a198059SLinus Walleij 6163a198059SLinus Walleij int nmk_gpio_get_mode(int gpio) 6173a198059SLinus Walleij { 6183a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip; 6193a198059SLinus Walleij u32 afunc, bfunc, bit; 6203a198059SLinus Walleij 6213a198059SLinus Walleij nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; 6223a198059SLinus Walleij if (!nmk_chip) 6233a198059SLinus Walleij return -EINVAL; 6243a198059SLinus Walleij 6253a198059SLinus Walleij bit = 1 << (gpio % NMK_GPIO_PER_CHIP); 6263a198059SLinus Walleij 6273a198059SLinus Walleij clk_enable(nmk_chip->clk); 6283a198059SLinus Walleij 6293a198059SLinus Walleij afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit; 6303a198059SLinus Walleij bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit; 6313a198059SLinus Walleij 6323a198059SLinus Walleij clk_disable(nmk_chip->clk); 6333a198059SLinus Walleij 6343a198059SLinus Walleij return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0); 6353a198059SLinus Walleij } 6363a198059SLinus Walleij EXPORT_SYMBOL(nmk_gpio_get_mode); 6373a198059SLinus Walleij 6383a198059SLinus Walleij 6393a198059SLinus Walleij /* IRQ functions */ 6403a198059SLinus Walleij static inline int nmk_gpio_get_bitmask(int gpio) 6413a198059SLinus Walleij { 6423a198059SLinus Walleij return 1 << (gpio % NMK_GPIO_PER_CHIP); 6433a198059SLinus Walleij } 6443a198059SLinus Walleij 6453a198059SLinus Walleij static void nmk_gpio_irq_ack(struct irq_data *d) 6463a198059SLinus Walleij { 6473a198059SLinus Walleij struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 6483a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); 6493a198059SLinus Walleij 6503a198059SLinus Walleij clk_enable(nmk_chip->clk); 6513a198059SLinus Walleij writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC); 6523a198059SLinus Walleij clk_disable(nmk_chip->clk); 6533a198059SLinus Walleij } 6543a198059SLinus Walleij 6553a198059SLinus Walleij enum nmk_gpio_irq_type { 6563a198059SLinus Walleij NORMAL, 6573a198059SLinus Walleij WAKE, 6583a198059SLinus Walleij }; 6593a198059SLinus Walleij 6603a198059SLinus Walleij static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, 6613a198059SLinus Walleij int gpio, enum nmk_gpio_irq_type which, 6623a198059SLinus Walleij bool enable) 6633a198059SLinus Walleij { 6643a198059SLinus Walleij u32 bitmask = nmk_gpio_get_bitmask(gpio); 6653a198059SLinus Walleij u32 *rimscval; 6663a198059SLinus Walleij u32 *fimscval; 6673a198059SLinus Walleij u32 rimscreg; 6683a198059SLinus Walleij u32 fimscreg; 6693a198059SLinus Walleij 6703a198059SLinus Walleij if (which == NORMAL) { 6713a198059SLinus Walleij rimscreg = NMK_GPIO_RIMSC; 6723a198059SLinus Walleij fimscreg = NMK_GPIO_FIMSC; 6733a198059SLinus Walleij rimscval = &nmk_chip->rimsc; 6743a198059SLinus Walleij fimscval = &nmk_chip->fimsc; 6753a198059SLinus Walleij } else { 6763a198059SLinus Walleij rimscreg = NMK_GPIO_RWIMSC; 6773a198059SLinus Walleij fimscreg = NMK_GPIO_FWIMSC; 6783a198059SLinus Walleij rimscval = &nmk_chip->rwimsc; 6793a198059SLinus Walleij fimscval = &nmk_chip->fwimsc; 6803a198059SLinus Walleij } 6813a198059SLinus Walleij 6823a198059SLinus Walleij /* we must individually set/clear the two edges */ 6833a198059SLinus Walleij if (nmk_chip->edge_rising & bitmask) { 6843a198059SLinus Walleij if (enable) 6853a198059SLinus Walleij *rimscval |= bitmask; 6863a198059SLinus Walleij else 6873a198059SLinus Walleij *rimscval &= ~bitmask; 6883a198059SLinus Walleij writel(*rimscval, nmk_chip->addr + rimscreg); 6893a198059SLinus Walleij } 6903a198059SLinus Walleij if (nmk_chip->edge_falling & bitmask) { 6913a198059SLinus Walleij if (enable) 6923a198059SLinus Walleij *fimscval |= bitmask; 6933a198059SLinus Walleij else 6943a198059SLinus Walleij *fimscval &= ~bitmask; 6953a198059SLinus Walleij writel(*fimscval, nmk_chip->addr + fimscreg); 6963a198059SLinus Walleij } 6973a198059SLinus Walleij } 6983a198059SLinus Walleij 6993a198059SLinus Walleij static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, 7003a198059SLinus Walleij int gpio, bool on) 7013a198059SLinus Walleij { 7023a198059SLinus Walleij /* 7033a198059SLinus Walleij * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is 7043a198059SLinus Walleij * disabled, since setting SLPM to 1 increases power consumption, and 7053a198059SLinus Walleij * wakeup is anyhow controlled by the RIMSC and FIMSC registers. 7063a198059SLinus Walleij */ 7073a198059SLinus Walleij if (nmk_chip->sleepmode && on) { 7083a198059SLinus Walleij __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, 7093a198059SLinus Walleij NMK_GPIO_SLPM_WAKEUP_ENABLE); 7103a198059SLinus Walleij } 7113a198059SLinus Walleij 7123a198059SLinus Walleij __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); 7133a198059SLinus Walleij } 7143a198059SLinus Walleij 7153a198059SLinus Walleij static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) 7163a198059SLinus Walleij { 7173a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip; 7183a198059SLinus Walleij unsigned long flags; 7193a198059SLinus Walleij u32 bitmask; 7203a198059SLinus Walleij 7213a198059SLinus Walleij nmk_chip = irq_data_get_irq_chip_data(d); 7223a198059SLinus Walleij bitmask = nmk_gpio_get_bitmask(d->hwirq); 7233a198059SLinus Walleij if (!nmk_chip) 7243a198059SLinus Walleij return -EINVAL; 7253a198059SLinus Walleij 7263a198059SLinus Walleij clk_enable(nmk_chip->clk); 7273a198059SLinus Walleij spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 7283a198059SLinus Walleij spin_lock(&nmk_chip->lock); 7293a198059SLinus Walleij 7303a198059SLinus Walleij __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable); 7313a198059SLinus Walleij 7323a198059SLinus Walleij if (!(nmk_chip->real_wake & bitmask)) 7333a198059SLinus Walleij __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable); 7343a198059SLinus Walleij 7353a198059SLinus Walleij spin_unlock(&nmk_chip->lock); 7363a198059SLinus Walleij spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 7373a198059SLinus Walleij clk_disable(nmk_chip->clk); 7383a198059SLinus Walleij 7393a198059SLinus Walleij return 0; 7403a198059SLinus Walleij } 7413a198059SLinus Walleij 7423a198059SLinus Walleij static void nmk_gpio_irq_mask(struct irq_data *d) 7433a198059SLinus Walleij { 7443a198059SLinus Walleij nmk_gpio_irq_maskunmask(d, false); 7453a198059SLinus Walleij } 7463a198059SLinus Walleij 7473a198059SLinus Walleij static void nmk_gpio_irq_unmask(struct irq_data *d) 7483a198059SLinus Walleij { 7493a198059SLinus Walleij nmk_gpio_irq_maskunmask(d, true); 7503a198059SLinus Walleij } 7513a198059SLinus Walleij 7523a198059SLinus Walleij static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 7533a198059SLinus Walleij { 7543a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip; 7553a198059SLinus Walleij unsigned long flags; 7563a198059SLinus Walleij u32 bitmask; 7573a198059SLinus Walleij 7583a198059SLinus Walleij nmk_chip = irq_data_get_irq_chip_data(d); 7593a198059SLinus Walleij if (!nmk_chip) 7603a198059SLinus Walleij return -EINVAL; 7613a198059SLinus Walleij bitmask = nmk_gpio_get_bitmask(d->hwirq); 7623a198059SLinus Walleij 7633a198059SLinus Walleij clk_enable(nmk_chip->clk); 7643a198059SLinus Walleij spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 7653a198059SLinus Walleij spin_lock(&nmk_chip->lock); 7663a198059SLinus Walleij 7673a198059SLinus Walleij if (irqd_irq_disabled(d)) 7683a198059SLinus Walleij __nmk_gpio_set_wake(nmk_chip, d->hwirq, on); 7693a198059SLinus Walleij 7703a198059SLinus Walleij if (on) 7713a198059SLinus Walleij nmk_chip->real_wake |= bitmask; 7723a198059SLinus Walleij else 7733a198059SLinus Walleij nmk_chip->real_wake &= ~bitmask; 7743a198059SLinus Walleij 7753a198059SLinus Walleij spin_unlock(&nmk_chip->lock); 7763a198059SLinus Walleij spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 7773a198059SLinus Walleij clk_disable(nmk_chip->clk); 7783a198059SLinus Walleij 7793a198059SLinus Walleij return 0; 7803a198059SLinus Walleij } 7813a198059SLinus Walleij 7823a198059SLinus Walleij static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) 7833a198059SLinus Walleij { 7843a198059SLinus Walleij bool enabled = !irqd_irq_disabled(d); 7853a198059SLinus Walleij bool wake = irqd_is_wakeup_set(d); 7863a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip; 7873a198059SLinus Walleij unsigned long flags; 7883a198059SLinus Walleij u32 bitmask; 7893a198059SLinus Walleij 7903a198059SLinus Walleij nmk_chip = irq_data_get_irq_chip_data(d); 7913a198059SLinus Walleij bitmask = nmk_gpio_get_bitmask(d->hwirq); 7923a198059SLinus Walleij if (!nmk_chip) 7933a198059SLinus Walleij return -EINVAL; 7943a198059SLinus Walleij if (type & IRQ_TYPE_LEVEL_HIGH) 7953a198059SLinus Walleij return -EINVAL; 7963a198059SLinus Walleij if (type & IRQ_TYPE_LEVEL_LOW) 7973a198059SLinus Walleij return -EINVAL; 7983a198059SLinus Walleij 7993a198059SLinus Walleij clk_enable(nmk_chip->clk); 8003a198059SLinus Walleij spin_lock_irqsave(&nmk_chip->lock, flags); 8013a198059SLinus Walleij 8023a198059SLinus Walleij if (enabled) 8033a198059SLinus Walleij __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false); 8043a198059SLinus Walleij 8053a198059SLinus Walleij if (enabled || wake) 8063a198059SLinus Walleij __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false); 8073a198059SLinus Walleij 8083a198059SLinus Walleij nmk_chip->edge_rising &= ~bitmask; 8093a198059SLinus Walleij if (type & IRQ_TYPE_EDGE_RISING) 8103a198059SLinus Walleij nmk_chip->edge_rising |= bitmask; 8113a198059SLinus Walleij 8123a198059SLinus Walleij nmk_chip->edge_falling &= ~bitmask; 8133a198059SLinus Walleij if (type & IRQ_TYPE_EDGE_FALLING) 8143a198059SLinus Walleij nmk_chip->edge_falling |= bitmask; 8153a198059SLinus Walleij 8163a198059SLinus Walleij if (enabled) 8173a198059SLinus Walleij __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true); 8183a198059SLinus Walleij 8193a198059SLinus Walleij if (enabled || wake) 8203a198059SLinus Walleij __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true); 8213a198059SLinus Walleij 8223a198059SLinus Walleij spin_unlock_irqrestore(&nmk_chip->lock, flags); 8233a198059SLinus Walleij clk_disable(nmk_chip->clk); 8243a198059SLinus Walleij 8253a198059SLinus Walleij return 0; 8263a198059SLinus Walleij } 8273a198059SLinus Walleij 8283a198059SLinus Walleij static unsigned int nmk_gpio_irq_startup(struct irq_data *d) 8293a198059SLinus Walleij { 8303a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); 8313a198059SLinus Walleij 8323a198059SLinus Walleij clk_enable(nmk_chip->clk); 8333a198059SLinus Walleij nmk_gpio_irq_unmask(d); 8343a198059SLinus Walleij return 0; 8353a198059SLinus Walleij } 8363a198059SLinus Walleij 8373a198059SLinus Walleij static void nmk_gpio_irq_shutdown(struct irq_data *d) 8383a198059SLinus Walleij { 8393a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); 8403a198059SLinus Walleij 8413a198059SLinus Walleij nmk_gpio_irq_mask(d); 8423a198059SLinus Walleij clk_disable(nmk_chip->clk); 8433a198059SLinus Walleij } 8443a198059SLinus Walleij 8453a198059SLinus Walleij static struct irq_chip nmk_gpio_irq_chip = { 8463a198059SLinus Walleij .name = "Nomadik-GPIO", 8473a198059SLinus Walleij .irq_ack = nmk_gpio_irq_ack, 8483a198059SLinus Walleij .irq_mask = nmk_gpio_irq_mask, 8493a198059SLinus Walleij .irq_unmask = nmk_gpio_irq_unmask, 8503a198059SLinus Walleij .irq_set_type = nmk_gpio_irq_set_type, 8513a198059SLinus Walleij .irq_set_wake = nmk_gpio_irq_set_wake, 8523a198059SLinus Walleij .irq_startup = nmk_gpio_irq_startup, 8533a198059SLinus Walleij .irq_shutdown = nmk_gpio_irq_shutdown, 8543a198059SLinus Walleij .flags = IRQCHIP_MASK_ON_SUSPEND, 8553a198059SLinus Walleij }; 8563a198059SLinus Walleij 8573a198059SLinus Walleij static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, 8583a198059SLinus Walleij u32 status) 8593a198059SLinus Walleij { 8603a198059SLinus Walleij struct irq_chip *host_chip = irq_get_chip(irq); 8613a198059SLinus Walleij struct gpio_chip *chip = irq_desc_get_handler_data(desc); 8623a198059SLinus Walleij 8633a198059SLinus Walleij chained_irq_enter(host_chip, desc); 8643a198059SLinus Walleij 8653a198059SLinus Walleij while (status) { 8663a198059SLinus Walleij int bit = __ffs(status); 8673a198059SLinus Walleij 8683a198059SLinus Walleij generic_handle_irq(irq_find_mapping(chip->irqdomain, bit)); 8693a198059SLinus Walleij status &= ~BIT(bit); 8703a198059SLinus Walleij } 8713a198059SLinus Walleij 8723a198059SLinus Walleij chained_irq_exit(host_chip, desc); 8733a198059SLinus Walleij } 8743a198059SLinus Walleij 8753a198059SLinus Walleij static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) 8763a198059SLinus Walleij { 8773a198059SLinus Walleij struct gpio_chip *chip = irq_desc_get_handler_data(desc); 8783a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); 8793a198059SLinus Walleij u32 status; 8803a198059SLinus Walleij 8813a198059SLinus Walleij clk_enable(nmk_chip->clk); 8823a198059SLinus Walleij status = readl(nmk_chip->addr + NMK_GPIO_IS); 8833a198059SLinus Walleij clk_disable(nmk_chip->clk); 8843a198059SLinus Walleij 8853a198059SLinus Walleij __nmk_gpio_irq_handler(irq, desc, status); 8863a198059SLinus Walleij } 8873a198059SLinus Walleij 8883a198059SLinus Walleij static void nmk_gpio_latent_irq_handler(unsigned int irq, 8893a198059SLinus Walleij struct irq_desc *desc) 8903a198059SLinus Walleij { 8913a198059SLinus Walleij struct gpio_chip *chip = irq_desc_get_handler_data(desc); 8923a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); 8933a198059SLinus Walleij u32 status = nmk_chip->get_latent_status(nmk_chip->bank); 8943a198059SLinus Walleij 8953a198059SLinus Walleij __nmk_gpio_irq_handler(irq, desc, status); 8963a198059SLinus Walleij } 8973a198059SLinus Walleij 8983a198059SLinus Walleij /* I/O Functions */ 8993a198059SLinus Walleij 9003a198059SLinus Walleij static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset) 9013a198059SLinus Walleij { 9023a198059SLinus Walleij /* 9033a198059SLinus Walleij * Map back to global GPIO space and request muxing, the direction 9043a198059SLinus Walleij * parameter does not matter for this controller. 9053a198059SLinus Walleij */ 9063a198059SLinus Walleij int gpio = chip->base + offset; 9073a198059SLinus Walleij 9083a198059SLinus Walleij return pinctrl_request_gpio(gpio); 9093a198059SLinus Walleij } 9103a198059SLinus Walleij 9113a198059SLinus Walleij static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset) 9123a198059SLinus Walleij { 9133a198059SLinus Walleij int gpio = chip->base + offset; 9143a198059SLinus Walleij 9153a198059SLinus Walleij pinctrl_free_gpio(gpio); 9163a198059SLinus Walleij } 9173a198059SLinus Walleij 9183a198059SLinus Walleij static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) 9193a198059SLinus Walleij { 9203a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip = 9213a198059SLinus Walleij container_of(chip, struct nmk_gpio_chip, chip); 9223a198059SLinus Walleij 9233a198059SLinus Walleij clk_enable(nmk_chip->clk); 9243a198059SLinus Walleij 9253a198059SLinus Walleij writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); 9263a198059SLinus Walleij 9273a198059SLinus Walleij clk_disable(nmk_chip->clk); 9283a198059SLinus Walleij 9293a198059SLinus Walleij return 0; 9303a198059SLinus Walleij } 9313a198059SLinus Walleij 9323a198059SLinus Walleij static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset) 9333a198059SLinus Walleij { 9343a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip = 9353a198059SLinus Walleij container_of(chip, struct nmk_gpio_chip, chip); 9363a198059SLinus Walleij u32 bit = 1 << offset; 9373a198059SLinus Walleij int value; 9383a198059SLinus Walleij 9393a198059SLinus Walleij clk_enable(nmk_chip->clk); 9403a198059SLinus Walleij 9413a198059SLinus Walleij value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0; 9423a198059SLinus Walleij 9433a198059SLinus Walleij clk_disable(nmk_chip->clk); 9443a198059SLinus Walleij 9453a198059SLinus Walleij return value; 9463a198059SLinus Walleij } 9473a198059SLinus Walleij 9483a198059SLinus Walleij static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset, 9493a198059SLinus Walleij int val) 9503a198059SLinus Walleij { 9513a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip = 9523a198059SLinus Walleij container_of(chip, struct nmk_gpio_chip, chip); 9533a198059SLinus Walleij 9543a198059SLinus Walleij clk_enable(nmk_chip->clk); 9553a198059SLinus Walleij 9563a198059SLinus Walleij __nmk_gpio_set_output(nmk_chip, offset, val); 9573a198059SLinus Walleij 9583a198059SLinus Walleij clk_disable(nmk_chip->clk); 9593a198059SLinus Walleij } 9603a198059SLinus Walleij 9613a198059SLinus Walleij static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, 9623a198059SLinus Walleij int val) 9633a198059SLinus Walleij { 9643a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip = 9653a198059SLinus Walleij container_of(chip, struct nmk_gpio_chip, chip); 9663a198059SLinus Walleij 9673a198059SLinus Walleij clk_enable(nmk_chip->clk); 9683a198059SLinus Walleij 9693a198059SLinus Walleij __nmk_gpio_make_output(nmk_chip, offset, val); 9703a198059SLinus Walleij 9713a198059SLinus Walleij clk_disable(nmk_chip->clk); 9723a198059SLinus Walleij 9733a198059SLinus Walleij return 0; 9743a198059SLinus Walleij } 9753a198059SLinus Walleij 9763a198059SLinus Walleij #ifdef CONFIG_DEBUG_FS 9773a198059SLinus Walleij 9783a198059SLinus Walleij #include <linux/seq_file.h> 9793a198059SLinus Walleij 9803a198059SLinus Walleij static void nmk_gpio_dbg_show_one(struct seq_file *s, 9813a198059SLinus Walleij struct pinctrl_dev *pctldev, struct gpio_chip *chip, 9823a198059SLinus Walleij unsigned offset, unsigned gpio) 9833a198059SLinus Walleij { 9843a198059SLinus Walleij const char *label = gpiochip_is_requested(chip, offset); 9853a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip = 9863a198059SLinus Walleij container_of(chip, struct nmk_gpio_chip, chip); 9873a198059SLinus Walleij int mode; 9883a198059SLinus Walleij bool is_out; 9898f1774a2SLinus Walleij bool data_out; 9903a198059SLinus Walleij bool pull; 9913a198059SLinus Walleij u32 bit = 1 << offset; 9923a198059SLinus Walleij const char *modes[] = { 9933a198059SLinus Walleij [NMK_GPIO_ALT_GPIO] = "gpio", 9943a198059SLinus Walleij [NMK_GPIO_ALT_A] = "altA", 9953a198059SLinus Walleij [NMK_GPIO_ALT_B] = "altB", 9963a198059SLinus Walleij [NMK_GPIO_ALT_C] = "altC", 9973a198059SLinus Walleij [NMK_GPIO_ALT_C+1] = "altC1", 9983a198059SLinus Walleij [NMK_GPIO_ALT_C+2] = "altC2", 9993a198059SLinus Walleij [NMK_GPIO_ALT_C+3] = "altC3", 10003a198059SLinus Walleij [NMK_GPIO_ALT_C+4] = "altC4", 10013a198059SLinus Walleij }; 10028f1774a2SLinus Walleij const char *pulls[] = { 10038f1774a2SLinus Walleij "none ", 10048f1774a2SLinus Walleij "pull down", 10058f1774a2SLinus Walleij "pull up ", 10068f1774a2SLinus Walleij }; 10073a198059SLinus Walleij 10083a198059SLinus Walleij clk_enable(nmk_chip->clk); 10093a198059SLinus Walleij is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit); 10103a198059SLinus Walleij pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); 10118f1774a2SLinus Walleij data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & bit); 10123a198059SLinus Walleij mode = nmk_gpio_get_mode(gpio); 10133a198059SLinus Walleij if ((mode == NMK_GPIO_ALT_C) && pctldev) 10143a198059SLinus Walleij mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio); 10153a198059SLinus Walleij 10168f1774a2SLinus Walleij if (is_out) { 10178f1774a2SLinus Walleij seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s", 10188f1774a2SLinus Walleij gpio, 10198f1774a2SLinus Walleij label ?: "(none)", 10208f1774a2SLinus Walleij data_out ? "hi" : "lo", 10218f1774a2SLinus Walleij (mode < 0) ? "unknown" : modes[mode]); 10228f1774a2SLinus Walleij } else { 10233a198059SLinus Walleij int irq = gpio_to_irq(gpio); 10243a198059SLinus Walleij struct irq_desc *desc = irq_to_desc(irq); 10258f1774a2SLinus Walleij int pullidx = 0; 10263a198059SLinus Walleij 10278f1774a2SLinus Walleij if (pull) 10288f1774a2SLinus Walleij pullidx = data_out ? 1 : 2; 10298f1774a2SLinus Walleij 10308f1774a2SLinus Walleij seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s", 10318f1774a2SLinus Walleij gpio, 10328f1774a2SLinus Walleij label ?: "(none)", 10338f1774a2SLinus Walleij pulls[pullidx], 10348f1774a2SLinus Walleij (mode < 0) ? "unknown" : modes[mode]); 10358f1774a2SLinus Walleij /* 10368f1774a2SLinus Walleij * This races with request_irq(), set_irq_type(), 10373a198059SLinus Walleij * and set_irq_wake() ... but those are "rare". 10383a198059SLinus Walleij */ 10393a198059SLinus Walleij if (irq > 0 && desc && desc->action) { 10403a198059SLinus Walleij char *trigger; 10413a198059SLinus Walleij u32 bitmask = nmk_gpio_get_bitmask(gpio); 10423a198059SLinus Walleij 10433a198059SLinus Walleij if (nmk_chip->edge_rising & bitmask) 10443a198059SLinus Walleij trigger = "edge-rising"; 10453a198059SLinus Walleij else if (nmk_chip->edge_falling & bitmask) 10463a198059SLinus Walleij trigger = "edge-falling"; 10473a198059SLinus Walleij else 10483a198059SLinus Walleij trigger = "edge-undefined"; 10493a198059SLinus Walleij 10503a198059SLinus Walleij seq_printf(s, " irq-%d %s%s", 10513a198059SLinus Walleij irq, trigger, 10523a198059SLinus Walleij irqd_is_wakeup_set(&desc->irq_data) 10533a198059SLinus Walleij ? " wakeup" : ""); 10543a198059SLinus Walleij } 10553a198059SLinus Walleij } 10563a198059SLinus Walleij clk_disable(nmk_chip->clk); 10573a198059SLinus Walleij } 10583a198059SLinus Walleij 10593a198059SLinus Walleij static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 10603a198059SLinus Walleij { 10613a198059SLinus Walleij unsigned i; 10623a198059SLinus Walleij unsigned gpio = chip->base; 10633a198059SLinus Walleij 10643a198059SLinus Walleij for (i = 0; i < chip->ngpio; i++, gpio++) { 10653a198059SLinus Walleij nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio); 10663a198059SLinus Walleij seq_printf(s, "\n"); 10673a198059SLinus Walleij } 10683a198059SLinus Walleij } 10693a198059SLinus Walleij 10703a198059SLinus Walleij #else 10713a198059SLinus Walleij static inline void nmk_gpio_dbg_show_one(struct seq_file *s, 10723a198059SLinus Walleij struct pinctrl_dev *pctldev, 10733a198059SLinus Walleij struct gpio_chip *chip, 10743a198059SLinus Walleij unsigned offset, unsigned gpio) 10753a198059SLinus Walleij { 10763a198059SLinus Walleij } 10773a198059SLinus Walleij #define nmk_gpio_dbg_show NULL 10783a198059SLinus Walleij #endif 10793a198059SLinus Walleij 10803a198059SLinus Walleij /* This structure is replicated for each GPIO block allocated at probe time */ 10813a198059SLinus Walleij static struct gpio_chip nmk_gpio_template = { 10823a198059SLinus Walleij .request = nmk_gpio_request, 10833a198059SLinus Walleij .free = nmk_gpio_free, 10843a198059SLinus Walleij .direction_input = nmk_gpio_make_input, 10853a198059SLinus Walleij .get = nmk_gpio_get_input, 10863a198059SLinus Walleij .direction_output = nmk_gpio_make_output, 10873a198059SLinus Walleij .set = nmk_gpio_set_output, 10883a198059SLinus Walleij .dbg_show = nmk_gpio_dbg_show, 10893a198059SLinus Walleij .can_sleep = false, 10903a198059SLinus Walleij }; 10913a198059SLinus Walleij 10923a198059SLinus Walleij void nmk_gpio_clocks_enable(void) 10933a198059SLinus Walleij { 10943a198059SLinus Walleij int i; 10953a198059SLinus Walleij 10963a198059SLinus Walleij for (i = 0; i < NUM_BANKS; i++) { 10973a198059SLinus Walleij struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 10983a198059SLinus Walleij 10993a198059SLinus Walleij if (!chip) 11003a198059SLinus Walleij continue; 11013a198059SLinus Walleij 11023a198059SLinus Walleij clk_enable(chip->clk); 11033a198059SLinus Walleij } 11043a198059SLinus Walleij } 11053a198059SLinus Walleij 11063a198059SLinus Walleij void nmk_gpio_clocks_disable(void) 11073a198059SLinus Walleij { 11083a198059SLinus Walleij int i; 11093a198059SLinus Walleij 11103a198059SLinus Walleij for (i = 0; i < NUM_BANKS; i++) { 11113a198059SLinus Walleij struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 11123a198059SLinus Walleij 11133a198059SLinus Walleij if (!chip) 11143a198059SLinus Walleij continue; 11153a198059SLinus Walleij 11163a198059SLinus Walleij clk_disable(chip->clk); 11173a198059SLinus Walleij } 11183a198059SLinus Walleij } 11193a198059SLinus Walleij 11203a198059SLinus Walleij /* 11213a198059SLinus Walleij * Called from the suspend/resume path to only keep the real wakeup interrupts 11223a198059SLinus Walleij * (those that have had set_irq_wake() called on them) as wakeup interrupts, 11233a198059SLinus Walleij * and not the rest of the interrupts which we needed to have as wakeups for 11243a198059SLinus Walleij * cpuidle. 11253a198059SLinus Walleij * 11263a198059SLinus Walleij * PM ops are not used since this needs to be done at the end, after all the 11273a198059SLinus Walleij * other drivers are done with their suspend callbacks. 11283a198059SLinus Walleij */ 11293a198059SLinus Walleij void nmk_gpio_wakeups_suspend(void) 11303a198059SLinus Walleij { 11313a198059SLinus Walleij int i; 11323a198059SLinus Walleij 11333a198059SLinus Walleij for (i = 0; i < NUM_BANKS; i++) { 11343a198059SLinus Walleij struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 11353a198059SLinus Walleij 11363a198059SLinus Walleij if (!chip) 11373a198059SLinus Walleij break; 11383a198059SLinus Walleij 11393a198059SLinus Walleij clk_enable(chip->clk); 11403a198059SLinus Walleij 11413a198059SLinus Walleij writel(chip->rwimsc & chip->real_wake, 11423a198059SLinus Walleij chip->addr + NMK_GPIO_RWIMSC); 11433a198059SLinus Walleij writel(chip->fwimsc & chip->real_wake, 11443a198059SLinus Walleij chip->addr + NMK_GPIO_FWIMSC); 11453a198059SLinus Walleij 11463a198059SLinus Walleij clk_disable(chip->clk); 11473a198059SLinus Walleij } 11483a198059SLinus Walleij } 11493a198059SLinus Walleij 11503a198059SLinus Walleij void nmk_gpio_wakeups_resume(void) 11513a198059SLinus Walleij { 11523a198059SLinus Walleij int i; 11533a198059SLinus Walleij 11543a198059SLinus Walleij for (i = 0; i < NUM_BANKS; i++) { 11553a198059SLinus Walleij struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 11563a198059SLinus Walleij 11573a198059SLinus Walleij if (!chip) 11583a198059SLinus Walleij break; 11593a198059SLinus Walleij 11603a198059SLinus Walleij clk_enable(chip->clk); 11613a198059SLinus Walleij 11623a198059SLinus Walleij writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC); 11633a198059SLinus Walleij writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC); 11643a198059SLinus Walleij 11653a198059SLinus Walleij clk_disable(chip->clk); 11663a198059SLinus Walleij } 11673a198059SLinus Walleij } 11683a198059SLinus Walleij 11693a198059SLinus Walleij /* 11703a198059SLinus Walleij * Read the pull up/pull down status. 11713a198059SLinus Walleij * A bit set in 'pull_up' means that pull up 11723a198059SLinus Walleij * is selected if pull is enabled in PDIS register. 11733a198059SLinus Walleij * Note: only pull up/down set via this driver can 11743a198059SLinus Walleij * be detected due to HW limitations. 11753a198059SLinus Walleij */ 11763a198059SLinus Walleij void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up) 11773a198059SLinus Walleij { 11783a198059SLinus Walleij if (gpio_bank < NUM_BANKS) { 11793a198059SLinus Walleij struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank]; 11803a198059SLinus Walleij 11813a198059SLinus Walleij if (!chip) 11823a198059SLinus Walleij return; 11833a198059SLinus Walleij 11843a198059SLinus Walleij *pull_up = chip->pull_up; 11853a198059SLinus Walleij } 11863a198059SLinus Walleij } 11873a198059SLinus Walleij 11883a198059SLinus Walleij static int nmk_gpio_probe(struct platform_device *dev) 11893a198059SLinus Walleij { 11903a198059SLinus Walleij struct device_node *np = dev->dev.of_node; 11913a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip; 11923a198059SLinus Walleij struct gpio_chip *chip; 11933a198059SLinus Walleij struct resource *res; 11943a198059SLinus Walleij struct clk *clk; 11953a198059SLinus Walleij int latent_irq; 11963a198059SLinus Walleij bool supports_sleepmode; 11973a198059SLinus Walleij void __iomem *base; 11983a198059SLinus Walleij int irq; 11993a198059SLinus Walleij int ret; 12003a198059SLinus Walleij 12013a198059SLinus Walleij if (of_get_property(np, "st,supports-sleepmode", NULL)) 12023a198059SLinus Walleij supports_sleepmode = true; 12033a198059SLinus Walleij else 12043a198059SLinus Walleij supports_sleepmode = false; 12053a198059SLinus Walleij 12063a198059SLinus Walleij if (of_property_read_u32(np, "gpio-bank", &dev->id)) { 12073a198059SLinus Walleij dev_err(&dev->dev, "gpio-bank property not found\n"); 12083a198059SLinus Walleij return -EINVAL; 12093a198059SLinus Walleij } 12103a198059SLinus Walleij 12113a198059SLinus Walleij irq = platform_get_irq(dev, 0); 12123a198059SLinus Walleij if (irq < 0) 12133a198059SLinus Walleij return irq; 12143a198059SLinus Walleij 12153a198059SLinus Walleij /* It's OK for this IRQ not to be present */ 12163a198059SLinus Walleij latent_irq = platform_get_irq(dev, 1); 12173a198059SLinus Walleij 12183a198059SLinus Walleij res = platform_get_resource(dev, IORESOURCE_MEM, 0); 12193a198059SLinus Walleij base = devm_ioremap_resource(&dev->dev, res); 12203a198059SLinus Walleij if (IS_ERR(base)) 12213a198059SLinus Walleij return PTR_ERR(base); 12223a198059SLinus Walleij 12233a198059SLinus Walleij clk = devm_clk_get(&dev->dev, NULL); 12243a198059SLinus Walleij if (IS_ERR(clk)) 12253a198059SLinus Walleij return PTR_ERR(clk); 12263a198059SLinus Walleij clk_prepare(clk); 12273a198059SLinus Walleij 12283a198059SLinus Walleij nmk_chip = devm_kzalloc(&dev->dev, sizeof(*nmk_chip), GFP_KERNEL); 12293a198059SLinus Walleij if (!nmk_chip) 12303a198059SLinus Walleij return -ENOMEM; 12313a198059SLinus Walleij 12323a198059SLinus Walleij /* 12333a198059SLinus Walleij * The virt address in nmk_chip->addr is in the nomadik register space, 12343a198059SLinus Walleij * so we can simply convert the resource address, without remapping 12353a198059SLinus Walleij */ 12363a198059SLinus Walleij nmk_chip->bank = dev->id; 12373a198059SLinus Walleij nmk_chip->clk = clk; 12383a198059SLinus Walleij nmk_chip->addr = base; 12393a198059SLinus Walleij nmk_chip->chip = nmk_gpio_template; 12403a198059SLinus Walleij nmk_chip->parent_irq = irq; 12413a198059SLinus Walleij nmk_chip->latent_parent_irq = latent_irq; 12423a198059SLinus Walleij nmk_chip->sleepmode = supports_sleepmode; 12433a198059SLinus Walleij spin_lock_init(&nmk_chip->lock); 12443a198059SLinus Walleij 12453a198059SLinus Walleij chip = &nmk_chip->chip; 12463a198059SLinus Walleij chip->base = dev->id * NMK_GPIO_PER_CHIP; 12473a198059SLinus Walleij chip->ngpio = NMK_GPIO_PER_CHIP; 12483a198059SLinus Walleij chip->label = dev_name(&dev->dev); 12493a198059SLinus Walleij chip->dev = &dev->dev; 12503a198059SLinus Walleij chip->owner = THIS_MODULE; 12513a198059SLinus Walleij 12523a198059SLinus Walleij clk_enable(nmk_chip->clk); 12533a198059SLinus Walleij nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); 12543a198059SLinus Walleij clk_disable(nmk_chip->clk); 12553a198059SLinus Walleij chip->of_node = np; 12563a198059SLinus Walleij 12573a198059SLinus Walleij ret = gpiochip_add(&nmk_chip->chip); 12583a198059SLinus Walleij if (ret) 12593a198059SLinus Walleij return ret; 12603a198059SLinus Walleij 12613a198059SLinus Walleij BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); 12623a198059SLinus Walleij 12633a198059SLinus Walleij nmk_gpio_chips[nmk_chip->bank] = nmk_chip; 12643a198059SLinus Walleij 12653a198059SLinus Walleij platform_set_drvdata(dev, nmk_chip); 12663a198059SLinus Walleij 12673a198059SLinus Walleij /* 12683a198059SLinus Walleij * Let the generic code handle this edge IRQ, the the chained 12693a198059SLinus Walleij * handler will perform the actual work of handling the parent 12703a198059SLinus Walleij * interrupt. 12713a198059SLinus Walleij */ 12723a198059SLinus Walleij ret = gpiochip_irqchip_add(&nmk_chip->chip, 12733a198059SLinus Walleij &nmk_gpio_irq_chip, 12743a198059SLinus Walleij 0, 12753a198059SLinus Walleij handle_edge_irq, 12763a198059SLinus Walleij IRQ_TYPE_EDGE_FALLING); 12773a198059SLinus Walleij if (ret) { 12783a198059SLinus Walleij dev_err(&dev->dev, "could not add irqchip\n"); 12793a198059SLinus Walleij ret = gpiochip_remove(&nmk_chip->chip); 12803a198059SLinus Walleij return -ENODEV; 12813a198059SLinus Walleij } 12823a198059SLinus Walleij /* Then register the chain on the parent IRQ */ 12833a198059SLinus Walleij gpiochip_set_chained_irqchip(&nmk_chip->chip, 12843a198059SLinus Walleij &nmk_gpio_irq_chip, 12853a198059SLinus Walleij nmk_chip->parent_irq, 12863a198059SLinus Walleij nmk_gpio_irq_handler); 12873a198059SLinus Walleij if (nmk_chip->latent_parent_irq > 0) 12883a198059SLinus Walleij gpiochip_set_chained_irqchip(&nmk_chip->chip, 12893a198059SLinus Walleij &nmk_gpio_irq_chip, 12903a198059SLinus Walleij nmk_chip->latent_parent_irq, 12913a198059SLinus Walleij nmk_gpio_latent_irq_handler); 12923a198059SLinus Walleij 12933a198059SLinus Walleij dev_info(&dev->dev, "at address %p\n", nmk_chip->addr); 12943a198059SLinus Walleij 12953a198059SLinus Walleij return 0; 12963a198059SLinus Walleij } 12973a198059SLinus Walleij 12983a198059SLinus Walleij static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev) 12993a198059SLinus Walleij { 13003a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 13013a198059SLinus Walleij 13023a198059SLinus Walleij return npct->soc->ngroups; 13033a198059SLinus Walleij } 13043a198059SLinus Walleij 13053a198059SLinus Walleij static const char *nmk_get_group_name(struct pinctrl_dev *pctldev, 13063a198059SLinus Walleij unsigned selector) 13073a198059SLinus Walleij { 13083a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 13093a198059SLinus Walleij 13103a198059SLinus Walleij return npct->soc->groups[selector].name; 13113a198059SLinus Walleij } 13123a198059SLinus Walleij 13133a198059SLinus Walleij static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, 13143a198059SLinus Walleij const unsigned **pins, 13153a198059SLinus Walleij unsigned *num_pins) 13163a198059SLinus Walleij { 13173a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 13183a198059SLinus Walleij 13193a198059SLinus Walleij *pins = npct->soc->groups[selector].pins; 13203a198059SLinus Walleij *num_pins = npct->soc->groups[selector].npins; 13213a198059SLinus Walleij return 0; 13223a198059SLinus Walleij } 13233a198059SLinus Walleij 13243a198059SLinus Walleij static struct pinctrl_gpio_range * 13253a198059SLinus Walleij nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset) 13263a198059SLinus Walleij { 13273a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 13283a198059SLinus Walleij int i; 13293a198059SLinus Walleij 13303a198059SLinus Walleij for (i = 0; i < npct->soc->gpio_num_ranges; i++) { 13313a198059SLinus Walleij struct pinctrl_gpio_range *range; 13323a198059SLinus Walleij 13333a198059SLinus Walleij range = &npct->soc->gpio_ranges[i]; 13343a198059SLinus Walleij if (offset >= range->pin_base && 13353a198059SLinus Walleij offset <= (range->pin_base + range->npins - 1)) 13363a198059SLinus Walleij return range; 13373a198059SLinus Walleij } 13383a198059SLinus Walleij return NULL; 13393a198059SLinus Walleij } 13403a198059SLinus Walleij 13413a198059SLinus Walleij static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 13423a198059SLinus Walleij unsigned offset) 13433a198059SLinus Walleij { 13443a198059SLinus Walleij struct pinctrl_gpio_range *range; 13453a198059SLinus Walleij struct gpio_chip *chip; 13463a198059SLinus Walleij 13473a198059SLinus Walleij range = nmk_match_gpio_range(pctldev, offset); 13483a198059SLinus Walleij if (!range || !range->gc) { 13493a198059SLinus Walleij seq_printf(s, "invalid pin offset"); 13503a198059SLinus Walleij return; 13513a198059SLinus Walleij } 13523a198059SLinus Walleij chip = range->gc; 13533a198059SLinus Walleij nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset); 13543a198059SLinus Walleij } 13553a198059SLinus Walleij 13563a198059SLinus Walleij static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps, 13573a198059SLinus Walleij unsigned *num_maps, const char *group, 13583a198059SLinus Walleij const char *function) 13593a198059SLinus Walleij { 13603a198059SLinus Walleij if (*num_maps == *reserved_maps) 13613a198059SLinus Walleij return -ENOSPC; 13623a198059SLinus Walleij 13633a198059SLinus Walleij (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 13643a198059SLinus Walleij (*map)[*num_maps].data.mux.group = group; 13653a198059SLinus Walleij (*map)[*num_maps].data.mux.function = function; 13663a198059SLinus Walleij (*num_maps)++; 13673a198059SLinus Walleij 13683a198059SLinus Walleij return 0; 13693a198059SLinus Walleij } 13703a198059SLinus Walleij 13713a198059SLinus Walleij static int nmk_dt_add_map_configs(struct pinctrl_map **map, 13723a198059SLinus Walleij unsigned *reserved_maps, 13733a198059SLinus Walleij unsigned *num_maps, const char *group, 13743a198059SLinus Walleij unsigned long *configs, unsigned num_configs) 13753a198059SLinus Walleij { 13763a198059SLinus Walleij unsigned long *dup_configs; 13773a198059SLinus Walleij 13783a198059SLinus Walleij if (*num_maps == *reserved_maps) 13793a198059SLinus Walleij return -ENOSPC; 13803a198059SLinus Walleij 13813a198059SLinus Walleij dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), 13823a198059SLinus Walleij GFP_KERNEL); 13833a198059SLinus Walleij if (!dup_configs) 13843a198059SLinus Walleij return -ENOMEM; 13853a198059SLinus Walleij 13863a198059SLinus Walleij (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN; 13873a198059SLinus Walleij 13883a198059SLinus Walleij (*map)[*num_maps].data.configs.group_or_pin = group; 13893a198059SLinus Walleij (*map)[*num_maps].data.configs.configs = dup_configs; 13903a198059SLinus Walleij (*map)[*num_maps].data.configs.num_configs = num_configs; 13913a198059SLinus Walleij (*num_maps)++; 13923a198059SLinus Walleij 13933a198059SLinus Walleij return 0; 13943a198059SLinus Walleij } 13953a198059SLinus Walleij 13963a198059SLinus Walleij #define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, } 13973a198059SLinus Walleij #define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \ 13983a198059SLinus Walleij .size = ARRAY_SIZE(y), } 13993a198059SLinus Walleij 14003a198059SLinus Walleij static const unsigned long nmk_pin_input_modes[] = { 14013a198059SLinus Walleij PIN_INPUT_NOPULL, 14023a198059SLinus Walleij PIN_INPUT_PULLUP, 14033a198059SLinus Walleij PIN_INPUT_PULLDOWN, 14043a198059SLinus Walleij }; 14053a198059SLinus Walleij 14063a198059SLinus Walleij static const unsigned long nmk_pin_output_modes[] = { 14073a198059SLinus Walleij PIN_OUTPUT_LOW, 14083a198059SLinus Walleij PIN_OUTPUT_HIGH, 14093a198059SLinus Walleij PIN_DIR_OUTPUT, 14103a198059SLinus Walleij }; 14113a198059SLinus Walleij 14123a198059SLinus Walleij static const unsigned long nmk_pin_sleep_modes[] = { 14133a198059SLinus Walleij PIN_SLEEPMODE_DISABLED, 14143a198059SLinus Walleij PIN_SLEEPMODE_ENABLED, 14153a198059SLinus Walleij }; 14163a198059SLinus Walleij 14173a198059SLinus Walleij static const unsigned long nmk_pin_sleep_input_modes[] = { 14183a198059SLinus Walleij PIN_SLPM_INPUT_NOPULL, 14193a198059SLinus Walleij PIN_SLPM_INPUT_PULLUP, 14203a198059SLinus Walleij PIN_SLPM_INPUT_PULLDOWN, 14213a198059SLinus Walleij PIN_SLPM_DIR_INPUT, 14223a198059SLinus Walleij }; 14233a198059SLinus Walleij 14243a198059SLinus Walleij static const unsigned long nmk_pin_sleep_output_modes[] = { 14253a198059SLinus Walleij PIN_SLPM_OUTPUT_LOW, 14263a198059SLinus Walleij PIN_SLPM_OUTPUT_HIGH, 14273a198059SLinus Walleij PIN_SLPM_DIR_OUTPUT, 14283a198059SLinus Walleij }; 14293a198059SLinus Walleij 14303a198059SLinus Walleij static const unsigned long nmk_pin_sleep_wakeup_modes[] = { 14313a198059SLinus Walleij PIN_SLPM_WAKEUP_DISABLE, 14323a198059SLinus Walleij PIN_SLPM_WAKEUP_ENABLE, 14333a198059SLinus Walleij }; 14343a198059SLinus Walleij 14353a198059SLinus Walleij static const unsigned long nmk_pin_gpio_modes[] = { 14363a198059SLinus Walleij PIN_GPIOMODE_DISABLED, 14373a198059SLinus Walleij PIN_GPIOMODE_ENABLED, 14383a198059SLinus Walleij }; 14393a198059SLinus Walleij 14403a198059SLinus Walleij static const unsigned long nmk_pin_sleep_pdis_modes[] = { 14413a198059SLinus Walleij PIN_SLPM_PDIS_DISABLED, 14423a198059SLinus Walleij PIN_SLPM_PDIS_ENABLED, 14433a198059SLinus Walleij }; 14443a198059SLinus Walleij 14453a198059SLinus Walleij struct nmk_cfg_param { 14463a198059SLinus Walleij const char *property; 14473a198059SLinus Walleij unsigned long config; 14483a198059SLinus Walleij const unsigned long *choice; 14493a198059SLinus Walleij int size; 14503a198059SLinus Walleij }; 14513a198059SLinus Walleij 14523a198059SLinus Walleij static const struct nmk_cfg_param nmk_cfg_params[] = { 14533a198059SLinus Walleij NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes), 14543a198059SLinus Walleij NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes), 14553a198059SLinus Walleij NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes), 14563a198059SLinus Walleij NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes), 14573a198059SLinus Walleij NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes), 14583a198059SLinus Walleij NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes), 14593a198059SLinus Walleij NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes), 14603a198059SLinus Walleij NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes), 14613a198059SLinus Walleij }; 14623a198059SLinus Walleij 14633a198059SLinus Walleij static int nmk_dt_pin_config(int index, int val, unsigned long *config) 14643a198059SLinus Walleij { 14653a198059SLinus Walleij int ret = 0; 14663a198059SLinus Walleij 14673a198059SLinus Walleij if (nmk_cfg_params[index].choice == NULL) 14683a198059SLinus Walleij *config = nmk_cfg_params[index].config; 14693a198059SLinus Walleij else { 14703a198059SLinus Walleij /* test if out of range */ 14713a198059SLinus Walleij if (val < nmk_cfg_params[index].size) { 14723a198059SLinus Walleij *config = nmk_cfg_params[index].config | 14733a198059SLinus Walleij nmk_cfg_params[index].choice[val]; 14743a198059SLinus Walleij } 14753a198059SLinus Walleij } 14763a198059SLinus Walleij return ret; 14773a198059SLinus Walleij } 14783a198059SLinus Walleij 14793a198059SLinus Walleij static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name) 14803a198059SLinus Walleij { 14813a198059SLinus Walleij int i, pin_number; 14823a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 14833a198059SLinus Walleij 14843a198059SLinus Walleij if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1) 14853a198059SLinus Walleij for (i = 0; i < npct->soc->npins; i++) 14863a198059SLinus Walleij if (npct->soc->pins[i].number == pin_number) 14873a198059SLinus Walleij return npct->soc->pins[i].name; 14883a198059SLinus Walleij return NULL; 14893a198059SLinus Walleij } 14903a198059SLinus Walleij 14913a198059SLinus Walleij static bool nmk_pinctrl_dt_get_config(struct device_node *np, 14923a198059SLinus Walleij unsigned long *configs) 14933a198059SLinus Walleij { 14943a198059SLinus Walleij bool has_config = 0; 14953a198059SLinus Walleij unsigned long cfg = 0; 14963a198059SLinus Walleij int i, val, ret; 14973a198059SLinus Walleij 14983a198059SLinus Walleij for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) { 14993a198059SLinus Walleij ret = of_property_read_u32(np, 15003a198059SLinus Walleij nmk_cfg_params[i].property, &val); 15013a198059SLinus Walleij if (ret != -EINVAL) { 15023a198059SLinus Walleij if (nmk_dt_pin_config(i, val, &cfg) == 0) { 15033a198059SLinus Walleij *configs |= cfg; 15043a198059SLinus Walleij has_config = 1; 15053a198059SLinus Walleij } 15063a198059SLinus Walleij } 15073a198059SLinus Walleij } 15083a198059SLinus Walleij 15093a198059SLinus Walleij return has_config; 15103a198059SLinus Walleij } 15113a198059SLinus Walleij 15123a198059SLinus Walleij static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 15133a198059SLinus Walleij struct device_node *np, 15143a198059SLinus Walleij struct pinctrl_map **map, 15153a198059SLinus Walleij unsigned *reserved_maps, 15163a198059SLinus Walleij unsigned *num_maps) 15173a198059SLinus Walleij { 15183a198059SLinus Walleij int ret; 15193a198059SLinus Walleij const char *function = NULL; 15203a198059SLinus Walleij unsigned long configs = 0; 15213a198059SLinus Walleij bool has_config = 0; 15223a198059SLinus Walleij struct property *prop; 15233a198059SLinus Walleij const char *group, *gpio_name; 15243a198059SLinus Walleij struct device_node *np_config; 15253a198059SLinus Walleij 15263a198059SLinus Walleij ret = of_property_read_string(np, "ste,function", &function); 1527c2f6d059SLinus Walleij if (ret >= 0) { 15283a198059SLinus Walleij ret = of_property_count_strings(np, "ste,pins"); 15293a198059SLinus Walleij if (ret < 0) 15303a198059SLinus Walleij goto exit; 15313a198059SLinus Walleij 1532c2f6d059SLinus Walleij ret = pinctrl_utils_reserve_map(pctldev, map, 1533c2f6d059SLinus Walleij reserved_maps, 1534c2f6d059SLinus Walleij num_maps, ret); 15353a198059SLinus Walleij if (ret < 0) 15363a198059SLinus Walleij goto exit; 15373a198059SLinus Walleij 15383a198059SLinus Walleij of_property_for_each_string(np, "ste,pins", prop, group) { 15393a198059SLinus Walleij ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps, 15403a198059SLinus Walleij group, function); 15413a198059SLinus Walleij if (ret < 0) 15423a198059SLinus Walleij goto exit; 15433a198059SLinus Walleij } 1544c2f6d059SLinus Walleij } 1545c2f6d059SLinus Walleij 1546c2f6d059SLinus Walleij has_config = nmk_pinctrl_dt_get_config(np, &configs); 1547c2f6d059SLinus Walleij np_config = of_parse_phandle(np, "ste,config", 0); 1548c2f6d059SLinus Walleij if (np_config) 1549c2f6d059SLinus Walleij has_config |= nmk_pinctrl_dt_get_config(np_config, &configs); 15503a198059SLinus Walleij if (has_config) { 1551c2f6d059SLinus Walleij ret = of_property_count_strings(np, "ste,pins"); 1552c2f6d059SLinus Walleij if (ret < 0) 1553c2f6d059SLinus Walleij goto exit; 1554c2f6d059SLinus Walleij ret = pinctrl_utils_reserve_map(pctldev, map, 1555c2f6d059SLinus Walleij reserved_maps, 1556c2f6d059SLinus Walleij num_maps, ret); 1557c2f6d059SLinus Walleij if (ret < 0) 1558c2f6d059SLinus Walleij goto exit; 1559c2f6d059SLinus Walleij 1560c2f6d059SLinus Walleij of_property_for_each_string(np, "ste,pins", prop, group) { 15613a198059SLinus Walleij gpio_name = nmk_find_pin_name(pctldev, group); 15623a198059SLinus Walleij 1563c2f6d059SLinus Walleij ret = nmk_dt_add_map_configs(map, reserved_maps, 1564c2f6d059SLinus Walleij num_maps, 15653a198059SLinus Walleij gpio_name, &configs, 1); 15663a198059SLinus Walleij if (ret < 0) 15673a198059SLinus Walleij goto exit; 15683a198059SLinus Walleij } 15693a198059SLinus Walleij } 1570c2f6d059SLinus Walleij 15713a198059SLinus Walleij exit: 15723a198059SLinus Walleij return ret; 15733a198059SLinus Walleij } 15743a198059SLinus Walleij 15753a198059SLinus Walleij static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 15763a198059SLinus Walleij struct device_node *np_config, 15773a198059SLinus Walleij struct pinctrl_map **map, unsigned *num_maps) 15783a198059SLinus Walleij { 15793a198059SLinus Walleij unsigned reserved_maps; 15803a198059SLinus Walleij struct device_node *np; 15813a198059SLinus Walleij int ret; 15823a198059SLinus Walleij 15833a198059SLinus Walleij reserved_maps = 0; 15843a198059SLinus Walleij *map = NULL; 15853a198059SLinus Walleij *num_maps = 0; 15863a198059SLinus Walleij 15873a198059SLinus Walleij for_each_child_of_node(np_config, np) { 15883a198059SLinus Walleij ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map, 15893a198059SLinus Walleij &reserved_maps, num_maps); 15903a198059SLinus Walleij if (ret < 0) { 15916e9b1c35SLinus Walleij pinctrl_utils_dt_free_map(pctldev, *map, *num_maps); 15923a198059SLinus Walleij return ret; 15933a198059SLinus Walleij } 15943a198059SLinus Walleij } 15953a198059SLinus Walleij 15963a198059SLinus Walleij return 0; 15973a198059SLinus Walleij } 15983a198059SLinus Walleij 15993a198059SLinus Walleij static const struct pinctrl_ops nmk_pinctrl_ops = { 16003a198059SLinus Walleij .get_groups_count = nmk_get_groups_cnt, 16013a198059SLinus Walleij .get_group_name = nmk_get_group_name, 16023a198059SLinus Walleij .get_group_pins = nmk_get_group_pins, 16033a198059SLinus Walleij .pin_dbg_show = nmk_pin_dbg_show, 16043a198059SLinus Walleij .dt_node_to_map = nmk_pinctrl_dt_node_to_map, 16056e9b1c35SLinus Walleij .dt_free_map = pinctrl_utils_dt_free_map, 16063a198059SLinus Walleij }; 16073a198059SLinus Walleij 16083a198059SLinus Walleij static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 16093a198059SLinus Walleij { 16103a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 16113a198059SLinus Walleij 16123a198059SLinus Walleij return npct->soc->nfunctions; 16133a198059SLinus Walleij } 16143a198059SLinus Walleij 16153a198059SLinus Walleij static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev, 16163a198059SLinus Walleij unsigned function) 16173a198059SLinus Walleij { 16183a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 16193a198059SLinus Walleij 16203a198059SLinus Walleij return npct->soc->functions[function].name; 16213a198059SLinus Walleij } 16223a198059SLinus Walleij 16233a198059SLinus Walleij static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev, 16243a198059SLinus Walleij unsigned function, 16253a198059SLinus Walleij const char * const **groups, 16263a198059SLinus Walleij unsigned * const num_groups) 16273a198059SLinus Walleij { 16283a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 16293a198059SLinus Walleij 16303a198059SLinus Walleij *groups = npct->soc->functions[function].groups; 16313a198059SLinus Walleij *num_groups = npct->soc->functions[function].ngroups; 16323a198059SLinus Walleij 16333a198059SLinus Walleij return 0; 16343a198059SLinus Walleij } 16353a198059SLinus Walleij 163603e9f0caSLinus Walleij static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned function, 16373a198059SLinus Walleij unsigned group) 16383a198059SLinus Walleij { 16393a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 16403a198059SLinus Walleij const struct nmk_pingroup *g; 16413a198059SLinus Walleij static unsigned int slpm[NUM_BANKS]; 16423a198059SLinus Walleij unsigned long flags = 0; 16433a198059SLinus Walleij bool glitch; 16443a198059SLinus Walleij int ret = -EINVAL; 16453a198059SLinus Walleij int i; 16463a198059SLinus Walleij 16473a198059SLinus Walleij g = &npct->soc->groups[group]; 16483a198059SLinus Walleij 16493a198059SLinus Walleij if (g->altsetting < 0) 16503a198059SLinus Walleij return -EINVAL; 16513a198059SLinus Walleij 16523a198059SLinus Walleij dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins); 16533a198059SLinus Walleij 16543a198059SLinus Walleij /* 16553a198059SLinus Walleij * If we're setting altfunc C by setting both AFSLA and AFSLB to 1, 16563a198059SLinus Walleij * we may pass through an undesired state. In this case we take 16573a198059SLinus Walleij * some extra care. 16583a198059SLinus Walleij * 16593a198059SLinus Walleij * Safe sequence used to switch IOs between GPIO and Alternate-C mode: 16603a198059SLinus Walleij * - Save SLPM registers (since we have a shadow register in the 16613a198059SLinus Walleij * nmk_chip we're using that as backup) 16623a198059SLinus Walleij * - Set SLPM=0 for the IOs you want to switch and others to 1 16633a198059SLinus Walleij * - Configure the GPIO registers for the IOs that are being switched 16643a198059SLinus Walleij * - Set IOFORCE=1 16653a198059SLinus Walleij * - Modify the AFLSA/B registers for the IOs that are being switched 16663a198059SLinus Walleij * - Set IOFORCE=0 16673a198059SLinus Walleij * - Restore SLPM registers 16683a198059SLinus Walleij * - Any spurious wake up event during switch sequence to be ignored 16693a198059SLinus Walleij * and cleared 16703a198059SLinus Walleij * 16713a198059SLinus Walleij * We REALLY need to save ALL slpm registers, because the external 16723a198059SLinus Walleij * IOFORCE will switch *all* ports to their sleepmode setting to as 16733a198059SLinus Walleij * to avoid glitches. (Not just one port!) 16743a198059SLinus Walleij */ 16753a198059SLinus Walleij glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C); 16763a198059SLinus Walleij 16773a198059SLinus Walleij if (glitch) { 16783a198059SLinus Walleij spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 16793a198059SLinus Walleij 16803a198059SLinus Walleij /* Initially don't put any pins to sleep when switching */ 16813a198059SLinus Walleij memset(slpm, 0xff, sizeof(slpm)); 16823a198059SLinus Walleij 16833a198059SLinus Walleij /* 16843a198059SLinus Walleij * Then mask the pins that need to be sleeping now when we're 16853a198059SLinus Walleij * switching to the ALT C function. 16863a198059SLinus Walleij */ 16873a198059SLinus Walleij for (i = 0; i < g->npins; i++) 16883a198059SLinus Walleij slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]); 16893a198059SLinus Walleij nmk_gpio_glitch_slpm_init(slpm); 16903a198059SLinus Walleij } 16913a198059SLinus Walleij 16923a198059SLinus Walleij for (i = 0; i < g->npins; i++) { 16933a198059SLinus Walleij struct pinctrl_gpio_range *range; 16943a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip; 16953a198059SLinus Walleij struct gpio_chip *chip; 16963a198059SLinus Walleij unsigned bit; 16973a198059SLinus Walleij 16983a198059SLinus Walleij range = nmk_match_gpio_range(pctldev, g->pins[i]); 16993a198059SLinus Walleij if (!range) { 17003a198059SLinus Walleij dev_err(npct->dev, 17013a198059SLinus Walleij "invalid pin offset %d in group %s at index %d\n", 17023a198059SLinus Walleij g->pins[i], g->name, i); 17033a198059SLinus Walleij goto out_glitch; 17043a198059SLinus Walleij } 17053a198059SLinus Walleij if (!range->gc) { 17063a198059SLinus Walleij dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n", 17073a198059SLinus Walleij g->pins[i], g->name, i); 17083a198059SLinus Walleij goto out_glitch; 17093a198059SLinus Walleij } 17103a198059SLinus Walleij chip = range->gc; 17113a198059SLinus Walleij nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); 17123a198059SLinus Walleij dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting); 17133a198059SLinus Walleij 17143a198059SLinus Walleij clk_enable(nmk_chip->clk); 17153a198059SLinus Walleij bit = g->pins[i] % NMK_GPIO_PER_CHIP; 17163a198059SLinus Walleij /* 17173a198059SLinus Walleij * If the pin is switching to altfunc, and there was an 17183a198059SLinus Walleij * interrupt installed on it which has been lazy disabled, 17193a198059SLinus Walleij * actually mask the interrupt to prevent spurious interrupts 17203a198059SLinus Walleij * that would occur while the pin is under control of the 17213a198059SLinus Walleij * peripheral. Only SKE does this. 17223a198059SLinus Walleij */ 17233a198059SLinus Walleij nmk_gpio_disable_lazy_irq(nmk_chip, bit); 17243a198059SLinus Walleij 17253a198059SLinus Walleij __nmk_gpio_set_mode_safe(nmk_chip, bit, 17263a198059SLinus Walleij (g->altsetting & NMK_GPIO_ALT_C), glitch); 17273a198059SLinus Walleij clk_disable(nmk_chip->clk); 17283a198059SLinus Walleij 17293a198059SLinus Walleij /* 17303a198059SLinus Walleij * Call PRCM GPIOCR config function in case ALTC 17313a198059SLinus Walleij * has been selected: 17323a198059SLinus Walleij * - If selection is a ALTCx, some bits in PRCM GPIOCR registers 17333a198059SLinus Walleij * must be set. 17343a198059SLinus Walleij * - If selection is pure ALTC and previous selection was ALTCx, 17353a198059SLinus Walleij * then some bits in PRCM GPIOCR registers must be cleared. 17363a198059SLinus Walleij */ 17373a198059SLinus Walleij if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C) 17383a198059SLinus Walleij nmk_prcm_altcx_set_mode(npct, g->pins[i], 17393a198059SLinus Walleij g->altsetting >> NMK_GPIO_ALT_CX_SHIFT); 17403a198059SLinus Walleij } 17413a198059SLinus Walleij 17423a198059SLinus Walleij /* When all pins are successfully reconfigured we get here */ 17433a198059SLinus Walleij ret = 0; 17443a198059SLinus Walleij 17453a198059SLinus Walleij out_glitch: 17463a198059SLinus Walleij if (glitch) { 17473a198059SLinus Walleij nmk_gpio_glitch_slpm_restore(slpm); 17483a198059SLinus Walleij spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 17493a198059SLinus Walleij } 17503a198059SLinus Walleij 17513a198059SLinus Walleij return ret; 17523a198059SLinus Walleij } 17533a198059SLinus Walleij 17543a198059SLinus Walleij static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev, 17553a198059SLinus Walleij struct pinctrl_gpio_range *range, 17563a198059SLinus Walleij unsigned offset) 17573a198059SLinus Walleij { 17583a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 17593a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip; 17603a198059SLinus Walleij struct gpio_chip *chip; 17613a198059SLinus Walleij unsigned bit; 17623a198059SLinus Walleij 17633a198059SLinus Walleij if (!range) { 17643a198059SLinus Walleij dev_err(npct->dev, "invalid range\n"); 17653a198059SLinus Walleij return -EINVAL; 17663a198059SLinus Walleij } 17673a198059SLinus Walleij if (!range->gc) { 17683a198059SLinus Walleij dev_err(npct->dev, "missing GPIO chip in range\n"); 17693a198059SLinus Walleij return -EINVAL; 17703a198059SLinus Walleij } 17713a198059SLinus Walleij chip = range->gc; 17723a198059SLinus Walleij nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); 17733a198059SLinus Walleij 17743a198059SLinus Walleij dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); 17753a198059SLinus Walleij 17763a198059SLinus Walleij clk_enable(nmk_chip->clk); 17773a198059SLinus Walleij bit = offset % NMK_GPIO_PER_CHIP; 17783a198059SLinus Walleij /* There is no glitch when converting any pin to GPIO */ 17793a198059SLinus Walleij __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); 17803a198059SLinus Walleij clk_disable(nmk_chip->clk); 17813a198059SLinus Walleij 17823a198059SLinus Walleij return 0; 17833a198059SLinus Walleij } 17843a198059SLinus Walleij 17853a198059SLinus Walleij static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev, 17863a198059SLinus Walleij struct pinctrl_gpio_range *range, 17873a198059SLinus Walleij unsigned offset) 17883a198059SLinus Walleij { 17893a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 17903a198059SLinus Walleij 17913a198059SLinus Walleij dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); 17923a198059SLinus Walleij /* Set the pin to some default state, GPIO is usually default */ 17933a198059SLinus Walleij } 17943a198059SLinus Walleij 17953a198059SLinus Walleij static const struct pinmux_ops nmk_pinmux_ops = { 17963a198059SLinus Walleij .get_functions_count = nmk_pmx_get_funcs_cnt, 17973a198059SLinus Walleij .get_function_name = nmk_pmx_get_func_name, 17983a198059SLinus Walleij .get_function_groups = nmk_pmx_get_func_groups, 179903e9f0caSLinus Walleij .set_mux = nmk_pmx_set, 18003a198059SLinus Walleij .gpio_request_enable = nmk_gpio_request_enable, 18013a198059SLinus Walleij .gpio_disable_free = nmk_gpio_disable_free, 18023a198059SLinus Walleij }; 18033a198059SLinus Walleij 18043a198059SLinus Walleij static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, 18053a198059SLinus Walleij unsigned long *config) 18063a198059SLinus Walleij { 18073a198059SLinus Walleij /* Not implemented */ 18083a198059SLinus Walleij return -EINVAL; 18093a198059SLinus Walleij } 18103a198059SLinus Walleij 18113a198059SLinus Walleij static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, 18123a198059SLinus Walleij unsigned long *configs, unsigned num_configs) 18133a198059SLinus Walleij { 18143a198059SLinus Walleij static const char *pullnames[] = { 18153a198059SLinus Walleij [NMK_GPIO_PULL_NONE] = "none", 18163a198059SLinus Walleij [NMK_GPIO_PULL_UP] = "up", 18173a198059SLinus Walleij [NMK_GPIO_PULL_DOWN] = "down", 18183a198059SLinus Walleij [3] /* illegal */ = "??" 18193a198059SLinus Walleij }; 18203a198059SLinus Walleij static const char *slpmnames[] = { 18213a198059SLinus Walleij [NMK_GPIO_SLPM_INPUT] = "input/wakeup", 18223a198059SLinus Walleij [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", 18233a198059SLinus Walleij }; 18243a198059SLinus Walleij struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 18253a198059SLinus Walleij struct nmk_gpio_chip *nmk_chip; 18263a198059SLinus Walleij struct pinctrl_gpio_range *range; 18273a198059SLinus Walleij struct gpio_chip *chip; 18283a198059SLinus Walleij unsigned bit; 18293a198059SLinus Walleij pin_cfg_t cfg; 18303a198059SLinus Walleij int pull, slpm, output, val, i; 18313a198059SLinus Walleij bool lowemi, gpiomode, sleep; 18323a198059SLinus Walleij 18333a198059SLinus Walleij range = nmk_match_gpio_range(pctldev, pin); 18343a198059SLinus Walleij if (!range) { 18353a198059SLinus Walleij dev_err(npct->dev, "invalid pin offset %d\n", pin); 18363a198059SLinus Walleij return -EINVAL; 18373a198059SLinus Walleij } 18383a198059SLinus Walleij if (!range->gc) { 18393a198059SLinus Walleij dev_err(npct->dev, "GPIO chip missing in range for pin %d\n", 18403a198059SLinus Walleij pin); 18413a198059SLinus Walleij return -EINVAL; 18423a198059SLinus Walleij } 18433a198059SLinus Walleij chip = range->gc; 18443a198059SLinus Walleij nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); 18453a198059SLinus Walleij 18463a198059SLinus Walleij for (i = 0; i < num_configs; i++) { 18473a198059SLinus Walleij /* 18483a198059SLinus Walleij * The pin config contains pin number and altfunction fields, 18493a198059SLinus Walleij * here we just ignore that part. It's being handled by the 18503a198059SLinus Walleij * framework and pinmux callback respectively. 18513a198059SLinus Walleij */ 18523a198059SLinus Walleij cfg = (pin_cfg_t) configs[i]; 18533a198059SLinus Walleij pull = PIN_PULL(cfg); 18543a198059SLinus Walleij slpm = PIN_SLPM(cfg); 18553a198059SLinus Walleij output = PIN_DIR(cfg); 18563a198059SLinus Walleij val = PIN_VAL(cfg); 18573a198059SLinus Walleij lowemi = PIN_LOWEMI(cfg); 18583a198059SLinus Walleij gpiomode = PIN_GPIOMODE(cfg); 18593a198059SLinus Walleij sleep = PIN_SLEEPMODE(cfg); 18603a198059SLinus Walleij 18613a198059SLinus Walleij if (sleep) { 18623a198059SLinus Walleij int slpm_pull = PIN_SLPM_PULL(cfg); 18633a198059SLinus Walleij int slpm_output = PIN_SLPM_DIR(cfg); 18643a198059SLinus Walleij int slpm_val = PIN_SLPM_VAL(cfg); 18653a198059SLinus Walleij 18663a198059SLinus Walleij /* All pins go into GPIO mode at sleep */ 18673a198059SLinus Walleij gpiomode = true; 18683a198059SLinus Walleij 18693a198059SLinus Walleij /* 18703a198059SLinus Walleij * The SLPM_* values are normal values + 1 to allow zero 18713a198059SLinus Walleij * to mean "same as normal". 18723a198059SLinus Walleij */ 18733a198059SLinus Walleij if (slpm_pull) 18743a198059SLinus Walleij pull = slpm_pull - 1; 18753a198059SLinus Walleij if (slpm_output) 18763a198059SLinus Walleij output = slpm_output - 1; 18773a198059SLinus Walleij if (slpm_val) 18783a198059SLinus Walleij val = slpm_val - 1; 18793a198059SLinus Walleij 18803a198059SLinus Walleij dev_dbg(nmk_chip->chip.dev, 18813a198059SLinus Walleij "pin %d: sleep pull %s, dir %s, val %s\n", 18823a198059SLinus Walleij pin, 18833a198059SLinus Walleij slpm_pull ? pullnames[pull] : "same", 18843a198059SLinus Walleij slpm_output ? (output ? "output" : "input") 18853a198059SLinus Walleij : "same", 18863a198059SLinus Walleij slpm_val ? (val ? "high" : "low") : "same"); 18873a198059SLinus Walleij } 18883a198059SLinus Walleij 18893a198059SLinus Walleij dev_dbg(nmk_chip->chip.dev, 18903a198059SLinus Walleij "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n", 18913a198059SLinus Walleij pin, cfg, pullnames[pull], slpmnames[slpm], 18923a198059SLinus Walleij output ? "output " : "input", 18933a198059SLinus Walleij output ? (val ? "high" : "low") : "", 18943a198059SLinus Walleij lowemi ? "on" : "off"); 18953a198059SLinus Walleij 18963a198059SLinus Walleij clk_enable(nmk_chip->clk); 18973a198059SLinus Walleij bit = pin % NMK_GPIO_PER_CHIP; 18983a198059SLinus Walleij if (gpiomode) 18993a198059SLinus Walleij /* No glitch when going to GPIO mode */ 19003a198059SLinus Walleij __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); 19013a198059SLinus Walleij if (output) 19023a198059SLinus Walleij __nmk_gpio_make_output(nmk_chip, bit, val); 19033a198059SLinus Walleij else { 19043a198059SLinus Walleij __nmk_gpio_make_input(nmk_chip, bit); 19053a198059SLinus Walleij __nmk_gpio_set_pull(nmk_chip, bit, pull); 19063a198059SLinus Walleij } 19073a198059SLinus Walleij /* TODO: isn't this only applicable on output pins? */ 19083a198059SLinus Walleij __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi); 19093a198059SLinus Walleij 19103a198059SLinus Walleij __nmk_gpio_set_slpm(nmk_chip, bit, slpm); 19113a198059SLinus Walleij clk_disable(nmk_chip->clk); 19123a198059SLinus Walleij } /* for each config */ 19133a198059SLinus Walleij 19143a198059SLinus Walleij return 0; 19153a198059SLinus Walleij } 19163a198059SLinus Walleij 19173a198059SLinus Walleij static const struct pinconf_ops nmk_pinconf_ops = { 19183a198059SLinus Walleij .pin_config_get = nmk_pin_config_get, 19193a198059SLinus Walleij .pin_config_set = nmk_pin_config_set, 19203a198059SLinus Walleij }; 19213a198059SLinus Walleij 19223a198059SLinus Walleij static struct pinctrl_desc nmk_pinctrl_desc = { 19233a198059SLinus Walleij .name = "pinctrl-nomadik", 19243a198059SLinus Walleij .pctlops = &nmk_pinctrl_ops, 19253a198059SLinus Walleij .pmxops = &nmk_pinmux_ops, 19263a198059SLinus Walleij .confops = &nmk_pinconf_ops, 19273a198059SLinus Walleij .owner = THIS_MODULE, 19283a198059SLinus Walleij }; 19293a198059SLinus Walleij 19303a198059SLinus Walleij static const struct of_device_id nmk_pinctrl_match[] = { 19313a198059SLinus Walleij { 19323a198059SLinus Walleij .compatible = "stericsson,stn8815-pinctrl", 19333a198059SLinus Walleij .data = (void *)PINCTRL_NMK_STN8815, 19343a198059SLinus Walleij }, 19353a198059SLinus Walleij { 19363a198059SLinus Walleij .compatible = "stericsson,db8500-pinctrl", 19373a198059SLinus Walleij .data = (void *)PINCTRL_NMK_DB8500, 19383a198059SLinus Walleij }, 19393a198059SLinus Walleij { 19403a198059SLinus Walleij .compatible = "stericsson,db8540-pinctrl", 19413a198059SLinus Walleij .data = (void *)PINCTRL_NMK_DB8540, 19423a198059SLinus Walleij }, 19433a198059SLinus Walleij {}, 19443a198059SLinus Walleij }; 19453a198059SLinus Walleij 19463a198059SLinus Walleij #ifdef CONFIG_PM_SLEEP 19473a198059SLinus Walleij static int nmk_pinctrl_suspend(struct device *dev) 19483a198059SLinus Walleij { 19493a198059SLinus Walleij struct nmk_pinctrl *npct; 19503a198059SLinus Walleij 19513a198059SLinus Walleij npct = dev_get_drvdata(dev); 19523a198059SLinus Walleij if (!npct) 19533a198059SLinus Walleij return -EINVAL; 19543a198059SLinus Walleij 19553a198059SLinus Walleij return pinctrl_force_sleep(npct->pctl); 19563a198059SLinus Walleij } 19573a198059SLinus Walleij 19583a198059SLinus Walleij static int nmk_pinctrl_resume(struct device *dev) 19593a198059SLinus Walleij { 19603a198059SLinus Walleij struct nmk_pinctrl *npct; 19613a198059SLinus Walleij 19623a198059SLinus Walleij npct = dev_get_drvdata(dev); 19633a198059SLinus Walleij if (!npct) 19643a198059SLinus Walleij return -EINVAL; 19653a198059SLinus Walleij 19663a198059SLinus Walleij return pinctrl_force_default(npct->pctl); 19673a198059SLinus Walleij } 19683a198059SLinus Walleij #endif 19693a198059SLinus Walleij 19703a198059SLinus Walleij static int nmk_pinctrl_probe(struct platform_device *pdev) 19713a198059SLinus Walleij { 19723a198059SLinus Walleij const struct of_device_id *match; 19733a198059SLinus Walleij struct device_node *np = pdev->dev.of_node; 19743a198059SLinus Walleij struct device_node *prcm_np; 19753a198059SLinus Walleij struct nmk_pinctrl *npct; 19763a198059SLinus Walleij unsigned int version = 0; 19773a198059SLinus Walleij int i; 19783a198059SLinus Walleij 19793a198059SLinus Walleij npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL); 19803a198059SLinus Walleij if (!npct) 19813a198059SLinus Walleij return -ENOMEM; 19823a198059SLinus Walleij 19833a198059SLinus Walleij match = of_match_device(nmk_pinctrl_match, &pdev->dev); 19843a198059SLinus Walleij if (!match) 19853a198059SLinus Walleij return -ENODEV; 19863a198059SLinus Walleij version = (unsigned int) match->data; 19873a198059SLinus Walleij 19883a198059SLinus Walleij /* Poke in other ASIC variants here */ 19893a198059SLinus Walleij if (version == PINCTRL_NMK_STN8815) 19903a198059SLinus Walleij nmk_pinctrl_stn8815_init(&npct->soc); 19913a198059SLinus Walleij if (version == PINCTRL_NMK_DB8500) 19923a198059SLinus Walleij nmk_pinctrl_db8500_init(&npct->soc); 19933a198059SLinus Walleij if (version == PINCTRL_NMK_DB8540) 19943a198059SLinus Walleij nmk_pinctrl_db8540_init(&npct->soc); 19953a198059SLinus Walleij 19963a198059SLinus Walleij prcm_np = of_parse_phandle(np, "prcm", 0); 19973a198059SLinus Walleij if (prcm_np) 19983a198059SLinus Walleij npct->prcm_base = of_iomap(prcm_np, 0); 19993a198059SLinus Walleij if (!npct->prcm_base) { 20003a198059SLinus Walleij if (version == PINCTRL_NMK_STN8815) { 20013a198059SLinus Walleij dev_info(&pdev->dev, 20023a198059SLinus Walleij "No PRCM base, " 20033a198059SLinus Walleij "assuming no ALT-Cx control is available\n"); 20043a198059SLinus Walleij } else { 20053a198059SLinus Walleij dev_err(&pdev->dev, "missing PRCM base address\n"); 20063a198059SLinus Walleij return -EINVAL; 20073a198059SLinus Walleij } 20083a198059SLinus Walleij } 20093a198059SLinus Walleij 20103a198059SLinus Walleij /* 20113a198059SLinus Walleij * We need all the GPIO drivers to probe FIRST, or we will not be able 20123a198059SLinus Walleij * to obtain references to the struct gpio_chip * for them, and we 20133a198059SLinus Walleij * need this to proceed. 20143a198059SLinus Walleij */ 20153a198059SLinus Walleij for (i = 0; i < npct->soc->gpio_num_ranges; i++) { 20163a198059SLinus Walleij if (!nmk_gpio_chips[npct->soc->gpio_ranges[i].id]) { 20173a198059SLinus Walleij dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i); 20183a198059SLinus Walleij return -EPROBE_DEFER; 20193a198059SLinus Walleij } 20203a198059SLinus Walleij npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[npct->soc->gpio_ranges[i].id]->chip; 20213a198059SLinus Walleij } 20223a198059SLinus Walleij 20233a198059SLinus Walleij nmk_pinctrl_desc.pins = npct->soc->pins; 20243a198059SLinus Walleij nmk_pinctrl_desc.npins = npct->soc->npins; 20253a198059SLinus Walleij npct->dev = &pdev->dev; 20263a198059SLinus Walleij 20273a198059SLinus Walleij npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct); 20283a198059SLinus Walleij if (!npct->pctl) { 20293a198059SLinus Walleij dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n"); 20303a198059SLinus Walleij return -EINVAL; 20313a198059SLinus Walleij } 20323a198059SLinus Walleij 20333a198059SLinus Walleij /* We will handle a range of GPIO pins */ 20343a198059SLinus Walleij for (i = 0; i < npct->soc->gpio_num_ranges; i++) 20353a198059SLinus Walleij pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]); 20363a198059SLinus Walleij 20373a198059SLinus Walleij platform_set_drvdata(pdev, npct); 20383a198059SLinus Walleij dev_info(&pdev->dev, "initialized Nomadik pin control driver\n"); 20393a198059SLinus Walleij 20403a198059SLinus Walleij return 0; 20413a198059SLinus Walleij } 20423a198059SLinus Walleij 20433a198059SLinus Walleij static const struct of_device_id nmk_gpio_match[] = { 20443a198059SLinus Walleij { .compatible = "st,nomadik-gpio", }, 20453a198059SLinus Walleij {} 20463a198059SLinus Walleij }; 20473a198059SLinus Walleij 20483a198059SLinus Walleij static struct platform_driver nmk_gpio_driver = { 20493a198059SLinus Walleij .driver = { 20503a198059SLinus Walleij .owner = THIS_MODULE, 20513a198059SLinus Walleij .name = "gpio", 20523a198059SLinus Walleij .of_match_table = nmk_gpio_match, 20533a198059SLinus Walleij }, 20543a198059SLinus Walleij .probe = nmk_gpio_probe, 20553a198059SLinus Walleij }; 20563a198059SLinus Walleij 20573a198059SLinus Walleij static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops, 20583a198059SLinus Walleij nmk_pinctrl_suspend, 20593a198059SLinus Walleij nmk_pinctrl_resume); 20603a198059SLinus Walleij 20613a198059SLinus Walleij static struct platform_driver nmk_pinctrl_driver = { 20623a198059SLinus Walleij .driver = { 20633a198059SLinus Walleij .owner = THIS_MODULE, 20643a198059SLinus Walleij .name = "pinctrl-nomadik", 20653a198059SLinus Walleij .of_match_table = nmk_pinctrl_match, 20663a198059SLinus Walleij .pm = &nmk_pinctrl_pm_ops, 20673a198059SLinus Walleij }, 20683a198059SLinus Walleij .probe = nmk_pinctrl_probe, 20693a198059SLinus Walleij }; 20703a198059SLinus Walleij 20713a198059SLinus Walleij static int __init nmk_gpio_init(void) 20723a198059SLinus Walleij { 20733a198059SLinus Walleij int ret; 20743a198059SLinus Walleij 20753a198059SLinus Walleij ret = platform_driver_register(&nmk_gpio_driver); 20763a198059SLinus Walleij if (ret) 20773a198059SLinus Walleij return ret; 20783a198059SLinus Walleij return platform_driver_register(&nmk_pinctrl_driver); 20793a198059SLinus Walleij } 20803a198059SLinus Walleij 20813a198059SLinus Walleij core_initcall(nmk_gpio_init); 20823a198059SLinus Walleij 20833a198059SLinus Walleij MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini"); 20843a198059SLinus Walleij MODULE_DESCRIPTION("Nomadik GPIO Driver"); 20853a198059SLinus Walleij MODULE_LICENSE("GPL"); 2086