1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef PINCTRL_PINCTRL_ABx500_H 3 #define PINCTRL_PINCTRL_ABx500_H 4 5 /* Package definitions */ 6 #define PINCTRL_AB8500 0 7 #define PINCTRL_AB8540 1 8 #define PINCTRL_AB9540 2 9 #define PINCTRL_AB8505 3 10 11 /* pins alternate function */ 12 enum abx500_pin_func { 13 ABX500_DEFAULT, 14 ABX500_ALT_A, 15 ABX500_ALT_B, 16 ABX500_ALT_C, 17 }; 18 19 enum abx500_gpio_pull_updown { 20 ABX500_GPIO_PULL_DOWN = 0x0, 21 ABX500_GPIO_PULL_NONE = 0x1, 22 ABX500_GPIO_PULL_UP = 0x3, 23 }; 24 25 enum abx500_gpio_vinsel { 26 ABX500_GPIO_VINSEL_VBAT = 0x0, 27 ABX500_GPIO_VINSEL_VIN_1V8 = 0x1, 28 ABX500_GPIO_VINSEL_VDD_BIF = 0x2, 29 }; 30 31 /** 32 * struct abx500_function - ABx500 pinctrl mux function 33 * @name: The name of the function, exported to pinctrl core. 34 * @groups: An array of pin groups that may select this function. 35 * @ngroups: The number of entries in @groups. 36 */ 37 struct abx500_function { 38 const char *name; 39 const char * const *groups; 40 unsigned ngroups; 41 }; 42 43 /** 44 * struct abx500_pingroup - describes a ABx500 pin group 45 * @name: the name of this specific pin group 46 * @pins: an array of discrete physical pins used in this group, taken 47 * from the driver-local pin enumeration space 48 * @num_pins: the number of pins in this group array, i.e. the number of 49 * elements in .pins so we can iterate over that array 50 * @altsetting: the altsetting to apply to all pins in this group to 51 * configure them to be used by a function 52 */ 53 struct abx500_pingroup { 54 const char *name; 55 const unsigned int *pins; 56 const unsigned npins; 57 int altsetting; 58 }; 59 60 #define ALTERNATE_FUNCTIONS(pin, sel_bit, alt1, alt2, alta, altb, altc) \ 61 { \ 62 .pin_number = pin, \ 63 .gpiosel_bit = sel_bit, \ 64 .alt_bit1 = alt1, \ 65 .alt_bit2 = alt2, \ 66 .alta_val = alta, \ 67 .altb_val = altb, \ 68 .altc_val = altc, \ 69 } 70 71 #define UNUSED -1 72 /** 73 * struct alternate_functions 74 * @pin_number: The pin number 75 * @gpiosel_bit: Control bit in GPIOSEL register, 76 * @alt_bit1: First AlternateFunction bit used to select the 77 * alternate function 78 * @alt_bit2: Second AlternateFunction bit used to select the 79 * alternate function 80 * 81 * these 3 following fields are necessary due to none 82 * coherency on how to select the altA, altB and altC 83 * function between the ABx500 SOC family when using 84 * alternatfunc register. 85 * @alta_val: value to write in alternatfunc to select altA function 86 * @altb_val: value to write in alternatfunc to select altB function 87 * @altc_val: value to write in alternatfunc to select altC function 88 */ 89 struct alternate_functions { 90 unsigned pin_number; 91 s8 gpiosel_bit; 92 s8 alt_bit1; 93 s8 alt_bit2; 94 u8 alta_val; 95 u8 altb_val; 96 u8 altc_val; 97 }; 98 99 /** 100 * struct pullud - specific pull up/down feature 101 * @first_pin: The pin number of the first pins which support 102 * specific pull up/down 103 * @last_pin: The pin number of the last pins 104 */ 105 struct pullud { 106 unsigned first_pin; 107 unsigned last_pin; 108 }; 109 110 #define GPIO_IRQ_CLUSTER(a, b, c) \ 111 { \ 112 .start = a, \ 113 .end = b, \ 114 .to_irq = c, \ 115 } 116 117 /** 118 * struct abx500_gpio_irq_cluster - indicates GPIOs which are interrupt 119 * capable 120 * @start: The pin number of the first pin interrupt capable 121 * @end: The pin number of the last pin interrupt capable 122 * @to_irq: The ABx500 GPIO's associated IRQs are clustered 123 * together throughout the interrupt numbers at irregular 124 * intervals. To solve this quandary, we will place the 125 * read-in values into the cluster information table 126 */ 127 128 struct abx500_gpio_irq_cluster { 129 int start; 130 int end; 131 int to_irq; 132 }; 133 134 /** 135 * struct abx500_pinrange - map pin numbers to GPIO offsets 136 * @offset: offset into the GPIO local numberspace, incidentally 137 * identical to the offset into the local pin numberspace 138 * @npins: number of pins to map from both offsets 139 * @altfunc: altfunc setting to be used to enable GPIO on a pin in 140 * this range (may vary) 141 */ 142 struct abx500_pinrange { 143 unsigned int offset; 144 unsigned int npins; 145 int altfunc; 146 }; 147 148 #define ABX500_PINRANGE(a, b, c) { .offset = a, .npins = b, .altfunc = c } 149 150 /** 151 * struct abx500_pinctrl_soc_data - ABx500 pin controller per-SoC configuration 152 * @gpio_ranges: An array of GPIO ranges for this SoC 153 * @gpio_num_ranges: The number of GPIO ranges for this SoC 154 * @pins: An array describing all pins the pin controller affects. 155 * All pins which are also GPIOs must be listed first within the 156 * array, and be numbered identically to the GPIO controller's 157 * numbering. 158 * @npins: The number of entries in @pins. 159 * @functions: The functions supported on this SoC. 160 * @nfunction: The number of entries in @functions. 161 * @groups: An array describing all pin groups the pin SoC supports. 162 * @ngroups: The number of entries in @groups. 163 * @alternate_functions: array describing pins which supports alternate and 164 * how to set it. 165 * @pullud: array describing pins which supports pull up/down 166 * specific registers. 167 * @gpio_irq_cluster: An array of GPIO interrupt capable for this SoC 168 * @ngpio_irq_cluster: The number of GPIO inetrrupt capable for this SoC 169 * @irq_gpio_rising_offset: Interrupt offset used as base to compute specific 170 * setting strategy of the rising interrupt line 171 * @irq_gpio_falling_offset: Interrupt offset used as base to compute specific 172 * setting strategy of the falling interrupt line 173 * @irq_gpio_factor: Factor used to compute specific setting strategy of 174 * the interrupt line 175 */ 176 177 struct abx500_pinctrl_soc_data { 178 const struct abx500_pinrange *gpio_ranges; 179 unsigned gpio_num_ranges; 180 const struct pinctrl_pin_desc *pins; 181 unsigned npins; 182 const struct abx500_function *functions; 183 unsigned nfunctions; 184 const struct abx500_pingroup *groups; 185 unsigned ngroups; 186 struct alternate_functions *alternate_functions; 187 struct pullud *pullud; 188 struct abx500_gpio_irq_cluster *gpio_irq_cluster; 189 unsigned ngpio_irq_cluster; 190 int irq_gpio_rising_offset; 191 int irq_gpio_falling_offset; 192 int irq_gpio_factor; 193 }; 194 195 #ifdef CONFIG_PINCTRL_AB8500 196 197 void abx500_pinctrl_ab8500_init(struct abx500_pinctrl_soc_data **soc); 198 199 #else 200 201 static inline void 202 abx500_pinctrl_ab8500_init(struct abx500_pinctrl_soc_data **soc) 203 { 204 } 205 206 #endif 207 208 #ifdef CONFIG_PINCTRL_AB8540 209 210 void abx500_pinctrl_ab8540_init(struct abx500_pinctrl_soc_data **soc); 211 212 #else 213 214 static inline void 215 abx500_pinctrl_ab8540_init(struct abx500_pinctrl_soc_data **soc) 216 { 217 } 218 219 #endif 220 221 #ifdef CONFIG_PINCTRL_AB9540 222 223 void abx500_pinctrl_ab9540_init(struct abx500_pinctrl_soc_data **soc); 224 225 #else 226 227 static inline void 228 abx500_pinctrl_ab9540_init(struct abx500_pinctrl_soc_data **soc) 229 { 230 } 231 232 #endif 233 234 #ifdef CONFIG_PINCTRL_AB8505 235 236 void abx500_pinctrl_ab8505_init(struct abx500_pinctrl_soc_data **soc); 237 238 #else 239 240 static inline void 241 abx500_pinctrl_ab8505_init(struct abx500_pinctrl_soc_data **soc) 242 { 243 } 244 245 #endif 246 247 #endif /* PINCTRL_PINCTRL_ABx500_H */ 248