1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) ST-Ericsson SA 2013 4 * 5 * Author: Patrice Chotard <patrice.chotard@st.com> 6 * 7 * Driver allows to use AxB5xx unused pins to be used as GPIO 8 */ 9 #include <linux/kernel.h> 10 #include <linux/types.h> 11 #include <linux/slab.h> 12 #include <linux/init.h> 13 #include <linux/err.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/platform_device.h> 17 #include <linux/gpio/driver.h> 18 #include <linux/irq.h> 19 #include <linux/irqdomain.h> 20 #include <linux/interrupt.h> 21 #include <linux/bitops.h> 22 #include <linux/mfd/abx500.h> 23 #include <linux/mfd/abx500/ab8500.h> 24 #include <linux/pinctrl/pinctrl.h> 25 #include <linux/pinctrl/consumer.h> 26 #include <linux/pinctrl/pinmux.h> 27 #include <linux/pinctrl/pinconf.h> 28 #include <linux/pinctrl/pinconf-generic.h> 29 #include <linux/pinctrl/machine.h> 30 31 #include "pinctrl-abx500.h" 32 #include "../core.h" 33 #include "../pinconf.h" 34 #include "../pinctrl-utils.h" 35 36 /* 37 * GPIO registers offset 38 * Bank: 0x10 39 */ 40 #define AB8500_GPIO_SEL1_REG 0x00 41 #define AB8500_GPIO_SEL2_REG 0x01 42 #define AB8500_GPIO_SEL3_REG 0x02 43 #define AB8500_GPIO_SEL4_REG 0x03 44 #define AB8500_GPIO_SEL5_REG 0x04 45 #define AB8500_GPIO_SEL6_REG 0x05 46 47 #define AB8500_GPIO_DIR1_REG 0x10 48 #define AB8500_GPIO_DIR2_REG 0x11 49 #define AB8500_GPIO_DIR3_REG 0x12 50 #define AB8500_GPIO_DIR4_REG 0x13 51 #define AB8500_GPIO_DIR5_REG 0x14 52 #define AB8500_GPIO_DIR6_REG 0x15 53 54 #define AB8500_GPIO_OUT1_REG 0x20 55 #define AB8500_GPIO_OUT2_REG 0x21 56 #define AB8500_GPIO_OUT3_REG 0x22 57 #define AB8500_GPIO_OUT4_REG 0x23 58 #define AB8500_GPIO_OUT5_REG 0x24 59 #define AB8500_GPIO_OUT6_REG 0x25 60 61 #define AB8500_GPIO_PUD1_REG 0x30 62 #define AB8500_GPIO_PUD2_REG 0x31 63 #define AB8500_GPIO_PUD3_REG 0x32 64 #define AB8500_GPIO_PUD4_REG 0x33 65 #define AB8500_GPIO_PUD5_REG 0x34 66 #define AB8500_GPIO_PUD6_REG 0x35 67 68 #define AB8500_GPIO_IN1_REG 0x40 69 #define AB8500_GPIO_IN2_REG 0x41 70 #define AB8500_GPIO_IN3_REG 0x42 71 #define AB8500_GPIO_IN4_REG 0x43 72 #define AB8500_GPIO_IN5_REG 0x44 73 #define AB8500_GPIO_IN6_REG 0x45 74 #define AB8500_GPIO_ALTFUN_REG 0x50 75 76 #define ABX500_GPIO_INPUT 0 77 #define ABX500_GPIO_OUTPUT 1 78 79 struct abx500_pinctrl { 80 struct device *dev; 81 struct pinctrl_dev *pctldev; 82 struct abx500_pinctrl_soc_data *soc; 83 struct gpio_chip chip; 84 struct ab8500 *parent; 85 struct abx500_gpio_irq_cluster *irq_cluster; 86 int irq_cluster_size; 87 }; 88 89 static int abx500_gpio_get_bit(struct gpio_chip *chip, u8 reg, 90 unsigned offset, bool *bit) 91 { 92 struct abx500_pinctrl *pct = gpiochip_get_data(chip); 93 u8 pos = offset % 8; 94 u8 val; 95 int ret; 96 97 reg += offset / 8; 98 ret = abx500_get_register_interruptible(pct->dev, 99 AB8500_MISC, reg, &val); 100 if (ret < 0) { 101 dev_err(pct->dev, 102 "%s read reg =%x, offset=%x failed (%d)\n", 103 __func__, reg, offset, ret); 104 return ret; 105 } 106 107 *bit = !!(val & BIT(pos)); 108 109 return 0; 110 } 111 112 static int abx500_gpio_set_bits(struct gpio_chip *chip, u8 reg, 113 unsigned offset, int val) 114 { 115 struct abx500_pinctrl *pct = gpiochip_get_data(chip); 116 u8 pos = offset % 8; 117 int ret; 118 119 reg += offset / 8; 120 ret = abx500_mask_and_set_register_interruptible(pct->dev, 121 AB8500_MISC, reg, BIT(pos), val << pos); 122 if (ret < 0) 123 dev_err(pct->dev, "%s write reg, %x offset %x failed (%d)\n", 124 __func__, reg, offset, ret); 125 126 return ret; 127 } 128 129 /** 130 * abx500_gpio_get() - Get the particular GPIO value 131 * @chip: Gpio device 132 * @offset: GPIO number to read 133 */ 134 static int abx500_gpio_get(struct gpio_chip *chip, unsigned offset) 135 { 136 struct abx500_pinctrl *pct = gpiochip_get_data(chip); 137 bool bit; 138 bool is_out; 139 u8 gpio_offset = offset - 1; 140 int ret; 141 142 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG, 143 gpio_offset, &is_out); 144 if (ret < 0) 145 goto out; 146 147 if (is_out) 148 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_OUT1_REG, 149 gpio_offset, &bit); 150 else 151 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_IN1_REG, 152 gpio_offset, &bit); 153 out: 154 if (ret < 0) { 155 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); 156 return ret; 157 } 158 159 return bit; 160 } 161 162 static void abx500_gpio_set(struct gpio_chip *chip, unsigned offset, int val) 163 { 164 struct abx500_pinctrl *pct = gpiochip_get_data(chip); 165 int ret; 166 167 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val); 168 if (ret < 0) 169 dev_err(pct->dev, "%s write failed (%d)\n", __func__, ret); 170 } 171 172 static int abx500_gpio_direction_output(struct gpio_chip *chip, 173 unsigned offset, 174 int val) 175 { 176 struct abx500_pinctrl *pct = gpiochip_get_data(chip); 177 int ret; 178 179 /* set direction as output */ 180 ret = abx500_gpio_set_bits(chip, 181 AB8500_GPIO_DIR1_REG, 182 offset, 183 ABX500_GPIO_OUTPUT); 184 if (ret < 0) 185 goto out; 186 187 /* disable pull down */ 188 ret = abx500_gpio_set_bits(chip, 189 AB8500_GPIO_PUD1_REG, 190 offset, 191 ABX500_GPIO_PULL_NONE); 192 193 out: 194 if (ret < 0) { 195 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); 196 return ret; 197 } 198 199 /* set the output as 1 or 0 */ 200 return abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val); 201 } 202 203 static int abx500_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 204 { 205 /* set the register as input */ 206 return abx500_gpio_set_bits(chip, 207 AB8500_GPIO_DIR1_REG, 208 offset, 209 ABX500_GPIO_INPUT); 210 } 211 212 static int abx500_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 213 { 214 struct abx500_pinctrl *pct = gpiochip_get_data(chip); 215 /* The AB8500 GPIO numbers are off by one */ 216 int gpio = offset + 1; 217 int hwirq; 218 int i; 219 220 for (i = 0; i < pct->irq_cluster_size; i++) { 221 struct abx500_gpio_irq_cluster *cluster = 222 &pct->irq_cluster[i]; 223 224 if (gpio >= cluster->start && gpio <= cluster->end) { 225 /* 226 * The ABx500 GPIO's associated IRQs are clustered together 227 * throughout the interrupt numbers at irregular intervals. 228 * To solve this quandry, we have placed the read-in values 229 * into the cluster information table. 230 */ 231 hwirq = gpio - cluster->start + cluster->to_irq; 232 return irq_create_mapping(pct->parent->domain, hwirq); 233 } 234 } 235 236 return -EINVAL; 237 } 238 239 static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, 240 unsigned gpio, int alt_setting) 241 { 242 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); 243 struct alternate_functions af = pct->soc->alternate_functions[gpio]; 244 int ret; 245 int val; 246 unsigned offset; 247 248 const char *modes[] = { 249 [ABX500_DEFAULT] = "default", 250 [ABX500_ALT_A] = "altA", 251 [ABX500_ALT_B] = "altB", 252 [ABX500_ALT_C] = "altC", 253 }; 254 255 /* sanity check */ 256 if (((alt_setting == ABX500_ALT_A) && (af.gpiosel_bit == UNUSED)) || 257 ((alt_setting == ABX500_ALT_B) && (af.alt_bit1 == UNUSED)) || 258 ((alt_setting == ABX500_ALT_C) && (af.alt_bit2 == UNUSED))) { 259 dev_dbg(pct->dev, "pin %d doesn't support %s mode\n", gpio, 260 modes[alt_setting]); 261 return -EINVAL; 262 } 263 264 /* on ABx5xx, there is no GPIO0, so adjust the offset */ 265 offset = gpio - 1; 266 267 switch (alt_setting) { 268 case ABX500_DEFAULT: 269 /* 270 * for ABx5xx family, default mode is always selected by 271 * writing 0 to GPIOSELx register, except for pins which 272 * support at least ALT_B mode, default mode is selected 273 * by writing 1 to GPIOSELx register 274 */ 275 val = 0; 276 if (af.alt_bit1 != UNUSED) 277 val++; 278 279 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, 280 offset, val); 281 break; 282 283 case ABX500_ALT_A: 284 /* 285 * for ABx5xx family, alt_a mode is always selected by 286 * writing 1 to GPIOSELx register, except for pins which 287 * support at least ALT_B mode, alt_a mode is selected 288 * by writing 0 to GPIOSELx register and 0 in ALTFUNC 289 * register 290 */ 291 if (af.alt_bit1 != UNUSED) { 292 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, 293 offset, 0); 294 if (ret < 0) 295 goto out; 296 297 ret = abx500_gpio_set_bits(chip, 298 AB8500_GPIO_ALTFUN_REG, 299 af.alt_bit1, 300 !!(af.alta_val & BIT(0))); 301 if (ret < 0) 302 goto out; 303 304 if (af.alt_bit2 != UNUSED) 305 ret = abx500_gpio_set_bits(chip, 306 AB8500_GPIO_ALTFUN_REG, 307 af.alt_bit2, 308 !!(af.alta_val & BIT(1))); 309 } else 310 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, 311 offset, 1); 312 break; 313 314 case ABX500_ALT_B: 315 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, 316 offset, 0); 317 if (ret < 0) 318 goto out; 319 320 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, 321 af.alt_bit1, !!(af.altb_val & BIT(0))); 322 if (ret < 0) 323 goto out; 324 325 if (af.alt_bit2 != UNUSED) 326 ret = abx500_gpio_set_bits(chip, 327 AB8500_GPIO_ALTFUN_REG, 328 af.alt_bit2, 329 !!(af.altb_val & BIT(1))); 330 break; 331 332 case ABX500_ALT_C: 333 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, 334 offset, 0); 335 if (ret < 0) 336 goto out; 337 338 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, 339 af.alt_bit2, !!(af.altc_val & BIT(0))); 340 if (ret < 0) 341 goto out; 342 343 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, 344 af.alt_bit2, !!(af.altc_val & BIT(1))); 345 break; 346 347 default: 348 dev_dbg(pct->dev, "unknown alt_setting %d\n", alt_setting); 349 350 return -EINVAL; 351 } 352 out: 353 if (ret < 0) 354 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); 355 356 return ret; 357 } 358 359 #ifdef CONFIG_DEBUG_FS 360 static int abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, 361 unsigned gpio) 362 { 363 u8 mode; 364 bool bit_mode; 365 bool alt_bit1; 366 bool alt_bit2; 367 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); 368 struct alternate_functions af = pct->soc->alternate_functions[gpio]; 369 /* on ABx5xx, there is no GPIO0, so adjust the offset */ 370 unsigned offset = gpio - 1; 371 int ret; 372 373 /* 374 * if gpiosel_bit is set to unused, 375 * it means no GPIO or special case 376 */ 377 if (af.gpiosel_bit == UNUSED) 378 return ABX500_DEFAULT; 379 380 /* read GpioSelx register */ 381 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_SEL1_REG + (offset / 8), 382 af.gpiosel_bit, &bit_mode); 383 if (ret < 0) 384 goto out; 385 386 mode = bit_mode; 387 388 /* sanity check */ 389 if ((af.alt_bit1 < UNUSED) || (af.alt_bit1 > 7) || 390 (af.alt_bit2 < UNUSED) || (af.alt_bit2 > 7)) { 391 dev_err(pct->dev, 392 "alt_bitX value not in correct range (-1 to 7)\n"); 393 return -EINVAL; 394 } 395 396 /* if alt_bit2 is used, alt_bit1 must be used too */ 397 if ((af.alt_bit2 != UNUSED) && (af.alt_bit1 == UNUSED)) { 398 dev_err(pct->dev, 399 "if alt_bit2 is used, alt_bit1 can't be unused\n"); 400 return -EINVAL; 401 } 402 403 /* check if pin use AlternateFunction register */ 404 if ((af.alt_bit1 == UNUSED) && (af.alt_bit2 == UNUSED)) 405 return mode; 406 /* 407 * if pin GPIOSEL bit is set and pin supports alternate function, 408 * it means DEFAULT mode 409 */ 410 if (mode) 411 return ABX500_DEFAULT; 412 413 /* 414 * pin use the AlternatFunction register 415 * read alt_bit1 value 416 */ 417 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, 418 af.alt_bit1, &alt_bit1); 419 if (ret < 0) 420 goto out; 421 422 if (af.alt_bit2 != UNUSED) { 423 /* read alt_bit2 value */ 424 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, 425 af.alt_bit2, 426 &alt_bit2); 427 if (ret < 0) 428 goto out; 429 } else 430 alt_bit2 = 0; 431 432 mode = (alt_bit2 << 1) + alt_bit1; 433 if (mode == af.alta_val) 434 return ABX500_ALT_A; 435 else if (mode == af.altb_val) 436 return ABX500_ALT_B; 437 else 438 return ABX500_ALT_C; 439 440 out: 441 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); 442 return ret; 443 } 444 445 static void abx500_gpio_dbg_show_one(struct seq_file *s, 446 struct pinctrl_dev *pctldev, 447 struct gpio_chip *chip, 448 unsigned offset, unsigned gpio) 449 { 450 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); 451 const char *label = gpiochip_is_requested(chip, offset - 1); 452 u8 gpio_offset = offset - 1; 453 int mode = -1; 454 bool is_out; 455 bool pd; 456 int ret; 457 458 const char *modes[] = { 459 [ABX500_DEFAULT] = "default", 460 [ABX500_ALT_A] = "altA", 461 [ABX500_ALT_B] = "altB", 462 [ABX500_ALT_C] = "altC", 463 }; 464 465 const char *pull_up_down[] = { 466 [ABX500_GPIO_PULL_DOWN] = "pull down", 467 [ABX500_GPIO_PULL_NONE] = "pull none", 468 [ABX500_GPIO_PULL_NONE + 1] = "pull none", 469 [ABX500_GPIO_PULL_UP] = "pull up", 470 }; 471 472 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG, 473 gpio_offset, &is_out); 474 if (ret < 0) 475 goto out; 476 477 seq_printf(s, " gpio-%-3d (%-20.20s) %-3s", 478 gpio, label ?: "(none)", 479 is_out ? "out" : "in "); 480 481 if (!is_out) { 482 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG, 483 gpio_offset, &pd); 484 if (ret < 0) 485 goto out; 486 487 seq_printf(s, " %-9s", pull_up_down[pd]); 488 } else 489 seq_printf(s, " %-9s", chip->get(chip, offset) ? "hi" : "lo"); 490 491 mode = abx500_get_mode(pctldev, chip, offset); 492 493 seq_printf(s, " %s", (mode < 0) ? "unknown" : modes[mode]); 494 495 out: 496 if (ret < 0) 497 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); 498 } 499 500 static void abx500_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 501 { 502 unsigned i; 503 unsigned gpio = chip->base; 504 struct abx500_pinctrl *pct = gpiochip_get_data(chip); 505 struct pinctrl_dev *pctldev = pct->pctldev; 506 507 for (i = 0; i < chip->ngpio; i++, gpio++) { 508 /* On AB8500, there is no GPIO0, the first is the GPIO 1 */ 509 abx500_gpio_dbg_show_one(s, pctldev, chip, i + 1, gpio); 510 seq_putc(s, '\n'); 511 } 512 } 513 514 #else 515 static inline void abx500_gpio_dbg_show_one(struct seq_file *s, 516 struct pinctrl_dev *pctldev, 517 struct gpio_chip *chip, 518 unsigned offset, unsigned gpio) 519 { 520 } 521 #define abx500_gpio_dbg_show NULL 522 #endif 523 524 static const struct gpio_chip abx500gpio_chip = { 525 .label = "abx500-gpio", 526 .owner = THIS_MODULE, 527 .request = gpiochip_generic_request, 528 .free = gpiochip_generic_free, 529 .direction_input = abx500_gpio_direction_input, 530 .get = abx500_gpio_get, 531 .direction_output = abx500_gpio_direction_output, 532 .set = abx500_gpio_set, 533 .to_irq = abx500_gpio_to_irq, 534 .dbg_show = abx500_gpio_dbg_show, 535 }; 536 537 static int abx500_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 538 { 539 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); 540 541 return pct->soc->nfunctions; 542 } 543 544 static const char *abx500_pmx_get_func_name(struct pinctrl_dev *pctldev, 545 unsigned function) 546 { 547 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); 548 549 return pct->soc->functions[function].name; 550 } 551 552 static int abx500_pmx_get_func_groups(struct pinctrl_dev *pctldev, 553 unsigned function, 554 const char * const **groups, 555 unsigned * const num_groups) 556 { 557 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); 558 559 *groups = pct->soc->functions[function].groups; 560 *num_groups = pct->soc->functions[function].ngroups; 561 562 return 0; 563 } 564 565 static int abx500_pmx_set(struct pinctrl_dev *pctldev, unsigned function, 566 unsigned group) 567 { 568 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); 569 struct gpio_chip *chip = &pct->chip; 570 const struct abx500_pingroup *g; 571 int i; 572 int ret = 0; 573 574 g = &pct->soc->groups[group]; 575 if (g->altsetting < 0) 576 return -EINVAL; 577 578 dev_dbg(pct->dev, "enable group %s, %u pins\n", g->name, g->npins); 579 580 for (i = 0; i < g->npins; i++) { 581 dev_dbg(pct->dev, "setting pin %d to altsetting %d\n", 582 g->pins[i], g->altsetting); 583 584 ret = abx500_set_mode(pctldev, chip, g->pins[i], g->altsetting); 585 } 586 587 if (ret < 0) 588 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); 589 590 return ret; 591 } 592 593 static int abx500_gpio_request_enable(struct pinctrl_dev *pctldev, 594 struct pinctrl_gpio_range *range, 595 unsigned offset) 596 { 597 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); 598 const struct abx500_pinrange *p; 599 int ret; 600 int i; 601 602 /* 603 * Different ranges have different ways to enable GPIO function on a 604 * pin, so refer back to our local range type, where we handily define 605 * what altfunc enables GPIO for a certain pin. 606 */ 607 for (i = 0; i < pct->soc->gpio_num_ranges; i++) { 608 p = &pct->soc->gpio_ranges[i]; 609 if ((offset >= p->offset) && 610 (offset < (p->offset + p->npins))) 611 break; 612 } 613 614 if (i == pct->soc->gpio_num_ranges) { 615 dev_err(pct->dev, "%s failed to locate range\n", __func__); 616 return -ENODEV; 617 } 618 619 dev_dbg(pct->dev, "enable GPIO by altfunc %d at gpio %d\n", 620 p->altfunc, offset); 621 622 ret = abx500_set_mode(pct->pctldev, &pct->chip, 623 offset, p->altfunc); 624 if (ret < 0) 625 dev_err(pct->dev, "%s setting altfunc failed\n", __func__); 626 627 return ret; 628 } 629 630 static void abx500_gpio_disable_free(struct pinctrl_dev *pctldev, 631 struct pinctrl_gpio_range *range, 632 unsigned offset) 633 { 634 } 635 636 static const struct pinmux_ops abx500_pinmux_ops = { 637 .get_functions_count = abx500_pmx_get_funcs_cnt, 638 .get_function_name = abx500_pmx_get_func_name, 639 .get_function_groups = abx500_pmx_get_func_groups, 640 .set_mux = abx500_pmx_set, 641 .gpio_request_enable = abx500_gpio_request_enable, 642 .gpio_disable_free = abx500_gpio_disable_free, 643 }; 644 645 static int abx500_get_groups_cnt(struct pinctrl_dev *pctldev) 646 { 647 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); 648 649 return pct->soc->ngroups; 650 } 651 652 static const char *abx500_get_group_name(struct pinctrl_dev *pctldev, 653 unsigned selector) 654 { 655 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); 656 657 return pct->soc->groups[selector].name; 658 } 659 660 static int abx500_get_group_pins(struct pinctrl_dev *pctldev, 661 unsigned selector, 662 const unsigned **pins, 663 unsigned *num_pins) 664 { 665 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); 666 667 *pins = pct->soc->groups[selector].pins; 668 *num_pins = pct->soc->groups[selector].npins; 669 670 return 0; 671 } 672 673 static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev, 674 struct seq_file *s, unsigned offset) 675 { 676 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); 677 struct gpio_chip *chip = &pct->chip; 678 679 abx500_gpio_dbg_show_one(s, pctldev, chip, offset, 680 chip->base + offset - 1); 681 } 682 683 static int abx500_dt_add_map_mux(struct pinctrl_map **map, 684 unsigned *reserved_maps, 685 unsigned *num_maps, const char *group, 686 const char *function) 687 { 688 if (*num_maps == *reserved_maps) 689 return -ENOSPC; 690 691 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 692 (*map)[*num_maps].data.mux.group = group; 693 (*map)[*num_maps].data.mux.function = function; 694 (*num_maps)++; 695 696 return 0; 697 } 698 699 static int abx500_dt_add_map_configs(struct pinctrl_map **map, 700 unsigned *reserved_maps, 701 unsigned *num_maps, const char *group, 702 unsigned long *configs, unsigned num_configs) 703 { 704 unsigned long *dup_configs; 705 706 if (*num_maps == *reserved_maps) 707 return -ENOSPC; 708 709 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), 710 GFP_KERNEL); 711 if (!dup_configs) 712 return -ENOMEM; 713 714 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN; 715 716 (*map)[*num_maps].data.configs.group_or_pin = group; 717 (*map)[*num_maps].data.configs.configs = dup_configs; 718 (*map)[*num_maps].data.configs.num_configs = num_configs; 719 (*num_maps)++; 720 721 return 0; 722 } 723 724 static const char *abx500_find_pin_name(struct pinctrl_dev *pctldev, 725 const char *pin_name) 726 { 727 int i, pin_number; 728 struct abx500_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 729 730 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1) 731 for (i = 0; i < npct->soc->npins; i++) 732 if (npct->soc->pins[i].number == pin_number) 733 return npct->soc->pins[i].name; 734 return NULL; 735 } 736 737 static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev, 738 struct device_node *np, 739 struct pinctrl_map **map, 740 unsigned *reserved_maps, 741 unsigned *num_maps) 742 { 743 int ret; 744 const char *function = NULL; 745 unsigned long *configs; 746 unsigned int nconfigs = 0; 747 struct property *prop; 748 749 ret = of_property_read_string(np, "function", &function); 750 if (ret >= 0) { 751 const char *group; 752 753 ret = of_property_count_strings(np, "groups"); 754 if (ret < 0) 755 goto exit; 756 757 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, 758 num_maps, ret); 759 if (ret < 0) 760 goto exit; 761 762 of_property_for_each_string(np, "groups", prop, group) { 763 ret = abx500_dt_add_map_mux(map, reserved_maps, 764 num_maps, group, function); 765 if (ret < 0) 766 goto exit; 767 } 768 } 769 770 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &nconfigs); 771 if (nconfigs) { 772 const char *gpio_name; 773 const char *pin; 774 775 ret = of_property_count_strings(np, "pins"); 776 if (ret < 0) 777 goto exit; 778 779 ret = pinctrl_utils_reserve_map(pctldev, map, 780 reserved_maps, 781 num_maps, ret); 782 if (ret < 0) 783 goto exit; 784 785 of_property_for_each_string(np, "pins", prop, pin) { 786 gpio_name = abx500_find_pin_name(pctldev, pin); 787 788 ret = abx500_dt_add_map_configs(map, reserved_maps, 789 num_maps, gpio_name, configs, 1); 790 if (ret < 0) 791 goto exit; 792 } 793 } 794 795 exit: 796 return ret; 797 } 798 799 static int abx500_dt_node_to_map(struct pinctrl_dev *pctldev, 800 struct device_node *np_config, 801 struct pinctrl_map **map, unsigned *num_maps) 802 { 803 unsigned reserved_maps; 804 struct device_node *np; 805 int ret; 806 807 reserved_maps = 0; 808 *map = NULL; 809 *num_maps = 0; 810 811 for_each_child_of_node(np_config, np) { 812 ret = abx500_dt_subnode_to_map(pctldev, np, map, 813 &reserved_maps, num_maps); 814 if (ret < 0) { 815 pinctrl_utils_free_map(pctldev, *map, *num_maps); 816 of_node_put(np); 817 return ret; 818 } 819 } 820 821 return 0; 822 } 823 824 static const struct pinctrl_ops abx500_pinctrl_ops = { 825 .get_groups_count = abx500_get_groups_cnt, 826 .get_group_name = abx500_get_group_name, 827 .get_group_pins = abx500_get_group_pins, 828 .pin_dbg_show = abx500_pin_dbg_show, 829 .dt_node_to_map = abx500_dt_node_to_map, 830 .dt_free_map = pinctrl_utils_free_map, 831 }; 832 833 static int abx500_pin_config_get(struct pinctrl_dev *pctldev, 834 unsigned pin, 835 unsigned long *config) 836 { 837 return -ENOSYS; 838 } 839 840 static int abx500_pin_config_set(struct pinctrl_dev *pctldev, 841 unsigned pin, 842 unsigned long *configs, 843 unsigned num_configs) 844 { 845 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); 846 struct gpio_chip *chip = &pct->chip; 847 unsigned offset; 848 int ret = -EINVAL; 849 int i; 850 enum pin_config_param param; 851 enum pin_config_param argument; 852 853 for (i = 0; i < num_configs; i++) { 854 param = pinconf_to_config_param(configs[i]); 855 argument = pinconf_to_config_argument(configs[i]); 856 857 dev_dbg(chip->parent, "pin %d [%#lx]: %s %s\n", 858 pin, configs[i], 859 (param == PIN_CONFIG_OUTPUT) ? "output " : "input", 860 (param == PIN_CONFIG_OUTPUT) ? 861 (argument ? "high" : "low") : 862 (argument ? "pull up" : "pull down")); 863 864 /* on ABx500, there is no GPIO0, so adjust the offset */ 865 offset = pin - 1; 866 867 switch (param) { 868 case PIN_CONFIG_BIAS_DISABLE: 869 ret = abx500_gpio_direction_input(chip, offset); 870 if (ret < 0) 871 goto out; 872 873 /* Chip only supports pull down */ 874 ret = abx500_gpio_set_bits(chip, 875 AB8500_GPIO_PUD1_REG, offset, 876 ABX500_GPIO_PULL_NONE); 877 break; 878 879 case PIN_CONFIG_BIAS_PULL_DOWN: 880 ret = abx500_gpio_direction_input(chip, offset); 881 if (ret < 0) 882 goto out; 883 /* 884 * if argument = 1 set the pull down 885 * else clear the pull down 886 * Chip only supports pull down 887 */ 888 ret = abx500_gpio_set_bits(chip, 889 AB8500_GPIO_PUD1_REG, 890 offset, 891 argument ? ABX500_GPIO_PULL_DOWN : 892 ABX500_GPIO_PULL_NONE); 893 break; 894 895 case PIN_CONFIG_BIAS_PULL_UP: 896 ret = abx500_gpio_direction_input(chip, offset); 897 if (ret < 0) 898 goto out; 899 /* 900 * if argument = 1 set the pull up 901 * else clear the pull up 902 */ 903 ret = abx500_gpio_direction_input(chip, offset); 904 break; 905 906 case PIN_CONFIG_OUTPUT: 907 ret = abx500_gpio_direction_output(chip, offset, 908 argument); 909 break; 910 911 default: 912 dev_err(chip->parent, 913 "illegal configuration requested\n"); 914 } 915 } /* for each config */ 916 out: 917 if (ret < 0) 918 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); 919 920 return ret; 921 } 922 923 static const struct pinconf_ops abx500_pinconf_ops = { 924 .pin_config_get = abx500_pin_config_get, 925 .pin_config_set = abx500_pin_config_set, 926 .is_generic = true, 927 }; 928 929 static struct pinctrl_desc abx500_pinctrl_desc = { 930 .name = "pinctrl-abx500", 931 .pctlops = &abx500_pinctrl_ops, 932 .pmxops = &abx500_pinmux_ops, 933 .confops = &abx500_pinconf_ops, 934 .owner = THIS_MODULE, 935 }; 936 937 static int abx500_get_gpio_num(struct abx500_pinctrl_soc_data *soc) 938 { 939 unsigned int lowest = 0; 940 unsigned int highest = 0; 941 unsigned int npins = 0; 942 int i; 943 944 /* 945 * Compute number of GPIOs from the last SoC gpio range descriptors 946 * These ranges may include "holes" but the GPIO number space shall 947 * still be homogeneous, so we need to detect and account for any 948 * such holes so that these are included in the number of GPIO pins. 949 */ 950 for (i = 0; i < soc->gpio_num_ranges; i++) { 951 unsigned gstart; 952 unsigned gend; 953 const struct abx500_pinrange *p; 954 955 p = &soc->gpio_ranges[i]; 956 gstart = p->offset; 957 gend = p->offset + p->npins - 1; 958 959 if (i == 0) { 960 /* First iteration, set start values */ 961 lowest = gstart; 962 highest = gend; 963 } else { 964 if (gstart < lowest) 965 lowest = gstart; 966 if (gend > highest) 967 highest = gend; 968 } 969 } 970 /* this gives the absolute number of pins */ 971 npins = highest - lowest + 1; 972 return npins; 973 } 974 975 static const struct of_device_id abx500_gpio_match[] = { 976 { .compatible = "stericsson,ab8500-gpio", .data = (void *)PINCTRL_AB8500, }, 977 { .compatible = "stericsson,ab8505-gpio", .data = (void *)PINCTRL_AB8505, }, 978 { } 979 }; 980 981 static int abx500_gpio_probe(struct platform_device *pdev) 982 { 983 struct device_node *np = pdev->dev.of_node; 984 const struct of_device_id *match; 985 struct abx500_pinctrl *pct; 986 unsigned int id = -1; 987 int ret; 988 int i; 989 990 if (!np) { 991 dev_err(&pdev->dev, "gpio dt node missing\n"); 992 return -ENODEV; 993 } 994 995 pct = devm_kzalloc(&pdev->dev, sizeof(*pct), GFP_KERNEL); 996 if (!pct) 997 return -ENOMEM; 998 999 pct->dev = &pdev->dev; 1000 pct->parent = dev_get_drvdata(pdev->dev.parent); 1001 pct->chip = abx500gpio_chip; 1002 pct->chip.parent = &pdev->dev; 1003 pct->chip.base = -1; /* Dynamic allocation */ 1004 1005 match = of_match_device(abx500_gpio_match, &pdev->dev); 1006 if (!match) { 1007 dev_err(&pdev->dev, "gpio dt not matching\n"); 1008 return -ENODEV; 1009 } 1010 id = (unsigned long)match->data; 1011 1012 /* Poke in other ASIC variants here */ 1013 switch (id) { 1014 case PINCTRL_AB8500: 1015 abx500_pinctrl_ab8500_init(&pct->soc); 1016 break; 1017 case PINCTRL_AB8505: 1018 abx500_pinctrl_ab8505_init(&pct->soc); 1019 break; 1020 default: 1021 dev_err(&pdev->dev, "Unsupported pinctrl sub driver (%d)\n", id); 1022 return -EINVAL; 1023 } 1024 1025 if (!pct->soc) { 1026 dev_err(&pdev->dev, "Invalid SOC data\n"); 1027 return -EINVAL; 1028 } 1029 1030 pct->chip.ngpio = abx500_get_gpio_num(pct->soc); 1031 pct->irq_cluster = pct->soc->gpio_irq_cluster; 1032 pct->irq_cluster_size = pct->soc->ngpio_irq_cluster; 1033 1034 ret = gpiochip_add_data(&pct->chip, pct); 1035 if (ret) { 1036 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret); 1037 return ret; 1038 } 1039 dev_info(&pdev->dev, "added gpiochip\n"); 1040 1041 abx500_pinctrl_desc.pins = pct->soc->pins; 1042 abx500_pinctrl_desc.npins = pct->soc->npins; 1043 pct->pctldev = devm_pinctrl_register(&pdev->dev, &abx500_pinctrl_desc, 1044 pct); 1045 if (IS_ERR(pct->pctldev)) { 1046 dev_err(&pdev->dev, 1047 "could not register abx500 pinctrl driver\n"); 1048 ret = PTR_ERR(pct->pctldev); 1049 goto out_rem_chip; 1050 } 1051 dev_info(&pdev->dev, "registered pin controller\n"); 1052 1053 /* We will handle a range of GPIO pins */ 1054 for (i = 0; i < pct->soc->gpio_num_ranges; i++) { 1055 const struct abx500_pinrange *p = &pct->soc->gpio_ranges[i]; 1056 1057 ret = gpiochip_add_pin_range(&pct->chip, 1058 dev_name(&pdev->dev), 1059 p->offset - 1, p->offset, p->npins); 1060 if (ret < 0) 1061 goto out_rem_chip; 1062 } 1063 1064 platform_set_drvdata(pdev, pct); 1065 dev_info(&pdev->dev, "initialized abx500 pinctrl driver\n"); 1066 1067 return 0; 1068 1069 out_rem_chip: 1070 gpiochip_remove(&pct->chip); 1071 return ret; 1072 } 1073 1074 /** 1075 * abx500_gpio_remove() - remove Ab8500-gpio driver 1076 * @pdev: Platform device registered 1077 */ 1078 static int abx500_gpio_remove(struct platform_device *pdev) 1079 { 1080 struct abx500_pinctrl *pct = platform_get_drvdata(pdev); 1081 1082 gpiochip_remove(&pct->chip); 1083 return 0; 1084 } 1085 1086 static struct platform_driver abx500_gpio_driver = { 1087 .driver = { 1088 .name = "abx500-gpio", 1089 .of_match_table = abx500_gpio_match, 1090 }, 1091 .probe = abx500_gpio_probe, 1092 .remove = abx500_gpio_remove, 1093 }; 1094 1095 static int __init abx500_gpio_init(void) 1096 { 1097 return platform_driver_register(&abx500_gpio_driver); 1098 } 1099 core_initcall(abx500_gpio_init); 1100