1 /* 2 * Marvell Dove pinctrl driver based on mvebu pinctrl core 3 * 4 * Author: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #include <linux/err.h> 13 #include <linux/init.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/bitops.h> 17 #include <linux/platform_device.h> 18 #include <linux/clk.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/mfd/syscon.h> 22 #include <linux/pinctrl/pinctrl.h> 23 #include <linux/regmap.h> 24 25 #include "pinctrl-mvebu.h" 26 27 /* Internal registers can be configured at any 1 MiB aligned address */ 28 #define INT_REGS_MASK ~(SZ_1M - 1) 29 #define MPP4_REGS_OFFS 0xd0440 30 #define PMU_REGS_OFFS 0xd802c 31 #define GC_REGS_OFFS 0xe802c 32 33 #define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000) 34 #define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200) 35 #define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10) 36 #define DOVE_AU0_AC97_SEL BIT(16) 37 #define DOVE_PMU_SIGNAL_SELECT_0 (DOVE_SB_REGS_VIRT_BASE + 0xd802C) 38 #define DOVE_PMU_SIGNAL_SELECT_1 (DOVE_SB_REGS_VIRT_BASE + 0xd8030) 39 #define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) 40 #define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) 41 #define DOVE_TWSI_ENABLE_OPTION1 BIT(7) 42 #define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030) 43 #define DOVE_TWSI_ENABLE_OPTION2 BIT(20) 44 #define DOVE_TWSI_ENABLE_OPTION3 BIT(21) 45 #define DOVE_TWSI_OPTION3_GPIO BIT(22) 46 #define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034) 47 #define DOVE_SSP_ON_AU1 BIT(0) 48 #define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c) 49 #define DOVE_AU1_SPDIFO_GPIO_EN BIT(1) 50 #define DOVE_NAND_GPIO_EN BIT(0) 51 #define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400) 52 #define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40) 53 #define DOVE_SPI_GPIO_SEL BIT(5) 54 #define DOVE_UART1_GPIO_SEL BIT(4) 55 #define DOVE_AU1_GPIO_SEL BIT(3) 56 #define DOVE_CAM_GPIO_SEL BIT(2) 57 #define DOVE_SD1_GPIO_SEL BIT(1) 58 #define DOVE_SD0_GPIO_SEL BIT(0) 59 60 #define CONFIG_PMU BIT(4) 61 62 static void __iomem *mpp_base; 63 static void __iomem *mpp4_base; 64 static void __iomem *pmu_base; 65 static struct regmap *gconfmap; 66 67 static int dove_mpp_ctrl_get(unsigned pid, unsigned long *config) 68 { 69 return default_mpp_ctrl_get(mpp_base, pid, config); 70 } 71 72 static int dove_mpp_ctrl_set(unsigned pid, unsigned long config) 73 { 74 return default_mpp_ctrl_set(mpp_base, pid, config); 75 } 76 77 static int dove_pmu_mpp_ctrl_get(unsigned pid, unsigned long *config) 78 { 79 unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; 80 unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; 81 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); 82 unsigned long func; 83 84 if ((pmu & BIT(pid)) == 0) 85 return default_mpp_ctrl_get(mpp_base, pid, config); 86 87 func = readl(DOVE_PMU_SIGNAL_SELECT_0 + off); 88 *config = (func >> shift) & MVEBU_MPP_MASK; 89 *config |= CONFIG_PMU; 90 91 return 0; 92 } 93 94 static int dove_pmu_mpp_ctrl_set(unsigned pid, unsigned long config) 95 { 96 unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; 97 unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; 98 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); 99 unsigned long func; 100 101 if ((config & CONFIG_PMU) == 0) { 102 writel(pmu & ~BIT(pid), DOVE_PMU_MPP_GENERAL_CTRL); 103 return default_mpp_ctrl_set(mpp_base, pid, config); 104 } 105 106 writel(pmu | BIT(pid), DOVE_PMU_MPP_GENERAL_CTRL); 107 func = readl(DOVE_PMU_SIGNAL_SELECT_0 + off); 108 func &= ~(MVEBU_MPP_MASK << shift); 109 func |= (config & MVEBU_MPP_MASK) << shift; 110 writel(func, DOVE_PMU_SIGNAL_SELECT_0 + off); 111 112 return 0; 113 } 114 115 static int dove_mpp4_ctrl_get(unsigned pid, unsigned long *config) 116 { 117 unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 118 unsigned long mask; 119 120 switch (pid) { 121 case 24: /* mpp_camera */ 122 mask = DOVE_CAM_GPIO_SEL; 123 break; 124 case 40: /* mpp_sdio0 */ 125 mask = DOVE_SD0_GPIO_SEL; 126 break; 127 case 46: /* mpp_sdio1 */ 128 mask = DOVE_SD1_GPIO_SEL; 129 break; 130 case 58: /* mpp_spi0 */ 131 mask = DOVE_SPI_GPIO_SEL; 132 break; 133 case 62: /* mpp_uart1 */ 134 mask = DOVE_UART1_GPIO_SEL; 135 break; 136 default: 137 return -EINVAL; 138 } 139 140 *config = ((mpp4 & mask) != 0); 141 142 return 0; 143 } 144 145 static int dove_mpp4_ctrl_set(unsigned pid, unsigned long config) 146 { 147 unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 148 unsigned long mask; 149 150 switch (pid) { 151 case 24: /* mpp_camera */ 152 mask = DOVE_CAM_GPIO_SEL; 153 break; 154 case 40: /* mpp_sdio0 */ 155 mask = DOVE_SD0_GPIO_SEL; 156 break; 157 case 46: /* mpp_sdio1 */ 158 mask = DOVE_SD1_GPIO_SEL; 159 break; 160 case 58: /* mpp_spi0 */ 161 mask = DOVE_SPI_GPIO_SEL; 162 break; 163 case 62: /* mpp_uart1 */ 164 mask = DOVE_UART1_GPIO_SEL; 165 break; 166 default: 167 return -EINVAL; 168 } 169 170 mpp4 &= ~mask; 171 if (config) 172 mpp4 |= mask; 173 174 writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE); 175 176 return 0; 177 } 178 179 static int dove_nand_ctrl_get(unsigned pid, unsigned long *config) 180 { 181 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 182 183 *config = ((gmpp & DOVE_NAND_GPIO_EN) != 0); 184 185 return 0; 186 } 187 188 static int dove_nand_ctrl_set(unsigned pid, unsigned long config) 189 { 190 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 191 192 gmpp &= ~DOVE_NAND_GPIO_EN; 193 if (config) 194 gmpp |= DOVE_NAND_GPIO_EN; 195 196 writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE); 197 198 return 0; 199 } 200 201 static int dove_audio0_ctrl_get(unsigned pid, unsigned long *config) 202 { 203 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); 204 205 *config = ((pmu & DOVE_AU0_AC97_SEL) != 0); 206 207 return 0; 208 } 209 210 static int dove_audio0_ctrl_set(unsigned pid, unsigned long config) 211 { 212 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); 213 214 pmu &= ~DOVE_AU0_AC97_SEL; 215 if (config) 216 pmu |= DOVE_AU0_AC97_SEL; 217 writel(pmu, DOVE_PMU_MPP_GENERAL_CTRL); 218 219 return 0; 220 } 221 222 static int dove_audio1_ctrl_get(unsigned pid, unsigned long *config) 223 { 224 unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 225 unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1); 226 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 227 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 228 229 *config = 0; 230 if (mpp4 & DOVE_AU1_GPIO_SEL) 231 *config |= BIT(3); 232 if (sspc1 & DOVE_SSP_ON_AU1) 233 *config |= BIT(2); 234 if (gmpp & DOVE_AU1_SPDIFO_GPIO_EN) 235 *config |= BIT(1); 236 if (gcfg2 & DOVE_TWSI_OPTION3_GPIO) 237 *config |= BIT(0); 238 239 /* SSP/TWSI only if I2S1 not set*/ 240 if ((*config & BIT(3)) == 0) 241 *config &= ~(BIT(2) | BIT(0)); 242 /* TWSI only if SPDIFO not set*/ 243 if ((*config & BIT(1)) == 0) 244 *config &= ~BIT(0); 245 return 0; 246 } 247 248 static int dove_audio1_ctrl_set(unsigned pid, unsigned long config) 249 { 250 unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 251 unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1); 252 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 253 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 254 255 /* 256 * clear all audio1 related bits before configure 257 */ 258 gcfg2 &= ~DOVE_TWSI_OPTION3_GPIO; 259 gmpp &= ~DOVE_AU1_SPDIFO_GPIO_EN; 260 sspc1 &= ~DOVE_SSP_ON_AU1; 261 mpp4 &= ~DOVE_AU1_GPIO_SEL; 262 263 if (config & BIT(0)) 264 gcfg2 |= DOVE_TWSI_OPTION3_GPIO; 265 if (config & BIT(1)) 266 gmpp |= DOVE_AU1_SPDIFO_GPIO_EN; 267 if (config & BIT(2)) 268 sspc1 |= DOVE_SSP_ON_AU1; 269 if (config & BIT(3)) 270 mpp4 |= DOVE_AU1_GPIO_SEL; 271 272 writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE); 273 writel(sspc1, DOVE_SSP_CTRL_STATUS_1); 274 writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE); 275 writel(gcfg2, DOVE_GLOBAL_CONFIG_2); 276 277 return 0; 278 } 279 280 /* mpp[52:57] gpio pins depend heavily on current config; 281 * gpio_req does not try to mux in gpio capabilities to not 282 * break other functions. If you require all mpps as gpio 283 * enforce gpio setting by pinctrl mapping. 284 */ 285 static int dove_audio1_ctrl_gpio_req(unsigned pid) 286 { 287 unsigned long config; 288 289 dove_audio1_ctrl_get(pid, &config); 290 291 switch (config) { 292 case 0x02: /* i2s1 : gpio[56:57] */ 293 case 0x0e: /* ssp : gpio[56:57] */ 294 if (pid >= 56) 295 return 0; 296 return -ENOTSUPP; 297 case 0x08: /* spdifo : gpio[52:55] */ 298 case 0x0b: /* twsi : gpio[52:55] */ 299 if (pid <= 55) 300 return 0; 301 return -ENOTSUPP; 302 case 0x0a: /* all gpio */ 303 return 0; 304 /* 0x00 : i2s1/spdifo : no gpio */ 305 /* 0x0c : ssp/spdifo : no gpio */ 306 /* 0x0f : ssp/twsi : no gpio */ 307 } 308 return -ENOTSUPP; 309 } 310 311 /* mpp[52:57] has gpio pins capable of in and out */ 312 static int dove_audio1_ctrl_gpio_dir(unsigned pid, bool input) 313 { 314 if (pid < 52 || pid > 57) 315 return -ENOTSUPP; 316 return 0; 317 } 318 319 static int dove_twsi_ctrl_get(unsigned pid, unsigned long *config) 320 { 321 unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1); 322 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 323 324 *config = 0; 325 if (gcfg1 & DOVE_TWSI_ENABLE_OPTION1) 326 *config = 1; 327 else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION2) 328 *config = 2; 329 else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION3) 330 *config = 3; 331 332 return 0; 333 } 334 335 static int dove_twsi_ctrl_set(unsigned pid, unsigned long config) 336 { 337 unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1); 338 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 339 340 gcfg1 &= ~DOVE_TWSI_ENABLE_OPTION1; 341 gcfg2 &= ~(DOVE_TWSI_ENABLE_OPTION2 | DOVE_TWSI_ENABLE_OPTION3); 342 343 switch (config) { 344 case 1: 345 gcfg1 |= DOVE_TWSI_ENABLE_OPTION1; 346 break; 347 case 2: 348 gcfg2 |= DOVE_TWSI_ENABLE_OPTION2; 349 break; 350 case 3: 351 gcfg2 |= DOVE_TWSI_ENABLE_OPTION3; 352 break; 353 } 354 355 writel(gcfg1, DOVE_GLOBAL_CONFIG_1); 356 writel(gcfg2, DOVE_GLOBAL_CONFIG_2); 357 358 return 0; 359 } 360 361 static struct mvebu_mpp_ctrl dove_mpp_controls[] = { 362 MPP_FUNC_CTRL(0, 15, NULL, dove_pmu_mpp_ctrl), 363 MPP_FUNC_CTRL(16, 23, NULL, dove_mpp_ctrl), 364 MPP_FUNC_CTRL(24, 39, "mpp_camera", dove_mpp4_ctrl), 365 MPP_FUNC_CTRL(40, 45, "mpp_sdio0", dove_mpp4_ctrl), 366 MPP_FUNC_CTRL(46, 51, "mpp_sdio1", dove_mpp4_ctrl), 367 MPP_FUNC_GPIO_CTRL(52, 57, "mpp_audio1", dove_audio1_ctrl), 368 MPP_FUNC_CTRL(58, 61, "mpp_spi0", dove_mpp4_ctrl), 369 MPP_FUNC_CTRL(62, 63, "mpp_uart1", dove_mpp4_ctrl), 370 MPP_FUNC_CTRL(64, 71, "mpp_nand", dove_nand_ctrl), 371 MPP_FUNC_CTRL(72, 72, "audio0", dove_audio0_ctrl), 372 MPP_FUNC_CTRL(73, 73, "twsi", dove_twsi_ctrl), 373 }; 374 375 static struct mvebu_mpp_mode dove_mpp_modes[] = { 376 MPP_MODE(0, 377 MPP_FUNCTION(0x00, "gpio", NULL), 378 MPP_FUNCTION(0x02, "uart2", "rts"), 379 MPP_FUNCTION(0x03, "sdio0", "cd"), 380 MPP_FUNCTION(0x0f, "lcd0", "pwm"), 381 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 382 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 383 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 384 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 385 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 386 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 387 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 388 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 389 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 390 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 391 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 392 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 393 MPP_MODE(1, 394 MPP_FUNCTION(0x00, "gpio", NULL), 395 MPP_FUNCTION(0x02, "uart2", "cts"), 396 MPP_FUNCTION(0x03, "sdio0", "wp"), 397 MPP_FUNCTION(0x0f, "lcd1", "pwm"), 398 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 399 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 400 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 401 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 402 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 403 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 404 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 405 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 406 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 407 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 408 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 409 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 410 MPP_MODE(2, 411 MPP_FUNCTION(0x00, "gpio", NULL), 412 MPP_FUNCTION(0x01, "sata", "prsnt"), 413 MPP_FUNCTION(0x02, "uart2", "txd"), 414 MPP_FUNCTION(0x03, "sdio0", "buspwr"), 415 MPP_FUNCTION(0x04, "uart1", "rts"), 416 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 417 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 418 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 419 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 420 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 421 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 422 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 423 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 424 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 425 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 426 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 427 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 428 MPP_MODE(3, 429 MPP_FUNCTION(0x00, "gpio", NULL), 430 MPP_FUNCTION(0x01, "sata", "act"), 431 MPP_FUNCTION(0x02, "uart2", "rxd"), 432 MPP_FUNCTION(0x03, "sdio0", "ledctrl"), 433 MPP_FUNCTION(0x04, "uart1", "cts"), 434 MPP_FUNCTION(0x0f, "lcd-spi", "cs1"), 435 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 436 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 437 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 438 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 439 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 440 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 441 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 442 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 443 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 444 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 445 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 446 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 447 MPP_MODE(4, 448 MPP_FUNCTION(0x00, "gpio", NULL), 449 MPP_FUNCTION(0x02, "uart3", "rts"), 450 MPP_FUNCTION(0x03, "sdio1", "cd"), 451 MPP_FUNCTION(0x04, "spi1", "miso"), 452 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 453 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 454 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 455 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 456 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 457 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 458 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 459 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 460 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 461 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 462 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 463 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 464 MPP_MODE(5, 465 MPP_FUNCTION(0x00, "gpio", NULL), 466 MPP_FUNCTION(0x02, "uart3", "cts"), 467 MPP_FUNCTION(0x03, "sdio1", "wp"), 468 MPP_FUNCTION(0x04, "spi1", "cs"), 469 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 470 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 471 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 472 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 473 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 474 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 475 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 476 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 477 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 478 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 479 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 480 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 481 MPP_MODE(6, 482 MPP_FUNCTION(0x00, "gpio", NULL), 483 MPP_FUNCTION(0x02, "uart3", "txd"), 484 MPP_FUNCTION(0x03, "sdio1", "buspwr"), 485 MPP_FUNCTION(0x04, "spi1", "mosi"), 486 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 487 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 488 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 489 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 490 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 491 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 492 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 493 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 494 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 495 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 496 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 497 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 498 MPP_MODE(7, 499 MPP_FUNCTION(0x00, "gpio", NULL), 500 MPP_FUNCTION(0x02, "uart3", "rxd"), 501 MPP_FUNCTION(0x03, "sdio1", "ledctrl"), 502 MPP_FUNCTION(0x04, "spi1", "sck"), 503 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 504 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 505 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 506 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 507 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 508 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 509 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 510 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 511 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 512 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 513 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 514 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 515 MPP_MODE(8, 516 MPP_FUNCTION(0x00, "gpio", NULL), 517 MPP_FUNCTION(0x01, "watchdog", "rstout"), 518 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 519 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 520 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 521 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 522 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 523 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 524 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 525 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 526 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 527 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 528 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 529 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 530 MPP_MODE(9, 531 MPP_FUNCTION(0x00, "gpio", NULL), 532 MPP_FUNCTION(0x05, "pex1", "clkreq"), 533 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 534 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 535 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 536 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 537 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 538 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 539 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 540 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 541 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 542 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 543 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 544 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 545 MPP_MODE(10, 546 MPP_FUNCTION(0x00, "gpio", NULL), 547 MPP_FUNCTION(0x05, "ssp", "sclk"), 548 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 549 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 550 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 551 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 552 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 553 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 554 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 555 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 556 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 557 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 558 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 559 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 560 MPP_MODE(11, 561 MPP_FUNCTION(0x00, "gpio", NULL), 562 MPP_FUNCTION(0x01, "sata", "prsnt"), 563 MPP_FUNCTION(0x02, "sata-1", "act"), 564 MPP_FUNCTION(0x03, "sdio0", "ledctrl"), 565 MPP_FUNCTION(0x04, "sdio1", "ledctrl"), 566 MPP_FUNCTION(0x05, "pex0", "clkreq"), 567 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 568 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 569 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 570 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 571 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 572 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 573 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 574 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 575 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 576 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 577 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 578 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 579 MPP_MODE(12, 580 MPP_FUNCTION(0x00, "gpio", NULL), 581 MPP_FUNCTION(0x01, "sata", "act"), 582 MPP_FUNCTION(0x02, "uart2", "rts"), 583 MPP_FUNCTION(0x03, "audio0", "extclk"), 584 MPP_FUNCTION(0x04, "sdio1", "cd"), 585 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 586 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 587 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 588 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 589 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 590 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 591 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 592 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 593 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 594 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 595 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 596 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 597 MPP_MODE(13, 598 MPP_FUNCTION(0x00, "gpio", NULL), 599 MPP_FUNCTION(0x02, "uart2", "cts"), 600 MPP_FUNCTION(0x03, "audio1", "extclk"), 601 MPP_FUNCTION(0x04, "sdio1", "wp"), 602 MPP_FUNCTION(0x05, "ssp", "extclk"), 603 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 604 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 605 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 606 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 607 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 608 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 609 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 610 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 611 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 612 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 613 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 614 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 615 MPP_MODE(14, 616 MPP_FUNCTION(0x00, "gpio", NULL), 617 MPP_FUNCTION(0x02, "uart2", "txd"), 618 MPP_FUNCTION(0x04, "sdio1", "buspwr"), 619 MPP_FUNCTION(0x05, "ssp", "rxd"), 620 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 621 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 622 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 623 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 624 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 625 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 626 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 627 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 628 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 629 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 630 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 631 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 632 MPP_MODE(15, 633 MPP_FUNCTION(0x00, "gpio", NULL), 634 MPP_FUNCTION(0x02, "uart2", "rxd"), 635 MPP_FUNCTION(0x04, "sdio1", "ledctrl"), 636 MPP_FUNCTION(0x05, "ssp", "sfrm"), 637 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 638 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 639 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 640 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 641 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 642 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 643 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 644 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 645 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 646 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 647 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 648 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 649 MPP_MODE(16, 650 MPP_FUNCTION(0x00, "gpio", NULL), 651 MPP_FUNCTION(0x02, "uart3", "rts"), 652 MPP_FUNCTION(0x03, "sdio0", "cd"), 653 MPP_FUNCTION(0x04, "lcd-spi", "cs1"), 654 MPP_FUNCTION(0x05, "ac97", "sdi1")), 655 MPP_MODE(17, 656 MPP_FUNCTION(0x00, "gpio", NULL), 657 MPP_FUNCTION(0x01, "ac97-1", "sysclko"), 658 MPP_FUNCTION(0x02, "uart3", "cts"), 659 MPP_FUNCTION(0x03, "sdio0", "wp"), 660 MPP_FUNCTION(0x04, "twsi", "sda"), 661 MPP_FUNCTION(0x05, "ac97", "sdi2")), 662 MPP_MODE(18, 663 MPP_FUNCTION(0x00, "gpio", NULL), 664 MPP_FUNCTION(0x02, "uart3", "txd"), 665 MPP_FUNCTION(0x03, "sdio0", "buspwr"), 666 MPP_FUNCTION(0x04, "lcd0", "pwm"), 667 MPP_FUNCTION(0x05, "ac97", "sdi3")), 668 MPP_MODE(19, 669 MPP_FUNCTION(0x00, "gpio", NULL), 670 MPP_FUNCTION(0x02, "uart3", "rxd"), 671 MPP_FUNCTION(0x03, "sdio0", "ledctrl"), 672 MPP_FUNCTION(0x04, "twsi", "sck")), 673 MPP_MODE(20, 674 MPP_FUNCTION(0x00, "gpio", NULL), 675 MPP_FUNCTION(0x01, "ac97", "sysclko"), 676 MPP_FUNCTION(0x02, "lcd-spi", "miso"), 677 MPP_FUNCTION(0x03, "sdio1", "cd"), 678 MPP_FUNCTION(0x05, "sdio0", "cd"), 679 MPP_FUNCTION(0x06, "spi1", "miso")), 680 MPP_MODE(21, 681 MPP_FUNCTION(0x00, "gpio", NULL), 682 MPP_FUNCTION(0x01, "uart1", "rts"), 683 MPP_FUNCTION(0x02, "lcd-spi", "cs0"), 684 MPP_FUNCTION(0x03, "sdio1", "wp"), 685 MPP_FUNCTION(0x04, "ssp", "sfrm"), 686 MPP_FUNCTION(0x05, "sdio0", "wp"), 687 MPP_FUNCTION(0x06, "spi1", "cs")), 688 MPP_MODE(22, 689 MPP_FUNCTION(0x00, "gpio", NULL), 690 MPP_FUNCTION(0x01, "uart1", "cts"), 691 MPP_FUNCTION(0x02, "lcd-spi", "mosi"), 692 MPP_FUNCTION(0x03, "sdio1", "buspwr"), 693 MPP_FUNCTION(0x04, "ssp", "txd"), 694 MPP_FUNCTION(0x05, "sdio0", "buspwr"), 695 MPP_FUNCTION(0x06, "spi1", "mosi")), 696 MPP_MODE(23, 697 MPP_FUNCTION(0x00, "gpio", NULL), 698 MPP_FUNCTION(0x02, "lcd-spi", "sck"), 699 MPP_FUNCTION(0x03, "sdio1", "ledctrl"), 700 MPP_FUNCTION(0x04, "ssp", "sclk"), 701 MPP_FUNCTION(0x05, "sdio0", "ledctrl"), 702 MPP_FUNCTION(0x06, "spi1", "sck")), 703 MPP_MODE(24, 704 MPP_FUNCTION(0x00, "camera", NULL), 705 MPP_FUNCTION(0x01, "gpio", NULL)), 706 MPP_MODE(40, 707 MPP_FUNCTION(0x00, "sdio0", NULL), 708 MPP_FUNCTION(0x01, "gpio", NULL)), 709 MPP_MODE(46, 710 MPP_FUNCTION(0x00, "sdio1", NULL), 711 MPP_FUNCTION(0x01, "gpio", NULL)), 712 MPP_MODE(52, 713 MPP_FUNCTION(0x00, "i2s1/spdifo", NULL), 714 MPP_FUNCTION(0x02, "i2s1", NULL), 715 MPP_FUNCTION(0x08, "spdifo", NULL), 716 MPP_FUNCTION(0x0a, "gpio", NULL), 717 MPP_FUNCTION(0x0b, "twsi", NULL), 718 MPP_FUNCTION(0x0c, "ssp/spdifo", NULL), 719 MPP_FUNCTION(0x0e, "ssp", NULL), 720 MPP_FUNCTION(0x0f, "ssp/twsi", NULL)), 721 MPP_MODE(58, 722 MPP_FUNCTION(0x00, "spi0", NULL), 723 MPP_FUNCTION(0x01, "gpio", NULL)), 724 MPP_MODE(62, 725 MPP_FUNCTION(0x00, "uart1", NULL), 726 MPP_FUNCTION(0x01, "gpio", NULL)), 727 MPP_MODE(64, 728 MPP_FUNCTION(0x00, "nand", NULL), 729 MPP_FUNCTION(0x01, "gpo", NULL)), 730 MPP_MODE(72, 731 MPP_FUNCTION(0x00, "i2s", NULL), 732 MPP_FUNCTION(0x01, "ac97", NULL)), 733 MPP_MODE(73, 734 MPP_FUNCTION(0x00, "twsi-none", NULL), 735 MPP_FUNCTION(0x01, "twsi-opt1", NULL), 736 MPP_FUNCTION(0x02, "twsi-opt2", NULL), 737 MPP_FUNCTION(0x03, "twsi-opt3", NULL)), 738 }; 739 740 static struct pinctrl_gpio_range dove_mpp_gpio_ranges[] = { 741 MPP_GPIO_RANGE(0, 0, 0, 32), 742 MPP_GPIO_RANGE(1, 32, 32, 32), 743 MPP_GPIO_RANGE(2, 64, 64, 8), 744 }; 745 746 static struct mvebu_pinctrl_soc_info dove_pinctrl_info = { 747 .controls = dove_mpp_controls, 748 .ncontrols = ARRAY_SIZE(dove_mpp_controls), 749 .modes = dove_mpp_modes, 750 .nmodes = ARRAY_SIZE(dove_mpp_modes), 751 .gpioranges = dove_mpp_gpio_ranges, 752 .ngpioranges = ARRAY_SIZE(dove_mpp_gpio_ranges), 753 .variant = 0, 754 }; 755 756 static struct clk *clk; 757 758 static struct of_device_id dove_pinctrl_of_match[] = { 759 { .compatible = "marvell,dove-pinctrl", .data = &dove_pinctrl_info }, 760 { } 761 }; 762 763 static struct regmap_config gc_regmap_config = { 764 .reg_bits = 32, 765 .val_bits = 32, 766 .reg_stride = 4, 767 .max_register = 5, 768 }; 769 770 static int dove_pinctrl_probe(struct platform_device *pdev) 771 { 772 struct resource *res, *mpp_res; 773 struct resource fb_res; 774 const struct of_device_id *match = 775 of_match_device(dove_pinctrl_of_match, &pdev->dev); 776 pdev->dev.platform_data = (void *)match->data; 777 778 /* 779 * General MPP Configuration Register is part of pdma registers. 780 * grab clk to make sure it is ticking. 781 */ 782 clk = devm_clk_get(&pdev->dev, NULL); 783 if (IS_ERR(clk)) { 784 dev_err(&pdev->dev, "Unable to get pdma clock"); 785 return PTR_ERR(clk); 786 } 787 clk_prepare_enable(clk); 788 789 mpp_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 790 mpp_base = devm_ioremap_resource(&pdev->dev, mpp_res); 791 if (IS_ERR(mpp_base)) 792 return PTR_ERR(mpp_base); 793 794 /* prepare fallback resource */ 795 memcpy(&fb_res, mpp_res, sizeof(struct resource)); 796 fb_res.start = 0; 797 798 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 799 if (!res) { 800 dev_warn(&pdev->dev, "falling back to hardcoded MPP4 resource\n"); 801 adjust_resource(&fb_res, 802 (mpp_res->start & INT_REGS_MASK) + MPP4_REGS_OFFS, 0x4); 803 res = &fb_res; 804 } 805 806 mpp4_base = devm_ioremap_resource(&pdev->dev, res); 807 if (IS_ERR(mpp4_base)) 808 return PTR_ERR(mpp4_base); 809 810 res = platform_get_resource(pdev, IORESOURCE_MEM, 2); 811 if (!res) { 812 dev_warn(&pdev->dev, "falling back to hardcoded PMU resource\n"); 813 adjust_resource(&fb_res, 814 (mpp_res->start & INT_REGS_MASK) + PMU_REGS_OFFS, 0x8); 815 res = &fb_res; 816 } 817 818 pmu_base = devm_ioremap_resource(&pdev->dev, res); 819 if (IS_ERR(pmu_base)) 820 return PTR_ERR(pmu_base); 821 822 gconfmap = syscon_regmap_lookup_by_compatible("marvell,dove-global-config"); 823 if (IS_ERR(gconfmap)) { 824 void __iomem *gc_base; 825 826 dev_warn(&pdev->dev, "falling back to hardcoded global registers\n"); 827 adjust_resource(&fb_res, 828 (mpp_res->start & INT_REGS_MASK) + GC_REGS_OFFS, 0x14); 829 gc_base = devm_ioremap_resource(&pdev->dev, &fb_res); 830 if (IS_ERR(gc_base)) 831 return PTR_ERR(gc_base); 832 gconfmap = devm_regmap_init_mmio(&pdev->dev, 833 gc_base, &gc_regmap_config); 834 if (IS_ERR(gconfmap)) 835 return PTR_ERR(gconfmap); 836 } 837 838 /* Warn on any missing DT resource */ 839 WARN(fb_res.start, FW_BUG "Missing pinctrl regs in DTB. Please update your firmware.\n"); 840 841 return mvebu_pinctrl_probe(pdev); 842 } 843 844 static int dove_pinctrl_remove(struct platform_device *pdev) 845 { 846 int ret; 847 848 ret = mvebu_pinctrl_remove(pdev); 849 if (!IS_ERR(clk)) 850 clk_disable_unprepare(clk); 851 return ret; 852 } 853 854 static struct platform_driver dove_pinctrl_driver = { 855 .driver = { 856 .name = "dove-pinctrl", 857 .owner = THIS_MODULE, 858 .of_match_table = dove_pinctrl_of_match, 859 }, 860 .probe = dove_pinctrl_probe, 861 .remove = dove_pinctrl_remove, 862 }; 863 864 module_platform_driver(dove_pinctrl_driver); 865 866 MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>"); 867 MODULE_DESCRIPTION("Marvell Dove pinctrl driver"); 868 MODULE_LICENSE("GPL v2"); 869