1 /* 2 * Marvell Dove pinctrl driver based on mvebu pinctrl core 3 * 4 * Author: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #include <linux/err.h> 13 #include <linux/init.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/bitops.h> 17 #include <linux/platform_device.h> 18 #include <linux/clk.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/pinctrl/pinctrl.h> 22 23 #include "pinctrl-mvebu.h" 24 25 #define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000) 26 #define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200) 27 #define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10) 28 #define DOVE_AU0_AC97_SEL BIT(16) 29 #define DOVE_PMU_SIGNAL_SELECT_0 (DOVE_SB_REGS_VIRT_BASE + 0xd802C) 30 #define DOVE_PMU_SIGNAL_SELECT_1 (DOVE_SB_REGS_VIRT_BASE + 0xd8030) 31 #define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) 32 #define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) 33 #define DOVE_TWSI_ENABLE_OPTION1 BIT(7) 34 #define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030) 35 #define DOVE_TWSI_ENABLE_OPTION2 BIT(20) 36 #define DOVE_TWSI_ENABLE_OPTION3 BIT(21) 37 #define DOVE_TWSI_OPTION3_GPIO BIT(22) 38 #define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034) 39 #define DOVE_SSP_ON_AU1 BIT(0) 40 #define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c) 41 #define DOVE_AU1_SPDIFO_GPIO_EN BIT(1) 42 #define DOVE_NAND_GPIO_EN BIT(0) 43 #define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400) 44 #define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40) 45 #define DOVE_SPI_GPIO_SEL BIT(5) 46 #define DOVE_UART1_GPIO_SEL BIT(4) 47 #define DOVE_AU1_GPIO_SEL BIT(3) 48 #define DOVE_CAM_GPIO_SEL BIT(2) 49 #define DOVE_SD1_GPIO_SEL BIT(1) 50 #define DOVE_SD0_GPIO_SEL BIT(0) 51 52 #define MPPS_PER_REG 8 53 #define MPP_BITS 4 54 #define MPP_MASK 0xf 55 56 #define CONFIG_PMU BIT(4) 57 58 static int dove_pmu_mpp_ctrl_get(struct mvebu_mpp_ctrl *ctrl, 59 unsigned long *config) 60 { 61 unsigned off = (ctrl->pid / MPPS_PER_REG) * MPP_BITS; 62 unsigned shift = (ctrl->pid % MPPS_PER_REG) * MPP_BITS; 63 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); 64 unsigned long func; 65 66 if (pmu & (1 << ctrl->pid)) { 67 func = readl(DOVE_PMU_SIGNAL_SELECT_0 + off); 68 *config = (func >> shift) & MPP_MASK; 69 *config |= CONFIG_PMU; 70 } else { 71 func = readl(DOVE_MPP_VIRT_BASE + off); 72 *config = (func >> shift) & MPP_MASK; 73 } 74 return 0; 75 } 76 77 static int dove_pmu_mpp_ctrl_set(struct mvebu_mpp_ctrl *ctrl, 78 unsigned long config) 79 { 80 unsigned off = (ctrl->pid / MPPS_PER_REG) * MPP_BITS; 81 unsigned shift = (ctrl->pid % MPPS_PER_REG) * MPP_BITS; 82 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); 83 unsigned long func; 84 85 if (config & CONFIG_PMU) { 86 writel(pmu | (1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL); 87 func = readl(DOVE_PMU_SIGNAL_SELECT_0 + off); 88 func &= ~(MPP_MASK << shift); 89 func |= (config & MPP_MASK) << shift; 90 writel(func, DOVE_PMU_SIGNAL_SELECT_0 + off); 91 } else { 92 writel(pmu & ~(1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL); 93 func = readl(DOVE_MPP_VIRT_BASE + off); 94 func &= ~(MPP_MASK << shift); 95 func |= (config & MPP_MASK) << shift; 96 writel(func, DOVE_MPP_VIRT_BASE + off); 97 } 98 return 0; 99 } 100 101 static int dove_mpp4_ctrl_get(struct mvebu_mpp_ctrl *ctrl, 102 unsigned long *config) 103 { 104 unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 105 unsigned long mask; 106 107 switch (ctrl->pid) { 108 case 24: /* mpp_camera */ 109 mask = DOVE_CAM_GPIO_SEL; 110 break; 111 case 40: /* mpp_sdio0 */ 112 mask = DOVE_SD0_GPIO_SEL; 113 break; 114 case 46: /* mpp_sdio1 */ 115 mask = DOVE_SD1_GPIO_SEL; 116 break; 117 case 58: /* mpp_spi0 */ 118 mask = DOVE_SPI_GPIO_SEL; 119 break; 120 case 62: /* mpp_uart1 */ 121 mask = DOVE_UART1_GPIO_SEL; 122 break; 123 default: 124 return -EINVAL; 125 } 126 127 *config = ((mpp4 & mask) != 0); 128 129 return 0; 130 } 131 132 static int dove_mpp4_ctrl_set(struct mvebu_mpp_ctrl *ctrl, 133 unsigned long config) 134 { 135 unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 136 unsigned long mask; 137 138 switch (ctrl->pid) { 139 case 24: /* mpp_camera */ 140 mask = DOVE_CAM_GPIO_SEL; 141 break; 142 case 40: /* mpp_sdio0 */ 143 mask = DOVE_SD0_GPIO_SEL; 144 break; 145 case 46: /* mpp_sdio1 */ 146 mask = DOVE_SD1_GPIO_SEL; 147 break; 148 case 58: /* mpp_spi0 */ 149 mask = DOVE_SPI_GPIO_SEL; 150 break; 151 case 62: /* mpp_uart1 */ 152 mask = DOVE_UART1_GPIO_SEL; 153 break; 154 default: 155 return -EINVAL; 156 } 157 158 mpp4 &= ~mask; 159 if (config) 160 mpp4 |= mask; 161 162 writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE); 163 164 return 0; 165 } 166 167 static int dove_nand_ctrl_get(struct mvebu_mpp_ctrl *ctrl, 168 unsigned long *config) 169 { 170 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 171 172 *config = ((gmpp & DOVE_NAND_GPIO_EN) != 0); 173 174 return 0; 175 } 176 177 static int dove_nand_ctrl_set(struct mvebu_mpp_ctrl *ctrl, 178 unsigned long config) 179 { 180 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 181 182 gmpp &= ~DOVE_NAND_GPIO_EN; 183 if (config) 184 gmpp |= DOVE_NAND_GPIO_EN; 185 186 writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE); 187 188 return 0; 189 } 190 191 static int dove_audio0_ctrl_get(struct mvebu_mpp_ctrl *ctrl, 192 unsigned long *config) 193 { 194 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); 195 196 *config = ((pmu & DOVE_AU0_AC97_SEL) != 0); 197 198 return 0; 199 } 200 201 static int dove_audio0_ctrl_set(struct mvebu_mpp_ctrl *ctrl, 202 unsigned long config) 203 { 204 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); 205 206 pmu &= ~DOVE_AU0_AC97_SEL; 207 if (config) 208 pmu |= DOVE_AU0_AC97_SEL; 209 writel(pmu, DOVE_PMU_MPP_GENERAL_CTRL); 210 211 return 0; 212 } 213 214 static int dove_audio1_ctrl_get(struct mvebu_mpp_ctrl *ctrl, 215 unsigned long *config) 216 { 217 unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 218 unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1); 219 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 220 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 221 222 *config = 0; 223 if (mpp4 & DOVE_AU1_GPIO_SEL) 224 *config |= BIT(3); 225 if (sspc1 & DOVE_SSP_ON_AU1) 226 *config |= BIT(2); 227 if (gmpp & DOVE_AU1_SPDIFO_GPIO_EN) 228 *config |= BIT(1); 229 if (gcfg2 & DOVE_TWSI_OPTION3_GPIO) 230 *config |= BIT(0); 231 232 /* SSP/TWSI only if I2S1 not set*/ 233 if ((*config & BIT(3)) == 0) 234 *config &= ~(BIT(2) | BIT(0)); 235 /* TWSI only if SPDIFO not set*/ 236 if ((*config & BIT(1)) == 0) 237 *config &= ~BIT(0); 238 return 0; 239 } 240 241 static int dove_audio1_ctrl_set(struct mvebu_mpp_ctrl *ctrl, 242 unsigned long config) 243 { 244 unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 245 unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1); 246 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 247 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 248 249 /* 250 * clear all audio1 related bits before configure 251 */ 252 gcfg2 &= ~DOVE_TWSI_OPTION3_GPIO; 253 gmpp &= ~DOVE_AU1_SPDIFO_GPIO_EN; 254 sspc1 &= ~DOVE_SSP_ON_AU1; 255 mpp4 &= ~DOVE_AU1_GPIO_SEL; 256 257 if (config & BIT(0)) 258 gcfg2 |= DOVE_TWSI_OPTION3_GPIO; 259 if (config & BIT(1)) 260 gmpp |= DOVE_AU1_SPDIFO_GPIO_EN; 261 if (config & BIT(2)) 262 sspc1 |= DOVE_SSP_ON_AU1; 263 if (config & BIT(3)) 264 mpp4 |= DOVE_AU1_GPIO_SEL; 265 266 writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE); 267 writel(sspc1, DOVE_SSP_CTRL_STATUS_1); 268 writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE); 269 writel(gcfg2, DOVE_GLOBAL_CONFIG_2); 270 271 return 0; 272 } 273 274 /* mpp[52:57] gpio pins depend heavily on current config; 275 * gpio_req does not try to mux in gpio capabilities to not 276 * break other functions. If you require all mpps as gpio 277 * enforce gpio setting by pinctrl mapping. 278 */ 279 static int dove_audio1_ctrl_gpio_req(struct mvebu_mpp_ctrl *ctrl, u8 pid) 280 { 281 unsigned long config; 282 283 dove_audio1_ctrl_get(ctrl, &config); 284 285 switch (config) { 286 case 0x02: /* i2s1 : gpio[56:57] */ 287 case 0x0e: /* ssp : gpio[56:57] */ 288 if (pid >= 56) 289 return 0; 290 return -ENOTSUPP; 291 case 0x08: /* spdifo : gpio[52:55] */ 292 case 0x0b: /* twsi : gpio[52:55] */ 293 if (pid <= 55) 294 return 0; 295 return -ENOTSUPP; 296 case 0x0a: /* all gpio */ 297 return 0; 298 /* 0x00 : i2s1/spdifo : no gpio */ 299 /* 0x0c : ssp/spdifo : no gpio */ 300 /* 0x0f : ssp/twsi : no gpio */ 301 } 302 return -ENOTSUPP; 303 } 304 305 /* mpp[52:57] has gpio pins capable of in and out */ 306 static int dove_audio1_ctrl_gpio_dir(struct mvebu_mpp_ctrl *ctrl, u8 pid, 307 bool input) 308 { 309 if (pid < 52 || pid > 57) 310 return -ENOTSUPP; 311 return 0; 312 } 313 314 static int dove_twsi_ctrl_get(struct mvebu_mpp_ctrl *ctrl, 315 unsigned long *config) 316 { 317 unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1); 318 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 319 320 *config = 0; 321 if (gcfg1 & DOVE_TWSI_ENABLE_OPTION1) 322 *config = 1; 323 else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION2) 324 *config = 2; 325 else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION3) 326 *config = 3; 327 328 return 0; 329 } 330 331 static int dove_twsi_ctrl_set(struct mvebu_mpp_ctrl *ctrl, 332 unsigned long config) 333 { 334 unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1); 335 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 336 337 gcfg1 &= ~DOVE_TWSI_ENABLE_OPTION1; 338 gcfg2 &= ~(DOVE_TWSI_ENABLE_OPTION2 | DOVE_TWSI_ENABLE_OPTION2); 339 340 switch (config) { 341 case 1: 342 gcfg1 |= DOVE_TWSI_ENABLE_OPTION1; 343 break; 344 case 2: 345 gcfg2 |= DOVE_TWSI_ENABLE_OPTION2; 346 break; 347 case 3: 348 gcfg2 |= DOVE_TWSI_ENABLE_OPTION3; 349 break; 350 } 351 352 writel(gcfg1, DOVE_GLOBAL_CONFIG_1); 353 writel(gcfg2, DOVE_GLOBAL_CONFIG_2); 354 355 return 0; 356 } 357 358 static struct mvebu_mpp_ctrl dove_mpp_controls[] = { 359 MPP_FUNC_CTRL(0, 0, "mpp0", dove_pmu_mpp_ctrl), 360 MPP_FUNC_CTRL(1, 1, "mpp1", dove_pmu_mpp_ctrl), 361 MPP_FUNC_CTRL(2, 2, "mpp2", dove_pmu_mpp_ctrl), 362 MPP_FUNC_CTRL(3, 3, "mpp3", dove_pmu_mpp_ctrl), 363 MPP_FUNC_CTRL(4, 4, "mpp4", dove_pmu_mpp_ctrl), 364 MPP_FUNC_CTRL(5, 5, "mpp5", dove_pmu_mpp_ctrl), 365 MPP_FUNC_CTRL(6, 6, "mpp6", dove_pmu_mpp_ctrl), 366 MPP_FUNC_CTRL(7, 7, "mpp7", dove_pmu_mpp_ctrl), 367 MPP_FUNC_CTRL(8, 8, "mpp8", dove_pmu_mpp_ctrl), 368 MPP_FUNC_CTRL(9, 9, "mpp9", dove_pmu_mpp_ctrl), 369 MPP_FUNC_CTRL(10, 10, "mpp10", dove_pmu_mpp_ctrl), 370 MPP_FUNC_CTRL(11, 11, "mpp11", dove_pmu_mpp_ctrl), 371 MPP_FUNC_CTRL(12, 12, "mpp12", dove_pmu_mpp_ctrl), 372 MPP_FUNC_CTRL(13, 13, "mpp13", dove_pmu_mpp_ctrl), 373 MPP_FUNC_CTRL(14, 14, "mpp14", dove_pmu_mpp_ctrl), 374 MPP_FUNC_CTRL(15, 15, "mpp15", dove_pmu_mpp_ctrl), 375 MPP_REG_CTRL(16, 23), 376 MPP_FUNC_CTRL(24, 39, "mpp_camera", dove_mpp4_ctrl), 377 MPP_FUNC_CTRL(40, 45, "mpp_sdio0", dove_mpp4_ctrl), 378 MPP_FUNC_CTRL(46, 51, "mpp_sdio1", dove_mpp4_ctrl), 379 MPP_FUNC_GPIO_CTRL(52, 57, "mpp_audio1", dove_audio1_ctrl), 380 MPP_FUNC_CTRL(58, 61, "mpp_spi0", dove_mpp4_ctrl), 381 MPP_FUNC_CTRL(62, 63, "mpp_uart1", dove_mpp4_ctrl), 382 MPP_FUNC_CTRL(64, 71, "mpp_nand", dove_nand_ctrl), 383 MPP_FUNC_CTRL(72, 72, "audio0", dove_audio0_ctrl), 384 MPP_FUNC_CTRL(73, 73, "twsi", dove_twsi_ctrl), 385 }; 386 387 static struct mvebu_mpp_mode dove_mpp_modes[] = { 388 MPP_MODE(0, 389 MPP_FUNCTION(0x00, "gpio", NULL), 390 MPP_FUNCTION(0x02, "uart2", "rts"), 391 MPP_FUNCTION(0x03, "sdio0", "cd"), 392 MPP_FUNCTION(0x0f, "lcd0", "pwm"), 393 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 394 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 395 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 396 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 397 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 398 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 399 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 400 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 401 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 402 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 403 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 404 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 405 MPP_MODE(1, 406 MPP_FUNCTION(0x00, "gpio", NULL), 407 MPP_FUNCTION(0x02, "uart2", "cts"), 408 MPP_FUNCTION(0x03, "sdio0", "wp"), 409 MPP_FUNCTION(0x0f, "lcd1", "pwm"), 410 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 411 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 412 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 413 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 414 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 415 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 416 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 417 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 418 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 419 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 420 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 421 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 422 MPP_MODE(2, 423 MPP_FUNCTION(0x00, "gpio", NULL), 424 MPP_FUNCTION(0x01, "sata", "prsnt"), 425 MPP_FUNCTION(0x02, "uart2", "txd"), 426 MPP_FUNCTION(0x03, "sdio0", "buspwr"), 427 MPP_FUNCTION(0x04, "uart1", "rts"), 428 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 429 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 430 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 431 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 432 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 433 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 434 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 435 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 436 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 437 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 438 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 439 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 440 MPP_MODE(3, 441 MPP_FUNCTION(0x00, "gpio", NULL), 442 MPP_FUNCTION(0x01, "sata", "act"), 443 MPP_FUNCTION(0x02, "uart2", "rxd"), 444 MPP_FUNCTION(0x03, "sdio0", "ledctrl"), 445 MPP_FUNCTION(0x04, "uart1", "cts"), 446 MPP_FUNCTION(0x0f, "lcd-spi", "cs1"), 447 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 448 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 449 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 450 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 451 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 452 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 453 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 454 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 455 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 456 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 457 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 458 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 459 MPP_MODE(4, 460 MPP_FUNCTION(0x00, "gpio", NULL), 461 MPP_FUNCTION(0x02, "uart3", "rts"), 462 MPP_FUNCTION(0x03, "sdio1", "cd"), 463 MPP_FUNCTION(0x04, "spi1", "miso"), 464 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 465 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 466 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 467 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 468 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 469 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 470 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 471 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 472 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 473 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 474 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 475 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 476 MPP_MODE(5, 477 MPP_FUNCTION(0x00, "gpio", NULL), 478 MPP_FUNCTION(0x02, "uart3", "cts"), 479 MPP_FUNCTION(0x03, "sdio1", "wp"), 480 MPP_FUNCTION(0x04, "spi1", "cs"), 481 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 482 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 483 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 484 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 485 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 486 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 487 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 488 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 489 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 490 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 491 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 492 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 493 MPP_MODE(6, 494 MPP_FUNCTION(0x00, "gpio", NULL), 495 MPP_FUNCTION(0x02, "uart3", "txd"), 496 MPP_FUNCTION(0x03, "sdio1", "buspwr"), 497 MPP_FUNCTION(0x04, "spi1", "mosi"), 498 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 499 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 500 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 501 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 502 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 503 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 504 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 505 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 506 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 507 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 508 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 509 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 510 MPP_MODE(7, 511 MPP_FUNCTION(0x00, "gpio", NULL), 512 MPP_FUNCTION(0x02, "uart3", "rxd"), 513 MPP_FUNCTION(0x03, "sdio1", "ledctrl"), 514 MPP_FUNCTION(0x04, "spi1", "sck"), 515 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 516 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 517 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 518 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 519 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 520 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 521 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 522 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 523 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 524 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 525 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 526 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 527 MPP_MODE(8, 528 MPP_FUNCTION(0x00, "gpio", NULL), 529 MPP_FUNCTION(0x01, "watchdog", "rstout"), 530 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 531 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 532 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 533 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 534 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 535 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 536 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 537 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 538 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 539 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 540 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 541 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 542 MPP_MODE(9, 543 MPP_FUNCTION(0x00, "gpio", NULL), 544 MPP_FUNCTION(0x05, "pex1", "clkreq"), 545 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 546 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 547 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 548 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 549 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 550 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 551 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 552 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 553 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 554 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 555 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 556 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 557 MPP_MODE(10, 558 MPP_FUNCTION(0x00, "gpio", NULL), 559 MPP_FUNCTION(0x05, "ssp", "sclk"), 560 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 561 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 562 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 563 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 564 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 565 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 566 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 567 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 568 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 569 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 570 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 571 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 572 MPP_MODE(11, 573 MPP_FUNCTION(0x00, "gpio", NULL), 574 MPP_FUNCTION(0x01, "sata", "prsnt"), 575 MPP_FUNCTION(0x02, "sata-1", "act"), 576 MPP_FUNCTION(0x03, "sdio0", "ledctrl"), 577 MPP_FUNCTION(0x04, "sdio1", "ledctrl"), 578 MPP_FUNCTION(0x05, "pex0", "clkreq"), 579 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 580 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 581 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 582 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 583 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 584 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 585 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 586 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 587 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 588 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 589 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 590 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 591 MPP_MODE(12, 592 MPP_FUNCTION(0x00, "gpio", NULL), 593 MPP_FUNCTION(0x01, "sata", "act"), 594 MPP_FUNCTION(0x02, "uart2", "rts"), 595 MPP_FUNCTION(0x03, "audio0", "extclk"), 596 MPP_FUNCTION(0x04, "sdio1", "cd"), 597 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 598 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 599 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 600 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 601 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 602 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 603 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 604 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 605 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 606 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 607 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 608 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 609 MPP_MODE(13, 610 MPP_FUNCTION(0x00, "gpio", NULL), 611 MPP_FUNCTION(0x02, "uart2", "cts"), 612 MPP_FUNCTION(0x03, "audio1", "extclk"), 613 MPP_FUNCTION(0x04, "sdio1", "wp"), 614 MPP_FUNCTION(0x05, "ssp", "extclk"), 615 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 616 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 617 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 618 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 619 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 620 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 621 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 622 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 623 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 624 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 625 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 626 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 627 MPP_MODE(14, 628 MPP_FUNCTION(0x00, "gpio", NULL), 629 MPP_FUNCTION(0x02, "uart2", "txd"), 630 MPP_FUNCTION(0x04, "sdio1", "buspwr"), 631 MPP_FUNCTION(0x05, "ssp", "rxd"), 632 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 633 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 634 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 635 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 636 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 637 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 638 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 639 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 640 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 641 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 642 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 643 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 644 MPP_MODE(15, 645 MPP_FUNCTION(0x00, "gpio", NULL), 646 MPP_FUNCTION(0x02, "uart2", "rxd"), 647 MPP_FUNCTION(0x04, "sdio1", "ledctrl"), 648 MPP_FUNCTION(0x05, "ssp", "sfrm"), 649 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 650 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 651 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 652 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 653 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 654 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 655 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 656 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 657 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 658 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 659 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 660 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 661 MPP_MODE(16, 662 MPP_FUNCTION(0x00, "gpio", NULL), 663 MPP_FUNCTION(0x02, "uart3", "rts"), 664 MPP_FUNCTION(0x03, "sdio0", "cd"), 665 MPP_FUNCTION(0x04, "lcd-spi", "cs1"), 666 MPP_FUNCTION(0x05, "ac97", "sdi1")), 667 MPP_MODE(17, 668 MPP_FUNCTION(0x00, "gpio", NULL), 669 MPP_FUNCTION(0x01, "ac97-1", "sysclko"), 670 MPP_FUNCTION(0x02, "uart3", "cts"), 671 MPP_FUNCTION(0x03, "sdio0", "wp"), 672 MPP_FUNCTION(0x04, "twsi", "sda"), 673 MPP_FUNCTION(0x05, "ac97", "sdi2")), 674 MPP_MODE(18, 675 MPP_FUNCTION(0x00, "gpio", NULL), 676 MPP_FUNCTION(0x02, "uart3", "txd"), 677 MPP_FUNCTION(0x03, "sdio0", "buspwr"), 678 MPP_FUNCTION(0x04, "lcd0", "pwm"), 679 MPP_FUNCTION(0x05, "ac97", "sdi3")), 680 MPP_MODE(19, 681 MPP_FUNCTION(0x00, "gpio", NULL), 682 MPP_FUNCTION(0x02, "uart3", "rxd"), 683 MPP_FUNCTION(0x03, "sdio0", "ledctrl"), 684 MPP_FUNCTION(0x04, "twsi", "sck")), 685 MPP_MODE(20, 686 MPP_FUNCTION(0x00, "gpio", NULL), 687 MPP_FUNCTION(0x01, "ac97", "sysclko"), 688 MPP_FUNCTION(0x02, "lcd-spi", "miso"), 689 MPP_FUNCTION(0x03, "sdio1", "cd"), 690 MPP_FUNCTION(0x05, "sdio0", "cd"), 691 MPP_FUNCTION(0x06, "spi1", "miso")), 692 MPP_MODE(21, 693 MPP_FUNCTION(0x00, "gpio", NULL), 694 MPP_FUNCTION(0x01, "uart1", "rts"), 695 MPP_FUNCTION(0x02, "lcd-spi", "cs0"), 696 MPP_FUNCTION(0x03, "sdio1", "wp"), 697 MPP_FUNCTION(0x04, "ssp", "sfrm"), 698 MPP_FUNCTION(0x05, "sdio0", "wp"), 699 MPP_FUNCTION(0x06, "spi1", "cs")), 700 MPP_MODE(22, 701 MPP_FUNCTION(0x00, "gpio", NULL), 702 MPP_FUNCTION(0x01, "uart1", "cts"), 703 MPP_FUNCTION(0x02, "lcd-spi", "mosi"), 704 MPP_FUNCTION(0x03, "sdio1", "buspwr"), 705 MPP_FUNCTION(0x04, "ssp", "txd"), 706 MPP_FUNCTION(0x05, "sdio0", "buspwr"), 707 MPP_FUNCTION(0x06, "spi1", "mosi")), 708 MPP_MODE(23, 709 MPP_FUNCTION(0x00, "gpio", NULL), 710 MPP_FUNCTION(0x02, "lcd-spi", "sck"), 711 MPP_FUNCTION(0x03, "sdio1", "ledctrl"), 712 MPP_FUNCTION(0x04, "ssp", "sclk"), 713 MPP_FUNCTION(0x05, "sdio0", "ledctrl"), 714 MPP_FUNCTION(0x06, "spi1", "sck")), 715 MPP_MODE(24, 716 MPP_FUNCTION(0x00, "camera", NULL), 717 MPP_FUNCTION(0x01, "gpio", NULL)), 718 MPP_MODE(40, 719 MPP_FUNCTION(0x00, "sdio0", NULL), 720 MPP_FUNCTION(0x01, "gpio", NULL)), 721 MPP_MODE(46, 722 MPP_FUNCTION(0x00, "sdio1", NULL), 723 MPP_FUNCTION(0x01, "gpio", NULL)), 724 MPP_MODE(52, 725 MPP_FUNCTION(0x00, "i2s1/spdifo", NULL), 726 MPP_FUNCTION(0x02, "i2s1", NULL), 727 MPP_FUNCTION(0x08, "spdifo", NULL), 728 MPP_FUNCTION(0x0a, "gpio", NULL), 729 MPP_FUNCTION(0x0b, "twsi", NULL), 730 MPP_FUNCTION(0x0c, "ssp/spdifo", NULL), 731 MPP_FUNCTION(0x0e, "ssp", NULL), 732 MPP_FUNCTION(0x0f, "ssp/twsi", NULL)), 733 MPP_MODE(58, 734 MPP_FUNCTION(0x00, "spi0", NULL), 735 MPP_FUNCTION(0x01, "gpio", NULL)), 736 MPP_MODE(62, 737 MPP_FUNCTION(0x00, "uart1", NULL), 738 MPP_FUNCTION(0x01, "gpio", NULL)), 739 MPP_MODE(64, 740 MPP_FUNCTION(0x00, "nand", NULL), 741 MPP_FUNCTION(0x01, "gpo", NULL)), 742 MPP_MODE(72, 743 MPP_FUNCTION(0x00, "i2s", NULL), 744 MPP_FUNCTION(0x01, "ac97", NULL)), 745 MPP_MODE(73, 746 MPP_FUNCTION(0x00, "twsi-none", NULL), 747 MPP_FUNCTION(0x01, "twsi-opt1", NULL), 748 MPP_FUNCTION(0x02, "twsi-opt2", NULL), 749 MPP_FUNCTION(0x03, "twsi-opt3", NULL)), 750 }; 751 752 static struct pinctrl_gpio_range dove_mpp_gpio_ranges[] = { 753 MPP_GPIO_RANGE(0, 0, 0, 32), 754 MPP_GPIO_RANGE(1, 32, 32, 32), 755 MPP_GPIO_RANGE(2, 64, 64, 8), 756 }; 757 758 static struct mvebu_pinctrl_soc_info dove_pinctrl_info = { 759 .controls = dove_mpp_controls, 760 .ncontrols = ARRAY_SIZE(dove_mpp_controls), 761 .modes = dove_mpp_modes, 762 .nmodes = ARRAY_SIZE(dove_mpp_modes), 763 .gpioranges = dove_mpp_gpio_ranges, 764 .ngpioranges = ARRAY_SIZE(dove_mpp_gpio_ranges), 765 .variant = 0, 766 }; 767 768 static struct clk *clk; 769 770 static struct of_device_id dove_pinctrl_of_match[] = { 771 { .compatible = "marvell,dove-pinctrl", .data = &dove_pinctrl_info }, 772 { } 773 }; 774 775 static int dove_pinctrl_probe(struct platform_device *pdev) 776 { 777 const struct of_device_id *match = 778 of_match_device(dove_pinctrl_of_match, &pdev->dev); 779 pdev->dev.platform_data = (void *)match->data; 780 781 /* 782 * General MPP Configuration Register is part of pdma registers. 783 * grab clk to make sure it is ticking. 784 */ 785 clk = devm_clk_get(&pdev->dev, NULL); 786 if (IS_ERR(clk)) { 787 dev_err(&pdev->dev, "Unable to get pdma clock"); 788 return PTR_RET(clk); 789 } 790 clk_prepare_enable(clk); 791 792 return mvebu_pinctrl_probe(pdev); 793 } 794 795 static int dove_pinctrl_remove(struct platform_device *pdev) 796 { 797 int ret; 798 799 ret = mvebu_pinctrl_remove(pdev); 800 if (!IS_ERR(clk)) 801 clk_disable_unprepare(clk); 802 return ret; 803 } 804 805 static struct platform_driver dove_pinctrl_driver = { 806 .driver = { 807 .name = "dove-pinctrl", 808 .owner = THIS_MODULE, 809 .of_match_table = of_match_ptr(dove_pinctrl_of_match), 810 }, 811 .probe = dove_pinctrl_probe, 812 .remove = dove_pinctrl_remove, 813 }; 814 815 module_platform_driver(dove_pinctrl_driver); 816 817 MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>"); 818 MODULE_DESCRIPTION("Marvell Dove pinctrl driver"); 819 MODULE_LICENSE("GPL v2"); 820