1 /* 2 * Marvell Dove pinctrl driver based on mvebu pinctrl core 3 * 4 * Author: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #include <linux/err.h> 13 #include <linux/init.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/bitops.h> 17 #include <linux/platform_device.h> 18 #include <linux/clk.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/pinctrl/pinctrl.h> 22 23 #include "pinctrl-mvebu.h" 24 25 #define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000) 26 #define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200) 27 #define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10) 28 #define DOVE_AU0_AC97_SEL BIT(16) 29 #define DOVE_PMU_SIGNAL_SELECT_0 (DOVE_SB_REGS_VIRT_BASE + 0xd802C) 30 #define DOVE_PMU_SIGNAL_SELECT_1 (DOVE_SB_REGS_VIRT_BASE + 0xd8030) 31 #define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) 32 #define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) 33 #define DOVE_TWSI_ENABLE_OPTION1 BIT(7) 34 #define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030) 35 #define DOVE_TWSI_ENABLE_OPTION2 BIT(20) 36 #define DOVE_TWSI_ENABLE_OPTION3 BIT(21) 37 #define DOVE_TWSI_OPTION3_GPIO BIT(22) 38 #define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034) 39 #define DOVE_SSP_ON_AU1 BIT(0) 40 #define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c) 41 #define DOVE_AU1_SPDIFO_GPIO_EN BIT(1) 42 #define DOVE_NAND_GPIO_EN BIT(0) 43 #define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400) 44 #define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40) 45 #define DOVE_SPI_GPIO_SEL BIT(5) 46 #define DOVE_UART1_GPIO_SEL BIT(4) 47 #define DOVE_AU1_GPIO_SEL BIT(3) 48 #define DOVE_CAM_GPIO_SEL BIT(2) 49 #define DOVE_SD1_GPIO_SEL BIT(1) 50 #define DOVE_SD0_GPIO_SEL BIT(0) 51 52 #define CONFIG_PMU BIT(4) 53 54 static void __iomem *mpp_base; 55 56 static int dove_mpp_ctrl_get(unsigned pid, unsigned long *config) 57 { 58 return default_mpp_ctrl_get(mpp_base, pid, config); 59 } 60 61 static int dove_mpp_ctrl_set(unsigned pid, unsigned long config) 62 { 63 return default_mpp_ctrl_set(mpp_base, pid, config); 64 } 65 66 static int dove_pmu_mpp_ctrl_get(unsigned pid, unsigned long *config) 67 { 68 unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; 69 unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; 70 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); 71 unsigned long func; 72 73 if ((pmu & BIT(pid)) == 0) 74 return default_mpp_ctrl_get(mpp_base, pid, config); 75 76 func = readl(DOVE_PMU_SIGNAL_SELECT_0 + off); 77 *config = (func >> shift) & MVEBU_MPP_MASK; 78 *config |= CONFIG_PMU; 79 80 return 0; 81 } 82 83 static int dove_pmu_mpp_ctrl_set(unsigned pid, unsigned long config) 84 { 85 unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; 86 unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; 87 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); 88 unsigned long func; 89 90 if ((config & CONFIG_PMU) == 0) { 91 writel(pmu & ~BIT(pid), DOVE_PMU_MPP_GENERAL_CTRL); 92 return default_mpp_ctrl_set(mpp_base, pid, config); 93 } 94 95 writel(pmu | BIT(pid), DOVE_PMU_MPP_GENERAL_CTRL); 96 func = readl(DOVE_PMU_SIGNAL_SELECT_0 + off); 97 func &= ~(MVEBU_MPP_MASK << shift); 98 func |= (config & MVEBU_MPP_MASK) << shift; 99 writel(func, DOVE_PMU_SIGNAL_SELECT_0 + off); 100 101 return 0; 102 } 103 104 static int dove_mpp4_ctrl_get(unsigned pid, unsigned long *config) 105 { 106 unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 107 unsigned long mask; 108 109 switch (pid) { 110 case 24: /* mpp_camera */ 111 mask = DOVE_CAM_GPIO_SEL; 112 break; 113 case 40: /* mpp_sdio0 */ 114 mask = DOVE_SD0_GPIO_SEL; 115 break; 116 case 46: /* mpp_sdio1 */ 117 mask = DOVE_SD1_GPIO_SEL; 118 break; 119 case 58: /* mpp_spi0 */ 120 mask = DOVE_SPI_GPIO_SEL; 121 break; 122 case 62: /* mpp_uart1 */ 123 mask = DOVE_UART1_GPIO_SEL; 124 break; 125 default: 126 return -EINVAL; 127 } 128 129 *config = ((mpp4 & mask) != 0); 130 131 return 0; 132 } 133 134 static int dove_mpp4_ctrl_set(unsigned pid, unsigned long config) 135 { 136 unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 137 unsigned long mask; 138 139 switch (pid) { 140 case 24: /* mpp_camera */ 141 mask = DOVE_CAM_GPIO_SEL; 142 break; 143 case 40: /* mpp_sdio0 */ 144 mask = DOVE_SD0_GPIO_SEL; 145 break; 146 case 46: /* mpp_sdio1 */ 147 mask = DOVE_SD1_GPIO_SEL; 148 break; 149 case 58: /* mpp_spi0 */ 150 mask = DOVE_SPI_GPIO_SEL; 151 break; 152 case 62: /* mpp_uart1 */ 153 mask = DOVE_UART1_GPIO_SEL; 154 break; 155 default: 156 return -EINVAL; 157 } 158 159 mpp4 &= ~mask; 160 if (config) 161 mpp4 |= mask; 162 163 writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE); 164 165 return 0; 166 } 167 168 static int dove_nand_ctrl_get(unsigned pid, unsigned long *config) 169 { 170 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 171 172 *config = ((gmpp & DOVE_NAND_GPIO_EN) != 0); 173 174 return 0; 175 } 176 177 static int dove_nand_ctrl_set(unsigned pid, unsigned long config) 178 { 179 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 180 181 gmpp &= ~DOVE_NAND_GPIO_EN; 182 if (config) 183 gmpp |= DOVE_NAND_GPIO_EN; 184 185 writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE); 186 187 return 0; 188 } 189 190 static int dove_audio0_ctrl_get(unsigned pid, unsigned long *config) 191 { 192 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); 193 194 *config = ((pmu & DOVE_AU0_AC97_SEL) != 0); 195 196 return 0; 197 } 198 199 static int dove_audio0_ctrl_set(unsigned pid, unsigned long config) 200 { 201 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); 202 203 pmu &= ~DOVE_AU0_AC97_SEL; 204 if (config) 205 pmu |= DOVE_AU0_AC97_SEL; 206 writel(pmu, DOVE_PMU_MPP_GENERAL_CTRL); 207 208 return 0; 209 } 210 211 static int dove_audio1_ctrl_get(unsigned pid, unsigned long *config) 212 { 213 unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 214 unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1); 215 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 216 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 217 218 *config = 0; 219 if (mpp4 & DOVE_AU1_GPIO_SEL) 220 *config |= BIT(3); 221 if (sspc1 & DOVE_SSP_ON_AU1) 222 *config |= BIT(2); 223 if (gmpp & DOVE_AU1_SPDIFO_GPIO_EN) 224 *config |= BIT(1); 225 if (gcfg2 & DOVE_TWSI_OPTION3_GPIO) 226 *config |= BIT(0); 227 228 /* SSP/TWSI only if I2S1 not set*/ 229 if ((*config & BIT(3)) == 0) 230 *config &= ~(BIT(2) | BIT(0)); 231 /* TWSI only if SPDIFO not set*/ 232 if ((*config & BIT(1)) == 0) 233 *config &= ~BIT(0); 234 return 0; 235 } 236 237 static int dove_audio1_ctrl_set(unsigned pid, unsigned long config) 238 { 239 unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 240 unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1); 241 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 242 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 243 244 /* 245 * clear all audio1 related bits before configure 246 */ 247 gcfg2 &= ~DOVE_TWSI_OPTION3_GPIO; 248 gmpp &= ~DOVE_AU1_SPDIFO_GPIO_EN; 249 sspc1 &= ~DOVE_SSP_ON_AU1; 250 mpp4 &= ~DOVE_AU1_GPIO_SEL; 251 252 if (config & BIT(0)) 253 gcfg2 |= DOVE_TWSI_OPTION3_GPIO; 254 if (config & BIT(1)) 255 gmpp |= DOVE_AU1_SPDIFO_GPIO_EN; 256 if (config & BIT(2)) 257 sspc1 |= DOVE_SSP_ON_AU1; 258 if (config & BIT(3)) 259 mpp4 |= DOVE_AU1_GPIO_SEL; 260 261 writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE); 262 writel(sspc1, DOVE_SSP_CTRL_STATUS_1); 263 writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE); 264 writel(gcfg2, DOVE_GLOBAL_CONFIG_2); 265 266 return 0; 267 } 268 269 /* mpp[52:57] gpio pins depend heavily on current config; 270 * gpio_req does not try to mux in gpio capabilities to not 271 * break other functions. If you require all mpps as gpio 272 * enforce gpio setting by pinctrl mapping. 273 */ 274 static int dove_audio1_ctrl_gpio_req(unsigned pid) 275 { 276 unsigned long config; 277 278 dove_audio1_ctrl_get(pid, &config); 279 280 switch (config) { 281 case 0x02: /* i2s1 : gpio[56:57] */ 282 case 0x0e: /* ssp : gpio[56:57] */ 283 if (pid >= 56) 284 return 0; 285 return -ENOTSUPP; 286 case 0x08: /* spdifo : gpio[52:55] */ 287 case 0x0b: /* twsi : gpio[52:55] */ 288 if (pid <= 55) 289 return 0; 290 return -ENOTSUPP; 291 case 0x0a: /* all gpio */ 292 return 0; 293 /* 0x00 : i2s1/spdifo : no gpio */ 294 /* 0x0c : ssp/spdifo : no gpio */ 295 /* 0x0f : ssp/twsi : no gpio */ 296 } 297 return -ENOTSUPP; 298 } 299 300 /* mpp[52:57] has gpio pins capable of in and out */ 301 static int dove_audio1_ctrl_gpio_dir(unsigned pid, bool input) 302 { 303 if (pid < 52 || pid > 57) 304 return -ENOTSUPP; 305 return 0; 306 } 307 308 static int dove_twsi_ctrl_get(unsigned pid, unsigned long *config) 309 { 310 unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1); 311 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 312 313 *config = 0; 314 if (gcfg1 & DOVE_TWSI_ENABLE_OPTION1) 315 *config = 1; 316 else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION2) 317 *config = 2; 318 else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION3) 319 *config = 3; 320 321 return 0; 322 } 323 324 static int dove_twsi_ctrl_set(unsigned pid, unsigned long config) 325 { 326 unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1); 327 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 328 329 gcfg1 &= ~DOVE_TWSI_ENABLE_OPTION1; 330 gcfg2 &= ~(DOVE_TWSI_ENABLE_OPTION2 | DOVE_TWSI_ENABLE_OPTION3); 331 332 switch (config) { 333 case 1: 334 gcfg1 |= DOVE_TWSI_ENABLE_OPTION1; 335 break; 336 case 2: 337 gcfg2 |= DOVE_TWSI_ENABLE_OPTION2; 338 break; 339 case 3: 340 gcfg2 |= DOVE_TWSI_ENABLE_OPTION3; 341 break; 342 } 343 344 writel(gcfg1, DOVE_GLOBAL_CONFIG_1); 345 writel(gcfg2, DOVE_GLOBAL_CONFIG_2); 346 347 return 0; 348 } 349 350 static struct mvebu_mpp_ctrl dove_mpp_controls[] = { 351 MPP_FUNC_CTRL(0, 15, NULL, dove_pmu_mpp_ctrl), 352 MPP_FUNC_CTRL(16, 23, NULL, dove_mpp_ctrl), 353 MPP_FUNC_CTRL(24, 39, "mpp_camera", dove_mpp4_ctrl), 354 MPP_FUNC_CTRL(40, 45, "mpp_sdio0", dove_mpp4_ctrl), 355 MPP_FUNC_CTRL(46, 51, "mpp_sdio1", dove_mpp4_ctrl), 356 MPP_FUNC_GPIO_CTRL(52, 57, "mpp_audio1", dove_audio1_ctrl), 357 MPP_FUNC_CTRL(58, 61, "mpp_spi0", dove_mpp4_ctrl), 358 MPP_FUNC_CTRL(62, 63, "mpp_uart1", dove_mpp4_ctrl), 359 MPP_FUNC_CTRL(64, 71, "mpp_nand", dove_nand_ctrl), 360 MPP_FUNC_CTRL(72, 72, "audio0", dove_audio0_ctrl), 361 MPP_FUNC_CTRL(73, 73, "twsi", dove_twsi_ctrl), 362 }; 363 364 static struct mvebu_mpp_mode dove_mpp_modes[] = { 365 MPP_MODE(0, 366 MPP_FUNCTION(0x00, "gpio", NULL), 367 MPP_FUNCTION(0x02, "uart2", "rts"), 368 MPP_FUNCTION(0x03, "sdio0", "cd"), 369 MPP_FUNCTION(0x0f, "lcd0", "pwm"), 370 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 371 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 372 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 373 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 374 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 375 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 376 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 377 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 378 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 379 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 380 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 381 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 382 MPP_MODE(1, 383 MPP_FUNCTION(0x00, "gpio", NULL), 384 MPP_FUNCTION(0x02, "uart2", "cts"), 385 MPP_FUNCTION(0x03, "sdio0", "wp"), 386 MPP_FUNCTION(0x0f, "lcd1", "pwm"), 387 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 388 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 389 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 390 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 391 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 392 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 393 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 394 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 395 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 396 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 397 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 398 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 399 MPP_MODE(2, 400 MPP_FUNCTION(0x00, "gpio", NULL), 401 MPP_FUNCTION(0x01, "sata", "prsnt"), 402 MPP_FUNCTION(0x02, "uart2", "txd"), 403 MPP_FUNCTION(0x03, "sdio0", "buspwr"), 404 MPP_FUNCTION(0x04, "uart1", "rts"), 405 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 406 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 407 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 408 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 409 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 410 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 411 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 412 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 413 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 414 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 415 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 416 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 417 MPP_MODE(3, 418 MPP_FUNCTION(0x00, "gpio", NULL), 419 MPP_FUNCTION(0x01, "sata", "act"), 420 MPP_FUNCTION(0x02, "uart2", "rxd"), 421 MPP_FUNCTION(0x03, "sdio0", "ledctrl"), 422 MPP_FUNCTION(0x04, "uart1", "cts"), 423 MPP_FUNCTION(0x0f, "lcd-spi", "cs1"), 424 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 425 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 426 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 427 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 428 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 429 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 430 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 431 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 432 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 433 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 434 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 435 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 436 MPP_MODE(4, 437 MPP_FUNCTION(0x00, "gpio", NULL), 438 MPP_FUNCTION(0x02, "uart3", "rts"), 439 MPP_FUNCTION(0x03, "sdio1", "cd"), 440 MPP_FUNCTION(0x04, "spi1", "miso"), 441 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 442 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 443 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 444 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 445 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 446 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 447 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 448 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 449 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 450 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 451 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 452 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 453 MPP_MODE(5, 454 MPP_FUNCTION(0x00, "gpio", NULL), 455 MPP_FUNCTION(0x02, "uart3", "cts"), 456 MPP_FUNCTION(0x03, "sdio1", "wp"), 457 MPP_FUNCTION(0x04, "spi1", "cs"), 458 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 459 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 460 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 461 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 462 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 463 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 464 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 465 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 466 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 467 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 468 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 469 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 470 MPP_MODE(6, 471 MPP_FUNCTION(0x00, "gpio", NULL), 472 MPP_FUNCTION(0x02, "uart3", "txd"), 473 MPP_FUNCTION(0x03, "sdio1", "buspwr"), 474 MPP_FUNCTION(0x04, "spi1", "mosi"), 475 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 476 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 477 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 478 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 479 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 480 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 481 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 482 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 483 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 484 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 485 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 486 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 487 MPP_MODE(7, 488 MPP_FUNCTION(0x00, "gpio", NULL), 489 MPP_FUNCTION(0x02, "uart3", "rxd"), 490 MPP_FUNCTION(0x03, "sdio1", "ledctrl"), 491 MPP_FUNCTION(0x04, "spi1", "sck"), 492 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 493 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 494 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 495 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 496 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 497 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 498 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 499 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 500 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 501 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 502 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 503 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 504 MPP_MODE(8, 505 MPP_FUNCTION(0x00, "gpio", NULL), 506 MPP_FUNCTION(0x01, "watchdog", "rstout"), 507 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 508 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 509 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 510 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 511 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 512 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 513 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 514 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 515 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 516 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 517 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 518 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 519 MPP_MODE(9, 520 MPP_FUNCTION(0x00, "gpio", NULL), 521 MPP_FUNCTION(0x05, "pex1", "clkreq"), 522 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 523 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 524 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 525 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 526 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 527 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 528 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 529 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 530 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 531 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 532 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 533 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 534 MPP_MODE(10, 535 MPP_FUNCTION(0x00, "gpio", NULL), 536 MPP_FUNCTION(0x05, "ssp", "sclk"), 537 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 538 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 539 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 540 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 541 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 542 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 543 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 544 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 545 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 546 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 547 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 548 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 549 MPP_MODE(11, 550 MPP_FUNCTION(0x00, "gpio", NULL), 551 MPP_FUNCTION(0x01, "sata", "prsnt"), 552 MPP_FUNCTION(0x02, "sata-1", "act"), 553 MPP_FUNCTION(0x03, "sdio0", "ledctrl"), 554 MPP_FUNCTION(0x04, "sdio1", "ledctrl"), 555 MPP_FUNCTION(0x05, "pex0", "clkreq"), 556 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 557 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 558 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 559 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 560 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 561 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 562 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 563 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 564 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 565 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 566 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 567 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 568 MPP_MODE(12, 569 MPP_FUNCTION(0x00, "gpio", NULL), 570 MPP_FUNCTION(0x01, "sata", "act"), 571 MPP_FUNCTION(0x02, "uart2", "rts"), 572 MPP_FUNCTION(0x03, "audio0", "extclk"), 573 MPP_FUNCTION(0x04, "sdio1", "cd"), 574 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 575 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 576 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 577 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 578 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 579 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 580 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 581 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 582 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 583 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 584 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 585 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 586 MPP_MODE(13, 587 MPP_FUNCTION(0x00, "gpio", NULL), 588 MPP_FUNCTION(0x02, "uart2", "cts"), 589 MPP_FUNCTION(0x03, "audio1", "extclk"), 590 MPP_FUNCTION(0x04, "sdio1", "wp"), 591 MPP_FUNCTION(0x05, "ssp", "extclk"), 592 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 593 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 594 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 595 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 596 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 597 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 598 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 599 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 600 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 601 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 602 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 603 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 604 MPP_MODE(14, 605 MPP_FUNCTION(0x00, "gpio", NULL), 606 MPP_FUNCTION(0x02, "uart2", "txd"), 607 MPP_FUNCTION(0x04, "sdio1", "buspwr"), 608 MPP_FUNCTION(0x05, "ssp", "rxd"), 609 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 610 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 611 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 612 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 613 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 614 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 615 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 616 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 617 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 618 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 619 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 620 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 621 MPP_MODE(15, 622 MPP_FUNCTION(0x00, "gpio", NULL), 623 MPP_FUNCTION(0x02, "uart2", "rxd"), 624 MPP_FUNCTION(0x04, "sdio1", "ledctrl"), 625 MPP_FUNCTION(0x05, "ssp", "sfrm"), 626 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 627 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 628 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 629 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 630 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 631 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 632 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 633 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 634 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 635 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 636 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 637 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 638 MPP_MODE(16, 639 MPP_FUNCTION(0x00, "gpio", NULL), 640 MPP_FUNCTION(0x02, "uart3", "rts"), 641 MPP_FUNCTION(0x03, "sdio0", "cd"), 642 MPP_FUNCTION(0x04, "lcd-spi", "cs1"), 643 MPP_FUNCTION(0x05, "ac97", "sdi1")), 644 MPP_MODE(17, 645 MPP_FUNCTION(0x00, "gpio", NULL), 646 MPP_FUNCTION(0x01, "ac97-1", "sysclko"), 647 MPP_FUNCTION(0x02, "uart3", "cts"), 648 MPP_FUNCTION(0x03, "sdio0", "wp"), 649 MPP_FUNCTION(0x04, "twsi", "sda"), 650 MPP_FUNCTION(0x05, "ac97", "sdi2")), 651 MPP_MODE(18, 652 MPP_FUNCTION(0x00, "gpio", NULL), 653 MPP_FUNCTION(0x02, "uart3", "txd"), 654 MPP_FUNCTION(0x03, "sdio0", "buspwr"), 655 MPP_FUNCTION(0x04, "lcd0", "pwm"), 656 MPP_FUNCTION(0x05, "ac97", "sdi3")), 657 MPP_MODE(19, 658 MPP_FUNCTION(0x00, "gpio", NULL), 659 MPP_FUNCTION(0x02, "uart3", "rxd"), 660 MPP_FUNCTION(0x03, "sdio0", "ledctrl"), 661 MPP_FUNCTION(0x04, "twsi", "sck")), 662 MPP_MODE(20, 663 MPP_FUNCTION(0x00, "gpio", NULL), 664 MPP_FUNCTION(0x01, "ac97", "sysclko"), 665 MPP_FUNCTION(0x02, "lcd-spi", "miso"), 666 MPP_FUNCTION(0x03, "sdio1", "cd"), 667 MPP_FUNCTION(0x05, "sdio0", "cd"), 668 MPP_FUNCTION(0x06, "spi1", "miso")), 669 MPP_MODE(21, 670 MPP_FUNCTION(0x00, "gpio", NULL), 671 MPP_FUNCTION(0x01, "uart1", "rts"), 672 MPP_FUNCTION(0x02, "lcd-spi", "cs0"), 673 MPP_FUNCTION(0x03, "sdio1", "wp"), 674 MPP_FUNCTION(0x04, "ssp", "sfrm"), 675 MPP_FUNCTION(0x05, "sdio0", "wp"), 676 MPP_FUNCTION(0x06, "spi1", "cs")), 677 MPP_MODE(22, 678 MPP_FUNCTION(0x00, "gpio", NULL), 679 MPP_FUNCTION(0x01, "uart1", "cts"), 680 MPP_FUNCTION(0x02, "lcd-spi", "mosi"), 681 MPP_FUNCTION(0x03, "sdio1", "buspwr"), 682 MPP_FUNCTION(0x04, "ssp", "txd"), 683 MPP_FUNCTION(0x05, "sdio0", "buspwr"), 684 MPP_FUNCTION(0x06, "spi1", "mosi")), 685 MPP_MODE(23, 686 MPP_FUNCTION(0x00, "gpio", NULL), 687 MPP_FUNCTION(0x02, "lcd-spi", "sck"), 688 MPP_FUNCTION(0x03, "sdio1", "ledctrl"), 689 MPP_FUNCTION(0x04, "ssp", "sclk"), 690 MPP_FUNCTION(0x05, "sdio0", "ledctrl"), 691 MPP_FUNCTION(0x06, "spi1", "sck")), 692 MPP_MODE(24, 693 MPP_FUNCTION(0x00, "camera", NULL), 694 MPP_FUNCTION(0x01, "gpio", NULL)), 695 MPP_MODE(40, 696 MPP_FUNCTION(0x00, "sdio0", NULL), 697 MPP_FUNCTION(0x01, "gpio", NULL)), 698 MPP_MODE(46, 699 MPP_FUNCTION(0x00, "sdio1", NULL), 700 MPP_FUNCTION(0x01, "gpio", NULL)), 701 MPP_MODE(52, 702 MPP_FUNCTION(0x00, "i2s1/spdifo", NULL), 703 MPP_FUNCTION(0x02, "i2s1", NULL), 704 MPP_FUNCTION(0x08, "spdifo", NULL), 705 MPP_FUNCTION(0x0a, "gpio", NULL), 706 MPP_FUNCTION(0x0b, "twsi", NULL), 707 MPP_FUNCTION(0x0c, "ssp/spdifo", NULL), 708 MPP_FUNCTION(0x0e, "ssp", NULL), 709 MPP_FUNCTION(0x0f, "ssp/twsi", NULL)), 710 MPP_MODE(58, 711 MPP_FUNCTION(0x00, "spi0", NULL), 712 MPP_FUNCTION(0x01, "gpio", NULL)), 713 MPP_MODE(62, 714 MPP_FUNCTION(0x00, "uart1", NULL), 715 MPP_FUNCTION(0x01, "gpio", NULL)), 716 MPP_MODE(64, 717 MPP_FUNCTION(0x00, "nand", NULL), 718 MPP_FUNCTION(0x01, "gpo", NULL)), 719 MPP_MODE(72, 720 MPP_FUNCTION(0x00, "i2s", NULL), 721 MPP_FUNCTION(0x01, "ac97", NULL)), 722 MPP_MODE(73, 723 MPP_FUNCTION(0x00, "twsi-none", NULL), 724 MPP_FUNCTION(0x01, "twsi-opt1", NULL), 725 MPP_FUNCTION(0x02, "twsi-opt2", NULL), 726 MPP_FUNCTION(0x03, "twsi-opt3", NULL)), 727 }; 728 729 static struct pinctrl_gpio_range dove_mpp_gpio_ranges[] = { 730 MPP_GPIO_RANGE(0, 0, 0, 32), 731 MPP_GPIO_RANGE(1, 32, 32, 32), 732 MPP_GPIO_RANGE(2, 64, 64, 8), 733 }; 734 735 static struct mvebu_pinctrl_soc_info dove_pinctrl_info = { 736 .controls = dove_mpp_controls, 737 .ncontrols = ARRAY_SIZE(dove_mpp_controls), 738 .modes = dove_mpp_modes, 739 .nmodes = ARRAY_SIZE(dove_mpp_modes), 740 .gpioranges = dove_mpp_gpio_ranges, 741 .ngpioranges = ARRAY_SIZE(dove_mpp_gpio_ranges), 742 .variant = 0, 743 }; 744 745 static struct clk *clk; 746 747 static struct of_device_id dove_pinctrl_of_match[] = { 748 { .compatible = "marvell,dove-pinctrl", .data = &dove_pinctrl_info }, 749 { } 750 }; 751 752 static int dove_pinctrl_probe(struct platform_device *pdev) 753 { 754 struct resource *res; 755 const struct of_device_id *match = 756 of_match_device(dove_pinctrl_of_match, &pdev->dev); 757 pdev->dev.platform_data = (void *)match->data; 758 759 /* 760 * General MPP Configuration Register is part of pdma registers. 761 * grab clk to make sure it is ticking. 762 */ 763 clk = devm_clk_get(&pdev->dev, NULL); 764 if (IS_ERR(clk)) { 765 dev_err(&pdev->dev, "Unable to get pdma clock"); 766 return PTR_ERR(clk); 767 } 768 clk_prepare_enable(clk); 769 770 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 771 mpp_base = devm_ioremap_resource(&pdev->dev, res); 772 if (IS_ERR(mpp_base)) 773 return PTR_ERR(mpp_base); 774 775 return mvebu_pinctrl_probe(pdev); 776 } 777 778 static int dove_pinctrl_remove(struct platform_device *pdev) 779 { 780 int ret; 781 782 ret = mvebu_pinctrl_remove(pdev); 783 if (!IS_ERR(clk)) 784 clk_disable_unprepare(clk); 785 return ret; 786 } 787 788 static struct platform_driver dove_pinctrl_driver = { 789 .driver = { 790 .name = "dove-pinctrl", 791 .owner = THIS_MODULE, 792 .of_match_table = dove_pinctrl_of_match, 793 }, 794 .probe = dove_pinctrl_probe, 795 .remove = dove_pinctrl_remove, 796 }; 797 798 module_platform_driver(dove_pinctrl_driver); 799 800 MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>"); 801 MODULE_DESCRIPTION("Marvell Dove pinctrl driver"); 802 MODULE_LICENSE("GPL v2"); 803