1 /* 2 * Marvell Dove pinctrl driver based on mvebu pinctrl core 3 * 4 * Author: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #include <linux/err.h> 13 #include <linux/init.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/bitops.h> 17 #include <linux/platform_device.h> 18 #include <linux/clk.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/pinctrl/pinctrl.h> 22 23 #include "pinctrl-mvebu.h" 24 25 /* Internal registers can be configured at any 1 MiB aligned address */ 26 #define INT_REGS_MASK ~(SZ_1M - 1) 27 #define MPP4_REGS_OFFS 0xd0440 28 #define PMU_REGS_OFFS 0xd802c 29 30 #define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000) 31 #define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200) 32 #define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10) 33 #define DOVE_AU0_AC97_SEL BIT(16) 34 #define DOVE_PMU_SIGNAL_SELECT_0 (DOVE_SB_REGS_VIRT_BASE + 0xd802C) 35 #define DOVE_PMU_SIGNAL_SELECT_1 (DOVE_SB_REGS_VIRT_BASE + 0xd8030) 36 #define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) 37 #define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) 38 #define DOVE_TWSI_ENABLE_OPTION1 BIT(7) 39 #define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030) 40 #define DOVE_TWSI_ENABLE_OPTION2 BIT(20) 41 #define DOVE_TWSI_ENABLE_OPTION3 BIT(21) 42 #define DOVE_TWSI_OPTION3_GPIO BIT(22) 43 #define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034) 44 #define DOVE_SSP_ON_AU1 BIT(0) 45 #define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c) 46 #define DOVE_AU1_SPDIFO_GPIO_EN BIT(1) 47 #define DOVE_NAND_GPIO_EN BIT(0) 48 #define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400) 49 #define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40) 50 #define DOVE_SPI_GPIO_SEL BIT(5) 51 #define DOVE_UART1_GPIO_SEL BIT(4) 52 #define DOVE_AU1_GPIO_SEL BIT(3) 53 #define DOVE_CAM_GPIO_SEL BIT(2) 54 #define DOVE_SD1_GPIO_SEL BIT(1) 55 #define DOVE_SD0_GPIO_SEL BIT(0) 56 57 #define CONFIG_PMU BIT(4) 58 59 static void __iomem *mpp_base; 60 static void __iomem *mpp4_base; 61 static void __iomem *pmu_base; 62 63 static int dove_mpp_ctrl_get(unsigned pid, unsigned long *config) 64 { 65 return default_mpp_ctrl_get(mpp_base, pid, config); 66 } 67 68 static int dove_mpp_ctrl_set(unsigned pid, unsigned long config) 69 { 70 return default_mpp_ctrl_set(mpp_base, pid, config); 71 } 72 73 static int dove_pmu_mpp_ctrl_get(unsigned pid, unsigned long *config) 74 { 75 unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; 76 unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; 77 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); 78 unsigned long func; 79 80 if ((pmu & BIT(pid)) == 0) 81 return default_mpp_ctrl_get(mpp_base, pid, config); 82 83 func = readl(DOVE_PMU_SIGNAL_SELECT_0 + off); 84 *config = (func >> shift) & MVEBU_MPP_MASK; 85 *config |= CONFIG_PMU; 86 87 return 0; 88 } 89 90 static int dove_pmu_mpp_ctrl_set(unsigned pid, unsigned long config) 91 { 92 unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; 93 unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; 94 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); 95 unsigned long func; 96 97 if ((config & CONFIG_PMU) == 0) { 98 writel(pmu & ~BIT(pid), DOVE_PMU_MPP_GENERAL_CTRL); 99 return default_mpp_ctrl_set(mpp_base, pid, config); 100 } 101 102 writel(pmu | BIT(pid), DOVE_PMU_MPP_GENERAL_CTRL); 103 func = readl(DOVE_PMU_SIGNAL_SELECT_0 + off); 104 func &= ~(MVEBU_MPP_MASK << shift); 105 func |= (config & MVEBU_MPP_MASK) << shift; 106 writel(func, DOVE_PMU_SIGNAL_SELECT_0 + off); 107 108 return 0; 109 } 110 111 static int dove_mpp4_ctrl_get(unsigned pid, unsigned long *config) 112 { 113 unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 114 unsigned long mask; 115 116 switch (pid) { 117 case 24: /* mpp_camera */ 118 mask = DOVE_CAM_GPIO_SEL; 119 break; 120 case 40: /* mpp_sdio0 */ 121 mask = DOVE_SD0_GPIO_SEL; 122 break; 123 case 46: /* mpp_sdio1 */ 124 mask = DOVE_SD1_GPIO_SEL; 125 break; 126 case 58: /* mpp_spi0 */ 127 mask = DOVE_SPI_GPIO_SEL; 128 break; 129 case 62: /* mpp_uart1 */ 130 mask = DOVE_UART1_GPIO_SEL; 131 break; 132 default: 133 return -EINVAL; 134 } 135 136 *config = ((mpp4 & mask) != 0); 137 138 return 0; 139 } 140 141 static int dove_mpp4_ctrl_set(unsigned pid, unsigned long config) 142 { 143 unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 144 unsigned long mask; 145 146 switch (pid) { 147 case 24: /* mpp_camera */ 148 mask = DOVE_CAM_GPIO_SEL; 149 break; 150 case 40: /* mpp_sdio0 */ 151 mask = DOVE_SD0_GPIO_SEL; 152 break; 153 case 46: /* mpp_sdio1 */ 154 mask = DOVE_SD1_GPIO_SEL; 155 break; 156 case 58: /* mpp_spi0 */ 157 mask = DOVE_SPI_GPIO_SEL; 158 break; 159 case 62: /* mpp_uart1 */ 160 mask = DOVE_UART1_GPIO_SEL; 161 break; 162 default: 163 return -EINVAL; 164 } 165 166 mpp4 &= ~mask; 167 if (config) 168 mpp4 |= mask; 169 170 writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE); 171 172 return 0; 173 } 174 175 static int dove_nand_ctrl_get(unsigned pid, unsigned long *config) 176 { 177 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 178 179 *config = ((gmpp & DOVE_NAND_GPIO_EN) != 0); 180 181 return 0; 182 } 183 184 static int dove_nand_ctrl_set(unsigned pid, unsigned long config) 185 { 186 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 187 188 gmpp &= ~DOVE_NAND_GPIO_EN; 189 if (config) 190 gmpp |= DOVE_NAND_GPIO_EN; 191 192 writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE); 193 194 return 0; 195 } 196 197 static int dove_audio0_ctrl_get(unsigned pid, unsigned long *config) 198 { 199 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); 200 201 *config = ((pmu & DOVE_AU0_AC97_SEL) != 0); 202 203 return 0; 204 } 205 206 static int dove_audio0_ctrl_set(unsigned pid, unsigned long config) 207 { 208 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); 209 210 pmu &= ~DOVE_AU0_AC97_SEL; 211 if (config) 212 pmu |= DOVE_AU0_AC97_SEL; 213 writel(pmu, DOVE_PMU_MPP_GENERAL_CTRL); 214 215 return 0; 216 } 217 218 static int dove_audio1_ctrl_get(unsigned pid, unsigned long *config) 219 { 220 unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 221 unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1); 222 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 223 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 224 225 *config = 0; 226 if (mpp4 & DOVE_AU1_GPIO_SEL) 227 *config |= BIT(3); 228 if (sspc1 & DOVE_SSP_ON_AU1) 229 *config |= BIT(2); 230 if (gmpp & DOVE_AU1_SPDIFO_GPIO_EN) 231 *config |= BIT(1); 232 if (gcfg2 & DOVE_TWSI_OPTION3_GPIO) 233 *config |= BIT(0); 234 235 /* SSP/TWSI only if I2S1 not set*/ 236 if ((*config & BIT(3)) == 0) 237 *config &= ~(BIT(2) | BIT(0)); 238 /* TWSI only if SPDIFO not set*/ 239 if ((*config & BIT(1)) == 0) 240 *config &= ~BIT(0); 241 return 0; 242 } 243 244 static int dove_audio1_ctrl_set(unsigned pid, unsigned long config) 245 { 246 unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 247 unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1); 248 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 249 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 250 251 /* 252 * clear all audio1 related bits before configure 253 */ 254 gcfg2 &= ~DOVE_TWSI_OPTION3_GPIO; 255 gmpp &= ~DOVE_AU1_SPDIFO_GPIO_EN; 256 sspc1 &= ~DOVE_SSP_ON_AU1; 257 mpp4 &= ~DOVE_AU1_GPIO_SEL; 258 259 if (config & BIT(0)) 260 gcfg2 |= DOVE_TWSI_OPTION3_GPIO; 261 if (config & BIT(1)) 262 gmpp |= DOVE_AU1_SPDIFO_GPIO_EN; 263 if (config & BIT(2)) 264 sspc1 |= DOVE_SSP_ON_AU1; 265 if (config & BIT(3)) 266 mpp4 |= DOVE_AU1_GPIO_SEL; 267 268 writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE); 269 writel(sspc1, DOVE_SSP_CTRL_STATUS_1); 270 writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE); 271 writel(gcfg2, DOVE_GLOBAL_CONFIG_2); 272 273 return 0; 274 } 275 276 /* mpp[52:57] gpio pins depend heavily on current config; 277 * gpio_req does not try to mux in gpio capabilities to not 278 * break other functions. If you require all mpps as gpio 279 * enforce gpio setting by pinctrl mapping. 280 */ 281 static int dove_audio1_ctrl_gpio_req(unsigned pid) 282 { 283 unsigned long config; 284 285 dove_audio1_ctrl_get(pid, &config); 286 287 switch (config) { 288 case 0x02: /* i2s1 : gpio[56:57] */ 289 case 0x0e: /* ssp : gpio[56:57] */ 290 if (pid >= 56) 291 return 0; 292 return -ENOTSUPP; 293 case 0x08: /* spdifo : gpio[52:55] */ 294 case 0x0b: /* twsi : gpio[52:55] */ 295 if (pid <= 55) 296 return 0; 297 return -ENOTSUPP; 298 case 0x0a: /* all gpio */ 299 return 0; 300 /* 0x00 : i2s1/spdifo : no gpio */ 301 /* 0x0c : ssp/spdifo : no gpio */ 302 /* 0x0f : ssp/twsi : no gpio */ 303 } 304 return -ENOTSUPP; 305 } 306 307 /* mpp[52:57] has gpio pins capable of in and out */ 308 static int dove_audio1_ctrl_gpio_dir(unsigned pid, bool input) 309 { 310 if (pid < 52 || pid > 57) 311 return -ENOTSUPP; 312 return 0; 313 } 314 315 static int dove_twsi_ctrl_get(unsigned pid, unsigned long *config) 316 { 317 unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1); 318 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 319 320 *config = 0; 321 if (gcfg1 & DOVE_TWSI_ENABLE_OPTION1) 322 *config = 1; 323 else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION2) 324 *config = 2; 325 else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION3) 326 *config = 3; 327 328 return 0; 329 } 330 331 static int dove_twsi_ctrl_set(unsigned pid, unsigned long config) 332 { 333 unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1); 334 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 335 336 gcfg1 &= ~DOVE_TWSI_ENABLE_OPTION1; 337 gcfg2 &= ~(DOVE_TWSI_ENABLE_OPTION2 | DOVE_TWSI_ENABLE_OPTION3); 338 339 switch (config) { 340 case 1: 341 gcfg1 |= DOVE_TWSI_ENABLE_OPTION1; 342 break; 343 case 2: 344 gcfg2 |= DOVE_TWSI_ENABLE_OPTION2; 345 break; 346 case 3: 347 gcfg2 |= DOVE_TWSI_ENABLE_OPTION3; 348 break; 349 } 350 351 writel(gcfg1, DOVE_GLOBAL_CONFIG_1); 352 writel(gcfg2, DOVE_GLOBAL_CONFIG_2); 353 354 return 0; 355 } 356 357 static struct mvebu_mpp_ctrl dove_mpp_controls[] = { 358 MPP_FUNC_CTRL(0, 15, NULL, dove_pmu_mpp_ctrl), 359 MPP_FUNC_CTRL(16, 23, NULL, dove_mpp_ctrl), 360 MPP_FUNC_CTRL(24, 39, "mpp_camera", dove_mpp4_ctrl), 361 MPP_FUNC_CTRL(40, 45, "mpp_sdio0", dove_mpp4_ctrl), 362 MPP_FUNC_CTRL(46, 51, "mpp_sdio1", dove_mpp4_ctrl), 363 MPP_FUNC_GPIO_CTRL(52, 57, "mpp_audio1", dove_audio1_ctrl), 364 MPP_FUNC_CTRL(58, 61, "mpp_spi0", dove_mpp4_ctrl), 365 MPP_FUNC_CTRL(62, 63, "mpp_uart1", dove_mpp4_ctrl), 366 MPP_FUNC_CTRL(64, 71, "mpp_nand", dove_nand_ctrl), 367 MPP_FUNC_CTRL(72, 72, "audio0", dove_audio0_ctrl), 368 MPP_FUNC_CTRL(73, 73, "twsi", dove_twsi_ctrl), 369 }; 370 371 static struct mvebu_mpp_mode dove_mpp_modes[] = { 372 MPP_MODE(0, 373 MPP_FUNCTION(0x00, "gpio", NULL), 374 MPP_FUNCTION(0x02, "uart2", "rts"), 375 MPP_FUNCTION(0x03, "sdio0", "cd"), 376 MPP_FUNCTION(0x0f, "lcd0", "pwm"), 377 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 378 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 379 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 380 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 381 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 382 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 383 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 384 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 385 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 386 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 387 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 388 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 389 MPP_MODE(1, 390 MPP_FUNCTION(0x00, "gpio", NULL), 391 MPP_FUNCTION(0x02, "uart2", "cts"), 392 MPP_FUNCTION(0x03, "sdio0", "wp"), 393 MPP_FUNCTION(0x0f, "lcd1", "pwm"), 394 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 395 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 396 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 397 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 398 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 399 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 400 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 401 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 402 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 403 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 404 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 405 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 406 MPP_MODE(2, 407 MPP_FUNCTION(0x00, "gpio", NULL), 408 MPP_FUNCTION(0x01, "sata", "prsnt"), 409 MPP_FUNCTION(0x02, "uart2", "txd"), 410 MPP_FUNCTION(0x03, "sdio0", "buspwr"), 411 MPP_FUNCTION(0x04, "uart1", "rts"), 412 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 413 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 414 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 415 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 416 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 417 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 418 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 419 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 420 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 421 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 422 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 423 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 424 MPP_MODE(3, 425 MPP_FUNCTION(0x00, "gpio", NULL), 426 MPP_FUNCTION(0x01, "sata", "act"), 427 MPP_FUNCTION(0x02, "uart2", "rxd"), 428 MPP_FUNCTION(0x03, "sdio0", "ledctrl"), 429 MPP_FUNCTION(0x04, "uart1", "cts"), 430 MPP_FUNCTION(0x0f, "lcd-spi", "cs1"), 431 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 432 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 433 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 434 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 435 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 436 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 437 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 438 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 439 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 440 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 441 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 442 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 443 MPP_MODE(4, 444 MPP_FUNCTION(0x00, "gpio", NULL), 445 MPP_FUNCTION(0x02, "uart3", "rts"), 446 MPP_FUNCTION(0x03, "sdio1", "cd"), 447 MPP_FUNCTION(0x04, "spi1", "miso"), 448 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 449 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 450 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 451 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 452 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 453 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 454 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 455 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 456 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 457 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 458 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 459 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 460 MPP_MODE(5, 461 MPP_FUNCTION(0x00, "gpio", NULL), 462 MPP_FUNCTION(0x02, "uart3", "cts"), 463 MPP_FUNCTION(0x03, "sdio1", "wp"), 464 MPP_FUNCTION(0x04, "spi1", "cs"), 465 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 466 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 467 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 468 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 469 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 470 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 471 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 472 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 473 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 474 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 475 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 476 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 477 MPP_MODE(6, 478 MPP_FUNCTION(0x00, "gpio", NULL), 479 MPP_FUNCTION(0x02, "uart3", "txd"), 480 MPP_FUNCTION(0x03, "sdio1", "buspwr"), 481 MPP_FUNCTION(0x04, "spi1", "mosi"), 482 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 483 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 484 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 485 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 486 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 487 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 488 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 489 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 490 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 491 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 492 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 493 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 494 MPP_MODE(7, 495 MPP_FUNCTION(0x00, "gpio", NULL), 496 MPP_FUNCTION(0x02, "uart3", "rxd"), 497 MPP_FUNCTION(0x03, "sdio1", "ledctrl"), 498 MPP_FUNCTION(0x04, "spi1", "sck"), 499 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 500 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 501 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 502 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 503 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 504 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 505 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 506 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 507 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 508 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 509 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 510 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 511 MPP_MODE(8, 512 MPP_FUNCTION(0x00, "gpio", NULL), 513 MPP_FUNCTION(0x01, "watchdog", "rstout"), 514 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 515 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 516 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 517 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 518 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 519 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 520 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 521 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 522 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 523 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 524 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 525 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 526 MPP_MODE(9, 527 MPP_FUNCTION(0x00, "gpio", NULL), 528 MPP_FUNCTION(0x05, "pex1", "clkreq"), 529 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 530 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 531 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 532 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 533 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 534 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 535 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 536 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 537 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 538 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 539 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 540 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 541 MPP_MODE(10, 542 MPP_FUNCTION(0x00, "gpio", NULL), 543 MPP_FUNCTION(0x05, "ssp", "sclk"), 544 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 545 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 546 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 547 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 548 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 549 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 550 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 551 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 552 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 553 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 554 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 555 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 556 MPP_MODE(11, 557 MPP_FUNCTION(0x00, "gpio", NULL), 558 MPP_FUNCTION(0x01, "sata", "prsnt"), 559 MPP_FUNCTION(0x02, "sata-1", "act"), 560 MPP_FUNCTION(0x03, "sdio0", "ledctrl"), 561 MPP_FUNCTION(0x04, "sdio1", "ledctrl"), 562 MPP_FUNCTION(0x05, "pex0", "clkreq"), 563 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 564 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 565 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 566 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 567 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 568 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 569 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 570 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 571 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 572 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 573 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 574 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 575 MPP_MODE(12, 576 MPP_FUNCTION(0x00, "gpio", NULL), 577 MPP_FUNCTION(0x01, "sata", "act"), 578 MPP_FUNCTION(0x02, "uart2", "rts"), 579 MPP_FUNCTION(0x03, "audio0", "extclk"), 580 MPP_FUNCTION(0x04, "sdio1", "cd"), 581 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 582 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 583 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 584 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 585 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 586 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 587 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 588 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 589 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 590 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 591 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 592 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 593 MPP_MODE(13, 594 MPP_FUNCTION(0x00, "gpio", NULL), 595 MPP_FUNCTION(0x02, "uart2", "cts"), 596 MPP_FUNCTION(0x03, "audio1", "extclk"), 597 MPP_FUNCTION(0x04, "sdio1", "wp"), 598 MPP_FUNCTION(0x05, "ssp", "extclk"), 599 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 600 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 601 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 602 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 603 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 604 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 605 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 606 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 607 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 608 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 609 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 610 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 611 MPP_MODE(14, 612 MPP_FUNCTION(0x00, "gpio", NULL), 613 MPP_FUNCTION(0x02, "uart2", "txd"), 614 MPP_FUNCTION(0x04, "sdio1", "buspwr"), 615 MPP_FUNCTION(0x05, "ssp", "rxd"), 616 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 617 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 618 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 619 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 620 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 621 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 622 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 623 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 624 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 625 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 626 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 627 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 628 MPP_MODE(15, 629 MPP_FUNCTION(0x00, "gpio", NULL), 630 MPP_FUNCTION(0x02, "uart2", "rxd"), 631 MPP_FUNCTION(0x04, "sdio1", "ledctrl"), 632 MPP_FUNCTION(0x05, "ssp", "sfrm"), 633 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 634 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 635 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 636 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 637 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 638 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 639 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 640 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 641 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 642 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 643 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 644 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 645 MPP_MODE(16, 646 MPP_FUNCTION(0x00, "gpio", NULL), 647 MPP_FUNCTION(0x02, "uart3", "rts"), 648 MPP_FUNCTION(0x03, "sdio0", "cd"), 649 MPP_FUNCTION(0x04, "lcd-spi", "cs1"), 650 MPP_FUNCTION(0x05, "ac97", "sdi1")), 651 MPP_MODE(17, 652 MPP_FUNCTION(0x00, "gpio", NULL), 653 MPP_FUNCTION(0x01, "ac97-1", "sysclko"), 654 MPP_FUNCTION(0x02, "uart3", "cts"), 655 MPP_FUNCTION(0x03, "sdio0", "wp"), 656 MPP_FUNCTION(0x04, "twsi", "sda"), 657 MPP_FUNCTION(0x05, "ac97", "sdi2")), 658 MPP_MODE(18, 659 MPP_FUNCTION(0x00, "gpio", NULL), 660 MPP_FUNCTION(0x02, "uart3", "txd"), 661 MPP_FUNCTION(0x03, "sdio0", "buspwr"), 662 MPP_FUNCTION(0x04, "lcd0", "pwm"), 663 MPP_FUNCTION(0x05, "ac97", "sdi3")), 664 MPP_MODE(19, 665 MPP_FUNCTION(0x00, "gpio", NULL), 666 MPP_FUNCTION(0x02, "uart3", "rxd"), 667 MPP_FUNCTION(0x03, "sdio0", "ledctrl"), 668 MPP_FUNCTION(0x04, "twsi", "sck")), 669 MPP_MODE(20, 670 MPP_FUNCTION(0x00, "gpio", NULL), 671 MPP_FUNCTION(0x01, "ac97", "sysclko"), 672 MPP_FUNCTION(0x02, "lcd-spi", "miso"), 673 MPP_FUNCTION(0x03, "sdio1", "cd"), 674 MPP_FUNCTION(0x05, "sdio0", "cd"), 675 MPP_FUNCTION(0x06, "spi1", "miso")), 676 MPP_MODE(21, 677 MPP_FUNCTION(0x00, "gpio", NULL), 678 MPP_FUNCTION(0x01, "uart1", "rts"), 679 MPP_FUNCTION(0x02, "lcd-spi", "cs0"), 680 MPP_FUNCTION(0x03, "sdio1", "wp"), 681 MPP_FUNCTION(0x04, "ssp", "sfrm"), 682 MPP_FUNCTION(0x05, "sdio0", "wp"), 683 MPP_FUNCTION(0x06, "spi1", "cs")), 684 MPP_MODE(22, 685 MPP_FUNCTION(0x00, "gpio", NULL), 686 MPP_FUNCTION(0x01, "uart1", "cts"), 687 MPP_FUNCTION(0x02, "lcd-spi", "mosi"), 688 MPP_FUNCTION(0x03, "sdio1", "buspwr"), 689 MPP_FUNCTION(0x04, "ssp", "txd"), 690 MPP_FUNCTION(0x05, "sdio0", "buspwr"), 691 MPP_FUNCTION(0x06, "spi1", "mosi")), 692 MPP_MODE(23, 693 MPP_FUNCTION(0x00, "gpio", NULL), 694 MPP_FUNCTION(0x02, "lcd-spi", "sck"), 695 MPP_FUNCTION(0x03, "sdio1", "ledctrl"), 696 MPP_FUNCTION(0x04, "ssp", "sclk"), 697 MPP_FUNCTION(0x05, "sdio0", "ledctrl"), 698 MPP_FUNCTION(0x06, "spi1", "sck")), 699 MPP_MODE(24, 700 MPP_FUNCTION(0x00, "camera", NULL), 701 MPP_FUNCTION(0x01, "gpio", NULL)), 702 MPP_MODE(40, 703 MPP_FUNCTION(0x00, "sdio0", NULL), 704 MPP_FUNCTION(0x01, "gpio", NULL)), 705 MPP_MODE(46, 706 MPP_FUNCTION(0x00, "sdio1", NULL), 707 MPP_FUNCTION(0x01, "gpio", NULL)), 708 MPP_MODE(52, 709 MPP_FUNCTION(0x00, "i2s1/spdifo", NULL), 710 MPP_FUNCTION(0x02, "i2s1", NULL), 711 MPP_FUNCTION(0x08, "spdifo", NULL), 712 MPP_FUNCTION(0x0a, "gpio", NULL), 713 MPP_FUNCTION(0x0b, "twsi", NULL), 714 MPP_FUNCTION(0x0c, "ssp/spdifo", NULL), 715 MPP_FUNCTION(0x0e, "ssp", NULL), 716 MPP_FUNCTION(0x0f, "ssp/twsi", NULL)), 717 MPP_MODE(58, 718 MPP_FUNCTION(0x00, "spi0", NULL), 719 MPP_FUNCTION(0x01, "gpio", NULL)), 720 MPP_MODE(62, 721 MPP_FUNCTION(0x00, "uart1", NULL), 722 MPP_FUNCTION(0x01, "gpio", NULL)), 723 MPP_MODE(64, 724 MPP_FUNCTION(0x00, "nand", NULL), 725 MPP_FUNCTION(0x01, "gpo", NULL)), 726 MPP_MODE(72, 727 MPP_FUNCTION(0x00, "i2s", NULL), 728 MPP_FUNCTION(0x01, "ac97", NULL)), 729 MPP_MODE(73, 730 MPP_FUNCTION(0x00, "twsi-none", NULL), 731 MPP_FUNCTION(0x01, "twsi-opt1", NULL), 732 MPP_FUNCTION(0x02, "twsi-opt2", NULL), 733 MPP_FUNCTION(0x03, "twsi-opt3", NULL)), 734 }; 735 736 static struct pinctrl_gpio_range dove_mpp_gpio_ranges[] = { 737 MPP_GPIO_RANGE(0, 0, 0, 32), 738 MPP_GPIO_RANGE(1, 32, 32, 32), 739 MPP_GPIO_RANGE(2, 64, 64, 8), 740 }; 741 742 static struct mvebu_pinctrl_soc_info dove_pinctrl_info = { 743 .controls = dove_mpp_controls, 744 .ncontrols = ARRAY_SIZE(dove_mpp_controls), 745 .modes = dove_mpp_modes, 746 .nmodes = ARRAY_SIZE(dove_mpp_modes), 747 .gpioranges = dove_mpp_gpio_ranges, 748 .ngpioranges = ARRAY_SIZE(dove_mpp_gpio_ranges), 749 .variant = 0, 750 }; 751 752 static struct clk *clk; 753 754 static struct of_device_id dove_pinctrl_of_match[] = { 755 { .compatible = "marvell,dove-pinctrl", .data = &dove_pinctrl_info }, 756 { } 757 }; 758 759 static int dove_pinctrl_probe(struct platform_device *pdev) 760 { 761 struct resource *res, *mpp_res; 762 struct resource fb_res; 763 const struct of_device_id *match = 764 of_match_device(dove_pinctrl_of_match, &pdev->dev); 765 pdev->dev.platform_data = (void *)match->data; 766 767 /* 768 * General MPP Configuration Register is part of pdma registers. 769 * grab clk to make sure it is ticking. 770 */ 771 clk = devm_clk_get(&pdev->dev, NULL); 772 if (IS_ERR(clk)) { 773 dev_err(&pdev->dev, "Unable to get pdma clock"); 774 return PTR_ERR(clk); 775 } 776 clk_prepare_enable(clk); 777 778 mpp_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 779 mpp_base = devm_ioremap_resource(&pdev->dev, mpp_res); 780 if (IS_ERR(mpp_base)) 781 return PTR_ERR(mpp_base); 782 783 /* prepare fallback resource */ 784 memcpy(&fb_res, mpp_res, sizeof(struct resource)); 785 fb_res.start = 0; 786 787 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 788 if (!res) { 789 dev_warn(&pdev->dev, "falling back to hardcoded MPP4 resource\n"); 790 adjust_resource(&fb_res, 791 (mpp_res->start & INT_REGS_MASK) + MPP4_REGS_OFFS, 0x4); 792 res = &fb_res; 793 } 794 795 mpp4_base = devm_ioremap_resource(&pdev->dev, res); 796 if (IS_ERR(mpp4_base)) 797 return PTR_ERR(mpp4_base); 798 799 res = platform_get_resource(pdev, IORESOURCE_MEM, 2); 800 if (!res) { 801 dev_warn(&pdev->dev, "falling back to hardcoded PMU resource\n"); 802 adjust_resource(&fb_res, 803 (mpp_res->start & INT_REGS_MASK) + PMU_REGS_OFFS, 0x8); 804 res = &fb_res; 805 } 806 807 pmu_base = devm_ioremap_resource(&pdev->dev, res); 808 if (IS_ERR(pmu_base)) 809 return PTR_ERR(pmu_base); 810 811 /* Warn on any missing DT resource */ 812 WARN(fb_res.start, FW_BUG "Missing pinctrl regs in DTB. Please update your firmware.\n"); 813 814 return mvebu_pinctrl_probe(pdev); 815 } 816 817 static int dove_pinctrl_remove(struct platform_device *pdev) 818 { 819 int ret; 820 821 ret = mvebu_pinctrl_remove(pdev); 822 if (!IS_ERR(clk)) 823 clk_disable_unprepare(clk); 824 return ret; 825 } 826 827 static struct platform_driver dove_pinctrl_driver = { 828 .driver = { 829 .name = "dove-pinctrl", 830 .owner = THIS_MODULE, 831 .of_match_table = dove_pinctrl_of_match, 832 }, 833 .probe = dove_pinctrl_probe, 834 .remove = dove_pinctrl_remove, 835 }; 836 837 module_platform_driver(dove_pinctrl_driver); 838 839 MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>"); 840 MODULE_DESCRIPTION("Marvell Dove pinctrl driver"); 841 MODULE_LICENSE("GPL v2"); 842