1 /* 2 * Marvell Dove pinctrl driver based on mvebu pinctrl core 3 * 4 * Author: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #include <linux/err.h> 13 #include <linux/init.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/bitops.h> 17 #include <linux/platform_device.h> 18 #include <linux/clk.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/mfd/syscon.h> 22 #include <linux/pinctrl/pinctrl.h> 23 #include <linux/regmap.h> 24 25 #include "pinctrl-mvebu.h" 26 27 /* Internal registers can be configured at any 1 MiB aligned address */ 28 #define INT_REGS_MASK ~(SZ_1M - 1) 29 #define MPP4_REGS_OFFS 0xd0440 30 #define PMU_REGS_OFFS 0xd802c 31 #define GC_REGS_OFFS 0xe802c 32 33 #define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000) 34 #define DOVE_PMU_SIGNAL_SELECT_0 (DOVE_SB_REGS_VIRT_BASE + 0xd802C) 35 #define DOVE_PMU_SIGNAL_SELECT_1 (DOVE_SB_REGS_VIRT_BASE + 0xd8030) 36 #define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) 37 #define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) 38 #define DOVE_TWSI_ENABLE_OPTION1 BIT(7) 39 #define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030) 40 #define DOVE_TWSI_ENABLE_OPTION2 BIT(20) 41 #define DOVE_TWSI_ENABLE_OPTION3 BIT(21) 42 #define DOVE_TWSI_OPTION3_GPIO BIT(22) 43 #define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034) 44 #define DOVE_SSP_ON_AU1 BIT(0) 45 #define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c) 46 #define DOVE_AU1_SPDIFO_GPIO_EN BIT(1) 47 #define DOVE_NAND_GPIO_EN BIT(0) 48 #define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400) 49 50 /* MPP Base registers */ 51 #define PMU_MPP_GENERAL_CTRL 0x10 52 #define AU0_AC97_SEL BIT(16) 53 54 /* MPP Control 4 register */ 55 #define SPI_GPIO_SEL BIT(5) 56 #define UART1_GPIO_SEL BIT(4) 57 #define AU1_GPIO_SEL BIT(3) 58 #define CAM_GPIO_SEL BIT(2) 59 #define SD1_GPIO_SEL BIT(1) 60 #define SD0_GPIO_SEL BIT(0) 61 62 #define CONFIG_PMU BIT(4) 63 64 static void __iomem *mpp_base; 65 static void __iomem *mpp4_base; 66 static void __iomem *pmu_base; 67 static struct regmap *gconfmap; 68 69 static int dove_mpp_ctrl_get(unsigned pid, unsigned long *config) 70 { 71 return default_mpp_ctrl_get(mpp_base, pid, config); 72 } 73 74 static int dove_mpp_ctrl_set(unsigned pid, unsigned long config) 75 { 76 return default_mpp_ctrl_set(mpp_base, pid, config); 77 } 78 79 static int dove_pmu_mpp_ctrl_get(unsigned pid, unsigned long *config) 80 { 81 unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; 82 unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; 83 unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL); 84 unsigned long func; 85 86 if ((pmu & BIT(pid)) == 0) 87 return default_mpp_ctrl_get(mpp_base, pid, config); 88 89 func = readl(DOVE_PMU_SIGNAL_SELECT_0 + off); 90 *config = (func >> shift) & MVEBU_MPP_MASK; 91 *config |= CONFIG_PMU; 92 93 return 0; 94 } 95 96 static int dove_pmu_mpp_ctrl_set(unsigned pid, unsigned long config) 97 { 98 unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; 99 unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; 100 unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL); 101 unsigned long func; 102 103 if ((config & CONFIG_PMU) == 0) { 104 writel(pmu & ~BIT(pid), mpp_base + PMU_MPP_GENERAL_CTRL); 105 return default_mpp_ctrl_set(mpp_base, pid, config); 106 } 107 108 writel(pmu | BIT(pid), mpp_base + PMU_MPP_GENERAL_CTRL); 109 func = readl(DOVE_PMU_SIGNAL_SELECT_0 + off); 110 func &= ~(MVEBU_MPP_MASK << shift); 111 func |= (config & MVEBU_MPP_MASK) << shift; 112 writel(func, DOVE_PMU_SIGNAL_SELECT_0 + off); 113 114 return 0; 115 } 116 117 static int dove_mpp4_ctrl_get(unsigned pid, unsigned long *config) 118 { 119 unsigned long mpp4 = readl(mpp4_base); 120 unsigned long mask; 121 122 switch (pid) { 123 case 24: /* mpp_camera */ 124 mask = CAM_GPIO_SEL; 125 break; 126 case 40: /* mpp_sdio0 */ 127 mask = SD0_GPIO_SEL; 128 break; 129 case 46: /* mpp_sdio1 */ 130 mask = SD1_GPIO_SEL; 131 break; 132 case 58: /* mpp_spi0 */ 133 mask = SPI_GPIO_SEL; 134 break; 135 case 62: /* mpp_uart1 */ 136 mask = UART1_GPIO_SEL; 137 break; 138 default: 139 return -EINVAL; 140 } 141 142 *config = ((mpp4 & mask) != 0); 143 144 return 0; 145 } 146 147 static int dove_mpp4_ctrl_set(unsigned pid, unsigned long config) 148 { 149 unsigned long mpp4 = readl(mpp4_base); 150 unsigned long mask; 151 152 switch (pid) { 153 case 24: /* mpp_camera */ 154 mask = CAM_GPIO_SEL; 155 break; 156 case 40: /* mpp_sdio0 */ 157 mask = SD0_GPIO_SEL; 158 break; 159 case 46: /* mpp_sdio1 */ 160 mask = SD1_GPIO_SEL; 161 break; 162 case 58: /* mpp_spi0 */ 163 mask = SPI_GPIO_SEL; 164 break; 165 case 62: /* mpp_uart1 */ 166 mask = UART1_GPIO_SEL; 167 break; 168 default: 169 return -EINVAL; 170 } 171 172 mpp4 &= ~mask; 173 if (config) 174 mpp4 |= mask; 175 176 writel(mpp4, mpp4_base); 177 178 return 0; 179 } 180 181 static int dove_nand_ctrl_get(unsigned pid, unsigned long *config) 182 { 183 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 184 185 *config = ((gmpp & DOVE_NAND_GPIO_EN) != 0); 186 187 return 0; 188 } 189 190 static int dove_nand_ctrl_set(unsigned pid, unsigned long config) 191 { 192 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 193 194 gmpp &= ~DOVE_NAND_GPIO_EN; 195 if (config) 196 gmpp |= DOVE_NAND_GPIO_EN; 197 198 writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE); 199 200 return 0; 201 } 202 203 static int dove_audio0_ctrl_get(unsigned pid, unsigned long *config) 204 { 205 unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL); 206 207 *config = ((pmu & AU0_AC97_SEL) != 0); 208 209 return 0; 210 } 211 212 static int dove_audio0_ctrl_set(unsigned pid, unsigned long config) 213 { 214 unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL); 215 216 pmu &= ~AU0_AC97_SEL; 217 if (config) 218 pmu |= AU0_AC97_SEL; 219 writel(pmu, mpp_base + PMU_MPP_GENERAL_CTRL); 220 221 return 0; 222 } 223 224 static int dove_audio1_ctrl_get(unsigned pid, unsigned long *config) 225 { 226 unsigned int mpp4 = readl(mpp4_base); 227 unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1); 228 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 229 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 230 231 *config = 0; 232 if (mpp4 & AU1_GPIO_SEL) 233 *config |= BIT(3); 234 if (sspc1 & DOVE_SSP_ON_AU1) 235 *config |= BIT(2); 236 if (gmpp & DOVE_AU1_SPDIFO_GPIO_EN) 237 *config |= BIT(1); 238 if (gcfg2 & DOVE_TWSI_OPTION3_GPIO) 239 *config |= BIT(0); 240 241 /* SSP/TWSI only if I2S1 not set*/ 242 if ((*config & BIT(3)) == 0) 243 *config &= ~(BIT(2) | BIT(0)); 244 /* TWSI only if SPDIFO not set*/ 245 if ((*config & BIT(1)) == 0) 246 *config &= ~BIT(0); 247 return 0; 248 } 249 250 static int dove_audio1_ctrl_set(unsigned pid, unsigned long config) 251 { 252 unsigned int mpp4 = readl(mpp4_base); 253 unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1); 254 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 255 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 256 257 /* 258 * clear all audio1 related bits before configure 259 */ 260 gcfg2 &= ~DOVE_TWSI_OPTION3_GPIO; 261 gmpp &= ~DOVE_AU1_SPDIFO_GPIO_EN; 262 sspc1 &= ~DOVE_SSP_ON_AU1; 263 mpp4 &= ~AU1_GPIO_SEL; 264 265 if (config & BIT(0)) 266 gcfg2 |= DOVE_TWSI_OPTION3_GPIO; 267 if (config & BIT(1)) 268 gmpp |= DOVE_AU1_SPDIFO_GPIO_EN; 269 if (config & BIT(2)) 270 sspc1 |= DOVE_SSP_ON_AU1; 271 if (config & BIT(3)) 272 mpp4 |= AU1_GPIO_SEL; 273 274 writel(mpp4, mpp4_base); 275 writel(sspc1, DOVE_SSP_CTRL_STATUS_1); 276 writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE); 277 writel(gcfg2, DOVE_GLOBAL_CONFIG_2); 278 279 return 0; 280 } 281 282 /* mpp[52:57] gpio pins depend heavily on current config; 283 * gpio_req does not try to mux in gpio capabilities to not 284 * break other functions. If you require all mpps as gpio 285 * enforce gpio setting by pinctrl mapping. 286 */ 287 static int dove_audio1_ctrl_gpio_req(unsigned pid) 288 { 289 unsigned long config; 290 291 dove_audio1_ctrl_get(pid, &config); 292 293 switch (config) { 294 case 0x02: /* i2s1 : gpio[56:57] */ 295 case 0x0e: /* ssp : gpio[56:57] */ 296 if (pid >= 56) 297 return 0; 298 return -ENOTSUPP; 299 case 0x08: /* spdifo : gpio[52:55] */ 300 case 0x0b: /* twsi : gpio[52:55] */ 301 if (pid <= 55) 302 return 0; 303 return -ENOTSUPP; 304 case 0x0a: /* all gpio */ 305 return 0; 306 /* 0x00 : i2s1/spdifo : no gpio */ 307 /* 0x0c : ssp/spdifo : no gpio */ 308 /* 0x0f : ssp/twsi : no gpio */ 309 } 310 return -ENOTSUPP; 311 } 312 313 /* mpp[52:57] has gpio pins capable of in and out */ 314 static int dove_audio1_ctrl_gpio_dir(unsigned pid, bool input) 315 { 316 if (pid < 52 || pid > 57) 317 return -ENOTSUPP; 318 return 0; 319 } 320 321 static int dove_twsi_ctrl_get(unsigned pid, unsigned long *config) 322 { 323 unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1); 324 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 325 326 *config = 0; 327 if (gcfg1 & DOVE_TWSI_ENABLE_OPTION1) 328 *config = 1; 329 else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION2) 330 *config = 2; 331 else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION3) 332 *config = 3; 333 334 return 0; 335 } 336 337 static int dove_twsi_ctrl_set(unsigned pid, unsigned long config) 338 { 339 unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1); 340 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 341 342 gcfg1 &= ~DOVE_TWSI_ENABLE_OPTION1; 343 gcfg2 &= ~(DOVE_TWSI_ENABLE_OPTION2 | DOVE_TWSI_ENABLE_OPTION3); 344 345 switch (config) { 346 case 1: 347 gcfg1 |= DOVE_TWSI_ENABLE_OPTION1; 348 break; 349 case 2: 350 gcfg2 |= DOVE_TWSI_ENABLE_OPTION2; 351 break; 352 case 3: 353 gcfg2 |= DOVE_TWSI_ENABLE_OPTION3; 354 break; 355 } 356 357 writel(gcfg1, DOVE_GLOBAL_CONFIG_1); 358 writel(gcfg2, DOVE_GLOBAL_CONFIG_2); 359 360 return 0; 361 } 362 363 static struct mvebu_mpp_ctrl dove_mpp_controls[] = { 364 MPP_FUNC_CTRL(0, 15, NULL, dove_pmu_mpp_ctrl), 365 MPP_FUNC_CTRL(16, 23, NULL, dove_mpp_ctrl), 366 MPP_FUNC_CTRL(24, 39, "mpp_camera", dove_mpp4_ctrl), 367 MPP_FUNC_CTRL(40, 45, "mpp_sdio0", dove_mpp4_ctrl), 368 MPP_FUNC_CTRL(46, 51, "mpp_sdio1", dove_mpp4_ctrl), 369 MPP_FUNC_GPIO_CTRL(52, 57, "mpp_audio1", dove_audio1_ctrl), 370 MPP_FUNC_CTRL(58, 61, "mpp_spi0", dove_mpp4_ctrl), 371 MPP_FUNC_CTRL(62, 63, "mpp_uart1", dove_mpp4_ctrl), 372 MPP_FUNC_CTRL(64, 71, "mpp_nand", dove_nand_ctrl), 373 MPP_FUNC_CTRL(72, 72, "audio0", dove_audio0_ctrl), 374 MPP_FUNC_CTRL(73, 73, "twsi", dove_twsi_ctrl), 375 }; 376 377 static struct mvebu_mpp_mode dove_mpp_modes[] = { 378 MPP_MODE(0, 379 MPP_FUNCTION(0x00, "gpio", NULL), 380 MPP_FUNCTION(0x02, "uart2", "rts"), 381 MPP_FUNCTION(0x03, "sdio0", "cd"), 382 MPP_FUNCTION(0x0f, "lcd0", "pwm"), 383 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 384 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 385 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 386 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 387 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 388 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 389 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 390 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 391 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 392 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 393 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 394 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 395 MPP_MODE(1, 396 MPP_FUNCTION(0x00, "gpio", NULL), 397 MPP_FUNCTION(0x02, "uart2", "cts"), 398 MPP_FUNCTION(0x03, "sdio0", "wp"), 399 MPP_FUNCTION(0x0f, "lcd1", "pwm"), 400 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 401 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 402 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 403 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 404 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 405 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 406 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 407 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 408 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 409 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 410 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 411 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 412 MPP_MODE(2, 413 MPP_FUNCTION(0x00, "gpio", NULL), 414 MPP_FUNCTION(0x01, "sata", "prsnt"), 415 MPP_FUNCTION(0x02, "uart2", "txd"), 416 MPP_FUNCTION(0x03, "sdio0", "buspwr"), 417 MPP_FUNCTION(0x04, "uart1", "rts"), 418 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 419 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 420 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 421 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 422 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 423 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 424 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 425 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 426 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 427 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 428 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 429 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 430 MPP_MODE(3, 431 MPP_FUNCTION(0x00, "gpio", NULL), 432 MPP_FUNCTION(0x01, "sata", "act"), 433 MPP_FUNCTION(0x02, "uart2", "rxd"), 434 MPP_FUNCTION(0x03, "sdio0", "ledctrl"), 435 MPP_FUNCTION(0x04, "uart1", "cts"), 436 MPP_FUNCTION(0x0f, "lcd-spi", "cs1"), 437 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 438 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 439 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 440 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 441 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 442 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 443 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 444 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 445 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 446 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 447 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 448 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 449 MPP_MODE(4, 450 MPP_FUNCTION(0x00, "gpio", NULL), 451 MPP_FUNCTION(0x02, "uart3", "rts"), 452 MPP_FUNCTION(0x03, "sdio1", "cd"), 453 MPP_FUNCTION(0x04, "spi1", "miso"), 454 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 455 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 456 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 457 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 458 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 459 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 460 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 461 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 462 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 463 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 464 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 465 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 466 MPP_MODE(5, 467 MPP_FUNCTION(0x00, "gpio", NULL), 468 MPP_FUNCTION(0x02, "uart3", "cts"), 469 MPP_FUNCTION(0x03, "sdio1", "wp"), 470 MPP_FUNCTION(0x04, "spi1", "cs"), 471 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 472 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 473 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 474 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 475 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 476 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 477 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 478 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 479 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 480 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 481 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 482 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 483 MPP_MODE(6, 484 MPP_FUNCTION(0x00, "gpio", NULL), 485 MPP_FUNCTION(0x02, "uart3", "txd"), 486 MPP_FUNCTION(0x03, "sdio1", "buspwr"), 487 MPP_FUNCTION(0x04, "spi1", "mosi"), 488 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 489 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 490 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 491 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 492 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 493 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 494 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 495 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 496 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 497 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 498 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 499 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 500 MPP_MODE(7, 501 MPP_FUNCTION(0x00, "gpio", NULL), 502 MPP_FUNCTION(0x02, "uart3", "rxd"), 503 MPP_FUNCTION(0x03, "sdio1", "ledctrl"), 504 MPP_FUNCTION(0x04, "spi1", "sck"), 505 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 506 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 507 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 508 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 509 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 510 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 511 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 512 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 513 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 514 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 515 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 516 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 517 MPP_MODE(8, 518 MPP_FUNCTION(0x00, "gpio", NULL), 519 MPP_FUNCTION(0x01, "watchdog", "rstout"), 520 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 521 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 522 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 523 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 524 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 525 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 526 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 527 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 528 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 529 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 530 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 531 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 532 MPP_MODE(9, 533 MPP_FUNCTION(0x00, "gpio", NULL), 534 MPP_FUNCTION(0x05, "pex1", "clkreq"), 535 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 536 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 537 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 538 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 539 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 540 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 541 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 542 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 543 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 544 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 545 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 546 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 547 MPP_MODE(10, 548 MPP_FUNCTION(0x00, "gpio", NULL), 549 MPP_FUNCTION(0x05, "ssp", "sclk"), 550 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 551 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 552 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 553 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 554 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 555 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 556 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 557 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 558 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 559 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 560 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 561 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 562 MPP_MODE(11, 563 MPP_FUNCTION(0x00, "gpio", NULL), 564 MPP_FUNCTION(0x01, "sata", "prsnt"), 565 MPP_FUNCTION(0x02, "sata-1", "act"), 566 MPP_FUNCTION(0x03, "sdio0", "ledctrl"), 567 MPP_FUNCTION(0x04, "sdio1", "ledctrl"), 568 MPP_FUNCTION(0x05, "pex0", "clkreq"), 569 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 570 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 571 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 572 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 573 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 574 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 575 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 576 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 577 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 578 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 579 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 580 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 581 MPP_MODE(12, 582 MPP_FUNCTION(0x00, "gpio", NULL), 583 MPP_FUNCTION(0x01, "sata", "act"), 584 MPP_FUNCTION(0x02, "uart2", "rts"), 585 MPP_FUNCTION(0x03, "audio0", "extclk"), 586 MPP_FUNCTION(0x04, "sdio1", "cd"), 587 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 588 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 589 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 590 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 591 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 592 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 593 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 594 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 595 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 596 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 597 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 598 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 599 MPP_MODE(13, 600 MPP_FUNCTION(0x00, "gpio", NULL), 601 MPP_FUNCTION(0x02, "uart2", "cts"), 602 MPP_FUNCTION(0x03, "audio1", "extclk"), 603 MPP_FUNCTION(0x04, "sdio1", "wp"), 604 MPP_FUNCTION(0x05, "ssp", "extclk"), 605 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 606 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 607 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 608 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 609 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 610 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 611 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 612 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 613 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 614 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 615 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 616 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 617 MPP_MODE(14, 618 MPP_FUNCTION(0x00, "gpio", NULL), 619 MPP_FUNCTION(0x02, "uart2", "txd"), 620 MPP_FUNCTION(0x04, "sdio1", "buspwr"), 621 MPP_FUNCTION(0x05, "ssp", "rxd"), 622 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 623 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 624 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 625 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 626 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 627 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 628 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 629 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 630 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 631 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 632 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 633 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 634 MPP_MODE(15, 635 MPP_FUNCTION(0x00, "gpio", NULL), 636 MPP_FUNCTION(0x02, "uart2", "rxd"), 637 MPP_FUNCTION(0x04, "sdio1", "ledctrl"), 638 MPP_FUNCTION(0x05, "ssp", "sfrm"), 639 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 640 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 641 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 642 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 643 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 644 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 645 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 646 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 647 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 648 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 649 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 650 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 651 MPP_MODE(16, 652 MPP_FUNCTION(0x00, "gpio", NULL), 653 MPP_FUNCTION(0x02, "uart3", "rts"), 654 MPP_FUNCTION(0x03, "sdio0", "cd"), 655 MPP_FUNCTION(0x04, "lcd-spi", "cs1"), 656 MPP_FUNCTION(0x05, "ac97", "sdi1")), 657 MPP_MODE(17, 658 MPP_FUNCTION(0x00, "gpio", NULL), 659 MPP_FUNCTION(0x01, "ac97-1", "sysclko"), 660 MPP_FUNCTION(0x02, "uart3", "cts"), 661 MPP_FUNCTION(0x03, "sdio0", "wp"), 662 MPP_FUNCTION(0x04, "twsi", "sda"), 663 MPP_FUNCTION(0x05, "ac97", "sdi2")), 664 MPP_MODE(18, 665 MPP_FUNCTION(0x00, "gpio", NULL), 666 MPP_FUNCTION(0x02, "uart3", "txd"), 667 MPP_FUNCTION(0x03, "sdio0", "buspwr"), 668 MPP_FUNCTION(0x04, "lcd0", "pwm"), 669 MPP_FUNCTION(0x05, "ac97", "sdi3")), 670 MPP_MODE(19, 671 MPP_FUNCTION(0x00, "gpio", NULL), 672 MPP_FUNCTION(0x02, "uart3", "rxd"), 673 MPP_FUNCTION(0x03, "sdio0", "ledctrl"), 674 MPP_FUNCTION(0x04, "twsi", "sck")), 675 MPP_MODE(20, 676 MPP_FUNCTION(0x00, "gpio", NULL), 677 MPP_FUNCTION(0x01, "ac97", "sysclko"), 678 MPP_FUNCTION(0x02, "lcd-spi", "miso"), 679 MPP_FUNCTION(0x03, "sdio1", "cd"), 680 MPP_FUNCTION(0x05, "sdio0", "cd"), 681 MPP_FUNCTION(0x06, "spi1", "miso")), 682 MPP_MODE(21, 683 MPP_FUNCTION(0x00, "gpio", NULL), 684 MPP_FUNCTION(0x01, "uart1", "rts"), 685 MPP_FUNCTION(0x02, "lcd-spi", "cs0"), 686 MPP_FUNCTION(0x03, "sdio1", "wp"), 687 MPP_FUNCTION(0x04, "ssp", "sfrm"), 688 MPP_FUNCTION(0x05, "sdio0", "wp"), 689 MPP_FUNCTION(0x06, "spi1", "cs")), 690 MPP_MODE(22, 691 MPP_FUNCTION(0x00, "gpio", NULL), 692 MPP_FUNCTION(0x01, "uart1", "cts"), 693 MPP_FUNCTION(0x02, "lcd-spi", "mosi"), 694 MPP_FUNCTION(0x03, "sdio1", "buspwr"), 695 MPP_FUNCTION(0x04, "ssp", "txd"), 696 MPP_FUNCTION(0x05, "sdio0", "buspwr"), 697 MPP_FUNCTION(0x06, "spi1", "mosi")), 698 MPP_MODE(23, 699 MPP_FUNCTION(0x00, "gpio", NULL), 700 MPP_FUNCTION(0x02, "lcd-spi", "sck"), 701 MPP_FUNCTION(0x03, "sdio1", "ledctrl"), 702 MPP_FUNCTION(0x04, "ssp", "sclk"), 703 MPP_FUNCTION(0x05, "sdio0", "ledctrl"), 704 MPP_FUNCTION(0x06, "spi1", "sck")), 705 MPP_MODE(24, 706 MPP_FUNCTION(0x00, "camera", NULL), 707 MPP_FUNCTION(0x01, "gpio", NULL)), 708 MPP_MODE(40, 709 MPP_FUNCTION(0x00, "sdio0", NULL), 710 MPP_FUNCTION(0x01, "gpio", NULL)), 711 MPP_MODE(46, 712 MPP_FUNCTION(0x00, "sdio1", NULL), 713 MPP_FUNCTION(0x01, "gpio", NULL)), 714 MPP_MODE(52, 715 MPP_FUNCTION(0x00, "i2s1/spdifo", NULL), 716 MPP_FUNCTION(0x02, "i2s1", NULL), 717 MPP_FUNCTION(0x08, "spdifo", NULL), 718 MPP_FUNCTION(0x0a, "gpio", NULL), 719 MPP_FUNCTION(0x0b, "twsi", NULL), 720 MPP_FUNCTION(0x0c, "ssp/spdifo", NULL), 721 MPP_FUNCTION(0x0e, "ssp", NULL), 722 MPP_FUNCTION(0x0f, "ssp/twsi", NULL)), 723 MPP_MODE(58, 724 MPP_FUNCTION(0x00, "spi0", NULL), 725 MPP_FUNCTION(0x01, "gpio", NULL)), 726 MPP_MODE(62, 727 MPP_FUNCTION(0x00, "uart1", NULL), 728 MPP_FUNCTION(0x01, "gpio", NULL)), 729 MPP_MODE(64, 730 MPP_FUNCTION(0x00, "nand", NULL), 731 MPP_FUNCTION(0x01, "gpo", NULL)), 732 MPP_MODE(72, 733 MPP_FUNCTION(0x00, "i2s", NULL), 734 MPP_FUNCTION(0x01, "ac97", NULL)), 735 MPP_MODE(73, 736 MPP_FUNCTION(0x00, "twsi-none", NULL), 737 MPP_FUNCTION(0x01, "twsi-opt1", NULL), 738 MPP_FUNCTION(0x02, "twsi-opt2", NULL), 739 MPP_FUNCTION(0x03, "twsi-opt3", NULL)), 740 }; 741 742 static struct pinctrl_gpio_range dove_mpp_gpio_ranges[] = { 743 MPP_GPIO_RANGE(0, 0, 0, 32), 744 MPP_GPIO_RANGE(1, 32, 32, 32), 745 MPP_GPIO_RANGE(2, 64, 64, 8), 746 }; 747 748 static struct mvebu_pinctrl_soc_info dove_pinctrl_info = { 749 .controls = dove_mpp_controls, 750 .ncontrols = ARRAY_SIZE(dove_mpp_controls), 751 .modes = dove_mpp_modes, 752 .nmodes = ARRAY_SIZE(dove_mpp_modes), 753 .gpioranges = dove_mpp_gpio_ranges, 754 .ngpioranges = ARRAY_SIZE(dove_mpp_gpio_ranges), 755 .variant = 0, 756 }; 757 758 static struct clk *clk; 759 760 static struct of_device_id dove_pinctrl_of_match[] = { 761 { .compatible = "marvell,dove-pinctrl", .data = &dove_pinctrl_info }, 762 { } 763 }; 764 765 static struct regmap_config gc_regmap_config = { 766 .reg_bits = 32, 767 .val_bits = 32, 768 .reg_stride = 4, 769 .max_register = 5, 770 }; 771 772 static int dove_pinctrl_probe(struct platform_device *pdev) 773 { 774 struct resource *res, *mpp_res; 775 struct resource fb_res; 776 const struct of_device_id *match = 777 of_match_device(dove_pinctrl_of_match, &pdev->dev); 778 pdev->dev.platform_data = (void *)match->data; 779 780 /* 781 * General MPP Configuration Register is part of pdma registers. 782 * grab clk to make sure it is ticking. 783 */ 784 clk = devm_clk_get(&pdev->dev, NULL); 785 if (IS_ERR(clk)) { 786 dev_err(&pdev->dev, "Unable to get pdma clock"); 787 return PTR_ERR(clk); 788 } 789 clk_prepare_enable(clk); 790 791 mpp_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 792 mpp_base = devm_ioremap_resource(&pdev->dev, mpp_res); 793 if (IS_ERR(mpp_base)) 794 return PTR_ERR(mpp_base); 795 796 /* prepare fallback resource */ 797 memcpy(&fb_res, mpp_res, sizeof(struct resource)); 798 fb_res.start = 0; 799 800 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 801 if (!res) { 802 dev_warn(&pdev->dev, "falling back to hardcoded MPP4 resource\n"); 803 adjust_resource(&fb_res, 804 (mpp_res->start & INT_REGS_MASK) + MPP4_REGS_OFFS, 0x4); 805 res = &fb_res; 806 } 807 808 mpp4_base = devm_ioremap_resource(&pdev->dev, res); 809 if (IS_ERR(mpp4_base)) 810 return PTR_ERR(mpp4_base); 811 812 res = platform_get_resource(pdev, IORESOURCE_MEM, 2); 813 if (!res) { 814 dev_warn(&pdev->dev, "falling back to hardcoded PMU resource\n"); 815 adjust_resource(&fb_res, 816 (mpp_res->start & INT_REGS_MASK) + PMU_REGS_OFFS, 0x8); 817 res = &fb_res; 818 } 819 820 pmu_base = devm_ioremap_resource(&pdev->dev, res); 821 if (IS_ERR(pmu_base)) 822 return PTR_ERR(pmu_base); 823 824 gconfmap = syscon_regmap_lookup_by_compatible("marvell,dove-global-config"); 825 if (IS_ERR(gconfmap)) { 826 void __iomem *gc_base; 827 828 dev_warn(&pdev->dev, "falling back to hardcoded global registers\n"); 829 adjust_resource(&fb_res, 830 (mpp_res->start & INT_REGS_MASK) + GC_REGS_OFFS, 0x14); 831 gc_base = devm_ioremap_resource(&pdev->dev, &fb_res); 832 if (IS_ERR(gc_base)) 833 return PTR_ERR(gc_base); 834 gconfmap = devm_regmap_init_mmio(&pdev->dev, 835 gc_base, &gc_regmap_config); 836 if (IS_ERR(gconfmap)) 837 return PTR_ERR(gconfmap); 838 } 839 840 /* Warn on any missing DT resource */ 841 WARN(fb_res.start, FW_BUG "Missing pinctrl regs in DTB. Please update your firmware.\n"); 842 843 return mvebu_pinctrl_probe(pdev); 844 } 845 846 static int dove_pinctrl_remove(struct platform_device *pdev) 847 { 848 int ret; 849 850 ret = mvebu_pinctrl_remove(pdev); 851 if (!IS_ERR(clk)) 852 clk_disable_unprepare(clk); 853 return ret; 854 } 855 856 static struct platform_driver dove_pinctrl_driver = { 857 .driver = { 858 .name = "dove-pinctrl", 859 .owner = THIS_MODULE, 860 .of_match_table = dove_pinctrl_of_match, 861 }, 862 .probe = dove_pinctrl_probe, 863 .remove = dove_pinctrl_remove, 864 }; 865 866 module_platform_driver(dove_pinctrl_driver); 867 868 MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>"); 869 MODULE_DESCRIPTION("Marvell Dove pinctrl driver"); 870 MODULE_LICENSE("GPL v2"); 871