1 /* 2 * Marvell Dove pinctrl driver based on mvebu pinctrl core 3 * 4 * Author: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #include <linux/err.h> 13 #include <linux/init.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/bitops.h> 17 #include <linux/platform_device.h> 18 #include <linux/clk.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/mfd/syscon.h> 22 #include <linux/pinctrl/pinctrl.h> 23 #include <linux/regmap.h> 24 25 #include "pinctrl-mvebu.h" 26 27 /* Internal registers can be configured at any 1 MiB aligned address */ 28 #define INT_REGS_MASK ~(SZ_1M - 1) 29 #define MPP4_REGS_OFFS 0xd0440 30 #define PMU_REGS_OFFS 0xd802c 31 #define GC_REGS_OFFS 0xe802c 32 33 /* MPP Base registers */ 34 #define PMU_MPP_GENERAL_CTRL 0x10 35 #define AU0_AC97_SEL BIT(16) 36 37 /* MPP Control 4 register */ 38 #define SPI_GPIO_SEL BIT(5) 39 #define UART1_GPIO_SEL BIT(4) 40 #define AU1_GPIO_SEL BIT(3) 41 #define CAM_GPIO_SEL BIT(2) 42 #define SD1_GPIO_SEL BIT(1) 43 #define SD0_GPIO_SEL BIT(0) 44 45 /* PMU Signal Select registers */ 46 #define PMU_SIGNAL_SELECT_0 0x00 47 #define PMU_SIGNAL_SELECT_1 0x04 48 49 /* Global Config regmap registers */ 50 #define GLOBAL_CONFIG_1 0x00 51 #define TWSI_ENABLE_OPTION1 BIT(7) 52 #define GLOBAL_CONFIG_2 0x04 53 #define TWSI_ENABLE_OPTION2 BIT(20) 54 #define TWSI_ENABLE_OPTION3 BIT(21) 55 #define TWSI_OPTION3_GPIO BIT(22) 56 #define SSP_CTRL_STATUS_1 0x08 57 #define SSP_ON_AU1 BIT(0) 58 #define MPP_GENERAL_CONFIG 0x10 59 #define AU1_SPDIFO_GPIO_EN BIT(1) 60 #define NAND_GPIO_EN BIT(0) 61 62 #define CONFIG_PMU BIT(4) 63 64 static void __iomem *mpp_base; 65 static void __iomem *mpp4_base; 66 static void __iomem *pmu_base; 67 static struct regmap *gconfmap; 68 69 static int dove_mpp_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid, 70 unsigned long *config) 71 { 72 return default_mpp_ctrl_get(mpp_base, pid, config); 73 } 74 75 static int dove_mpp_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid, 76 unsigned long config) 77 { 78 return default_mpp_ctrl_set(mpp_base, pid, config); 79 } 80 81 static int dove_pmu_mpp_ctrl_get(struct mvebu_mpp_ctrl_data *data, 82 unsigned pid, unsigned long *config) 83 { 84 unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; 85 unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; 86 unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL); 87 unsigned long func; 88 89 if ((pmu & BIT(pid)) == 0) 90 return default_mpp_ctrl_get(mpp_base, pid, config); 91 92 func = readl(pmu_base + PMU_SIGNAL_SELECT_0 + off); 93 *config = (func >> shift) & MVEBU_MPP_MASK; 94 *config |= CONFIG_PMU; 95 96 return 0; 97 } 98 99 static int dove_pmu_mpp_ctrl_set(struct mvebu_mpp_ctrl_data *data, 100 unsigned pid, unsigned long config) 101 { 102 unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; 103 unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; 104 unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL); 105 unsigned long func; 106 107 if ((config & CONFIG_PMU) == 0) { 108 writel(pmu & ~BIT(pid), mpp_base + PMU_MPP_GENERAL_CTRL); 109 return default_mpp_ctrl_set(mpp_base, pid, config); 110 } 111 112 writel(pmu | BIT(pid), mpp_base + PMU_MPP_GENERAL_CTRL); 113 func = readl(pmu_base + PMU_SIGNAL_SELECT_0 + off); 114 func &= ~(MVEBU_MPP_MASK << shift); 115 func |= (config & MVEBU_MPP_MASK) << shift; 116 writel(func, pmu_base + PMU_SIGNAL_SELECT_0 + off); 117 118 return 0; 119 } 120 121 static int dove_mpp4_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid, 122 unsigned long *config) 123 { 124 unsigned long mpp4 = readl(mpp4_base); 125 unsigned long mask; 126 127 switch (pid) { 128 case 24: /* mpp_camera */ 129 mask = CAM_GPIO_SEL; 130 break; 131 case 40: /* mpp_sdio0 */ 132 mask = SD0_GPIO_SEL; 133 break; 134 case 46: /* mpp_sdio1 */ 135 mask = SD1_GPIO_SEL; 136 break; 137 case 58: /* mpp_spi0 */ 138 mask = SPI_GPIO_SEL; 139 break; 140 case 62: /* mpp_uart1 */ 141 mask = UART1_GPIO_SEL; 142 break; 143 default: 144 return -EINVAL; 145 } 146 147 *config = ((mpp4 & mask) != 0); 148 149 return 0; 150 } 151 152 static int dove_mpp4_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid, 153 unsigned long config) 154 { 155 unsigned long mpp4 = readl(mpp4_base); 156 unsigned long mask; 157 158 switch (pid) { 159 case 24: /* mpp_camera */ 160 mask = CAM_GPIO_SEL; 161 break; 162 case 40: /* mpp_sdio0 */ 163 mask = SD0_GPIO_SEL; 164 break; 165 case 46: /* mpp_sdio1 */ 166 mask = SD1_GPIO_SEL; 167 break; 168 case 58: /* mpp_spi0 */ 169 mask = SPI_GPIO_SEL; 170 break; 171 case 62: /* mpp_uart1 */ 172 mask = UART1_GPIO_SEL; 173 break; 174 default: 175 return -EINVAL; 176 } 177 178 mpp4 &= ~mask; 179 if (config) 180 mpp4 |= mask; 181 182 writel(mpp4, mpp4_base); 183 184 return 0; 185 } 186 187 static int dove_nand_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid, 188 unsigned long *config) 189 { 190 unsigned int gmpp; 191 192 regmap_read(gconfmap, MPP_GENERAL_CONFIG, &gmpp); 193 *config = ((gmpp & NAND_GPIO_EN) != 0); 194 195 return 0; 196 } 197 198 static int dove_nand_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid, 199 unsigned long config) 200 { 201 regmap_update_bits(gconfmap, MPP_GENERAL_CONFIG, 202 NAND_GPIO_EN, 203 (config) ? NAND_GPIO_EN : 0); 204 return 0; 205 } 206 207 static int dove_audio0_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid, 208 unsigned long *config) 209 { 210 unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL); 211 212 *config = ((pmu & AU0_AC97_SEL) != 0); 213 214 return 0; 215 } 216 217 static int dove_audio0_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid, 218 unsigned long config) 219 { 220 unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL); 221 222 pmu &= ~AU0_AC97_SEL; 223 if (config) 224 pmu |= AU0_AC97_SEL; 225 writel(pmu, mpp_base + PMU_MPP_GENERAL_CTRL); 226 227 return 0; 228 } 229 230 static int dove_audio1_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid, 231 unsigned long *config) 232 { 233 unsigned int mpp4 = readl(mpp4_base); 234 unsigned int sspc1; 235 unsigned int gmpp; 236 unsigned int gcfg2; 237 238 regmap_read(gconfmap, SSP_CTRL_STATUS_1, &sspc1); 239 regmap_read(gconfmap, MPP_GENERAL_CONFIG, &gmpp); 240 regmap_read(gconfmap, GLOBAL_CONFIG_2, &gcfg2); 241 242 *config = 0; 243 if (mpp4 & AU1_GPIO_SEL) 244 *config |= BIT(3); 245 if (sspc1 & SSP_ON_AU1) 246 *config |= BIT(2); 247 if (gmpp & AU1_SPDIFO_GPIO_EN) 248 *config |= BIT(1); 249 if (gcfg2 & TWSI_OPTION3_GPIO) 250 *config |= BIT(0); 251 252 /* SSP/TWSI only if I2S1 not set*/ 253 if ((*config & BIT(3)) == 0) 254 *config &= ~(BIT(2) | BIT(0)); 255 /* TWSI only if SPDIFO not set*/ 256 if ((*config & BIT(1)) == 0) 257 *config &= ~BIT(0); 258 return 0; 259 } 260 261 static int dove_audio1_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid, 262 unsigned long config) 263 { 264 unsigned int mpp4 = readl(mpp4_base); 265 266 mpp4 &= ~AU1_GPIO_SEL; 267 if (config & BIT(3)) 268 mpp4 |= AU1_GPIO_SEL; 269 writel(mpp4, mpp4_base); 270 271 regmap_update_bits(gconfmap, SSP_CTRL_STATUS_1, 272 SSP_ON_AU1, 273 (config & BIT(2)) ? SSP_ON_AU1 : 0); 274 regmap_update_bits(gconfmap, MPP_GENERAL_CONFIG, 275 AU1_SPDIFO_GPIO_EN, 276 (config & BIT(1)) ? AU1_SPDIFO_GPIO_EN : 0); 277 regmap_update_bits(gconfmap, GLOBAL_CONFIG_2, 278 TWSI_OPTION3_GPIO, 279 (config & BIT(0)) ? TWSI_OPTION3_GPIO : 0); 280 281 return 0; 282 } 283 284 /* mpp[52:57] gpio pins depend heavily on current config; 285 * gpio_req does not try to mux in gpio capabilities to not 286 * break other functions. If you require all mpps as gpio 287 * enforce gpio setting by pinctrl mapping. 288 */ 289 static int dove_audio1_ctrl_gpio_req(struct mvebu_mpp_ctrl_data *data, 290 unsigned pid) 291 { 292 unsigned long config; 293 294 dove_audio1_ctrl_get(data, pid, &config); 295 296 switch (config) { 297 case 0x02: /* i2s1 : gpio[56:57] */ 298 case 0x0e: /* ssp : gpio[56:57] */ 299 if (pid >= 56) 300 return 0; 301 return -ENOTSUPP; 302 case 0x08: /* spdifo : gpio[52:55] */ 303 case 0x0b: /* twsi : gpio[52:55] */ 304 if (pid <= 55) 305 return 0; 306 return -ENOTSUPP; 307 case 0x0a: /* all gpio */ 308 return 0; 309 /* 0x00 : i2s1/spdifo : no gpio */ 310 /* 0x0c : ssp/spdifo : no gpio */ 311 /* 0x0f : ssp/twsi : no gpio */ 312 } 313 return -ENOTSUPP; 314 } 315 316 /* mpp[52:57] has gpio pins capable of in and out */ 317 static int dove_audio1_ctrl_gpio_dir(struct mvebu_mpp_ctrl_data *data, 318 unsigned pid, bool input) 319 { 320 if (pid < 52 || pid > 57) 321 return -ENOTSUPP; 322 return 0; 323 } 324 325 static int dove_twsi_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid, 326 unsigned long *config) 327 { 328 unsigned int gcfg1; 329 unsigned int gcfg2; 330 331 regmap_read(gconfmap, GLOBAL_CONFIG_1, &gcfg1); 332 regmap_read(gconfmap, GLOBAL_CONFIG_2, &gcfg2); 333 334 *config = 0; 335 if (gcfg1 & TWSI_ENABLE_OPTION1) 336 *config = 1; 337 else if (gcfg2 & TWSI_ENABLE_OPTION2) 338 *config = 2; 339 else if (gcfg2 & TWSI_ENABLE_OPTION3) 340 *config = 3; 341 342 return 0; 343 } 344 345 static int dove_twsi_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid, 346 unsigned long config) 347 { 348 unsigned int gcfg1 = 0; 349 unsigned int gcfg2 = 0; 350 351 switch (config) { 352 case 1: 353 gcfg1 = TWSI_ENABLE_OPTION1; 354 break; 355 case 2: 356 gcfg2 = TWSI_ENABLE_OPTION2; 357 break; 358 case 3: 359 gcfg2 = TWSI_ENABLE_OPTION3; 360 break; 361 } 362 363 regmap_update_bits(gconfmap, GLOBAL_CONFIG_1, 364 TWSI_ENABLE_OPTION1, 365 gcfg1); 366 regmap_update_bits(gconfmap, GLOBAL_CONFIG_2, 367 TWSI_ENABLE_OPTION2 | TWSI_ENABLE_OPTION3, 368 gcfg2); 369 370 return 0; 371 } 372 373 static const struct mvebu_mpp_ctrl dove_mpp_controls[] = { 374 MPP_FUNC_CTRL(0, 15, NULL, dove_pmu_mpp_ctrl), 375 MPP_FUNC_CTRL(16, 23, NULL, dove_mpp_ctrl), 376 MPP_FUNC_CTRL(24, 39, "mpp_camera", dove_mpp4_ctrl), 377 MPP_FUNC_CTRL(40, 45, "mpp_sdio0", dove_mpp4_ctrl), 378 MPP_FUNC_CTRL(46, 51, "mpp_sdio1", dove_mpp4_ctrl), 379 MPP_FUNC_GPIO_CTRL(52, 57, "mpp_audio1", dove_audio1_ctrl), 380 MPP_FUNC_CTRL(58, 61, "mpp_spi0", dove_mpp4_ctrl), 381 MPP_FUNC_CTRL(62, 63, "mpp_uart1", dove_mpp4_ctrl), 382 MPP_FUNC_CTRL(64, 71, "mpp_nand", dove_nand_ctrl), 383 MPP_FUNC_CTRL(72, 72, "audio0", dove_audio0_ctrl), 384 MPP_FUNC_CTRL(73, 73, "twsi", dove_twsi_ctrl), 385 }; 386 387 static struct mvebu_mpp_mode dove_mpp_modes[] = { 388 MPP_MODE(0, 389 MPP_FUNCTION(0x00, "gpio", NULL), 390 MPP_FUNCTION(0x02, "uart2", "rts"), 391 MPP_FUNCTION(0x03, "sdio0", "cd"), 392 MPP_FUNCTION(0x0f, "lcd0", "pwm"), 393 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 394 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 395 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 396 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 397 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 398 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 399 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 400 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 401 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 402 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 403 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 404 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 405 MPP_MODE(1, 406 MPP_FUNCTION(0x00, "gpio", NULL), 407 MPP_FUNCTION(0x02, "uart2", "cts"), 408 MPP_FUNCTION(0x03, "sdio0", "wp"), 409 MPP_FUNCTION(0x0f, "lcd1", "pwm"), 410 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 411 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 412 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 413 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 414 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 415 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 416 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 417 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 418 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 419 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 420 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 421 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 422 MPP_MODE(2, 423 MPP_FUNCTION(0x00, "gpio", NULL), 424 MPP_FUNCTION(0x01, "sata", "prsnt"), 425 MPP_FUNCTION(0x02, "uart2", "txd"), 426 MPP_FUNCTION(0x03, "sdio0", "buspwr"), 427 MPP_FUNCTION(0x04, "uart1", "rts"), 428 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 429 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 430 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 431 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 432 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 433 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 434 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 435 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 436 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 437 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 438 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 439 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 440 MPP_MODE(3, 441 MPP_FUNCTION(0x00, "gpio", NULL), 442 MPP_FUNCTION(0x01, "sata", "act"), 443 MPP_FUNCTION(0x02, "uart2", "rxd"), 444 MPP_FUNCTION(0x03, "sdio0", "ledctrl"), 445 MPP_FUNCTION(0x04, "uart1", "cts"), 446 MPP_FUNCTION(0x0f, "lcd-spi", "cs1"), 447 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 448 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 449 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 450 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 451 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 452 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 453 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 454 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 455 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 456 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 457 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 458 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 459 MPP_MODE(4, 460 MPP_FUNCTION(0x00, "gpio", NULL), 461 MPP_FUNCTION(0x02, "uart3", "rts"), 462 MPP_FUNCTION(0x03, "sdio1", "cd"), 463 MPP_FUNCTION(0x04, "spi1", "miso"), 464 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 465 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 466 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 467 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 468 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 469 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 470 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 471 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 472 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 473 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 474 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 475 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 476 MPP_MODE(5, 477 MPP_FUNCTION(0x00, "gpio", NULL), 478 MPP_FUNCTION(0x02, "uart3", "cts"), 479 MPP_FUNCTION(0x03, "sdio1", "wp"), 480 MPP_FUNCTION(0x04, "spi1", "cs"), 481 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 482 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 483 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 484 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 485 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 486 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 487 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 488 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 489 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 490 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 491 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 492 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 493 MPP_MODE(6, 494 MPP_FUNCTION(0x00, "gpio", NULL), 495 MPP_FUNCTION(0x02, "uart3", "txd"), 496 MPP_FUNCTION(0x03, "sdio1", "buspwr"), 497 MPP_FUNCTION(0x04, "spi1", "mosi"), 498 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 499 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 500 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 501 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 502 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 503 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 504 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 505 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 506 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 507 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 508 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 509 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 510 MPP_MODE(7, 511 MPP_FUNCTION(0x00, "gpio", NULL), 512 MPP_FUNCTION(0x02, "uart3", "rxd"), 513 MPP_FUNCTION(0x03, "sdio1", "ledctrl"), 514 MPP_FUNCTION(0x04, "spi1", "sck"), 515 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 516 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 517 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 518 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 519 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 520 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 521 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 522 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 523 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 524 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 525 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 526 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 527 MPP_MODE(8, 528 MPP_FUNCTION(0x00, "gpio", NULL), 529 MPP_FUNCTION(0x01, "watchdog", "rstout"), 530 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 531 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 532 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 533 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 534 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 535 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 536 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 537 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 538 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 539 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 540 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 541 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 542 MPP_MODE(9, 543 MPP_FUNCTION(0x00, "gpio", NULL), 544 MPP_FUNCTION(0x05, "pex1", "clkreq"), 545 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 546 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 547 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 548 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 549 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 550 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 551 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 552 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 553 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 554 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 555 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 556 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 557 MPP_MODE(10, 558 MPP_FUNCTION(0x00, "gpio", NULL), 559 MPP_FUNCTION(0x05, "ssp", "sclk"), 560 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 561 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 562 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 563 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 564 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 565 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 566 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 567 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 568 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 569 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 570 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 571 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 572 MPP_MODE(11, 573 MPP_FUNCTION(0x00, "gpio", NULL), 574 MPP_FUNCTION(0x01, "sata", "prsnt"), 575 MPP_FUNCTION(0x02, "sata-1", "act"), 576 MPP_FUNCTION(0x03, "sdio0", "ledctrl"), 577 MPP_FUNCTION(0x04, "sdio1", "ledctrl"), 578 MPP_FUNCTION(0x05, "pex0", "clkreq"), 579 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 580 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 581 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 582 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 583 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 584 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 585 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 586 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 587 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 588 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 589 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 590 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 591 MPP_MODE(12, 592 MPP_FUNCTION(0x00, "gpio", NULL), 593 MPP_FUNCTION(0x01, "sata", "act"), 594 MPP_FUNCTION(0x02, "uart2", "rts"), 595 MPP_FUNCTION(0x03, "audio0", "extclk"), 596 MPP_FUNCTION(0x04, "sdio1", "cd"), 597 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 598 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 599 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 600 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 601 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 602 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 603 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 604 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 605 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 606 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 607 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 608 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 609 MPP_MODE(13, 610 MPP_FUNCTION(0x00, "gpio", NULL), 611 MPP_FUNCTION(0x02, "uart2", "cts"), 612 MPP_FUNCTION(0x03, "audio1", "extclk"), 613 MPP_FUNCTION(0x04, "sdio1", "wp"), 614 MPP_FUNCTION(0x05, "ssp", "extclk"), 615 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 616 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 617 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 618 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 619 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 620 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 621 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 622 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 623 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 624 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 625 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 626 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 627 MPP_MODE(14, 628 MPP_FUNCTION(0x00, "gpio", NULL), 629 MPP_FUNCTION(0x02, "uart2", "txd"), 630 MPP_FUNCTION(0x04, "sdio1", "buspwr"), 631 MPP_FUNCTION(0x05, "ssp", "rxd"), 632 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 633 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 634 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 635 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 636 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 637 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 638 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 639 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 640 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 641 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 642 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 643 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 644 MPP_MODE(15, 645 MPP_FUNCTION(0x00, "gpio", NULL), 646 MPP_FUNCTION(0x02, "uart2", "rxd"), 647 MPP_FUNCTION(0x04, "sdio1", "ledctrl"), 648 MPP_FUNCTION(0x05, "ssp", "sfrm"), 649 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 650 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 651 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 652 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 653 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 654 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 655 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 656 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 657 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 658 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 659 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 660 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 661 MPP_MODE(16, 662 MPP_FUNCTION(0x00, "gpio", NULL), 663 MPP_FUNCTION(0x02, "uart3", "rts"), 664 MPP_FUNCTION(0x03, "sdio0", "cd"), 665 MPP_FUNCTION(0x04, "lcd-spi", "cs1"), 666 MPP_FUNCTION(0x05, "ac97", "sdi1")), 667 MPP_MODE(17, 668 MPP_FUNCTION(0x00, "gpio", NULL), 669 MPP_FUNCTION(0x01, "ac97-1", "sysclko"), 670 MPP_FUNCTION(0x02, "uart3", "cts"), 671 MPP_FUNCTION(0x03, "sdio0", "wp"), 672 MPP_FUNCTION(0x04, "twsi", "sda"), 673 MPP_FUNCTION(0x05, "ac97", "sdi2")), 674 MPP_MODE(18, 675 MPP_FUNCTION(0x00, "gpio", NULL), 676 MPP_FUNCTION(0x02, "uart3", "txd"), 677 MPP_FUNCTION(0x03, "sdio0", "buspwr"), 678 MPP_FUNCTION(0x04, "lcd0", "pwm"), 679 MPP_FUNCTION(0x05, "ac97", "sdi3")), 680 MPP_MODE(19, 681 MPP_FUNCTION(0x00, "gpio", NULL), 682 MPP_FUNCTION(0x02, "uart3", "rxd"), 683 MPP_FUNCTION(0x03, "sdio0", "ledctrl"), 684 MPP_FUNCTION(0x04, "twsi", "sck")), 685 MPP_MODE(20, 686 MPP_FUNCTION(0x00, "gpio", NULL), 687 MPP_FUNCTION(0x01, "ac97", "sysclko"), 688 MPP_FUNCTION(0x02, "lcd-spi", "miso"), 689 MPP_FUNCTION(0x03, "sdio1", "cd"), 690 MPP_FUNCTION(0x05, "sdio0", "cd"), 691 MPP_FUNCTION(0x06, "spi1", "miso")), 692 MPP_MODE(21, 693 MPP_FUNCTION(0x00, "gpio", NULL), 694 MPP_FUNCTION(0x01, "uart1", "rts"), 695 MPP_FUNCTION(0x02, "lcd-spi", "cs0"), 696 MPP_FUNCTION(0x03, "sdio1", "wp"), 697 MPP_FUNCTION(0x04, "ssp", "sfrm"), 698 MPP_FUNCTION(0x05, "sdio0", "wp"), 699 MPP_FUNCTION(0x06, "spi1", "cs")), 700 MPP_MODE(22, 701 MPP_FUNCTION(0x00, "gpio", NULL), 702 MPP_FUNCTION(0x01, "uart1", "cts"), 703 MPP_FUNCTION(0x02, "lcd-spi", "mosi"), 704 MPP_FUNCTION(0x03, "sdio1", "buspwr"), 705 MPP_FUNCTION(0x04, "ssp", "txd"), 706 MPP_FUNCTION(0x05, "sdio0", "buspwr"), 707 MPP_FUNCTION(0x06, "spi1", "mosi")), 708 MPP_MODE(23, 709 MPP_FUNCTION(0x00, "gpio", NULL), 710 MPP_FUNCTION(0x02, "lcd-spi", "sck"), 711 MPP_FUNCTION(0x03, "sdio1", "ledctrl"), 712 MPP_FUNCTION(0x04, "ssp", "sclk"), 713 MPP_FUNCTION(0x05, "sdio0", "ledctrl"), 714 MPP_FUNCTION(0x06, "spi1", "sck")), 715 MPP_MODE(24, 716 MPP_FUNCTION(0x00, "camera", NULL), 717 MPP_FUNCTION(0x01, "gpio", NULL)), 718 MPP_MODE(40, 719 MPP_FUNCTION(0x00, "sdio0", NULL), 720 MPP_FUNCTION(0x01, "gpio", NULL)), 721 MPP_MODE(46, 722 MPP_FUNCTION(0x00, "sdio1", NULL), 723 MPP_FUNCTION(0x01, "gpio", NULL)), 724 MPP_MODE(52, 725 MPP_FUNCTION(0x00, "i2s1/spdifo", NULL), 726 MPP_FUNCTION(0x02, "i2s1", NULL), 727 MPP_FUNCTION(0x08, "spdifo", NULL), 728 MPP_FUNCTION(0x0a, "gpio", NULL), 729 MPP_FUNCTION(0x0b, "twsi", NULL), 730 MPP_FUNCTION(0x0c, "ssp/spdifo", NULL), 731 MPP_FUNCTION(0x0e, "ssp", NULL), 732 MPP_FUNCTION(0x0f, "ssp/twsi", NULL)), 733 MPP_MODE(58, 734 MPP_FUNCTION(0x00, "spi0", NULL), 735 MPP_FUNCTION(0x01, "gpio", NULL)), 736 MPP_MODE(62, 737 MPP_FUNCTION(0x00, "uart1", NULL), 738 MPP_FUNCTION(0x01, "gpio", NULL)), 739 MPP_MODE(64, 740 MPP_FUNCTION(0x00, "nand", NULL), 741 MPP_FUNCTION(0x01, "gpo", NULL)), 742 MPP_MODE(72, 743 MPP_FUNCTION(0x00, "i2s", NULL), 744 MPP_FUNCTION(0x01, "ac97", NULL)), 745 MPP_MODE(73, 746 MPP_FUNCTION(0x00, "twsi-none", NULL), 747 MPP_FUNCTION(0x01, "twsi-opt1", NULL), 748 MPP_FUNCTION(0x02, "twsi-opt2", NULL), 749 MPP_FUNCTION(0x03, "twsi-opt3", NULL)), 750 }; 751 752 static struct pinctrl_gpio_range dove_mpp_gpio_ranges[] = { 753 MPP_GPIO_RANGE(0, 0, 0, 32), 754 MPP_GPIO_RANGE(1, 32, 32, 32), 755 MPP_GPIO_RANGE(2, 64, 64, 8), 756 }; 757 758 static struct mvebu_pinctrl_soc_info dove_pinctrl_info = { 759 .controls = dove_mpp_controls, 760 .ncontrols = ARRAY_SIZE(dove_mpp_controls), 761 .modes = dove_mpp_modes, 762 .nmodes = ARRAY_SIZE(dove_mpp_modes), 763 .gpioranges = dove_mpp_gpio_ranges, 764 .ngpioranges = ARRAY_SIZE(dove_mpp_gpio_ranges), 765 .variant = 0, 766 }; 767 768 static struct clk *clk; 769 770 static const struct of_device_id dove_pinctrl_of_match[] = { 771 { .compatible = "marvell,dove-pinctrl", .data = &dove_pinctrl_info }, 772 { } 773 }; 774 775 static const struct regmap_config gc_regmap_config = { 776 .reg_bits = 32, 777 .val_bits = 32, 778 .reg_stride = 4, 779 .max_register = 5, 780 }; 781 782 static int dove_pinctrl_probe(struct platform_device *pdev) 783 { 784 struct resource *res, *mpp_res; 785 struct resource fb_res; 786 const struct of_device_id *match = 787 of_match_device(dove_pinctrl_of_match, &pdev->dev); 788 pdev->dev.platform_data = (void *)match->data; 789 790 /* 791 * General MPP Configuration Register is part of pdma registers. 792 * grab clk to make sure it is ticking. 793 */ 794 clk = devm_clk_get(&pdev->dev, NULL); 795 if (IS_ERR(clk)) { 796 dev_err(&pdev->dev, "Unable to get pdma clock"); 797 return PTR_ERR(clk); 798 } 799 clk_prepare_enable(clk); 800 801 mpp_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 802 mpp_base = devm_ioremap_resource(&pdev->dev, mpp_res); 803 if (IS_ERR(mpp_base)) 804 return PTR_ERR(mpp_base); 805 806 /* prepare fallback resource */ 807 memcpy(&fb_res, mpp_res, sizeof(struct resource)); 808 fb_res.start = 0; 809 810 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 811 if (!res) { 812 dev_warn(&pdev->dev, "falling back to hardcoded MPP4 resource\n"); 813 adjust_resource(&fb_res, 814 (mpp_res->start & INT_REGS_MASK) + MPP4_REGS_OFFS, 0x4); 815 res = &fb_res; 816 } 817 818 mpp4_base = devm_ioremap_resource(&pdev->dev, res); 819 if (IS_ERR(mpp4_base)) 820 return PTR_ERR(mpp4_base); 821 822 res = platform_get_resource(pdev, IORESOURCE_MEM, 2); 823 if (!res) { 824 dev_warn(&pdev->dev, "falling back to hardcoded PMU resource\n"); 825 adjust_resource(&fb_res, 826 (mpp_res->start & INT_REGS_MASK) + PMU_REGS_OFFS, 0x8); 827 res = &fb_res; 828 } 829 830 pmu_base = devm_ioremap_resource(&pdev->dev, res); 831 if (IS_ERR(pmu_base)) 832 return PTR_ERR(pmu_base); 833 834 gconfmap = syscon_regmap_lookup_by_compatible("marvell,dove-global-config"); 835 if (IS_ERR(gconfmap)) { 836 void __iomem *gc_base; 837 838 dev_warn(&pdev->dev, "falling back to hardcoded global registers\n"); 839 adjust_resource(&fb_res, 840 (mpp_res->start & INT_REGS_MASK) + GC_REGS_OFFS, 0x14); 841 gc_base = devm_ioremap_resource(&pdev->dev, &fb_res); 842 if (IS_ERR(gc_base)) 843 return PTR_ERR(gc_base); 844 gconfmap = devm_regmap_init_mmio(&pdev->dev, 845 gc_base, &gc_regmap_config); 846 if (IS_ERR(gconfmap)) 847 return PTR_ERR(gconfmap); 848 } 849 850 /* Warn on any missing DT resource */ 851 if (fb_res.start) 852 dev_warn(&pdev->dev, FW_BUG "Missing pinctrl regs in DTB. Please update your firmware.\n"); 853 854 return mvebu_pinctrl_probe(pdev); 855 } 856 857 static int dove_pinctrl_remove(struct platform_device *pdev) 858 { 859 if (!IS_ERR(clk)) 860 clk_disable_unprepare(clk); 861 return 0; 862 } 863 864 static struct platform_driver dove_pinctrl_driver = { 865 .driver = { 866 .name = "dove-pinctrl", 867 .of_match_table = dove_pinctrl_of_match, 868 }, 869 .probe = dove_pinctrl_probe, 870 .remove = dove_pinctrl_remove, 871 }; 872 873 module_platform_driver(dove_pinctrl_driver); 874 875 MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>"); 876 MODULE_DESCRIPTION("Marvell Dove pinctrl driver"); 877 MODULE_LICENSE("GPL v2"); 878