1 /* 2 * Marvell Dove pinctrl driver based on mvebu pinctrl core 3 * 4 * Author: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #include <linux/err.h> 13 #include <linux/init.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/bitops.h> 17 #include <linux/platform_device.h> 18 #include <linux/clk.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/mfd/syscon.h> 22 #include <linux/pinctrl/pinctrl.h> 23 #include <linux/regmap.h> 24 25 #include "pinctrl-mvebu.h" 26 27 /* Internal registers can be configured at any 1 MiB aligned address */ 28 #define INT_REGS_MASK ~(SZ_1M - 1) 29 #define MPP4_REGS_OFFS 0xd0440 30 #define PMU_REGS_OFFS 0xd802c 31 #define GC_REGS_OFFS 0xe802c 32 33 #define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000) 34 #define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) 35 #define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) 36 #define DOVE_TWSI_ENABLE_OPTION1 BIT(7) 37 #define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030) 38 #define DOVE_TWSI_ENABLE_OPTION2 BIT(20) 39 #define DOVE_TWSI_ENABLE_OPTION3 BIT(21) 40 #define DOVE_TWSI_OPTION3_GPIO BIT(22) 41 #define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034) 42 #define DOVE_SSP_ON_AU1 BIT(0) 43 #define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c) 44 #define DOVE_AU1_SPDIFO_GPIO_EN BIT(1) 45 #define DOVE_NAND_GPIO_EN BIT(0) 46 #define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400) 47 48 /* MPP Base registers */ 49 #define PMU_MPP_GENERAL_CTRL 0x10 50 #define AU0_AC97_SEL BIT(16) 51 52 /* MPP Control 4 register */ 53 #define SPI_GPIO_SEL BIT(5) 54 #define UART1_GPIO_SEL BIT(4) 55 #define AU1_GPIO_SEL BIT(3) 56 #define CAM_GPIO_SEL BIT(2) 57 #define SD1_GPIO_SEL BIT(1) 58 #define SD0_GPIO_SEL BIT(0) 59 60 /* PMU Signal Select registers */ 61 #define PMU_SIGNAL_SELECT_0 0x00 62 #define PMU_SIGNAL_SELECT_1 0x04 63 64 #define CONFIG_PMU BIT(4) 65 66 static void __iomem *mpp_base; 67 static void __iomem *mpp4_base; 68 static void __iomem *pmu_base; 69 static struct regmap *gconfmap; 70 71 static int dove_mpp_ctrl_get(unsigned pid, unsigned long *config) 72 { 73 return default_mpp_ctrl_get(mpp_base, pid, config); 74 } 75 76 static int dove_mpp_ctrl_set(unsigned pid, unsigned long config) 77 { 78 return default_mpp_ctrl_set(mpp_base, pid, config); 79 } 80 81 static int dove_pmu_mpp_ctrl_get(unsigned pid, unsigned long *config) 82 { 83 unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; 84 unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; 85 unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL); 86 unsigned long func; 87 88 if ((pmu & BIT(pid)) == 0) 89 return default_mpp_ctrl_get(mpp_base, pid, config); 90 91 func = readl(pmu_base + PMU_SIGNAL_SELECT_0 + off); 92 *config = (func >> shift) & MVEBU_MPP_MASK; 93 *config |= CONFIG_PMU; 94 95 return 0; 96 } 97 98 static int dove_pmu_mpp_ctrl_set(unsigned pid, unsigned long config) 99 { 100 unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; 101 unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; 102 unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL); 103 unsigned long func; 104 105 if ((config & CONFIG_PMU) == 0) { 106 writel(pmu & ~BIT(pid), mpp_base + PMU_MPP_GENERAL_CTRL); 107 return default_mpp_ctrl_set(mpp_base, pid, config); 108 } 109 110 writel(pmu | BIT(pid), mpp_base + PMU_MPP_GENERAL_CTRL); 111 func = readl(pmu_base + PMU_SIGNAL_SELECT_0 + off); 112 func &= ~(MVEBU_MPP_MASK << shift); 113 func |= (config & MVEBU_MPP_MASK) << shift; 114 writel(func, pmu_base + PMU_SIGNAL_SELECT_0 + off); 115 116 return 0; 117 } 118 119 static int dove_mpp4_ctrl_get(unsigned pid, unsigned long *config) 120 { 121 unsigned long mpp4 = readl(mpp4_base); 122 unsigned long mask; 123 124 switch (pid) { 125 case 24: /* mpp_camera */ 126 mask = CAM_GPIO_SEL; 127 break; 128 case 40: /* mpp_sdio0 */ 129 mask = SD0_GPIO_SEL; 130 break; 131 case 46: /* mpp_sdio1 */ 132 mask = SD1_GPIO_SEL; 133 break; 134 case 58: /* mpp_spi0 */ 135 mask = SPI_GPIO_SEL; 136 break; 137 case 62: /* mpp_uart1 */ 138 mask = UART1_GPIO_SEL; 139 break; 140 default: 141 return -EINVAL; 142 } 143 144 *config = ((mpp4 & mask) != 0); 145 146 return 0; 147 } 148 149 static int dove_mpp4_ctrl_set(unsigned pid, unsigned long config) 150 { 151 unsigned long mpp4 = readl(mpp4_base); 152 unsigned long mask; 153 154 switch (pid) { 155 case 24: /* mpp_camera */ 156 mask = CAM_GPIO_SEL; 157 break; 158 case 40: /* mpp_sdio0 */ 159 mask = SD0_GPIO_SEL; 160 break; 161 case 46: /* mpp_sdio1 */ 162 mask = SD1_GPIO_SEL; 163 break; 164 case 58: /* mpp_spi0 */ 165 mask = SPI_GPIO_SEL; 166 break; 167 case 62: /* mpp_uart1 */ 168 mask = UART1_GPIO_SEL; 169 break; 170 default: 171 return -EINVAL; 172 } 173 174 mpp4 &= ~mask; 175 if (config) 176 mpp4 |= mask; 177 178 writel(mpp4, mpp4_base); 179 180 return 0; 181 } 182 183 static int dove_nand_ctrl_get(unsigned pid, unsigned long *config) 184 { 185 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 186 187 *config = ((gmpp & DOVE_NAND_GPIO_EN) != 0); 188 189 return 0; 190 } 191 192 static int dove_nand_ctrl_set(unsigned pid, unsigned long config) 193 { 194 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 195 196 gmpp &= ~DOVE_NAND_GPIO_EN; 197 if (config) 198 gmpp |= DOVE_NAND_GPIO_EN; 199 200 writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE); 201 202 return 0; 203 } 204 205 static int dove_audio0_ctrl_get(unsigned pid, unsigned long *config) 206 { 207 unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL); 208 209 *config = ((pmu & AU0_AC97_SEL) != 0); 210 211 return 0; 212 } 213 214 static int dove_audio0_ctrl_set(unsigned pid, unsigned long config) 215 { 216 unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL); 217 218 pmu &= ~AU0_AC97_SEL; 219 if (config) 220 pmu |= AU0_AC97_SEL; 221 writel(pmu, mpp_base + PMU_MPP_GENERAL_CTRL); 222 223 return 0; 224 } 225 226 static int dove_audio1_ctrl_get(unsigned pid, unsigned long *config) 227 { 228 unsigned int mpp4 = readl(mpp4_base); 229 unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1); 230 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 231 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 232 233 *config = 0; 234 if (mpp4 & AU1_GPIO_SEL) 235 *config |= BIT(3); 236 if (sspc1 & DOVE_SSP_ON_AU1) 237 *config |= BIT(2); 238 if (gmpp & DOVE_AU1_SPDIFO_GPIO_EN) 239 *config |= BIT(1); 240 if (gcfg2 & DOVE_TWSI_OPTION3_GPIO) 241 *config |= BIT(0); 242 243 /* SSP/TWSI only if I2S1 not set*/ 244 if ((*config & BIT(3)) == 0) 245 *config &= ~(BIT(2) | BIT(0)); 246 /* TWSI only if SPDIFO not set*/ 247 if ((*config & BIT(1)) == 0) 248 *config &= ~BIT(0); 249 return 0; 250 } 251 252 static int dove_audio1_ctrl_set(unsigned pid, unsigned long config) 253 { 254 unsigned int mpp4 = readl(mpp4_base); 255 unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1); 256 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 257 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 258 259 /* 260 * clear all audio1 related bits before configure 261 */ 262 gcfg2 &= ~DOVE_TWSI_OPTION3_GPIO; 263 gmpp &= ~DOVE_AU1_SPDIFO_GPIO_EN; 264 sspc1 &= ~DOVE_SSP_ON_AU1; 265 mpp4 &= ~AU1_GPIO_SEL; 266 267 if (config & BIT(0)) 268 gcfg2 |= DOVE_TWSI_OPTION3_GPIO; 269 if (config & BIT(1)) 270 gmpp |= DOVE_AU1_SPDIFO_GPIO_EN; 271 if (config & BIT(2)) 272 sspc1 |= DOVE_SSP_ON_AU1; 273 if (config & BIT(3)) 274 mpp4 |= AU1_GPIO_SEL; 275 276 writel(mpp4, mpp4_base); 277 writel(sspc1, DOVE_SSP_CTRL_STATUS_1); 278 writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE); 279 writel(gcfg2, DOVE_GLOBAL_CONFIG_2); 280 281 return 0; 282 } 283 284 /* mpp[52:57] gpio pins depend heavily on current config; 285 * gpio_req does not try to mux in gpio capabilities to not 286 * break other functions. If you require all mpps as gpio 287 * enforce gpio setting by pinctrl mapping. 288 */ 289 static int dove_audio1_ctrl_gpio_req(unsigned pid) 290 { 291 unsigned long config; 292 293 dove_audio1_ctrl_get(pid, &config); 294 295 switch (config) { 296 case 0x02: /* i2s1 : gpio[56:57] */ 297 case 0x0e: /* ssp : gpio[56:57] */ 298 if (pid >= 56) 299 return 0; 300 return -ENOTSUPP; 301 case 0x08: /* spdifo : gpio[52:55] */ 302 case 0x0b: /* twsi : gpio[52:55] */ 303 if (pid <= 55) 304 return 0; 305 return -ENOTSUPP; 306 case 0x0a: /* all gpio */ 307 return 0; 308 /* 0x00 : i2s1/spdifo : no gpio */ 309 /* 0x0c : ssp/spdifo : no gpio */ 310 /* 0x0f : ssp/twsi : no gpio */ 311 } 312 return -ENOTSUPP; 313 } 314 315 /* mpp[52:57] has gpio pins capable of in and out */ 316 static int dove_audio1_ctrl_gpio_dir(unsigned pid, bool input) 317 { 318 if (pid < 52 || pid > 57) 319 return -ENOTSUPP; 320 return 0; 321 } 322 323 static int dove_twsi_ctrl_get(unsigned pid, unsigned long *config) 324 { 325 unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1); 326 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 327 328 *config = 0; 329 if (gcfg1 & DOVE_TWSI_ENABLE_OPTION1) 330 *config = 1; 331 else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION2) 332 *config = 2; 333 else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION3) 334 *config = 3; 335 336 return 0; 337 } 338 339 static int dove_twsi_ctrl_set(unsigned pid, unsigned long config) 340 { 341 unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1); 342 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 343 344 gcfg1 &= ~DOVE_TWSI_ENABLE_OPTION1; 345 gcfg2 &= ~(DOVE_TWSI_ENABLE_OPTION2 | DOVE_TWSI_ENABLE_OPTION3); 346 347 switch (config) { 348 case 1: 349 gcfg1 |= DOVE_TWSI_ENABLE_OPTION1; 350 break; 351 case 2: 352 gcfg2 |= DOVE_TWSI_ENABLE_OPTION2; 353 break; 354 case 3: 355 gcfg2 |= DOVE_TWSI_ENABLE_OPTION3; 356 break; 357 } 358 359 writel(gcfg1, DOVE_GLOBAL_CONFIG_1); 360 writel(gcfg2, DOVE_GLOBAL_CONFIG_2); 361 362 return 0; 363 } 364 365 static struct mvebu_mpp_ctrl dove_mpp_controls[] = { 366 MPP_FUNC_CTRL(0, 15, NULL, dove_pmu_mpp_ctrl), 367 MPP_FUNC_CTRL(16, 23, NULL, dove_mpp_ctrl), 368 MPP_FUNC_CTRL(24, 39, "mpp_camera", dove_mpp4_ctrl), 369 MPP_FUNC_CTRL(40, 45, "mpp_sdio0", dove_mpp4_ctrl), 370 MPP_FUNC_CTRL(46, 51, "mpp_sdio1", dove_mpp4_ctrl), 371 MPP_FUNC_GPIO_CTRL(52, 57, "mpp_audio1", dove_audio1_ctrl), 372 MPP_FUNC_CTRL(58, 61, "mpp_spi0", dove_mpp4_ctrl), 373 MPP_FUNC_CTRL(62, 63, "mpp_uart1", dove_mpp4_ctrl), 374 MPP_FUNC_CTRL(64, 71, "mpp_nand", dove_nand_ctrl), 375 MPP_FUNC_CTRL(72, 72, "audio0", dove_audio0_ctrl), 376 MPP_FUNC_CTRL(73, 73, "twsi", dove_twsi_ctrl), 377 }; 378 379 static struct mvebu_mpp_mode dove_mpp_modes[] = { 380 MPP_MODE(0, 381 MPP_FUNCTION(0x00, "gpio", NULL), 382 MPP_FUNCTION(0x02, "uart2", "rts"), 383 MPP_FUNCTION(0x03, "sdio0", "cd"), 384 MPP_FUNCTION(0x0f, "lcd0", "pwm"), 385 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 386 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 387 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 388 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 389 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 390 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 391 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 392 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 393 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 394 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 395 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 396 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 397 MPP_MODE(1, 398 MPP_FUNCTION(0x00, "gpio", NULL), 399 MPP_FUNCTION(0x02, "uart2", "cts"), 400 MPP_FUNCTION(0x03, "sdio0", "wp"), 401 MPP_FUNCTION(0x0f, "lcd1", "pwm"), 402 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 403 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 404 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 405 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 406 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 407 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 408 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 409 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 410 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 411 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 412 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 413 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 414 MPP_MODE(2, 415 MPP_FUNCTION(0x00, "gpio", NULL), 416 MPP_FUNCTION(0x01, "sata", "prsnt"), 417 MPP_FUNCTION(0x02, "uart2", "txd"), 418 MPP_FUNCTION(0x03, "sdio0", "buspwr"), 419 MPP_FUNCTION(0x04, "uart1", "rts"), 420 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 421 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 422 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 423 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 424 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 425 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 426 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 427 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 428 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 429 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 430 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 431 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 432 MPP_MODE(3, 433 MPP_FUNCTION(0x00, "gpio", NULL), 434 MPP_FUNCTION(0x01, "sata", "act"), 435 MPP_FUNCTION(0x02, "uart2", "rxd"), 436 MPP_FUNCTION(0x03, "sdio0", "ledctrl"), 437 MPP_FUNCTION(0x04, "uart1", "cts"), 438 MPP_FUNCTION(0x0f, "lcd-spi", "cs1"), 439 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 440 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 441 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 442 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 443 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 444 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 445 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 446 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 447 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 448 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 449 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 450 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 451 MPP_MODE(4, 452 MPP_FUNCTION(0x00, "gpio", NULL), 453 MPP_FUNCTION(0x02, "uart3", "rts"), 454 MPP_FUNCTION(0x03, "sdio1", "cd"), 455 MPP_FUNCTION(0x04, "spi1", "miso"), 456 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 457 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 458 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 459 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 460 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 461 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 462 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 463 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 464 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 465 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 466 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 467 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 468 MPP_MODE(5, 469 MPP_FUNCTION(0x00, "gpio", NULL), 470 MPP_FUNCTION(0x02, "uart3", "cts"), 471 MPP_FUNCTION(0x03, "sdio1", "wp"), 472 MPP_FUNCTION(0x04, "spi1", "cs"), 473 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 474 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 475 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 476 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 477 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 478 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 479 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 480 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 481 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 482 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 483 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 484 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 485 MPP_MODE(6, 486 MPP_FUNCTION(0x00, "gpio", NULL), 487 MPP_FUNCTION(0x02, "uart3", "txd"), 488 MPP_FUNCTION(0x03, "sdio1", "buspwr"), 489 MPP_FUNCTION(0x04, "spi1", "mosi"), 490 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 491 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 492 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 493 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 494 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 495 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 496 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 497 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 498 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 499 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 500 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 501 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 502 MPP_MODE(7, 503 MPP_FUNCTION(0x00, "gpio", NULL), 504 MPP_FUNCTION(0x02, "uart3", "rxd"), 505 MPP_FUNCTION(0x03, "sdio1", "ledctrl"), 506 MPP_FUNCTION(0x04, "spi1", "sck"), 507 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 508 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 509 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 510 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 511 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 512 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 513 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 514 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 515 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 516 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 517 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 518 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 519 MPP_MODE(8, 520 MPP_FUNCTION(0x00, "gpio", NULL), 521 MPP_FUNCTION(0x01, "watchdog", "rstout"), 522 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 523 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 524 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 525 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 526 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 527 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 528 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 529 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 530 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 531 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 532 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 533 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 534 MPP_MODE(9, 535 MPP_FUNCTION(0x00, "gpio", NULL), 536 MPP_FUNCTION(0x05, "pex1", "clkreq"), 537 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 538 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 539 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 540 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 541 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 542 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 543 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 544 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 545 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 546 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 547 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 548 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 549 MPP_MODE(10, 550 MPP_FUNCTION(0x00, "gpio", NULL), 551 MPP_FUNCTION(0x05, "ssp", "sclk"), 552 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 553 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 554 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 555 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 556 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 557 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 558 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 559 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 560 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 561 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 562 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 563 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 564 MPP_MODE(11, 565 MPP_FUNCTION(0x00, "gpio", NULL), 566 MPP_FUNCTION(0x01, "sata", "prsnt"), 567 MPP_FUNCTION(0x02, "sata-1", "act"), 568 MPP_FUNCTION(0x03, "sdio0", "ledctrl"), 569 MPP_FUNCTION(0x04, "sdio1", "ledctrl"), 570 MPP_FUNCTION(0x05, "pex0", "clkreq"), 571 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 572 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 573 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 574 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 575 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 576 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 577 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 578 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 579 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 580 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 581 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 582 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 583 MPP_MODE(12, 584 MPP_FUNCTION(0x00, "gpio", NULL), 585 MPP_FUNCTION(0x01, "sata", "act"), 586 MPP_FUNCTION(0x02, "uart2", "rts"), 587 MPP_FUNCTION(0x03, "audio0", "extclk"), 588 MPP_FUNCTION(0x04, "sdio1", "cd"), 589 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 590 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 591 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 592 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 593 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 594 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 595 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 596 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 597 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 598 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 599 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 600 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 601 MPP_MODE(13, 602 MPP_FUNCTION(0x00, "gpio", NULL), 603 MPP_FUNCTION(0x02, "uart2", "cts"), 604 MPP_FUNCTION(0x03, "audio1", "extclk"), 605 MPP_FUNCTION(0x04, "sdio1", "wp"), 606 MPP_FUNCTION(0x05, "ssp", "extclk"), 607 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 608 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 609 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 610 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 611 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 612 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 613 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 614 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 615 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 616 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 617 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 618 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 619 MPP_MODE(14, 620 MPP_FUNCTION(0x00, "gpio", NULL), 621 MPP_FUNCTION(0x02, "uart2", "txd"), 622 MPP_FUNCTION(0x04, "sdio1", "buspwr"), 623 MPP_FUNCTION(0x05, "ssp", "rxd"), 624 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 625 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 626 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 627 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 628 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 629 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 630 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 631 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 632 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 633 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 634 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 635 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 636 MPP_MODE(15, 637 MPP_FUNCTION(0x00, "gpio", NULL), 638 MPP_FUNCTION(0x02, "uart2", "rxd"), 639 MPP_FUNCTION(0x04, "sdio1", "ledctrl"), 640 MPP_FUNCTION(0x05, "ssp", "sfrm"), 641 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 642 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 643 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 644 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 645 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 646 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 647 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 648 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 649 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 650 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 651 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 652 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 653 MPP_MODE(16, 654 MPP_FUNCTION(0x00, "gpio", NULL), 655 MPP_FUNCTION(0x02, "uart3", "rts"), 656 MPP_FUNCTION(0x03, "sdio0", "cd"), 657 MPP_FUNCTION(0x04, "lcd-spi", "cs1"), 658 MPP_FUNCTION(0x05, "ac97", "sdi1")), 659 MPP_MODE(17, 660 MPP_FUNCTION(0x00, "gpio", NULL), 661 MPP_FUNCTION(0x01, "ac97-1", "sysclko"), 662 MPP_FUNCTION(0x02, "uart3", "cts"), 663 MPP_FUNCTION(0x03, "sdio0", "wp"), 664 MPP_FUNCTION(0x04, "twsi", "sda"), 665 MPP_FUNCTION(0x05, "ac97", "sdi2")), 666 MPP_MODE(18, 667 MPP_FUNCTION(0x00, "gpio", NULL), 668 MPP_FUNCTION(0x02, "uart3", "txd"), 669 MPP_FUNCTION(0x03, "sdio0", "buspwr"), 670 MPP_FUNCTION(0x04, "lcd0", "pwm"), 671 MPP_FUNCTION(0x05, "ac97", "sdi3")), 672 MPP_MODE(19, 673 MPP_FUNCTION(0x00, "gpio", NULL), 674 MPP_FUNCTION(0x02, "uart3", "rxd"), 675 MPP_FUNCTION(0x03, "sdio0", "ledctrl"), 676 MPP_FUNCTION(0x04, "twsi", "sck")), 677 MPP_MODE(20, 678 MPP_FUNCTION(0x00, "gpio", NULL), 679 MPP_FUNCTION(0x01, "ac97", "sysclko"), 680 MPP_FUNCTION(0x02, "lcd-spi", "miso"), 681 MPP_FUNCTION(0x03, "sdio1", "cd"), 682 MPP_FUNCTION(0x05, "sdio0", "cd"), 683 MPP_FUNCTION(0x06, "spi1", "miso")), 684 MPP_MODE(21, 685 MPP_FUNCTION(0x00, "gpio", NULL), 686 MPP_FUNCTION(0x01, "uart1", "rts"), 687 MPP_FUNCTION(0x02, "lcd-spi", "cs0"), 688 MPP_FUNCTION(0x03, "sdio1", "wp"), 689 MPP_FUNCTION(0x04, "ssp", "sfrm"), 690 MPP_FUNCTION(0x05, "sdio0", "wp"), 691 MPP_FUNCTION(0x06, "spi1", "cs")), 692 MPP_MODE(22, 693 MPP_FUNCTION(0x00, "gpio", NULL), 694 MPP_FUNCTION(0x01, "uart1", "cts"), 695 MPP_FUNCTION(0x02, "lcd-spi", "mosi"), 696 MPP_FUNCTION(0x03, "sdio1", "buspwr"), 697 MPP_FUNCTION(0x04, "ssp", "txd"), 698 MPP_FUNCTION(0x05, "sdio0", "buspwr"), 699 MPP_FUNCTION(0x06, "spi1", "mosi")), 700 MPP_MODE(23, 701 MPP_FUNCTION(0x00, "gpio", NULL), 702 MPP_FUNCTION(0x02, "lcd-spi", "sck"), 703 MPP_FUNCTION(0x03, "sdio1", "ledctrl"), 704 MPP_FUNCTION(0x04, "ssp", "sclk"), 705 MPP_FUNCTION(0x05, "sdio0", "ledctrl"), 706 MPP_FUNCTION(0x06, "spi1", "sck")), 707 MPP_MODE(24, 708 MPP_FUNCTION(0x00, "camera", NULL), 709 MPP_FUNCTION(0x01, "gpio", NULL)), 710 MPP_MODE(40, 711 MPP_FUNCTION(0x00, "sdio0", NULL), 712 MPP_FUNCTION(0x01, "gpio", NULL)), 713 MPP_MODE(46, 714 MPP_FUNCTION(0x00, "sdio1", NULL), 715 MPP_FUNCTION(0x01, "gpio", NULL)), 716 MPP_MODE(52, 717 MPP_FUNCTION(0x00, "i2s1/spdifo", NULL), 718 MPP_FUNCTION(0x02, "i2s1", NULL), 719 MPP_FUNCTION(0x08, "spdifo", NULL), 720 MPP_FUNCTION(0x0a, "gpio", NULL), 721 MPP_FUNCTION(0x0b, "twsi", NULL), 722 MPP_FUNCTION(0x0c, "ssp/spdifo", NULL), 723 MPP_FUNCTION(0x0e, "ssp", NULL), 724 MPP_FUNCTION(0x0f, "ssp/twsi", NULL)), 725 MPP_MODE(58, 726 MPP_FUNCTION(0x00, "spi0", NULL), 727 MPP_FUNCTION(0x01, "gpio", NULL)), 728 MPP_MODE(62, 729 MPP_FUNCTION(0x00, "uart1", NULL), 730 MPP_FUNCTION(0x01, "gpio", NULL)), 731 MPP_MODE(64, 732 MPP_FUNCTION(0x00, "nand", NULL), 733 MPP_FUNCTION(0x01, "gpo", NULL)), 734 MPP_MODE(72, 735 MPP_FUNCTION(0x00, "i2s", NULL), 736 MPP_FUNCTION(0x01, "ac97", NULL)), 737 MPP_MODE(73, 738 MPP_FUNCTION(0x00, "twsi-none", NULL), 739 MPP_FUNCTION(0x01, "twsi-opt1", NULL), 740 MPP_FUNCTION(0x02, "twsi-opt2", NULL), 741 MPP_FUNCTION(0x03, "twsi-opt3", NULL)), 742 }; 743 744 static struct pinctrl_gpio_range dove_mpp_gpio_ranges[] = { 745 MPP_GPIO_RANGE(0, 0, 0, 32), 746 MPP_GPIO_RANGE(1, 32, 32, 32), 747 MPP_GPIO_RANGE(2, 64, 64, 8), 748 }; 749 750 static struct mvebu_pinctrl_soc_info dove_pinctrl_info = { 751 .controls = dove_mpp_controls, 752 .ncontrols = ARRAY_SIZE(dove_mpp_controls), 753 .modes = dove_mpp_modes, 754 .nmodes = ARRAY_SIZE(dove_mpp_modes), 755 .gpioranges = dove_mpp_gpio_ranges, 756 .ngpioranges = ARRAY_SIZE(dove_mpp_gpio_ranges), 757 .variant = 0, 758 }; 759 760 static struct clk *clk; 761 762 static struct of_device_id dove_pinctrl_of_match[] = { 763 { .compatible = "marvell,dove-pinctrl", .data = &dove_pinctrl_info }, 764 { } 765 }; 766 767 static struct regmap_config gc_regmap_config = { 768 .reg_bits = 32, 769 .val_bits = 32, 770 .reg_stride = 4, 771 .max_register = 5, 772 }; 773 774 static int dove_pinctrl_probe(struct platform_device *pdev) 775 { 776 struct resource *res, *mpp_res; 777 struct resource fb_res; 778 const struct of_device_id *match = 779 of_match_device(dove_pinctrl_of_match, &pdev->dev); 780 pdev->dev.platform_data = (void *)match->data; 781 782 /* 783 * General MPP Configuration Register is part of pdma registers. 784 * grab clk to make sure it is ticking. 785 */ 786 clk = devm_clk_get(&pdev->dev, NULL); 787 if (IS_ERR(clk)) { 788 dev_err(&pdev->dev, "Unable to get pdma clock"); 789 return PTR_ERR(clk); 790 } 791 clk_prepare_enable(clk); 792 793 mpp_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 794 mpp_base = devm_ioremap_resource(&pdev->dev, mpp_res); 795 if (IS_ERR(mpp_base)) 796 return PTR_ERR(mpp_base); 797 798 /* prepare fallback resource */ 799 memcpy(&fb_res, mpp_res, sizeof(struct resource)); 800 fb_res.start = 0; 801 802 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 803 if (!res) { 804 dev_warn(&pdev->dev, "falling back to hardcoded MPP4 resource\n"); 805 adjust_resource(&fb_res, 806 (mpp_res->start & INT_REGS_MASK) + MPP4_REGS_OFFS, 0x4); 807 res = &fb_res; 808 } 809 810 mpp4_base = devm_ioremap_resource(&pdev->dev, res); 811 if (IS_ERR(mpp4_base)) 812 return PTR_ERR(mpp4_base); 813 814 res = platform_get_resource(pdev, IORESOURCE_MEM, 2); 815 if (!res) { 816 dev_warn(&pdev->dev, "falling back to hardcoded PMU resource\n"); 817 adjust_resource(&fb_res, 818 (mpp_res->start & INT_REGS_MASK) + PMU_REGS_OFFS, 0x8); 819 res = &fb_res; 820 } 821 822 pmu_base = devm_ioremap_resource(&pdev->dev, res); 823 if (IS_ERR(pmu_base)) 824 return PTR_ERR(pmu_base); 825 826 gconfmap = syscon_regmap_lookup_by_compatible("marvell,dove-global-config"); 827 if (IS_ERR(gconfmap)) { 828 void __iomem *gc_base; 829 830 dev_warn(&pdev->dev, "falling back to hardcoded global registers\n"); 831 adjust_resource(&fb_res, 832 (mpp_res->start & INT_REGS_MASK) + GC_REGS_OFFS, 0x14); 833 gc_base = devm_ioremap_resource(&pdev->dev, &fb_res); 834 if (IS_ERR(gc_base)) 835 return PTR_ERR(gc_base); 836 gconfmap = devm_regmap_init_mmio(&pdev->dev, 837 gc_base, &gc_regmap_config); 838 if (IS_ERR(gconfmap)) 839 return PTR_ERR(gconfmap); 840 } 841 842 /* Warn on any missing DT resource */ 843 WARN(fb_res.start, FW_BUG "Missing pinctrl regs in DTB. Please update your firmware.\n"); 844 845 return mvebu_pinctrl_probe(pdev); 846 } 847 848 static int dove_pinctrl_remove(struct platform_device *pdev) 849 { 850 int ret; 851 852 ret = mvebu_pinctrl_remove(pdev); 853 if (!IS_ERR(clk)) 854 clk_disable_unprepare(clk); 855 return ret; 856 } 857 858 static struct platform_driver dove_pinctrl_driver = { 859 .driver = { 860 .name = "dove-pinctrl", 861 .owner = THIS_MODULE, 862 .of_match_table = dove_pinctrl_of_match, 863 }, 864 .probe = dove_pinctrl_probe, 865 .remove = dove_pinctrl_remove, 866 }; 867 868 module_platform_driver(dove_pinctrl_driver); 869 870 MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>"); 871 MODULE_DESCRIPTION("Marvell Dove pinctrl driver"); 872 MODULE_LICENSE("GPL v2"); 873