1 /* 2 * Marvell Dove pinctrl driver based on mvebu pinctrl core 3 * 4 * Author: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #include <linux/err.h> 13 #include <linux/init.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/bitops.h> 17 #include <linux/platform_device.h> 18 #include <linux/clk.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/pinctrl/pinctrl.h> 22 23 #include "pinctrl-mvebu.h" 24 25 #define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000) 26 #define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200) 27 #define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10) 28 #define DOVE_AU0_AC97_SEL BIT(16) 29 #define DOVE_PMU_SIGNAL_SELECT_0 (DOVE_SB_REGS_VIRT_BASE + 0xd802C) 30 #define DOVE_PMU_SIGNAL_SELECT_1 (DOVE_SB_REGS_VIRT_BASE + 0xd8030) 31 #define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) 32 #define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) 33 #define DOVE_TWSI_ENABLE_OPTION1 BIT(7) 34 #define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030) 35 #define DOVE_TWSI_ENABLE_OPTION2 BIT(20) 36 #define DOVE_TWSI_ENABLE_OPTION3 BIT(21) 37 #define DOVE_TWSI_OPTION3_GPIO BIT(22) 38 #define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034) 39 #define DOVE_SSP_ON_AU1 BIT(0) 40 #define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c) 41 #define DOVE_AU1_SPDIFO_GPIO_EN BIT(1) 42 #define DOVE_NAND_GPIO_EN BIT(0) 43 #define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400) 44 #define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40) 45 #define DOVE_SPI_GPIO_SEL BIT(5) 46 #define DOVE_UART1_GPIO_SEL BIT(4) 47 #define DOVE_AU1_GPIO_SEL BIT(3) 48 #define DOVE_CAM_GPIO_SEL BIT(2) 49 #define DOVE_SD1_GPIO_SEL BIT(1) 50 #define DOVE_SD0_GPIO_SEL BIT(0) 51 52 #define CONFIG_PMU BIT(4) 53 54 static void __iomem *mpp_base; 55 56 static int dove_mpp_ctrl_get(unsigned pid, unsigned long *config) 57 { 58 return default_mpp_ctrl_get(mpp_base, pid, config); 59 } 60 61 static int dove_mpp_ctrl_set(unsigned pid, unsigned long config) 62 { 63 return default_mpp_ctrl_set(mpp_base, pid, config); 64 } 65 66 static int dove_pmu_mpp_ctrl_get(unsigned pid, unsigned long *config) 67 { 68 unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; 69 unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; 70 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); 71 unsigned long func; 72 73 if (pmu & (1 << pid)) { 74 func = readl(DOVE_PMU_SIGNAL_SELECT_0 + off); 75 *config = (func >> shift) & MVEBU_MPP_MASK; 76 *config |= CONFIG_PMU; 77 } else { 78 func = readl(DOVE_MPP_VIRT_BASE + off); 79 *config = (func >> shift) & MVEBU_MPP_MASK; 80 } 81 return 0; 82 } 83 84 static int dove_pmu_mpp_ctrl_set(unsigned pid, unsigned long config) 85 { 86 unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; 87 unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; 88 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); 89 unsigned long func; 90 91 if (config & CONFIG_PMU) { 92 writel(pmu | (1 << pid), DOVE_PMU_MPP_GENERAL_CTRL); 93 func = readl(DOVE_PMU_SIGNAL_SELECT_0 + off); 94 func &= ~(MVEBU_MPP_MASK << shift); 95 func |= (config & MVEBU_MPP_MASK) << shift; 96 writel(func, DOVE_PMU_SIGNAL_SELECT_0 + off); 97 } else { 98 writel(pmu & ~(1 << pid), DOVE_PMU_MPP_GENERAL_CTRL); 99 func = readl(DOVE_MPP_VIRT_BASE + off); 100 func &= ~(MVEBU_MPP_MASK << shift); 101 func |= (config & MVEBU_MPP_MASK) << shift; 102 writel(func, DOVE_MPP_VIRT_BASE + off); 103 } 104 return 0; 105 } 106 107 static int dove_mpp4_ctrl_get(unsigned pid, unsigned long *config) 108 { 109 unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 110 unsigned long mask; 111 112 switch (pid) { 113 case 24: /* mpp_camera */ 114 mask = DOVE_CAM_GPIO_SEL; 115 break; 116 case 40: /* mpp_sdio0 */ 117 mask = DOVE_SD0_GPIO_SEL; 118 break; 119 case 46: /* mpp_sdio1 */ 120 mask = DOVE_SD1_GPIO_SEL; 121 break; 122 case 58: /* mpp_spi0 */ 123 mask = DOVE_SPI_GPIO_SEL; 124 break; 125 case 62: /* mpp_uart1 */ 126 mask = DOVE_UART1_GPIO_SEL; 127 break; 128 default: 129 return -EINVAL; 130 } 131 132 *config = ((mpp4 & mask) != 0); 133 134 return 0; 135 } 136 137 static int dove_mpp4_ctrl_set(unsigned pid, unsigned long config) 138 { 139 unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 140 unsigned long mask; 141 142 switch (pid) { 143 case 24: /* mpp_camera */ 144 mask = DOVE_CAM_GPIO_SEL; 145 break; 146 case 40: /* mpp_sdio0 */ 147 mask = DOVE_SD0_GPIO_SEL; 148 break; 149 case 46: /* mpp_sdio1 */ 150 mask = DOVE_SD1_GPIO_SEL; 151 break; 152 case 58: /* mpp_spi0 */ 153 mask = DOVE_SPI_GPIO_SEL; 154 break; 155 case 62: /* mpp_uart1 */ 156 mask = DOVE_UART1_GPIO_SEL; 157 break; 158 default: 159 return -EINVAL; 160 } 161 162 mpp4 &= ~mask; 163 if (config) 164 mpp4 |= mask; 165 166 writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE); 167 168 return 0; 169 } 170 171 static int dove_nand_ctrl_get(unsigned pid, unsigned long *config) 172 { 173 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 174 175 *config = ((gmpp & DOVE_NAND_GPIO_EN) != 0); 176 177 return 0; 178 } 179 180 static int dove_nand_ctrl_set(unsigned pid, unsigned long config) 181 { 182 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 183 184 gmpp &= ~DOVE_NAND_GPIO_EN; 185 if (config) 186 gmpp |= DOVE_NAND_GPIO_EN; 187 188 writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE); 189 190 return 0; 191 } 192 193 static int dove_audio0_ctrl_get(unsigned pid, unsigned long *config) 194 { 195 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); 196 197 *config = ((pmu & DOVE_AU0_AC97_SEL) != 0); 198 199 return 0; 200 } 201 202 static int dove_audio0_ctrl_set(unsigned pid, unsigned long config) 203 { 204 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); 205 206 pmu &= ~DOVE_AU0_AC97_SEL; 207 if (config) 208 pmu |= DOVE_AU0_AC97_SEL; 209 writel(pmu, DOVE_PMU_MPP_GENERAL_CTRL); 210 211 return 0; 212 } 213 214 static int dove_audio1_ctrl_get(unsigned pid, unsigned long *config) 215 { 216 unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 217 unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1); 218 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 219 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 220 221 *config = 0; 222 if (mpp4 & DOVE_AU1_GPIO_SEL) 223 *config |= BIT(3); 224 if (sspc1 & DOVE_SSP_ON_AU1) 225 *config |= BIT(2); 226 if (gmpp & DOVE_AU1_SPDIFO_GPIO_EN) 227 *config |= BIT(1); 228 if (gcfg2 & DOVE_TWSI_OPTION3_GPIO) 229 *config |= BIT(0); 230 231 /* SSP/TWSI only if I2S1 not set*/ 232 if ((*config & BIT(3)) == 0) 233 *config &= ~(BIT(2) | BIT(0)); 234 /* TWSI only if SPDIFO not set*/ 235 if ((*config & BIT(1)) == 0) 236 *config &= ~BIT(0); 237 return 0; 238 } 239 240 static int dove_audio1_ctrl_set(unsigned pid, unsigned long config) 241 { 242 unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 243 unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1); 244 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 245 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 246 247 /* 248 * clear all audio1 related bits before configure 249 */ 250 gcfg2 &= ~DOVE_TWSI_OPTION3_GPIO; 251 gmpp &= ~DOVE_AU1_SPDIFO_GPIO_EN; 252 sspc1 &= ~DOVE_SSP_ON_AU1; 253 mpp4 &= ~DOVE_AU1_GPIO_SEL; 254 255 if (config & BIT(0)) 256 gcfg2 |= DOVE_TWSI_OPTION3_GPIO; 257 if (config & BIT(1)) 258 gmpp |= DOVE_AU1_SPDIFO_GPIO_EN; 259 if (config & BIT(2)) 260 sspc1 |= DOVE_SSP_ON_AU1; 261 if (config & BIT(3)) 262 mpp4 |= DOVE_AU1_GPIO_SEL; 263 264 writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE); 265 writel(sspc1, DOVE_SSP_CTRL_STATUS_1); 266 writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE); 267 writel(gcfg2, DOVE_GLOBAL_CONFIG_2); 268 269 return 0; 270 } 271 272 /* mpp[52:57] gpio pins depend heavily on current config; 273 * gpio_req does not try to mux in gpio capabilities to not 274 * break other functions. If you require all mpps as gpio 275 * enforce gpio setting by pinctrl mapping. 276 */ 277 static int dove_audio1_ctrl_gpio_req(unsigned pid) 278 { 279 unsigned long config; 280 281 dove_audio1_ctrl_get(pid, &config); 282 283 switch (config) { 284 case 0x02: /* i2s1 : gpio[56:57] */ 285 case 0x0e: /* ssp : gpio[56:57] */ 286 if (pid >= 56) 287 return 0; 288 return -ENOTSUPP; 289 case 0x08: /* spdifo : gpio[52:55] */ 290 case 0x0b: /* twsi : gpio[52:55] */ 291 if (pid <= 55) 292 return 0; 293 return -ENOTSUPP; 294 case 0x0a: /* all gpio */ 295 return 0; 296 /* 0x00 : i2s1/spdifo : no gpio */ 297 /* 0x0c : ssp/spdifo : no gpio */ 298 /* 0x0f : ssp/twsi : no gpio */ 299 } 300 return -ENOTSUPP; 301 } 302 303 /* mpp[52:57] has gpio pins capable of in and out */ 304 static int dove_audio1_ctrl_gpio_dir(unsigned pid, bool input) 305 { 306 if (pid < 52 || pid > 57) 307 return -ENOTSUPP; 308 return 0; 309 } 310 311 static int dove_twsi_ctrl_get(unsigned pid, unsigned long *config) 312 { 313 unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1); 314 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 315 316 *config = 0; 317 if (gcfg1 & DOVE_TWSI_ENABLE_OPTION1) 318 *config = 1; 319 else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION2) 320 *config = 2; 321 else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION3) 322 *config = 3; 323 324 return 0; 325 } 326 327 static int dove_twsi_ctrl_set(unsigned pid, unsigned long config) 328 { 329 unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1); 330 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 331 332 gcfg1 &= ~DOVE_TWSI_ENABLE_OPTION1; 333 gcfg2 &= ~(DOVE_TWSI_ENABLE_OPTION2 | DOVE_TWSI_ENABLE_OPTION3); 334 335 switch (config) { 336 case 1: 337 gcfg1 |= DOVE_TWSI_ENABLE_OPTION1; 338 break; 339 case 2: 340 gcfg2 |= DOVE_TWSI_ENABLE_OPTION2; 341 break; 342 case 3: 343 gcfg2 |= DOVE_TWSI_ENABLE_OPTION3; 344 break; 345 } 346 347 writel(gcfg1, DOVE_GLOBAL_CONFIG_1); 348 writel(gcfg2, DOVE_GLOBAL_CONFIG_2); 349 350 return 0; 351 } 352 353 static struct mvebu_mpp_ctrl dove_mpp_controls[] = { 354 MPP_FUNC_CTRL(0, 0, "mpp0", dove_pmu_mpp_ctrl), 355 MPP_FUNC_CTRL(1, 1, "mpp1", dove_pmu_mpp_ctrl), 356 MPP_FUNC_CTRL(2, 2, "mpp2", dove_pmu_mpp_ctrl), 357 MPP_FUNC_CTRL(3, 3, "mpp3", dove_pmu_mpp_ctrl), 358 MPP_FUNC_CTRL(4, 4, "mpp4", dove_pmu_mpp_ctrl), 359 MPP_FUNC_CTRL(5, 5, "mpp5", dove_pmu_mpp_ctrl), 360 MPP_FUNC_CTRL(6, 6, "mpp6", dove_pmu_mpp_ctrl), 361 MPP_FUNC_CTRL(7, 7, "mpp7", dove_pmu_mpp_ctrl), 362 MPP_FUNC_CTRL(8, 8, "mpp8", dove_pmu_mpp_ctrl), 363 MPP_FUNC_CTRL(9, 9, "mpp9", dove_pmu_mpp_ctrl), 364 MPP_FUNC_CTRL(10, 10, "mpp10", dove_pmu_mpp_ctrl), 365 MPP_FUNC_CTRL(11, 11, "mpp11", dove_pmu_mpp_ctrl), 366 MPP_FUNC_CTRL(12, 12, "mpp12", dove_pmu_mpp_ctrl), 367 MPP_FUNC_CTRL(13, 13, "mpp13", dove_pmu_mpp_ctrl), 368 MPP_FUNC_CTRL(14, 14, "mpp14", dove_pmu_mpp_ctrl), 369 MPP_FUNC_CTRL(15, 15, "mpp15", dove_pmu_mpp_ctrl), 370 MPP_REG_CTRL(16, 23), 371 MPP_FUNC_CTRL(24, 39, "mpp_camera", dove_mpp4_ctrl), 372 MPP_FUNC_CTRL(40, 45, "mpp_sdio0", dove_mpp4_ctrl), 373 MPP_FUNC_CTRL(46, 51, "mpp_sdio1", dove_mpp4_ctrl), 374 MPP_FUNC_GPIO_CTRL(52, 57, "mpp_audio1", dove_audio1_ctrl), 375 MPP_FUNC_CTRL(58, 61, "mpp_spi0", dove_mpp4_ctrl), 376 MPP_FUNC_CTRL(62, 63, "mpp_uart1", dove_mpp4_ctrl), 377 MPP_FUNC_CTRL(64, 71, "mpp_nand", dove_nand_ctrl), 378 MPP_FUNC_CTRL(72, 72, "audio0", dove_audio0_ctrl), 379 MPP_FUNC_CTRL(73, 73, "twsi", dove_twsi_ctrl), 380 }; 381 382 static struct mvebu_mpp_mode dove_mpp_modes[] = { 383 MPP_MODE(0, 384 MPP_FUNCTION(0x00, "gpio", NULL), 385 MPP_FUNCTION(0x02, "uart2", "rts"), 386 MPP_FUNCTION(0x03, "sdio0", "cd"), 387 MPP_FUNCTION(0x0f, "lcd0", "pwm"), 388 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 389 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 390 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 391 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 392 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 393 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 394 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 395 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 396 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 397 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 398 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 399 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 400 MPP_MODE(1, 401 MPP_FUNCTION(0x00, "gpio", NULL), 402 MPP_FUNCTION(0x02, "uart2", "cts"), 403 MPP_FUNCTION(0x03, "sdio0", "wp"), 404 MPP_FUNCTION(0x0f, "lcd1", "pwm"), 405 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 406 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 407 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 408 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 409 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 410 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 411 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 412 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 413 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 414 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 415 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 416 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 417 MPP_MODE(2, 418 MPP_FUNCTION(0x00, "gpio", NULL), 419 MPP_FUNCTION(0x01, "sata", "prsnt"), 420 MPP_FUNCTION(0x02, "uart2", "txd"), 421 MPP_FUNCTION(0x03, "sdio0", "buspwr"), 422 MPP_FUNCTION(0x04, "uart1", "rts"), 423 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 424 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 425 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 426 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 427 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 428 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 429 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 430 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 431 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 432 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 433 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 434 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 435 MPP_MODE(3, 436 MPP_FUNCTION(0x00, "gpio", NULL), 437 MPP_FUNCTION(0x01, "sata", "act"), 438 MPP_FUNCTION(0x02, "uart2", "rxd"), 439 MPP_FUNCTION(0x03, "sdio0", "ledctrl"), 440 MPP_FUNCTION(0x04, "uart1", "cts"), 441 MPP_FUNCTION(0x0f, "lcd-spi", "cs1"), 442 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 443 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 444 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 445 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 446 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 447 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 448 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 449 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 450 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 451 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 452 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 453 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 454 MPP_MODE(4, 455 MPP_FUNCTION(0x00, "gpio", NULL), 456 MPP_FUNCTION(0x02, "uart3", "rts"), 457 MPP_FUNCTION(0x03, "sdio1", "cd"), 458 MPP_FUNCTION(0x04, "spi1", "miso"), 459 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 460 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 461 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 462 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 463 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 464 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 465 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 466 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 467 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 468 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 469 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 470 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 471 MPP_MODE(5, 472 MPP_FUNCTION(0x00, "gpio", NULL), 473 MPP_FUNCTION(0x02, "uart3", "cts"), 474 MPP_FUNCTION(0x03, "sdio1", "wp"), 475 MPP_FUNCTION(0x04, "spi1", "cs"), 476 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 477 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 478 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 479 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 480 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 481 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 482 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 483 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 484 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 485 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 486 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 487 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 488 MPP_MODE(6, 489 MPP_FUNCTION(0x00, "gpio", NULL), 490 MPP_FUNCTION(0x02, "uart3", "txd"), 491 MPP_FUNCTION(0x03, "sdio1", "buspwr"), 492 MPP_FUNCTION(0x04, "spi1", "mosi"), 493 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 494 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 495 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 496 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 497 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 498 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 499 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 500 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 501 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 502 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 503 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 504 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 505 MPP_MODE(7, 506 MPP_FUNCTION(0x00, "gpio", NULL), 507 MPP_FUNCTION(0x02, "uart3", "rxd"), 508 MPP_FUNCTION(0x03, "sdio1", "ledctrl"), 509 MPP_FUNCTION(0x04, "spi1", "sck"), 510 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 511 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 512 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 513 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 514 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 515 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 516 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), 517 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 518 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 519 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 520 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 521 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 522 MPP_MODE(8, 523 MPP_FUNCTION(0x00, "gpio", NULL), 524 MPP_FUNCTION(0x01, "watchdog", "rstout"), 525 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 526 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 527 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 528 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 529 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 530 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 531 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 532 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 533 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 534 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 535 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 536 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 537 MPP_MODE(9, 538 MPP_FUNCTION(0x00, "gpio", NULL), 539 MPP_FUNCTION(0x05, "pex1", "clkreq"), 540 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 541 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 542 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 543 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 544 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 545 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 546 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 547 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 548 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 549 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 550 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 551 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 552 MPP_MODE(10, 553 MPP_FUNCTION(0x00, "gpio", NULL), 554 MPP_FUNCTION(0x05, "ssp", "sclk"), 555 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 556 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 557 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 558 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 559 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 560 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 561 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 562 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 563 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 564 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 565 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 566 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 567 MPP_MODE(11, 568 MPP_FUNCTION(0x00, "gpio", NULL), 569 MPP_FUNCTION(0x01, "sata", "prsnt"), 570 MPP_FUNCTION(0x02, "sata-1", "act"), 571 MPP_FUNCTION(0x03, "sdio0", "ledctrl"), 572 MPP_FUNCTION(0x04, "sdio1", "ledctrl"), 573 MPP_FUNCTION(0x05, "pex0", "clkreq"), 574 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 575 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 576 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 577 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 578 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 579 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 580 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 581 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 582 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 583 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 584 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 585 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 586 MPP_MODE(12, 587 MPP_FUNCTION(0x00, "gpio", NULL), 588 MPP_FUNCTION(0x01, "sata", "act"), 589 MPP_FUNCTION(0x02, "uart2", "rts"), 590 MPP_FUNCTION(0x03, "audio0", "extclk"), 591 MPP_FUNCTION(0x04, "sdio1", "cd"), 592 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 593 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 594 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 595 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 596 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 597 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 598 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 599 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 600 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 601 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 602 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 603 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 604 MPP_MODE(13, 605 MPP_FUNCTION(0x00, "gpio", NULL), 606 MPP_FUNCTION(0x02, "uart2", "cts"), 607 MPP_FUNCTION(0x03, "audio1", "extclk"), 608 MPP_FUNCTION(0x04, "sdio1", "wp"), 609 MPP_FUNCTION(0x05, "ssp", "extclk"), 610 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 611 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 612 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 613 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 614 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 615 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 616 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 617 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 618 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 619 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 620 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 621 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 622 MPP_MODE(14, 623 MPP_FUNCTION(0x00, "gpio", NULL), 624 MPP_FUNCTION(0x02, "uart2", "txd"), 625 MPP_FUNCTION(0x04, "sdio1", "buspwr"), 626 MPP_FUNCTION(0x05, "ssp", "rxd"), 627 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 628 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 629 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 630 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 631 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 632 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 633 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 634 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 635 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 636 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 637 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 638 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 639 MPP_MODE(15, 640 MPP_FUNCTION(0x00, "gpio", NULL), 641 MPP_FUNCTION(0x02, "uart2", "rxd"), 642 MPP_FUNCTION(0x04, "sdio1", "ledctrl"), 643 MPP_FUNCTION(0x05, "ssp", "sfrm"), 644 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), 645 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), 646 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), 647 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), 648 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), 649 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), 650 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), 651 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), 652 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), 653 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), 654 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), 655 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), 656 MPP_MODE(16, 657 MPP_FUNCTION(0x00, "gpio", NULL), 658 MPP_FUNCTION(0x02, "uart3", "rts"), 659 MPP_FUNCTION(0x03, "sdio0", "cd"), 660 MPP_FUNCTION(0x04, "lcd-spi", "cs1"), 661 MPP_FUNCTION(0x05, "ac97", "sdi1")), 662 MPP_MODE(17, 663 MPP_FUNCTION(0x00, "gpio", NULL), 664 MPP_FUNCTION(0x01, "ac97-1", "sysclko"), 665 MPP_FUNCTION(0x02, "uart3", "cts"), 666 MPP_FUNCTION(0x03, "sdio0", "wp"), 667 MPP_FUNCTION(0x04, "twsi", "sda"), 668 MPP_FUNCTION(0x05, "ac97", "sdi2")), 669 MPP_MODE(18, 670 MPP_FUNCTION(0x00, "gpio", NULL), 671 MPP_FUNCTION(0x02, "uart3", "txd"), 672 MPP_FUNCTION(0x03, "sdio0", "buspwr"), 673 MPP_FUNCTION(0x04, "lcd0", "pwm"), 674 MPP_FUNCTION(0x05, "ac97", "sdi3")), 675 MPP_MODE(19, 676 MPP_FUNCTION(0x00, "gpio", NULL), 677 MPP_FUNCTION(0x02, "uart3", "rxd"), 678 MPP_FUNCTION(0x03, "sdio0", "ledctrl"), 679 MPP_FUNCTION(0x04, "twsi", "sck")), 680 MPP_MODE(20, 681 MPP_FUNCTION(0x00, "gpio", NULL), 682 MPP_FUNCTION(0x01, "ac97", "sysclko"), 683 MPP_FUNCTION(0x02, "lcd-spi", "miso"), 684 MPP_FUNCTION(0x03, "sdio1", "cd"), 685 MPP_FUNCTION(0x05, "sdio0", "cd"), 686 MPP_FUNCTION(0x06, "spi1", "miso")), 687 MPP_MODE(21, 688 MPP_FUNCTION(0x00, "gpio", NULL), 689 MPP_FUNCTION(0x01, "uart1", "rts"), 690 MPP_FUNCTION(0x02, "lcd-spi", "cs0"), 691 MPP_FUNCTION(0x03, "sdio1", "wp"), 692 MPP_FUNCTION(0x04, "ssp", "sfrm"), 693 MPP_FUNCTION(0x05, "sdio0", "wp"), 694 MPP_FUNCTION(0x06, "spi1", "cs")), 695 MPP_MODE(22, 696 MPP_FUNCTION(0x00, "gpio", NULL), 697 MPP_FUNCTION(0x01, "uart1", "cts"), 698 MPP_FUNCTION(0x02, "lcd-spi", "mosi"), 699 MPP_FUNCTION(0x03, "sdio1", "buspwr"), 700 MPP_FUNCTION(0x04, "ssp", "txd"), 701 MPP_FUNCTION(0x05, "sdio0", "buspwr"), 702 MPP_FUNCTION(0x06, "spi1", "mosi")), 703 MPP_MODE(23, 704 MPP_FUNCTION(0x00, "gpio", NULL), 705 MPP_FUNCTION(0x02, "lcd-spi", "sck"), 706 MPP_FUNCTION(0x03, "sdio1", "ledctrl"), 707 MPP_FUNCTION(0x04, "ssp", "sclk"), 708 MPP_FUNCTION(0x05, "sdio0", "ledctrl"), 709 MPP_FUNCTION(0x06, "spi1", "sck")), 710 MPP_MODE(24, 711 MPP_FUNCTION(0x00, "camera", NULL), 712 MPP_FUNCTION(0x01, "gpio", NULL)), 713 MPP_MODE(40, 714 MPP_FUNCTION(0x00, "sdio0", NULL), 715 MPP_FUNCTION(0x01, "gpio", NULL)), 716 MPP_MODE(46, 717 MPP_FUNCTION(0x00, "sdio1", NULL), 718 MPP_FUNCTION(0x01, "gpio", NULL)), 719 MPP_MODE(52, 720 MPP_FUNCTION(0x00, "i2s1/spdifo", NULL), 721 MPP_FUNCTION(0x02, "i2s1", NULL), 722 MPP_FUNCTION(0x08, "spdifo", NULL), 723 MPP_FUNCTION(0x0a, "gpio", NULL), 724 MPP_FUNCTION(0x0b, "twsi", NULL), 725 MPP_FUNCTION(0x0c, "ssp/spdifo", NULL), 726 MPP_FUNCTION(0x0e, "ssp", NULL), 727 MPP_FUNCTION(0x0f, "ssp/twsi", NULL)), 728 MPP_MODE(58, 729 MPP_FUNCTION(0x00, "spi0", NULL), 730 MPP_FUNCTION(0x01, "gpio", NULL)), 731 MPP_MODE(62, 732 MPP_FUNCTION(0x00, "uart1", NULL), 733 MPP_FUNCTION(0x01, "gpio", NULL)), 734 MPP_MODE(64, 735 MPP_FUNCTION(0x00, "nand", NULL), 736 MPP_FUNCTION(0x01, "gpo", NULL)), 737 MPP_MODE(72, 738 MPP_FUNCTION(0x00, "i2s", NULL), 739 MPP_FUNCTION(0x01, "ac97", NULL)), 740 MPP_MODE(73, 741 MPP_FUNCTION(0x00, "twsi-none", NULL), 742 MPP_FUNCTION(0x01, "twsi-opt1", NULL), 743 MPP_FUNCTION(0x02, "twsi-opt2", NULL), 744 MPP_FUNCTION(0x03, "twsi-opt3", NULL)), 745 }; 746 747 static struct pinctrl_gpio_range dove_mpp_gpio_ranges[] = { 748 MPP_GPIO_RANGE(0, 0, 0, 32), 749 MPP_GPIO_RANGE(1, 32, 32, 32), 750 MPP_GPIO_RANGE(2, 64, 64, 8), 751 }; 752 753 static struct mvebu_pinctrl_soc_info dove_pinctrl_info = { 754 .controls = dove_mpp_controls, 755 .ncontrols = ARRAY_SIZE(dove_mpp_controls), 756 .modes = dove_mpp_modes, 757 .nmodes = ARRAY_SIZE(dove_mpp_modes), 758 .gpioranges = dove_mpp_gpio_ranges, 759 .ngpioranges = ARRAY_SIZE(dove_mpp_gpio_ranges), 760 .variant = 0, 761 }; 762 763 static struct clk *clk; 764 765 static struct of_device_id dove_pinctrl_of_match[] = { 766 { .compatible = "marvell,dove-pinctrl", .data = &dove_pinctrl_info }, 767 { } 768 }; 769 770 static int dove_pinctrl_probe(struct platform_device *pdev) 771 { 772 const struct of_device_id *match = 773 of_match_device(dove_pinctrl_of_match, &pdev->dev); 774 pdev->dev.platform_data = (void *)match->data; 775 776 /* 777 * General MPP Configuration Register is part of pdma registers. 778 * grab clk to make sure it is ticking. 779 */ 780 clk = devm_clk_get(&pdev->dev, NULL); 781 if (IS_ERR(clk)) { 782 dev_err(&pdev->dev, "Unable to get pdma clock"); 783 return PTR_ERR(clk); 784 } 785 clk_prepare_enable(clk); 786 787 return mvebu_pinctrl_probe(pdev); 788 } 789 790 static int dove_pinctrl_remove(struct platform_device *pdev) 791 { 792 int ret; 793 794 ret = mvebu_pinctrl_remove(pdev); 795 if (!IS_ERR(clk)) 796 clk_disable_unprepare(clk); 797 return ret; 798 } 799 800 static struct platform_driver dove_pinctrl_driver = { 801 .driver = { 802 .name = "dove-pinctrl", 803 .owner = THIS_MODULE, 804 .of_match_table = dove_pinctrl_of_match, 805 }, 806 .probe = dove_pinctrl_probe, 807 .remove = dove_pinctrl_remove, 808 }; 809 810 module_platform_driver(dove_pinctrl_driver); 811 812 MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>"); 813 MODULE_DESCRIPTION("Marvell Dove pinctrl driver"); 814 MODULE_LICENSE("GPL v2"); 815