1 /* 2 * Marvell 37xx SoC pinctrl driver 3 * 4 * Copyright (C) 2017 Marvell 5 * 6 * Gregory CLEMENT <gregory.clement@free-electrons.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2 or later. This program is licensed "as is" 10 * without any warranty of any kind, whether express or implied. 11 */ 12 13 #include <linux/gpio/driver.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/of_device.h> 18 #include <linux/of_irq.h> 19 #include <linux/pinctrl/pinconf-generic.h> 20 #include <linux/pinctrl/pinconf.h> 21 #include <linux/pinctrl/pinctrl.h> 22 #include <linux/pinctrl/pinmux.h> 23 #include <linux/platform_device.h> 24 #include <linux/regmap.h> 25 #include <linux/slab.h> 26 27 #include "../pinctrl-utils.h" 28 29 #define OUTPUT_EN 0x0 30 #define INPUT_VAL 0x10 31 #define OUTPUT_VAL 0x18 32 #define OUTPUT_CTL 0x20 33 #define SELECTION 0x30 34 35 #define IRQ_EN 0x0 36 #define IRQ_POL 0x08 37 #define IRQ_STATUS 0x10 38 #define IRQ_WKUP 0x18 39 40 #define NB_FUNCS 2 41 #define GPIO_PER_REG 32 42 43 /** 44 * struct armada_37xx_pin_group: represents group of pins of a pinmux function. 45 * The pins of a pinmux groups are composed of one or two groups of contiguous 46 * pins. 47 * @name: Name of the pin group, used to lookup the group. 48 * @start_pins: Index of the first pin of the main range of pins belonging to 49 * the group 50 * @npins: Number of pins included in the first range 51 * @reg_mask: Bit mask matching the group in the selection register 52 * @extra_pins: Index of the first pin of the optional second range of pins 53 * belonging to the group 54 * @npins: Number of pins included in the second optional range 55 * @funcs: A list of pinmux functions that can be selected for this group. 56 * @pins: List of the pins included in the group 57 */ 58 struct armada_37xx_pin_group { 59 const char *name; 60 unsigned int start_pin; 61 unsigned int npins; 62 u32 reg_mask; 63 u32 val[NB_FUNCS]; 64 unsigned int extra_pin; 65 unsigned int extra_npins; 66 const char *funcs[NB_FUNCS]; 67 unsigned int *pins; 68 }; 69 70 struct armada_37xx_pin_data { 71 u8 nr_pins; 72 char *name; 73 struct armada_37xx_pin_group *groups; 74 int ngroups; 75 }; 76 77 struct armada_37xx_pmx_func { 78 const char *name; 79 const char **groups; 80 unsigned int ngroups; 81 }; 82 83 struct armada_37xx_pinctrl { 84 struct regmap *regmap; 85 void __iomem *base; 86 const struct armada_37xx_pin_data *data; 87 struct device *dev; 88 struct gpio_chip gpio_chip; 89 struct irq_chip irq_chip; 90 spinlock_t irq_lock; 91 struct pinctrl_desc pctl; 92 struct pinctrl_dev *pctl_dev; 93 struct armada_37xx_pin_group *groups; 94 unsigned int ngroups; 95 struct armada_37xx_pmx_func *funcs; 96 unsigned int nfuncs; 97 }; 98 99 #define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \ 100 { \ 101 .name = _name, \ 102 .start_pin = _start, \ 103 .npins = _nr, \ 104 .reg_mask = _mask, \ 105 .val = {0, _mask}, \ 106 .funcs = {_func1, _func2} \ 107 } 108 109 #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \ 110 { \ 111 .name = _name, \ 112 .start_pin = _start, \ 113 .npins = _nr, \ 114 .reg_mask = _mask, \ 115 .val = {0, _mask}, \ 116 .funcs = {_func1, "gpio"} \ 117 } 118 119 #define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \ 120 { \ 121 .name = _name, \ 122 .start_pin = _start, \ 123 .npins = _nr, \ 124 .reg_mask = _mask, \ 125 .val = {_val1, _val2}, \ 126 .funcs = {_func1, "gpio"} \ 127 } 128 129 #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \ 130 _f1, _f2) \ 131 { \ 132 .name = _name, \ 133 .start_pin = _start, \ 134 .npins = _nr, \ 135 .reg_mask = _mask, \ 136 .val = {_v1, _v2}, \ 137 .extra_pin = _start2, \ 138 .extra_npins = _nr2, \ 139 .funcs = {_f1, _f2} \ 140 } 141 142 static struct armada_37xx_pin_group armada_37xx_nb_groups[] = { 143 PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"), 144 PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"), 145 PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"), 146 PIN_GRP_GPIO("pwm0", 11, 1, BIT(3), "pwm"), 147 PIN_GRP_GPIO("pwm1", 12, 1, BIT(4), "pwm"), 148 PIN_GRP_GPIO("pwm2", 13, 1, BIT(5), "pwm"), 149 PIN_GRP_GPIO("pwm3", 14, 1, BIT(6), "pwm"), 150 PIN_GRP_GPIO("pmic1", 17, 1, BIT(7), "pmic"), 151 PIN_GRP_GPIO("pmic0", 16, 1, BIT(8), "pmic"), 152 PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"), 153 PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"), 154 PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"), 155 PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"), 156 PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"), 157 PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"), 158 PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"), 159 PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"), 160 PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19), 161 BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19), 162 18, 2, "gpio", "uart"), 163 PIN_GRP_GPIO("led0_od", 11, 1, BIT(20), "led"), 164 PIN_GRP_GPIO("led1_od", 12, 1, BIT(21), "led"), 165 PIN_GRP_GPIO("led2_od", 13, 1, BIT(22), "led"), 166 PIN_GRP_GPIO("led3_od", 14, 1, BIT(23), "led"), 167 168 }; 169 170 static struct armada_37xx_pin_group armada_37xx_sb_groups[] = { 171 PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"), 172 PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"), 173 PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"), 174 PIN_GRP_EXTRA("rgmii", 6, 12, BIT(3), 0, BIT(3), 23, 1, "mii", "gpio"), 175 PIN_GRP_GPIO("pcie1", 3, 2, BIT(4), "pcie"), 176 PIN_GRP_GPIO("ptp", 20, 3, BIT(5), "ptp"), 177 PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"), 178 PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"), 179 PIN_GRP("mii_col", 23, 1, BIT(8), "mii", "mii_err"), 180 }; 181 182 const struct armada_37xx_pin_data armada_37xx_pin_nb = { 183 .nr_pins = 36, 184 .name = "GPIO1", 185 .groups = armada_37xx_nb_groups, 186 .ngroups = ARRAY_SIZE(armada_37xx_nb_groups), 187 }; 188 189 const struct armada_37xx_pin_data armada_37xx_pin_sb = { 190 .nr_pins = 29, 191 .name = "GPIO2", 192 .groups = armada_37xx_sb_groups, 193 .ngroups = ARRAY_SIZE(armada_37xx_sb_groups), 194 }; 195 196 static inline void armada_37xx_update_reg(unsigned int *reg, 197 unsigned int offset) 198 { 199 /* We never have more than 2 registers */ 200 if (offset >= GPIO_PER_REG) { 201 offset -= GPIO_PER_REG; 202 *reg += sizeof(u32); 203 } 204 } 205 206 static int armada_37xx_get_func_reg(struct armada_37xx_pin_group *grp, 207 const char *func) 208 { 209 int f; 210 211 for (f = 0; f < NB_FUNCS; f++) 212 if (!strcmp(grp->funcs[f], func)) 213 return f; 214 215 return -ENOTSUPP; 216 } 217 218 static struct armada_37xx_pin_group *armada_37xx_find_next_grp_by_pin( 219 struct armada_37xx_pinctrl *info, int pin, int *grp) 220 { 221 while (*grp < info->ngroups) { 222 struct armada_37xx_pin_group *group = &info->groups[*grp]; 223 int j; 224 225 *grp = *grp + 1; 226 for (j = 0; j < (group->npins + group->extra_npins); j++) 227 if (group->pins[j] == pin) 228 return group; 229 } 230 return NULL; 231 } 232 233 static int armada_37xx_pin_config_group_get(struct pinctrl_dev *pctldev, 234 unsigned int selector, unsigned long *config) 235 { 236 return -ENOTSUPP; 237 } 238 239 static int armada_37xx_pin_config_group_set(struct pinctrl_dev *pctldev, 240 unsigned int selector, unsigned long *configs, 241 unsigned int num_configs) 242 { 243 return -ENOTSUPP; 244 } 245 246 static struct pinconf_ops armada_37xx_pinconf_ops = { 247 .is_generic = true, 248 .pin_config_group_get = armada_37xx_pin_config_group_get, 249 .pin_config_group_set = armada_37xx_pin_config_group_set, 250 }; 251 252 static int armada_37xx_get_groups_count(struct pinctrl_dev *pctldev) 253 { 254 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 255 256 return info->ngroups; 257 } 258 259 static const char *armada_37xx_get_group_name(struct pinctrl_dev *pctldev, 260 unsigned int group) 261 { 262 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 263 264 return info->groups[group].name; 265 } 266 267 static int armada_37xx_get_group_pins(struct pinctrl_dev *pctldev, 268 unsigned int selector, 269 const unsigned int **pins, 270 unsigned int *npins) 271 { 272 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 273 274 if (selector >= info->ngroups) 275 return -EINVAL; 276 277 *pins = info->groups[selector].pins; 278 *npins = info->groups[selector].npins + 279 info->groups[selector].extra_npins; 280 281 return 0; 282 } 283 284 static const struct pinctrl_ops armada_37xx_pctrl_ops = { 285 .get_groups_count = armada_37xx_get_groups_count, 286 .get_group_name = armada_37xx_get_group_name, 287 .get_group_pins = armada_37xx_get_group_pins, 288 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 289 .dt_free_map = pinctrl_utils_free_map, 290 }; 291 292 /* 293 * Pinmux_ops handling 294 */ 295 296 static int armada_37xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 297 { 298 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 299 300 return info->nfuncs; 301 } 302 303 static const char *armada_37xx_pmx_get_func_name(struct pinctrl_dev *pctldev, 304 unsigned int selector) 305 { 306 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 307 308 return info->funcs[selector].name; 309 } 310 311 static int armada_37xx_pmx_get_groups(struct pinctrl_dev *pctldev, 312 unsigned int selector, 313 const char * const **groups, 314 unsigned int * const num_groups) 315 { 316 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 317 318 *groups = info->funcs[selector].groups; 319 *num_groups = info->funcs[selector].ngroups; 320 321 return 0; 322 } 323 324 static int armada_37xx_pmx_set_by_name(struct pinctrl_dev *pctldev, 325 const char *name, 326 struct armada_37xx_pin_group *grp) 327 { 328 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 329 unsigned int reg = SELECTION; 330 unsigned int mask = grp->reg_mask; 331 int func, val; 332 333 dev_dbg(info->dev, "enable function %s group %s\n", 334 name, grp->name); 335 336 func = armada_37xx_get_func_reg(grp, name); 337 338 if (func < 0) 339 return func; 340 341 val = grp->val[func]; 342 343 regmap_update_bits(info->regmap, reg, mask, val); 344 345 return 0; 346 } 347 348 static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev, 349 unsigned int selector, 350 unsigned int group) 351 { 352 353 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 354 struct armada_37xx_pin_group *grp = &info->groups[group]; 355 const char *name = info->funcs[selector].name; 356 357 return armada_37xx_pmx_set_by_name(pctldev, name, grp); 358 } 359 360 static inline void armada_37xx_irq_update_reg(unsigned int *reg, 361 struct irq_data *d) 362 { 363 int offset = irqd_to_hwirq(d); 364 365 armada_37xx_update_reg(reg, offset); 366 } 367 368 static int armada_37xx_gpio_direction_input(struct gpio_chip *chip, 369 unsigned int offset) 370 { 371 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 372 unsigned int reg = OUTPUT_EN; 373 unsigned int mask; 374 375 armada_37xx_update_reg(®, offset); 376 mask = BIT(offset); 377 378 return regmap_update_bits(info->regmap, reg, mask, 0); 379 } 380 381 static int armada_37xx_gpio_get_direction(struct gpio_chip *chip, 382 unsigned int offset) 383 { 384 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 385 unsigned int reg = OUTPUT_EN; 386 unsigned int val, mask; 387 388 armada_37xx_update_reg(®, offset); 389 mask = BIT(offset); 390 regmap_read(info->regmap, reg, &val); 391 392 return !(val & mask); 393 } 394 395 static int armada_37xx_gpio_direction_output(struct gpio_chip *chip, 396 unsigned int offset, int value) 397 { 398 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 399 unsigned int reg = OUTPUT_EN; 400 unsigned int mask; 401 402 armada_37xx_update_reg(®, offset); 403 mask = BIT(offset); 404 405 return regmap_update_bits(info->regmap, reg, mask, mask); 406 } 407 408 static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset) 409 { 410 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 411 unsigned int reg = INPUT_VAL; 412 unsigned int val, mask; 413 414 armada_37xx_update_reg(®, offset); 415 mask = BIT(offset); 416 417 regmap_read(info->regmap, reg, &val); 418 419 return (val & mask) != 0; 420 } 421 422 static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset, 423 int value) 424 { 425 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 426 unsigned int reg = OUTPUT_VAL; 427 unsigned int mask, val; 428 429 armada_37xx_update_reg(®, offset); 430 mask = BIT(offset); 431 val = value ? mask : 0; 432 433 regmap_update_bits(info->regmap, reg, mask, val); 434 } 435 436 static int armada_37xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 437 struct pinctrl_gpio_range *range, 438 unsigned int offset, bool input) 439 { 440 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 441 struct gpio_chip *chip = range->gc; 442 443 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", 444 offset, range->name, offset, input ? "input" : "output"); 445 446 if (input) 447 armada_37xx_gpio_direction_input(chip, offset); 448 else 449 armada_37xx_gpio_direction_output(chip, offset, 0); 450 451 return 0; 452 } 453 454 static int armada_37xx_gpio_request_enable(struct pinctrl_dev *pctldev, 455 struct pinctrl_gpio_range *range, 456 unsigned int offset) 457 { 458 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 459 struct armada_37xx_pin_group *group; 460 int grp = 0; 461 462 dev_dbg(info->dev, "requesting gpio %d\n", offset); 463 464 while ((group = armada_37xx_find_next_grp_by_pin(info, offset, &grp))) 465 armada_37xx_pmx_set_by_name(pctldev, "gpio", group); 466 467 return 0; 468 } 469 470 static const struct pinmux_ops armada_37xx_pmx_ops = { 471 .get_functions_count = armada_37xx_pmx_get_funcs_count, 472 .get_function_name = armada_37xx_pmx_get_func_name, 473 .get_function_groups = armada_37xx_pmx_get_groups, 474 .set_mux = armada_37xx_pmx_set, 475 .gpio_request_enable = armada_37xx_gpio_request_enable, 476 .gpio_set_direction = armada_37xx_pmx_gpio_set_direction, 477 }; 478 479 static const struct gpio_chip armada_37xx_gpiolib_chip = { 480 .request = gpiochip_generic_request, 481 .free = gpiochip_generic_free, 482 .set = armada_37xx_gpio_set, 483 .get = armada_37xx_gpio_get, 484 .get_direction = armada_37xx_gpio_get_direction, 485 .direction_input = armada_37xx_gpio_direction_input, 486 .direction_output = armada_37xx_gpio_direction_output, 487 .owner = THIS_MODULE, 488 }; 489 490 static void armada_37xx_irq_ack(struct irq_data *d) 491 { 492 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 493 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 494 u32 reg = IRQ_STATUS; 495 unsigned long flags; 496 497 armada_37xx_irq_update_reg(®, d); 498 spin_lock_irqsave(&info->irq_lock, flags); 499 writel(d->mask, info->base + reg); 500 spin_unlock_irqrestore(&info->irq_lock, flags); 501 } 502 503 static void armada_37xx_irq_mask(struct irq_data *d) 504 { 505 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 506 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 507 u32 val, reg = IRQ_EN; 508 unsigned long flags; 509 510 armada_37xx_irq_update_reg(®, d); 511 spin_lock_irqsave(&info->irq_lock, flags); 512 val = readl(info->base + reg); 513 writel(val & ~d->mask, info->base + reg); 514 spin_unlock_irqrestore(&info->irq_lock, flags); 515 } 516 517 static void armada_37xx_irq_unmask(struct irq_data *d) 518 { 519 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 520 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 521 u32 val, reg = IRQ_EN; 522 unsigned long flags; 523 524 armada_37xx_irq_update_reg(®, d); 525 spin_lock_irqsave(&info->irq_lock, flags); 526 val = readl(info->base + reg); 527 writel(val | d->mask, info->base + reg); 528 spin_unlock_irqrestore(&info->irq_lock, flags); 529 } 530 531 static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on) 532 { 533 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 534 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 535 u32 val, reg = IRQ_WKUP; 536 unsigned long flags; 537 538 armada_37xx_irq_update_reg(®, d); 539 spin_lock_irqsave(&info->irq_lock, flags); 540 val = readl(info->base + reg); 541 if (on) 542 val |= d->mask; 543 else 544 val &= ~d->mask; 545 writel(val, info->base + reg); 546 spin_unlock_irqrestore(&info->irq_lock, flags); 547 548 return 0; 549 } 550 551 static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type) 552 { 553 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 554 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 555 u32 val, reg = IRQ_POL; 556 unsigned long flags; 557 558 spin_lock_irqsave(&info->irq_lock, flags); 559 armada_37xx_irq_update_reg(®, d); 560 val = readl(info->base + reg); 561 switch (type) { 562 case IRQ_TYPE_EDGE_RISING: 563 val &= ~d->mask; 564 break; 565 case IRQ_TYPE_EDGE_FALLING: 566 val |= d->mask; 567 break; 568 default: 569 spin_unlock_irqrestore(&info->irq_lock, flags); 570 return -EINVAL; 571 } 572 writel(val, info->base + reg); 573 spin_unlock_irqrestore(&info->irq_lock, flags); 574 575 return 0; 576 } 577 578 579 static void armada_37xx_irq_handler(struct irq_desc *desc) 580 { 581 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 582 struct irq_chip *chip = irq_desc_get_chip(desc); 583 struct armada_37xx_pinctrl *info = gpiochip_get_data(gc); 584 struct irq_domain *d = gc->irqdomain; 585 int i; 586 587 chained_irq_enter(chip, desc); 588 for (i = 0; i <= d->revmap_size / GPIO_PER_REG; i++) { 589 u32 status; 590 unsigned long flags; 591 592 spin_lock_irqsave(&info->irq_lock, flags); 593 status = readl_relaxed(info->base + IRQ_STATUS + 4 * i); 594 /* Manage only the interrupt that was enabled */ 595 status &= readl_relaxed(info->base + IRQ_EN + 4 * i); 596 spin_unlock_irqrestore(&info->irq_lock, flags); 597 while (status) { 598 u32 hwirq = ffs(status) - 1; 599 u32 virq = irq_find_mapping(d, hwirq + 600 i * GPIO_PER_REG); 601 602 generic_handle_irq(virq); 603 604 /* Update status in case a new IRQ appears */ 605 spin_lock_irqsave(&info->irq_lock, flags); 606 status = readl_relaxed(info->base + 607 IRQ_STATUS + 4 * i); 608 /* Manage only the interrupt that was enabled */ 609 status &= readl_relaxed(info->base + IRQ_EN + 4 * i); 610 spin_unlock_irqrestore(&info->irq_lock, flags); 611 } 612 } 613 chained_irq_exit(chip, desc); 614 } 615 616 static int armada_37xx_irqchip_register(struct platform_device *pdev, 617 struct armada_37xx_pinctrl *info) 618 { 619 struct device_node *np = info->dev->of_node; 620 int nrirqs = info->data->nr_pins; 621 struct gpio_chip *gc = &info->gpio_chip; 622 struct irq_chip *irqchip = &info->irq_chip; 623 struct resource res; 624 int ret = -ENODEV, i, nr_irq_parent; 625 626 /* Check if we have at least one gpio-controller child node */ 627 for_each_child_of_node(info->dev->of_node, np) { 628 if (of_property_read_bool(np, "gpio-controller")) { 629 ret = 0; 630 break; 631 } 632 }; 633 if (ret) 634 return ret; 635 636 nr_irq_parent = of_irq_count(np); 637 spin_lock_init(&info->irq_lock); 638 639 if (!nr_irq_parent) { 640 dev_err(&pdev->dev, "Invalid or no IRQ\n"); 641 return 0; 642 } 643 644 if (of_address_to_resource(info->dev->of_node, 1, &res)) { 645 dev_err(info->dev, "cannot find IO resource\n"); 646 return -ENOENT; 647 } 648 649 info->base = devm_ioremap_resource(info->dev, &res); 650 if (IS_ERR(info->base)) 651 return PTR_ERR(info->base); 652 653 irqchip->irq_ack = armada_37xx_irq_ack; 654 irqchip->irq_mask = armada_37xx_irq_mask; 655 irqchip->irq_unmask = armada_37xx_irq_unmask; 656 irqchip->irq_set_wake = armada_37xx_irq_set_wake; 657 irqchip->irq_set_type = armada_37xx_irq_set_type; 658 irqchip->name = info->data->name; 659 660 ret = gpiochip_irqchip_add(gc, irqchip, 0, 661 handle_edge_irq, IRQ_TYPE_NONE); 662 if (ret) { 663 dev_info(&pdev->dev, "could not add irqchip\n"); 664 return ret; 665 } 666 667 /* 668 * Many interrupts are connected to the parent interrupt 669 * controller. But we do not take advantage of this and use 670 * the chained irq with all of them. 671 */ 672 for (i = 0; i < nrirqs; i++) { 673 struct irq_data *d = irq_get_irq_data(gc->irq_base + i); 674 675 /* 676 * The mask field is a "precomputed bitmask for 677 * accessing the chip registers" which was introduced 678 * for the generic irqchip framework. As we don't use 679 * this framework, we can reuse this field for our own 680 * usage. 681 */ 682 d->mask = BIT(i % GPIO_PER_REG); 683 } 684 685 for (i = 0; i < nr_irq_parent; i++) { 686 int irq = irq_of_parse_and_map(np, i); 687 688 if (irq < 0) 689 continue; 690 691 gpiochip_set_chained_irqchip(gc, irqchip, irq, 692 armada_37xx_irq_handler); 693 } 694 695 return 0; 696 } 697 698 static int armada_37xx_gpiochip_register(struct platform_device *pdev, 699 struct armada_37xx_pinctrl *info) 700 { 701 struct device_node *np; 702 struct gpio_chip *gc; 703 int ret = -ENODEV; 704 705 for_each_child_of_node(info->dev->of_node, np) { 706 if (of_find_property(np, "gpio-controller", NULL)) { 707 ret = 0; 708 break; 709 } 710 }; 711 if (ret) 712 return ret; 713 714 info->gpio_chip = armada_37xx_gpiolib_chip; 715 716 gc = &info->gpio_chip; 717 gc->ngpio = info->data->nr_pins; 718 gc->parent = &pdev->dev; 719 gc->base = -1; 720 gc->of_node = np; 721 gc->label = info->data->name; 722 723 ret = devm_gpiochip_add_data(&pdev->dev, gc, info); 724 if (ret) 725 return ret; 726 ret = armada_37xx_irqchip_register(pdev, info); 727 if (ret) 728 return ret; 729 730 return 0; 731 } 732 733 /** 734 * armada_37xx_add_function() - Add a new function to the list 735 * @funcs: array of function to add the new one 736 * @funcsize: size of the remaining space for the function 737 * @name: name of the function to add 738 * 739 * If it is a new function then create it by adding its name else 740 * increment the number of group associated to this function. 741 */ 742 static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs, 743 int *funcsize, const char *name) 744 { 745 int i = 0; 746 747 if (*funcsize <= 0) 748 return -EOVERFLOW; 749 750 while (funcs->ngroups) { 751 /* function already there */ 752 if (strcmp(funcs->name, name) == 0) { 753 funcs->ngroups++; 754 755 return -EEXIST; 756 } 757 funcs++; 758 i++; 759 } 760 761 /* append new unique function */ 762 funcs->name = name; 763 funcs->ngroups = 1; 764 (*funcsize)--; 765 766 return 0; 767 } 768 769 /** 770 * armada_37xx_fill_group() - complete the group array 771 * @info: info driver instance 772 * 773 * Based on the data available from the armada_37xx_pin_group array 774 * completes the last member of the struct for each function: the list 775 * of the groups associated to this function. 776 * 777 */ 778 static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info) 779 { 780 int n, num = 0, funcsize = info->data->nr_pins; 781 782 for (n = 0; n < info->ngroups; n++) { 783 struct armada_37xx_pin_group *grp = &info->groups[n]; 784 int i, j, f; 785 786 grp->pins = devm_kzalloc(info->dev, 787 (grp->npins + grp->extra_npins) * 788 sizeof(*grp->pins), GFP_KERNEL); 789 if (!grp->pins) 790 return -ENOMEM; 791 792 for (i = 0; i < grp->npins; i++) 793 grp->pins[i] = grp->start_pin + i; 794 795 for (j = 0; j < grp->extra_npins; j++) 796 grp->pins[i+j] = grp->extra_pin + j; 797 798 for (f = 0; f < NB_FUNCS; f++) { 799 int ret; 800 /* check for unique functions and count groups */ 801 ret = armada_37xx_add_function(info->funcs, &funcsize, 802 grp->funcs[f]); 803 if (ret == -EOVERFLOW) 804 dev_err(info->dev, 805 "More functions than pins(%d)\n", 806 info->data->nr_pins); 807 if (ret < 0) 808 continue; 809 num++; 810 } 811 } 812 813 info->nfuncs = num; 814 815 return 0; 816 } 817 818 /** 819 * armada_37xx_fill_funcs() - complete the funcs array 820 * @info: info driver instance 821 * 822 * Based on the data available from the armada_37xx_pin_group array 823 * completes the last two member of the struct for each group: 824 * - the list of the pins included in the group 825 * - the list of pinmux functions that can be selected for this group 826 * 827 */ 828 static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info) 829 { 830 struct armada_37xx_pmx_func *funcs = info->funcs; 831 int n; 832 833 for (n = 0; n < info->nfuncs; n++) { 834 const char *name = funcs[n].name; 835 const char **groups; 836 int g; 837 838 funcs[n].groups = devm_kzalloc(info->dev, funcs[n].ngroups * 839 sizeof(*(funcs[n].groups)), 840 GFP_KERNEL); 841 if (!funcs[n].groups) 842 return -ENOMEM; 843 844 groups = funcs[n].groups; 845 846 for (g = 0; g < info->ngroups; g++) { 847 struct armada_37xx_pin_group *gp = &info->groups[g]; 848 int f; 849 850 for (f = 0; f < NB_FUNCS; f++) { 851 if (strcmp(gp->funcs[f], name) == 0) { 852 *groups = gp->name; 853 groups++; 854 } 855 } 856 } 857 } 858 return 0; 859 } 860 861 static int armada_37xx_pinctrl_register(struct platform_device *pdev, 862 struct armada_37xx_pinctrl *info) 863 { 864 const struct armada_37xx_pin_data *pin_data = info->data; 865 struct pinctrl_desc *ctrldesc = &info->pctl; 866 struct pinctrl_pin_desc *pindesc, *pdesc; 867 int pin, ret; 868 869 info->groups = pin_data->groups; 870 info->ngroups = pin_data->ngroups; 871 872 ctrldesc->name = "armada_37xx-pinctrl"; 873 ctrldesc->owner = THIS_MODULE; 874 ctrldesc->pctlops = &armada_37xx_pctrl_ops; 875 ctrldesc->pmxops = &armada_37xx_pmx_ops; 876 ctrldesc->confops = &armada_37xx_pinconf_ops; 877 878 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) * 879 pin_data->nr_pins, GFP_KERNEL); 880 if (!pindesc) 881 return -ENOMEM; 882 883 ctrldesc->pins = pindesc; 884 ctrldesc->npins = pin_data->nr_pins; 885 886 pdesc = pindesc; 887 for (pin = 0; pin < pin_data->nr_pins; pin++) { 888 pdesc->number = pin; 889 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", 890 pin_data->name, pin); 891 pdesc++; 892 } 893 894 /* 895 * we allocate functions for number of pins and hope there are 896 * fewer unique functions than pins available 897 */ 898 info->funcs = devm_kzalloc(&pdev->dev, pin_data->nr_pins * 899 sizeof(struct armada_37xx_pmx_func), GFP_KERNEL); 900 if (!info->funcs) 901 return -ENOMEM; 902 903 904 ret = armada_37xx_fill_group(info); 905 if (ret) 906 return ret; 907 908 ret = armada_37xx_fill_func(info); 909 if (ret) 910 return ret; 911 912 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info); 913 if (IS_ERR(info->pctl_dev)) { 914 dev_err(&pdev->dev, "could not register pinctrl driver\n"); 915 return PTR_ERR(info->pctl_dev); 916 } 917 918 return 0; 919 } 920 921 static const struct of_device_id armada_37xx_pinctrl_of_match[] = { 922 { 923 .compatible = "marvell,armada3710-sb-pinctrl", 924 .data = (void *)&armada_37xx_pin_sb, 925 }, 926 { 927 .compatible = "marvell,armada3710-nb-pinctrl", 928 .data = (void *)&armada_37xx_pin_nb, 929 }, 930 { }, 931 }; 932 933 static int __init armada_37xx_pinctrl_probe(struct platform_device *pdev) 934 { 935 struct armada_37xx_pinctrl *info; 936 struct device *dev = &pdev->dev; 937 struct device_node *np = dev->of_node; 938 struct regmap *regmap; 939 int ret; 940 941 info = devm_kzalloc(dev, sizeof(struct armada_37xx_pinctrl), 942 GFP_KERNEL); 943 if (!info) 944 return -ENOMEM; 945 946 info->dev = dev; 947 948 regmap = syscon_node_to_regmap(np); 949 if (IS_ERR(regmap)) { 950 dev_err(&pdev->dev, "cannot get regmap\n"); 951 return PTR_ERR(regmap); 952 } 953 info->regmap = regmap; 954 955 info->data = of_device_get_match_data(dev); 956 957 ret = armada_37xx_pinctrl_register(pdev, info); 958 if (ret) 959 return ret; 960 961 ret = armada_37xx_gpiochip_register(pdev, info); 962 if (ret) 963 return ret; 964 965 platform_set_drvdata(pdev, info); 966 967 return 0; 968 } 969 970 static struct platform_driver armada_37xx_pinctrl_driver = { 971 .driver = { 972 .name = "armada-37xx-pinctrl", 973 .of_match_table = armada_37xx_pinctrl_of_match, 974 }, 975 }; 976 977 builtin_platform_driver_probe(armada_37xx_pinctrl_driver, 978 armada_37xx_pinctrl_probe); 979