1 /* 2 * Marvell 37xx SoC pinctrl driver 3 * 4 * Copyright (C) 2017 Marvell 5 * 6 * Gregory CLEMENT <gregory.clement@free-electrons.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2 or later. This program is licensed "as is" 10 * without any warranty of any kind, whether express or implied. 11 */ 12 13 #include <linux/gpio/driver.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/of_device.h> 18 #include <linux/of_irq.h> 19 #include <linux/pinctrl/pinconf-generic.h> 20 #include <linux/pinctrl/pinconf.h> 21 #include <linux/pinctrl/pinctrl.h> 22 #include <linux/pinctrl/pinmux.h> 23 #include <linux/platform_device.h> 24 #include <linux/regmap.h> 25 #include <linux/slab.h> 26 27 #include "../pinctrl-utils.h" 28 29 #define OUTPUT_EN 0x0 30 #define INPUT_VAL 0x10 31 #define OUTPUT_VAL 0x18 32 #define OUTPUT_CTL 0x20 33 #define SELECTION 0x30 34 35 #define IRQ_EN 0x0 36 #define IRQ_POL 0x08 37 #define IRQ_STATUS 0x10 38 #define IRQ_WKUP 0x18 39 40 #define NB_FUNCS 3 41 #define GPIO_PER_REG 32 42 43 /** 44 * struct armada_37xx_pin_group: represents group of pins of a pinmux function. 45 * The pins of a pinmux groups are composed of one or two groups of contiguous 46 * pins. 47 * @name: Name of the pin group, used to lookup the group. 48 * @start_pins: Index of the first pin of the main range of pins belonging to 49 * the group 50 * @npins: Number of pins included in the first range 51 * @reg_mask: Bit mask matching the group in the selection register 52 * @extra_pins: Index of the first pin of the optional second range of pins 53 * belonging to the group 54 * @npins: Number of pins included in the second optional range 55 * @funcs: A list of pinmux functions that can be selected for this group. 56 * @pins: List of the pins included in the group 57 */ 58 struct armada_37xx_pin_group { 59 const char *name; 60 unsigned int start_pin; 61 unsigned int npins; 62 u32 reg_mask; 63 u32 val[NB_FUNCS]; 64 unsigned int extra_pin; 65 unsigned int extra_npins; 66 const char *funcs[NB_FUNCS]; 67 unsigned int *pins; 68 }; 69 70 struct armada_37xx_pin_data { 71 u8 nr_pins; 72 char *name; 73 struct armada_37xx_pin_group *groups; 74 int ngroups; 75 }; 76 77 struct armada_37xx_pmx_func { 78 const char *name; 79 const char **groups; 80 unsigned int ngroups; 81 }; 82 83 struct armada_37xx_pm_state { 84 u32 out_en_l; 85 u32 out_en_h; 86 u32 out_val_l; 87 u32 out_val_h; 88 u32 irq_en_l; 89 u32 irq_en_h; 90 u32 irq_pol_l; 91 u32 irq_pol_h; 92 u32 selection; 93 }; 94 95 struct armada_37xx_pinctrl { 96 struct regmap *regmap; 97 void __iomem *base; 98 const struct armada_37xx_pin_data *data; 99 struct device *dev; 100 struct gpio_chip gpio_chip; 101 struct irq_chip irq_chip; 102 spinlock_t irq_lock; 103 struct pinctrl_desc pctl; 104 struct pinctrl_dev *pctl_dev; 105 struct armada_37xx_pin_group *groups; 106 unsigned int ngroups; 107 struct armada_37xx_pmx_func *funcs; 108 unsigned int nfuncs; 109 struct armada_37xx_pm_state pm; 110 }; 111 112 #define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \ 113 { \ 114 .name = _name, \ 115 .start_pin = _start, \ 116 .npins = _nr, \ 117 .reg_mask = _mask, \ 118 .val = {0, _mask}, \ 119 .funcs = {_func1, _func2} \ 120 } 121 122 #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \ 123 { \ 124 .name = _name, \ 125 .start_pin = _start, \ 126 .npins = _nr, \ 127 .reg_mask = _mask, \ 128 .val = {0, _mask}, \ 129 .funcs = {_func1, "gpio"} \ 130 } 131 132 #define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \ 133 { \ 134 .name = _name, \ 135 .start_pin = _start, \ 136 .npins = _nr, \ 137 .reg_mask = _mask, \ 138 .val = {_val1, _val2}, \ 139 .funcs = {_func1, "gpio"} \ 140 } 141 142 #define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \ 143 { \ 144 .name = _name, \ 145 .start_pin = _start, \ 146 .npins = _nr, \ 147 .reg_mask = _mask, \ 148 .val = {_v1, _v2, _v3}, \ 149 .funcs = {_f1, _f2, "gpio"} \ 150 } 151 152 #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \ 153 _f1, _f2) \ 154 { \ 155 .name = _name, \ 156 .start_pin = _start, \ 157 .npins = _nr, \ 158 .reg_mask = _mask, \ 159 .val = {_v1, _v2}, \ 160 .extra_pin = _start2, \ 161 .extra_npins = _nr2, \ 162 .funcs = {_f1, _f2} \ 163 } 164 165 static struct armada_37xx_pin_group armada_37xx_nb_groups[] = { 166 PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"), 167 PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"), 168 PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"), 169 PIN_GRP_GPIO("pwm0", 11, 1, BIT(3), "pwm"), 170 PIN_GRP_GPIO("pwm1", 12, 1, BIT(4), "pwm"), 171 PIN_GRP_GPIO("pwm2", 13, 1, BIT(5), "pwm"), 172 PIN_GRP_GPIO("pwm3", 14, 1, BIT(6), "pwm"), 173 PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"), 174 PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"), 175 PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"), 176 PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"), 177 PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"), 178 PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"), 179 PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"), 180 PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"), 181 PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"), 182 PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"), 183 PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19), 184 BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19), 185 18, 2, "gpio", "uart"), 186 PIN_GRP_GPIO_2("led0_od", 11, 1, BIT(20), BIT(20), 0, "led"), 187 PIN_GRP_GPIO_2("led1_od", 12, 1, BIT(21), BIT(21), 0, "led"), 188 PIN_GRP_GPIO_2("led2_od", 13, 1, BIT(22), BIT(22), 0, "led"), 189 PIN_GRP_GPIO_2("led3_od", 14, 1, BIT(23), BIT(23), 0, "led"), 190 191 }; 192 193 static struct armada_37xx_pin_group armada_37xx_sb_groups[] = { 194 PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"), 195 PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"), 196 PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"), 197 PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"), 198 PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"), 199 PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), 200 PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"), 201 PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"), 202 PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"), 203 PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"), 204 PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"), 205 PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14), 206 "mii", "mii_err"), 207 }; 208 209 static const struct armada_37xx_pin_data armada_37xx_pin_nb = { 210 .nr_pins = 36, 211 .name = "GPIO1", 212 .groups = armada_37xx_nb_groups, 213 .ngroups = ARRAY_SIZE(armada_37xx_nb_groups), 214 }; 215 216 static const struct armada_37xx_pin_data armada_37xx_pin_sb = { 217 .nr_pins = 30, 218 .name = "GPIO2", 219 .groups = armada_37xx_sb_groups, 220 .ngroups = ARRAY_SIZE(armada_37xx_sb_groups), 221 }; 222 223 static inline void armada_37xx_update_reg(unsigned int *reg, 224 unsigned int *offset) 225 { 226 /* We never have more than 2 registers */ 227 if (*offset >= GPIO_PER_REG) { 228 *offset -= GPIO_PER_REG; 229 *reg += sizeof(u32); 230 } 231 } 232 233 static struct armada_37xx_pin_group *armada_37xx_find_next_grp_by_pin( 234 struct armada_37xx_pinctrl *info, int pin, int *grp) 235 { 236 while (*grp < info->ngroups) { 237 struct armada_37xx_pin_group *group = &info->groups[*grp]; 238 int j; 239 240 *grp = *grp + 1; 241 for (j = 0; j < (group->npins + group->extra_npins); j++) 242 if (group->pins[j] == pin) 243 return group; 244 } 245 return NULL; 246 } 247 248 static int armada_37xx_pin_config_group_get(struct pinctrl_dev *pctldev, 249 unsigned int selector, unsigned long *config) 250 { 251 return -ENOTSUPP; 252 } 253 254 static int armada_37xx_pin_config_group_set(struct pinctrl_dev *pctldev, 255 unsigned int selector, unsigned long *configs, 256 unsigned int num_configs) 257 { 258 return -ENOTSUPP; 259 } 260 261 static const struct pinconf_ops armada_37xx_pinconf_ops = { 262 .is_generic = true, 263 .pin_config_group_get = armada_37xx_pin_config_group_get, 264 .pin_config_group_set = armada_37xx_pin_config_group_set, 265 }; 266 267 static int armada_37xx_get_groups_count(struct pinctrl_dev *pctldev) 268 { 269 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 270 271 return info->ngroups; 272 } 273 274 static const char *armada_37xx_get_group_name(struct pinctrl_dev *pctldev, 275 unsigned int group) 276 { 277 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 278 279 return info->groups[group].name; 280 } 281 282 static int armada_37xx_get_group_pins(struct pinctrl_dev *pctldev, 283 unsigned int selector, 284 const unsigned int **pins, 285 unsigned int *npins) 286 { 287 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 288 289 if (selector >= info->ngroups) 290 return -EINVAL; 291 292 *pins = info->groups[selector].pins; 293 *npins = info->groups[selector].npins + 294 info->groups[selector].extra_npins; 295 296 return 0; 297 } 298 299 static const struct pinctrl_ops armada_37xx_pctrl_ops = { 300 .get_groups_count = armada_37xx_get_groups_count, 301 .get_group_name = armada_37xx_get_group_name, 302 .get_group_pins = armada_37xx_get_group_pins, 303 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 304 .dt_free_map = pinctrl_utils_free_map, 305 }; 306 307 /* 308 * Pinmux_ops handling 309 */ 310 311 static int armada_37xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 312 { 313 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 314 315 return info->nfuncs; 316 } 317 318 static const char *armada_37xx_pmx_get_func_name(struct pinctrl_dev *pctldev, 319 unsigned int selector) 320 { 321 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 322 323 return info->funcs[selector].name; 324 } 325 326 static int armada_37xx_pmx_get_groups(struct pinctrl_dev *pctldev, 327 unsigned int selector, 328 const char * const **groups, 329 unsigned int * const num_groups) 330 { 331 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 332 333 *groups = info->funcs[selector].groups; 334 *num_groups = info->funcs[selector].ngroups; 335 336 return 0; 337 } 338 339 static int armada_37xx_pmx_set_by_name(struct pinctrl_dev *pctldev, 340 const char *name, 341 struct armada_37xx_pin_group *grp) 342 { 343 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 344 unsigned int reg = SELECTION; 345 unsigned int mask = grp->reg_mask; 346 int func, val; 347 348 dev_dbg(info->dev, "enable function %s group %s\n", 349 name, grp->name); 350 351 func = match_string(grp->funcs, NB_FUNCS, name); 352 if (func < 0) 353 return -ENOTSUPP; 354 355 val = grp->val[func]; 356 357 regmap_update_bits(info->regmap, reg, mask, val); 358 359 return 0; 360 } 361 362 static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev, 363 unsigned int selector, 364 unsigned int group) 365 { 366 367 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 368 struct armada_37xx_pin_group *grp = &info->groups[group]; 369 const char *name = info->funcs[selector].name; 370 371 return armada_37xx_pmx_set_by_name(pctldev, name, grp); 372 } 373 374 static inline void armada_37xx_irq_update_reg(unsigned int *reg, 375 struct irq_data *d) 376 { 377 int offset = irqd_to_hwirq(d); 378 379 armada_37xx_update_reg(reg, &offset); 380 } 381 382 static int armada_37xx_gpio_direction_input(struct gpio_chip *chip, 383 unsigned int offset) 384 { 385 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 386 unsigned int reg = OUTPUT_EN; 387 unsigned int mask; 388 389 armada_37xx_update_reg(®, &offset); 390 mask = BIT(offset); 391 392 return regmap_update_bits(info->regmap, reg, mask, 0); 393 } 394 395 static int armada_37xx_gpio_get_direction(struct gpio_chip *chip, 396 unsigned int offset) 397 { 398 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 399 unsigned int reg = OUTPUT_EN; 400 unsigned int val, mask; 401 402 armada_37xx_update_reg(®, &offset); 403 mask = BIT(offset); 404 regmap_read(info->regmap, reg, &val); 405 406 return !(val & mask); 407 } 408 409 static int armada_37xx_gpio_direction_output(struct gpio_chip *chip, 410 unsigned int offset, int value) 411 { 412 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 413 unsigned int reg = OUTPUT_EN; 414 unsigned int mask, val, ret; 415 416 armada_37xx_update_reg(®, &offset); 417 mask = BIT(offset); 418 419 ret = regmap_update_bits(info->regmap, reg, mask, mask); 420 421 if (ret) 422 return ret; 423 424 reg = OUTPUT_VAL; 425 val = value ? mask : 0; 426 regmap_update_bits(info->regmap, reg, mask, val); 427 428 return 0; 429 } 430 431 static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset) 432 { 433 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 434 unsigned int reg = INPUT_VAL; 435 unsigned int val, mask; 436 437 armada_37xx_update_reg(®, &offset); 438 mask = BIT(offset); 439 440 regmap_read(info->regmap, reg, &val); 441 442 return (val & mask) != 0; 443 } 444 445 static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset, 446 int value) 447 { 448 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 449 unsigned int reg = OUTPUT_VAL; 450 unsigned int mask, val; 451 452 armada_37xx_update_reg(®, &offset); 453 mask = BIT(offset); 454 val = value ? mask : 0; 455 456 regmap_update_bits(info->regmap, reg, mask, val); 457 } 458 459 static int armada_37xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 460 struct pinctrl_gpio_range *range, 461 unsigned int offset, bool input) 462 { 463 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 464 struct gpio_chip *chip = range->gc; 465 466 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", 467 offset, range->name, offset, input ? "input" : "output"); 468 469 if (input) 470 armada_37xx_gpio_direction_input(chip, offset); 471 else 472 armada_37xx_gpio_direction_output(chip, offset, 0); 473 474 return 0; 475 } 476 477 static int armada_37xx_gpio_request_enable(struct pinctrl_dev *pctldev, 478 struct pinctrl_gpio_range *range, 479 unsigned int offset) 480 { 481 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 482 struct armada_37xx_pin_group *group; 483 int grp = 0; 484 485 dev_dbg(info->dev, "requesting gpio %d\n", offset); 486 487 while ((group = armada_37xx_find_next_grp_by_pin(info, offset, &grp))) 488 armada_37xx_pmx_set_by_name(pctldev, "gpio", group); 489 490 return 0; 491 } 492 493 static const struct pinmux_ops armada_37xx_pmx_ops = { 494 .get_functions_count = armada_37xx_pmx_get_funcs_count, 495 .get_function_name = armada_37xx_pmx_get_func_name, 496 .get_function_groups = armada_37xx_pmx_get_groups, 497 .set_mux = armada_37xx_pmx_set, 498 .gpio_request_enable = armada_37xx_gpio_request_enable, 499 .gpio_set_direction = armada_37xx_pmx_gpio_set_direction, 500 }; 501 502 static const struct gpio_chip armada_37xx_gpiolib_chip = { 503 .request = gpiochip_generic_request, 504 .free = gpiochip_generic_free, 505 .set = armada_37xx_gpio_set, 506 .get = armada_37xx_gpio_get, 507 .get_direction = armada_37xx_gpio_get_direction, 508 .direction_input = armada_37xx_gpio_direction_input, 509 .direction_output = armada_37xx_gpio_direction_output, 510 .owner = THIS_MODULE, 511 }; 512 513 static void armada_37xx_irq_ack(struct irq_data *d) 514 { 515 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 516 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 517 u32 reg = IRQ_STATUS; 518 unsigned long flags; 519 520 armada_37xx_irq_update_reg(®, d); 521 spin_lock_irqsave(&info->irq_lock, flags); 522 writel(d->mask, info->base + reg); 523 spin_unlock_irqrestore(&info->irq_lock, flags); 524 } 525 526 static void armada_37xx_irq_mask(struct irq_data *d) 527 { 528 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 529 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 530 u32 val, reg = IRQ_EN; 531 unsigned long flags; 532 533 armada_37xx_irq_update_reg(®, d); 534 spin_lock_irqsave(&info->irq_lock, flags); 535 val = readl(info->base + reg); 536 writel(val & ~d->mask, info->base + reg); 537 spin_unlock_irqrestore(&info->irq_lock, flags); 538 } 539 540 static void armada_37xx_irq_unmask(struct irq_data *d) 541 { 542 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 543 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 544 u32 val, reg = IRQ_EN; 545 unsigned long flags; 546 547 armada_37xx_irq_update_reg(®, d); 548 spin_lock_irqsave(&info->irq_lock, flags); 549 val = readl(info->base + reg); 550 writel(val | d->mask, info->base + reg); 551 spin_unlock_irqrestore(&info->irq_lock, flags); 552 } 553 554 static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on) 555 { 556 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 557 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 558 u32 val, reg = IRQ_WKUP; 559 unsigned long flags; 560 561 armada_37xx_irq_update_reg(®, d); 562 spin_lock_irqsave(&info->irq_lock, flags); 563 val = readl(info->base + reg); 564 if (on) 565 val |= (BIT(d->hwirq % GPIO_PER_REG)); 566 else 567 val &= ~(BIT(d->hwirq % GPIO_PER_REG)); 568 writel(val, info->base + reg); 569 spin_unlock_irqrestore(&info->irq_lock, flags); 570 571 return 0; 572 } 573 574 static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type) 575 { 576 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 577 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 578 u32 val, reg = IRQ_POL; 579 unsigned long flags; 580 581 spin_lock_irqsave(&info->irq_lock, flags); 582 armada_37xx_irq_update_reg(®, d); 583 val = readl(info->base + reg); 584 switch (type) { 585 case IRQ_TYPE_EDGE_RISING: 586 val &= ~(BIT(d->hwirq % GPIO_PER_REG)); 587 break; 588 case IRQ_TYPE_EDGE_FALLING: 589 val |= (BIT(d->hwirq % GPIO_PER_REG)); 590 break; 591 case IRQ_TYPE_EDGE_BOTH: { 592 u32 in_val, in_reg = INPUT_VAL; 593 594 armada_37xx_irq_update_reg(&in_reg, d); 595 regmap_read(info->regmap, in_reg, &in_val); 596 597 /* Set initial polarity based on current input level. */ 598 if (in_val & BIT(d->hwirq % GPIO_PER_REG)) 599 val |= BIT(d->hwirq % GPIO_PER_REG); /* falling */ 600 else 601 val &= ~(BIT(d->hwirq % GPIO_PER_REG)); /* rising */ 602 break; 603 } 604 default: 605 spin_unlock_irqrestore(&info->irq_lock, flags); 606 return -EINVAL; 607 } 608 writel(val, info->base + reg); 609 spin_unlock_irqrestore(&info->irq_lock, flags); 610 611 return 0; 612 } 613 614 static int armada_37xx_edge_both_irq_swap_pol(struct armada_37xx_pinctrl *info, 615 u32 pin_idx) 616 { 617 u32 reg_idx = pin_idx / GPIO_PER_REG; 618 u32 bit_num = pin_idx % GPIO_PER_REG; 619 u32 p, l, ret; 620 unsigned long flags; 621 622 regmap_read(info->regmap, INPUT_VAL + 4*reg_idx, &l); 623 624 spin_lock_irqsave(&info->irq_lock, flags); 625 p = readl(info->base + IRQ_POL + 4 * reg_idx); 626 if ((p ^ l) & (1 << bit_num)) { 627 /* 628 * For the gpios which are used for both-edge irqs, when their 629 * interrupts happen, their input levels are changed, 630 * yet their interrupt polarities are kept in old values, we 631 * should synchronize their interrupt polarities; for example, 632 * at first a gpio's input level is low and its interrupt 633 * polarity control is "Detect rising edge", then the gpio has 634 * a interrupt , its level turns to high, we should change its 635 * polarity control to "Detect falling edge" correspondingly. 636 */ 637 p ^= 1 << bit_num; 638 writel(p, info->base + IRQ_POL + 4 * reg_idx); 639 ret = 0; 640 } else { 641 /* Spurious irq */ 642 ret = -1; 643 } 644 645 spin_unlock_irqrestore(&info->irq_lock, flags); 646 return ret; 647 } 648 649 static void armada_37xx_irq_handler(struct irq_desc *desc) 650 { 651 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 652 struct irq_chip *chip = irq_desc_get_chip(desc); 653 struct armada_37xx_pinctrl *info = gpiochip_get_data(gc); 654 struct irq_domain *d = gc->irq.domain; 655 int i; 656 657 chained_irq_enter(chip, desc); 658 for (i = 0; i <= d->revmap_size / GPIO_PER_REG; i++) { 659 u32 status; 660 unsigned long flags; 661 662 spin_lock_irqsave(&info->irq_lock, flags); 663 status = readl_relaxed(info->base + IRQ_STATUS + 4 * i); 664 /* Manage only the interrupt that was enabled */ 665 status &= readl_relaxed(info->base + IRQ_EN + 4 * i); 666 spin_unlock_irqrestore(&info->irq_lock, flags); 667 while (status) { 668 u32 hwirq = ffs(status) - 1; 669 u32 virq = irq_find_mapping(d, hwirq + 670 i * GPIO_PER_REG); 671 u32 t = irq_get_trigger_type(virq); 672 673 if ((t & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 674 /* Swap polarity (race with GPIO line) */ 675 if (armada_37xx_edge_both_irq_swap_pol(info, 676 hwirq + i * GPIO_PER_REG)) { 677 /* 678 * For spurious irq, which gpio level 679 * is not as expected after incoming 680 * edge, just ack the gpio irq. 681 */ 682 writel(1 << hwirq, 683 info->base + 684 IRQ_STATUS + 4 * i); 685 goto update_status; 686 } 687 } 688 689 generic_handle_irq(virq); 690 691 update_status: 692 /* Update status in case a new IRQ appears */ 693 spin_lock_irqsave(&info->irq_lock, flags); 694 status = readl_relaxed(info->base + 695 IRQ_STATUS + 4 * i); 696 /* Manage only the interrupt that was enabled */ 697 status &= readl_relaxed(info->base + IRQ_EN + 4 * i); 698 spin_unlock_irqrestore(&info->irq_lock, flags); 699 } 700 } 701 chained_irq_exit(chip, desc); 702 } 703 704 static unsigned int armada_37xx_irq_startup(struct irq_data *d) 705 { 706 /* 707 * The mask field is a "precomputed bitmask for accessing the 708 * chip registers" which was introduced for the generic 709 * irqchip framework. As we don't use this framework, we can 710 * reuse this field for our own usage. 711 */ 712 d->mask = BIT(d->hwirq % GPIO_PER_REG); 713 714 armada_37xx_irq_unmask(d); 715 716 return 0; 717 } 718 719 static int armada_37xx_irqchip_register(struct platform_device *pdev, 720 struct armada_37xx_pinctrl *info) 721 { 722 struct device_node *np = info->dev->of_node; 723 struct gpio_chip *gc = &info->gpio_chip; 724 struct irq_chip *irqchip = &info->irq_chip; 725 struct gpio_irq_chip *girq = &gc->irq; 726 struct device *dev = &pdev->dev; 727 struct resource res; 728 int ret = -ENODEV, i, nr_irq_parent; 729 730 /* Check if we have at least one gpio-controller child node */ 731 for_each_child_of_node(info->dev->of_node, np) { 732 if (of_property_read_bool(np, "gpio-controller")) { 733 ret = 0; 734 break; 735 } 736 }; 737 if (ret) { 738 dev_err(dev, "no gpio-controller child node\n"); 739 return ret; 740 } 741 742 nr_irq_parent = of_irq_count(np); 743 spin_lock_init(&info->irq_lock); 744 745 if (!nr_irq_parent) { 746 dev_err(dev, "invalid or no IRQ\n"); 747 return 0; 748 } 749 750 if (of_address_to_resource(info->dev->of_node, 1, &res)) { 751 dev_err(dev, "cannot find IO resource\n"); 752 return -ENOENT; 753 } 754 755 info->base = devm_ioremap_resource(info->dev, &res); 756 if (IS_ERR(info->base)) 757 return PTR_ERR(info->base); 758 759 irqchip->irq_ack = armada_37xx_irq_ack; 760 irqchip->irq_mask = armada_37xx_irq_mask; 761 irqchip->irq_unmask = armada_37xx_irq_unmask; 762 irqchip->irq_set_wake = armada_37xx_irq_set_wake; 763 irqchip->irq_set_type = armada_37xx_irq_set_type; 764 irqchip->irq_startup = armada_37xx_irq_startup; 765 irqchip->name = info->data->name; 766 girq->chip = irqchip; 767 girq->parent_handler = armada_37xx_irq_handler; 768 /* 769 * Many interrupts are connected to the parent interrupt 770 * controller. But we do not take advantage of this and use 771 * the chained irq with all of them. 772 */ 773 girq->num_parents = nr_irq_parent; 774 girq->parents = devm_kcalloc(&pdev->dev, nr_irq_parent, 775 sizeof(*girq->parents), GFP_KERNEL); 776 if (!girq->parents) 777 return -ENOMEM; 778 for (i = 0; i < nr_irq_parent; i++) { 779 int irq = irq_of_parse_and_map(np, i); 780 781 if (irq < 0) 782 continue; 783 girq->parents[i] = irq; 784 } 785 girq->default_type = IRQ_TYPE_NONE; 786 girq->handler = handle_edge_irq; 787 788 return 0; 789 } 790 791 static int armada_37xx_gpiochip_register(struct platform_device *pdev, 792 struct armada_37xx_pinctrl *info) 793 { 794 struct device_node *np; 795 struct gpio_chip *gc; 796 int ret = -ENODEV; 797 798 for_each_child_of_node(info->dev->of_node, np) { 799 if (of_find_property(np, "gpio-controller", NULL)) { 800 ret = 0; 801 break; 802 } 803 }; 804 if (ret) 805 return ret; 806 807 info->gpio_chip = armada_37xx_gpiolib_chip; 808 809 gc = &info->gpio_chip; 810 gc->ngpio = info->data->nr_pins; 811 gc->parent = &pdev->dev; 812 gc->base = -1; 813 gc->of_node = np; 814 gc->label = info->data->name; 815 816 ret = armada_37xx_irqchip_register(pdev, info); 817 if (ret) 818 return ret; 819 ret = devm_gpiochip_add_data(&pdev->dev, gc, info); 820 if (ret) 821 return ret; 822 823 return 0; 824 } 825 826 /** 827 * armada_37xx_add_function() - Add a new function to the list 828 * @funcs: array of function to add the new one 829 * @funcsize: size of the remaining space for the function 830 * @name: name of the function to add 831 * 832 * If it is a new function then create it by adding its name else 833 * increment the number of group associated to this function. 834 */ 835 static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs, 836 int *funcsize, const char *name) 837 { 838 int i = 0; 839 840 if (*funcsize <= 0) 841 return -EOVERFLOW; 842 843 while (funcs->ngroups) { 844 /* function already there */ 845 if (strcmp(funcs->name, name) == 0) { 846 funcs->ngroups++; 847 848 return -EEXIST; 849 } 850 funcs++; 851 i++; 852 } 853 854 /* append new unique function */ 855 funcs->name = name; 856 funcs->ngroups = 1; 857 (*funcsize)--; 858 859 return 0; 860 } 861 862 /** 863 * armada_37xx_fill_group() - complete the group array 864 * @info: info driver instance 865 * 866 * Based on the data available from the armada_37xx_pin_group array 867 * completes the last member of the struct for each function: the list 868 * of the groups associated to this function. 869 * 870 */ 871 static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info) 872 { 873 int n, num = 0, funcsize = info->data->nr_pins; 874 875 for (n = 0; n < info->ngroups; n++) { 876 struct armada_37xx_pin_group *grp = &info->groups[n]; 877 int i, j, f; 878 879 grp->pins = devm_kcalloc(info->dev, 880 grp->npins + grp->extra_npins, 881 sizeof(*grp->pins), 882 GFP_KERNEL); 883 if (!grp->pins) 884 return -ENOMEM; 885 886 for (i = 0; i < grp->npins; i++) 887 grp->pins[i] = grp->start_pin + i; 888 889 for (j = 0; j < grp->extra_npins; j++) 890 grp->pins[i+j] = grp->extra_pin + j; 891 892 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) { 893 int ret; 894 /* check for unique functions and count groups */ 895 ret = armada_37xx_add_function(info->funcs, &funcsize, 896 grp->funcs[f]); 897 if (ret == -EOVERFLOW) 898 dev_err(info->dev, 899 "More functions than pins(%d)\n", 900 info->data->nr_pins); 901 if (ret < 0) 902 continue; 903 num++; 904 } 905 } 906 907 info->nfuncs = num; 908 909 return 0; 910 } 911 912 /** 913 * armada_37xx_fill_funcs() - complete the funcs array 914 * @info: info driver instance 915 * 916 * Based on the data available from the armada_37xx_pin_group array 917 * completes the last two member of the struct for each group: 918 * - the list of the pins included in the group 919 * - the list of pinmux functions that can be selected for this group 920 * 921 */ 922 static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info) 923 { 924 struct armada_37xx_pmx_func *funcs = info->funcs; 925 int n; 926 927 for (n = 0; n < info->nfuncs; n++) { 928 const char *name = funcs[n].name; 929 const char **groups; 930 int g; 931 932 funcs[n].groups = devm_kcalloc(info->dev, 933 funcs[n].ngroups, 934 sizeof(*(funcs[n].groups)), 935 GFP_KERNEL); 936 if (!funcs[n].groups) 937 return -ENOMEM; 938 939 groups = funcs[n].groups; 940 941 for (g = 0; g < info->ngroups; g++) { 942 struct armada_37xx_pin_group *gp = &info->groups[g]; 943 int f; 944 945 f = match_string(gp->funcs, NB_FUNCS, name); 946 if (f < 0) 947 continue; 948 949 *groups = gp->name; 950 groups++; 951 } 952 } 953 return 0; 954 } 955 956 static int armada_37xx_pinctrl_register(struct platform_device *pdev, 957 struct armada_37xx_pinctrl *info) 958 { 959 const struct armada_37xx_pin_data *pin_data = info->data; 960 struct pinctrl_desc *ctrldesc = &info->pctl; 961 struct pinctrl_pin_desc *pindesc, *pdesc; 962 int pin, ret; 963 964 info->groups = pin_data->groups; 965 info->ngroups = pin_data->ngroups; 966 967 ctrldesc->name = "armada_37xx-pinctrl"; 968 ctrldesc->owner = THIS_MODULE; 969 ctrldesc->pctlops = &armada_37xx_pctrl_ops; 970 ctrldesc->pmxops = &armada_37xx_pmx_ops; 971 ctrldesc->confops = &armada_37xx_pinconf_ops; 972 973 pindesc = devm_kcalloc(&pdev->dev, 974 pin_data->nr_pins, sizeof(*pindesc), 975 GFP_KERNEL); 976 if (!pindesc) 977 return -ENOMEM; 978 979 ctrldesc->pins = pindesc; 980 ctrldesc->npins = pin_data->nr_pins; 981 982 pdesc = pindesc; 983 for (pin = 0; pin < pin_data->nr_pins; pin++) { 984 pdesc->number = pin; 985 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", 986 pin_data->name, pin); 987 pdesc++; 988 } 989 990 /* 991 * we allocate functions for number of pins and hope there are 992 * fewer unique functions than pins available 993 */ 994 info->funcs = devm_kcalloc(&pdev->dev, 995 pin_data->nr_pins, 996 sizeof(struct armada_37xx_pmx_func), 997 GFP_KERNEL); 998 if (!info->funcs) 999 return -ENOMEM; 1000 1001 1002 ret = armada_37xx_fill_group(info); 1003 if (ret) 1004 return ret; 1005 1006 ret = armada_37xx_fill_func(info); 1007 if (ret) 1008 return ret; 1009 1010 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info); 1011 if (IS_ERR(info->pctl_dev)) { 1012 dev_err(&pdev->dev, "could not register pinctrl driver\n"); 1013 return PTR_ERR(info->pctl_dev); 1014 } 1015 1016 return 0; 1017 } 1018 1019 #if defined(CONFIG_PM) 1020 static int armada_3700_pinctrl_suspend(struct device *dev) 1021 { 1022 struct armada_37xx_pinctrl *info = dev_get_drvdata(dev); 1023 1024 /* Save GPIO state */ 1025 regmap_read(info->regmap, OUTPUT_EN, &info->pm.out_en_l); 1026 regmap_read(info->regmap, OUTPUT_EN + sizeof(u32), &info->pm.out_en_h); 1027 regmap_read(info->regmap, OUTPUT_VAL, &info->pm.out_val_l); 1028 regmap_read(info->regmap, OUTPUT_VAL + sizeof(u32), 1029 &info->pm.out_val_h); 1030 1031 info->pm.irq_en_l = readl(info->base + IRQ_EN); 1032 info->pm.irq_en_h = readl(info->base + IRQ_EN + sizeof(u32)); 1033 info->pm.irq_pol_l = readl(info->base + IRQ_POL); 1034 info->pm.irq_pol_h = readl(info->base + IRQ_POL + sizeof(u32)); 1035 1036 /* Save pinctrl state */ 1037 regmap_read(info->regmap, SELECTION, &info->pm.selection); 1038 1039 return 0; 1040 } 1041 1042 static int armada_3700_pinctrl_resume(struct device *dev) 1043 { 1044 struct armada_37xx_pinctrl *info = dev_get_drvdata(dev); 1045 struct gpio_chip *gc; 1046 struct irq_domain *d; 1047 int i; 1048 1049 /* Restore GPIO state */ 1050 regmap_write(info->regmap, OUTPUT_EN, info->pm.out_en_l); 1051 regmap_write(info->regmap, OUTPUT_EN + sizeof(u32), 1052 info->pm.out_en_h); 1053 regmap_write(info->regmap, OUTPUT_VAL, info->pm.out_val_l); 1054 regmap_write(info->regmap, OUTPUT_VAL + sizeof(u32), 1055 info->pm.out_val_h); 1056 1057 /* 1058 * Input levels may change during suspend, which is not monitored at 1059 * that time. GPIOs used for both-edge IRQs may not be synchronized 1060 * anymore with their polarities (rising/falling edge) and must be 1061 * re-configured manually. 1062 */ 1063 gc = &info->gpio_chip; 1064 d = gc->irq.domain; 1065 for (i = 0; i < gc->ngpio; i++) { 1066 u32 irq_bit = BIT(i % GPIO_PER_REG); 1067 u32 mask, *irq_pol, input_reg, virq, type, level; 1068 1069 if (i < GPIO_PER_REG) { 1070 mask = info->pm.irq_en_l; 1071 irq_pol = &info->pm.irq_pol_l; 1072 input_reg = INPUT_VAL; 1073 } else { 1074 mask = info->pm.irq_en_h; 1075 irq_pol = &info->pm.irq_pol_h; 1076 input_reg = INPUT_VAL + sizeof(u32); 1077 } 1078 1079 if (!(mask & irq_bit)) 1080 continue; 1081 1082 virq = irq_find_mapping(d, i); 1083 type = irq_get_trigger_type(virq); 1084 1085 /* 1086 * Synchronize level and polarity for both-edge irqs: 1087 * - a high input level expects a falling edge, 1088 * - a low input level exepects a rising edge. 1089 */ 1090 if ((type & IRQ_TYPE_SENSE_MASK) == 1091 IRQ_TYPE_EDGE_BOTH) { 1092 regmap_read(info->regmap, input_reg, &level); 1093 if ((*irq_pol ^ level) & irq_bit) 1094 *irq_pol ^= irq_bit; 1095 } 1096 } 1097 1098 writel(info->pm.irq_en_l, info->base + IRQ_EN); 1099 writel(info->pm.irq_en_h, info->base + IRQ_EN + sizeof(u32)); 1100 writel(info->pm.irq_pol_l, info->base + IRQ_POL); 1101 writel(info->pm.irq_pol_h, info->base + IRQ_POL + sizeof(u32)); 1102 1103 /* Restore pinctrl state */ 1104 regmap_write(info->regmap, SELECTION, info->pm.selection); 1105 1106 return 0; 1107 } 1108 1109 /* 1110 * Since pinctrl is an infrastructure module, its resume should be issued prior 1111 * to other IO drivers. 1112 */ 1113 static const struct dev_pm_ops armada_3700_pinctrl_pm_ops = { 1114 .suspend_noirq = armada_3700_pinctrl_suspend, 1115 .resume_noirq = armada_3700_pinctrl_resume, 1116 }; 1117 1118 #define PINCTRL_ARMADA_37XX_DEV_PM_OPS (&armada_3700_pinctrl_pm_ops) 1119 #else 1120 #define PINCTRL_ARMADA_37XX_DEV_PM_OPS NULL 1121 #endif /* CONFIG_PM */ 1122 1123 static const struct of_device_id armada_37xx_pinctrl_of_match[] = { 1124 { 1125 .compatible = "marvell,armada3710-sb-pinctrl", 1126 .data = &armada_37xx_pin_sb, 1127 }, 1128 { 1129 .compatible = "marvell,armada3710-nb-pinctrl", 1130 .data = &armada_37xx_pin_nb, 1131 }, 1132 { }, 1133 }; 1134 1135 static int __init armada_37xx_pinctrl_probe(struct platform_device *pdev) 1136 { 1137 struct armada_37xx_pinctrl *info; 1138 struct device *dev = &pdev->dev; 1139 struct device_node *np = dev->of_node; 1140 struct regmap *regmap; 1141 int ret; 1142 1143 info = devm_kzalloc(dev, sizeof(struct armada_37xx_pinctrl), 1144 GFP_KERNEL); 1145 if (!info) 1146 return -ENOMEM; 1147 1148 info->dev = dev; 1149 1150 regmap = syscon_node_to_regmap(np); 1151 if (IS_ERR(regmap)) { 1152 dev_err(&pdev->dev, "cannot get regmap\n"); 1153 return PTR_ERR(regmap); 1154 } 1155 info->regmap = regmap; 1156 1157 info->data = of_device_get_match_data(dev); 1158 1159 ret = armada_37xx_pinctrl_register(pdev, info); 1160 if (ret) 1161 return ret; 1162 1163 ret = armada_37xx_gpiochip_register(pdev, info); 1164 if (ret) 1165 return ret; 1166 1167 platform_set_drvdata(pdev, info); 1168 1169 return 0; 1170 } 1171 1172 static struct platform_driver armada_37xx_pinctrl_driver = { 1173 .driver = { 1174 .name = "armada-37xx-pinctrl", 1175 .of_match_table = armada_37xx_pinctrl_of_match, 1176 .pm = PINCTRL_ARMADA_37XX_DEV_PM_OPS, 1177 }, 1178 }; 1179 1180 builtin_platform_driver_probe(armada_37xx_pinctrl_driver, 1181 armada_37xx_pinctrl_probe); 1182