1 /*
2  * Marvell 37xx SoC pinctrl driver
3  *
4  * Copyright (C) 2017 Marvell
5  *
6  * Gregory CLEMENT <gregory.clement@free-electrons.com>
7  *
8  * This file is licensed under the terms of the GNU General Public
9  * License version 2 or later. This program is licensed "as is"
10  * without any warranty of any kind, whether express or implied.
11  */
12 
13 #include <linux/gpio/driver.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/of_device.h>
18 #include <linux/of_irq.h>
19 #include <linux/pinctrl/pinconf-generic.h>
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 #include <linux/platform_device.h>
24 #include <linux/regmap.h>
25 #include <linux/slab.h>
26 
27 #include "../pinctrl-utils.h"
28 
29 #define OUTPUT_EN	0x0
30 #define INPUT_VAL	0x10
31 #define OUTPUT_VAL	0x18
32 #define OUTPUT_CTL	0x20
33 #define SELECTION	0x30
34 
35 #define IRQ_EN		0x0
36 #define IRQ_POL		0x08
37 #define IRQ_STATUS	0x10
38 #define IRQ_WKUP	0x18
39 
40 #define NB_FUNCS 3
41 #define GPIO_PER_REG	32
42 
43 /**
44  * struct armada_37xx_pin_group: represents group of pins of a pinmux function.
45  * The pins of a pinmux groups are composed of one or two groups of contiguous
46  * pins.
47  * @name:	Name of the pin group, used to lookup the group.
48  * @start_pin:	Index of the first pin of the main range of pins belonging to
49  *		the group
50  * @npins:	Number of pins included in the first range
51  * @reg_mask:	Bit mask matching the group in the selection register
52  * @val:	Value to write to the registers for a given function
53  * @extra_pin:	Index of the first pin of the optional second range of pins
54  *		belonging to the group
55  * @extra_npins:Number of pins included in the second optional range
56  * @funcs:	A list of pinmux functions that can be selected for this group.
57  * @pins:	List of the pins included in the group
58  */
59 struct armada_37xx_pin_group {
60 	const char	*name;
61 	unsigned int	start_pin;
62 	unsigned int	npins;
63 	u32		reg_mask;
64 	u32		val[NB_FUNCS];
65 	unsigned int	extra_pin;
66 	unsigned int	extra_npins;
67 	const char	*funcs[NB_FUNCS];
68 	unsigned int	*pins;
69 };
70 
71 struct armada_37xx_pin_data {
72 	u8				nr_pins;
73 	char				*name;
74 	struct armada_37xx_pin_group	*groups;
75 	int				ngroups;
76 };
77 
78 struct armada_37xx_pmx_func {
79 	const char		*name;
80 	const char		**groups;
81 	unsigned int		ngroups;
82 };
83 
84 struct armada_37xx_pm_state {
85 	u32 out_en_l;
86 	u32 out_en_h;
87 	u32 out_val_l;
88 	u32 out_val_h;
89 	u32 irq_en_l;
90 	u32 irq_en_h;
91 	u32 irq_pol_l;
92 	u32 irq_pol_h;
93 	u32 selection;
94 };
95 
96 struct armada_37xx_pinctrl {
97 	struct regmap			*regmap;
98 	void __iomem			*base;
99 	const struct armada_37xx_pin_data	*data;
100 	struct device			*dev;
101 	struct gpio_chip		gpio_chip;
102 	struct irq_chip			irq_chip;
103 	spinlock_t			irq_lock;
104 	struct pinctrl_desc		pctl;
105 	struct pinctrl_dev		*pctl_dev;
106 	struct armada_37xx_pin_group	*groups;
107 	unsigned int			ngroups;
108 	struct armada_37xx_pmx_func	*funcs;
109 	unsigned int			nfuncs;
110 	struct armada_37xx_pm_state	pm;
111 };
112 
113 #define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2)	\
114 	{					\
115 		.name = _name,			\
116 		.start_pin = _start,		\
117 		.npins = _nr,			\
118 		.reg_mask = _mask,		\
119 		.val = {0, _mask},		\
120 		.funcs = {_func1, _func2}	\
121 	}
122 
123 #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1)	\
124 	{					\
125 		.name = _name,			\
126 		.start_pin = _start,		\
127 		.npins = _nr,			\
128 		.reg_mask = _mask,		\
129 		.val = {0, _mask},		\
130 		.funcs = {_func1, "gpio"}	\
131 	}
132 
133 #define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1)   \
134 	{					\
135 		.name = _name,			\
136 		.start_pin = _start,		\
137 		.npins = _nr,			\
138 		.reg_mask = _mask,		\
139 		.val = {_val1, _val2},		\
140 		.funcs = {_func1, "gpio"}	\
141 	}
142 
143 #define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \
144 	{					\
145 		.name = _name,			\
146 		.start_pin = _start,		\
147 		.npins = _nr,			\
148 		.reg_mask = _mask,		\
149 		.val = {_v1, _v2, _v3},	\
150 		.funcs = {_f1, _f2, "gpio"}	\
151 	}
152 
153 #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \
154 		      _f1, _f2)				\
155 	{						\
156 		.name = _name,				\
157 		.start_pin = _start,			\
158 		.npins = _nr,				\
159 		.reg_mask = _mask,			\
160 		.val = {_v1, _v2},			\
161 		.extra_pin = _start2,			\
162 		.extra_npins = _nr2,			\
163 		.funcs = {_f1, _f2}			\
164 	}
165 
166 static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
167 	PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"),
168 	PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"),
169 	PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
170 	PIN_GRP_GPIO("pwm0", 11, 1, BIT(3), "pwm"),
171 	PIN_GRP_GPIO("pwm1", 12, 1, BIT(4), "pwm"),
172 	PIN_GRP_GPIO("pwm2", 13, 1, BIT(5), "pwm"),
173 	PIN_GRP_GPIO("pwm3", 14, 1, BIT(6), "pwm"),
174 	PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
175 	PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
176 	PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
177 	PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
178 	PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
179 	PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"),
180 	PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"),
181 	PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
182 	PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
183 	PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
184 	PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
185 		      BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
186 		      18, 2, "gpio", "uart"),
187 	PIN_GRP_GPIO_2("led0_od", 11, 1, BIT(20), BIT(20), 0, "led"),
188 	PIN_GRP_GPIO_2("led1_od", 12, 1, BIT(21), BIT(21), 0, "led"),
189 	PIN_GRP_GPIO_2("led2_od", 13, 1, BIT(22), BIT(22), 0, "led"),
190 	PIN_GRP_GPIO_2("led3_od", 14, 1, BIT(23), BIT(23), 0, "led"),
191 };
192 
193 static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
194 	PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
195 	PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
196 	PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
197 	PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
198 	PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
199 	PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */
200 	PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"),
201 	PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"),
202 	PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"),
203 	PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
204 	PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
205 	PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
206 		       "mii", "mii_err"),
207 };
208 
209 static const struct armada_37xx_pin_data armada_37xx_pin_nb = {
210 	.nr_pins = 36,
211 	.name = "GPIO1",
212 	.groups = armada_37xx_nb_groups,
213 	.ngroups = ARRAY_SIZE(armada_37xx_nb_groups),
214 };
215 
216 static const struct armada_37xx_pin_data armada_37xx_pin_sb = {
217 	.nr_pins = 30,
218 	.name = "GPIO2",
219 	.groups = armada_37xx_sb_groups,
220 	.ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
221 };
222 
223 static inline void armada_37xx_update_reg(unsigned int *reg,
224 					  unsigned int *offset)
225 {
226 	/* We never have more than 2 registers */
227 	if (*offset >= GPIO_PER_REG) {
228 		*offset -= GPIO_PER_REG;
229 		*reg += sizeof(u32);
230 	}
231 }
232 
233 static struct armada_37xx_pin_group *armada_37xx_find_next_grp_by_pin(
234 	struct armada_37xx_pinctrl *info, int pin, int *grp)
235 {
236 	while (*grp < info->ngroups) {
237 		struct armada_37xx_pin_group *group = &info->groups[*grp];
238 		int j;
239 
240 		*grp = *grp + 1;
241 		for (j = 0; j < (group->npins + group->extra_npins); j++)
242 			if (group->pins[j] == pin)
243 				return group;
244 	}
245 	return NULL;
246 }
247 
248 static int armada_37xx_pin_config_group_get(struct pinctrl_dev *pctldev,
249 			    unsigned int selector, unsigned long *config)
250 {
251 	return -ENOTSUPP;
252 }
253 
254 static int armada_37xx_pin_config_group_set(struct pinctrl_dev *pctldev,
255 			    unsigned int selector, unsigned long *configs,
256 			    unsigned int num_configs)
257 {
258 	return -ENOTSUPP;
259 }
260 
261 static const struct pinconf_ops armada_37xx_pinconf_ops = {
262 	.is_generic = true,
263 	.pin_config_group_get = armada_37xx_pin_config_group_get,
264 	.pin_config_group_set = armada_37xx_pin_config_group_set,
265 };
266 
267 static int armada_37xx_get_groups_count(struct pinctrl_dev *pctldev)
268 {
269 	struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
270 
271 	return info->ngroups;
272 }
273 
274 static const char *armada_37xx_get_group_name(struct pinctrl_dev *pctldev,
275 					      unsigned int group)
276 {
277 	struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
278 
279 	return info->groups[group].name;
280 }
281 
282 static int armada_37xx_get_group_pins(struct pinctrl_dev *pctldev,
283 				      unsigned int selector,
284 				      const unsigned int **pins,
285 				      unsigned int *npins)
286 {
287 	struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
288 
289 	if (selector >= info->ngroups)
290 		return -EINVAL;
291 
292 	*pins = info->groups[selector].pins;
293 	*npins = info->groups[selector].npins +
294 		info->groups[selector].extra_npins;
295 
296 	return 0;
297 }
298 
299 static const struct pinctrl_ops armada_37xx_pctrl_ops = {
300 	.get_groups_count	= armada_37xx_get_groups_count,
301 	.get_group_name		= armada_37xx_get_group_name,
302 	.get_group_pins		= armada_37xx_get_group_pins,
303 	.dt_node_to_map		= pinconf_generic_dt_node_to_map_group,
304 	.dt_free_map		= pinctrl_utils_free_map,
305 };
306 
307 /*
308  * Pinmux_ops handling
309  */
310 
311 static int armada_37xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
312 {
313 	struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
314 
315 	return info->nfuncs;
316 }
317 
318 static const char *armada_37xx_pmx_get_func_name(struct pinctrl_dev *pctldev,
319 						 unsigned int selector)
320 {
321 	struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
322 
323 	return info->funcs[selector].name;
324 }
325 
326 static int armada_37xx_pmx_get_groups(struct pinctrl_dev *pctldev,
327 				      unsigned int selector,
328 				      const char * const **groups,
329 				      unsigned int * const num_groups)
330 {
331 	struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
332 
333 	*groups = info->funcs[selector].groups;
334 	*num_groups = info->funcs[selector].ngroups;
335 
336 	return 0;
337 }
338 
339 static int armada_37xx_pmx_set_by_name(struct pinctrl_dev *pctldev,
340 				       const char *name,
341 				       struct armada_37xx_pin_group *grp)
342 {
343 	struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
344 	unsigned int reg = SELECTION;
345 	unsigned int mask = grp->reg_mask;
346 	int func, val;
347 
348 	dev_dbg(info->dev, "enable function %s group %s\n",
349 		name, grp->name);
350 
351 	func = match_string(grp->funcs, NB_FUNCS, name);
352 	if (func < 0)
353 		return -ENOTSUPP;
354 
355 	val = grp->val[func];
356 
357 	regmap_update_bits(info->regmap, reg, mask, val);
358 
359 	return 0;
360 }
361 
362 static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev,
363 			       unsigned int selector,
364 			       unsigned int group)
365 {
366 
367 	struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
368 	struct armada_37xx_pin_group *grp = &info->groups[group];
369 	const char *name = info->funcs[selector].name;
370 
371 	return armada_37xx_pmx_set_by_name(pctldev, name, grp);
372 }
373 
374 static inline void armada_37xx_irq_update_reg(unsigned int *reg,
375 					  struct irq_data *d)
376 {
377 	int offset = irqd_to_hwirq(d);
378 
379 	armada_37xx_update_reg(reg, &offset);
380 }
381 
382 static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
383 					    unsigned int offset)
384 {
385 	struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
386 	unsigned int reg = OUTPUT_EN;
387 	unsigned int mask;
388 
389 	armada_37xx_update_reg(&reg, &offset);
390 	mask = BIT(offset);
391 
392 	return regmap_update_bits(info->regmap, reg, mask, 0);
393 }
394 
395 static int armada_37xx_gpio_get_direction(struct gpio_chip *chip,
396 					  unsigned int offset)
397 {
398 	struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
399 	unsigned int reg = OUTPUT_EN;
400 	unsigned int val, mask;
401 
402 	armada_37xx_update_reg(&reg, &offset);
403 	mask = BIT(offset);
404 	regmap_read(info->regmap, reg, &val);
405 
406 	if (val & mask)
407 		return GPIO_LINE_DIRECTION_OUT;
408 
409 	return GPIO_LINE_DIRECTION_IN;
410 }
411 
412 static int armada_37xx_gpio_direction_output(struct gpio_chip *chip,
413 					     unsigned int offset, int value)
414 {
415 	struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
416 	unsigned int reg = OUTPUT_EN;
417 	unsigned int mask, val, ret;
418 
419 	armada_37xx_update_reg(&reg, &offset);
420 	mask = BIT(offset);
421 
422 	ret = regmap_update_bits(info->regmap, reg, mask, mask);
423 
424 	if (ret)
425 		return ret;
426 
427 	reg = OUTPUT_VAL;
428 	val = value ? mask : 0;
429 	regmap_update_bits(info->regmap, reg, mask, val);
430 
431 	return 0;
432 }
433 
434 static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
435 {
436 	struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
437 	unsigned int reg = INPUT_VAL;
438 	unsigned int val, mask;
439 
440 	armada_37xx_update_reg(&reg, &offset);
441 	mask = BIT(offset);
442 
443 	regmap_read(info->regmap, reg, &val);
444 
445 	return (val & mask) != 0;
446 }
447 
448 static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
449 				 int value)
450 {
451 	struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
452 	unsigned int reg = OUTPUT_VAL;
453 	unsigned int mask, val;
454 
455 	armada_37xx_update_reg(&reg, &offset);
456 	mask = BIT(offset);
457 	val = value ? mask : 0;
458 
459 	regmap_update_bits(info->regmap, reg, mask, val);
460 }
461 
462 static int armada_37xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
463 					      struct pinctrl_gpio_range *range,
464 					      unsigned int offset, bool input)
465 {
466 	struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
467 	struct gpio_chip *chip = range->gc;
468 
469 	dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
470 		offset, range->name, offset, input ? "input" : "output");
471 
472 	if (input)
473 		armada_37xx_gpio_direction_input(chip, offset);
474 	else
475 		armada_37xx_gpio_direction_output(chip, offset, 0);
476 
477 	return 0;
478 }
479 
480 static int armada_37xx_gpio_request_enable(struct pinctrl_dev *pctldev,
481 					   struct pinctrl_gpio_range *range,
482 					   unsigned int offset)
483 {
484 	struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
485 	struct armada_37xx_pin_group *group;
486 	int grp = 0;
487 
488 	dev_dbg(info->dev, "requesting gpio %d\n", offset);
489 
490 	while ((group = armada_37xx_find_next_grp_by_pin(info, offset, &grp)))
491 		armada_37xx_pmx_set_by_name(pctldev, "gpio", group);
492 
493 	return 0;
494 }
495 
496 static const struct pinmux_ops armada_37xx_pmx_ops = {
497 	.get_functions_count	= armada_37xx_pmx_get_funcs_count,
498 	.get_function_name	= armada_37xx_pmx_get_func_name,
499 	.get_function_groups	= armada_37xx_pmx_get_groups,
500 	.set_mux		= armada_37xx_pmx_set,
501 	.gpio_request_enable	= armada_37xx_gpio_request_enable,
502 	.gpio_set_direction	= armada_37xx_pmx_gpio_set_direction,
503 };
504 
505 static const struct gpio_chip armada_37xx_gpiolib_chip = {
506 	.request = gpiochip_generic_request,
507 	.free = gpiochip_generic_free,
508 	.set = armada_37xx_gpio_set,
509 	.get = armada_37xx_gpio_get,
510 	.get_direction	= armada_37xx_gpio_get_direction,
511 	.direction_input = armada_37xx_gpio_direction_input,
512 	.direction_output = armada_37xx_gpio_direction_output,
513 	.owner = THIS_MODULE,
514 };
515 
516 static void armada_37xx_irq_ack(struct irq_data *d)
517 {
518 	struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
519 	struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
520 	u32 reg = IRQ_STATUS;
521 	unsigned long flags;
522 
523 	armada_37xx_irq_update_reg(&reg, d);
524 	spin_lock_irqsave(&info->irq_lock, flags);
525 	writel(d->mask, info->base + reg);
526 	spin_unlock_irqrestore(&info->irq_lock, flags);
527 }
528 
529 static void armada_37xx_irq_mask(struct irq_data *d)
530 {
531 	struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
532 	struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
533 	u32 val, reg = IRQ_EN;
534 	unsigned long flags;
535 
536 	armada_37xx_irq_update_reg(&reg, d);
537 	spin_lock_irqsave(&info->irq_lock, flags);
538 	val = readl(info->base + reg);
539 	writel(val & ~d->mask, info->base + reg);
540 	spin_unlock_irqrestore(&info->irq_lock, flags);
541 }
542 
543 static void armada_37xx_irq_unmask(struct irq_data *d)
544 {
545 	struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
546 	struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
547 	u32 val, reg = IRQ_EN;
548 	unsigned long flags;
549 
550 	armada_37xx_irq_update_reg(&reg, d);
551 	spin_lock_irqsave(&info->irq_lock, flags);
552 	val = readl(info->base + reg);
553 	writel(val | d->mask, info->base + reg);
554 	spin_unlock_irqrestore(&info->irq_lock, flags);
555 }
556 
557 static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on)
558 {
559 	struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
560 	struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
561 	u32 val, reg = IRQ_WKUP;
562 	unsigned long flags;
563 
564 	armada_37xx_irq_update_reg(&reg, d);
565 	spin_lock_irqsave(&info->irq_lock, flags);
566 	val = readl(info->base + reg);
567 	if (on)
568 		val |= (BIT(d->hwirq % GPIO_PER_REG));
569 	else
570 		val &= ~(BIT(d->hwirq % GPIO_PER_REG));
571 	writel(val, info->base + reg);
572 	spin_unlock_irqrestore(&info->irq_lock, flags);
573 
574 	return 0;
575 }
576 
577 static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type)
578 {
579 	struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
580 	struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
581 	u32 val, reg = IRQ_POL;
582 	unsigned long flags;
583 
584 	spin_lock_irqsave(&info->irq_lock, flags);
585 	armada_37xx_irq_update_reg(&reg, d);
586 	val = readl(info->base + reg);
587 	switch (type) {
588 	case IRQ_TYPE_EDGE_RISING:
589 		val &= ~(BIT(d->hwirq % GPIO_PER_REG));
590 		break;
591 	case IRQ_TYPE_EDGE_FALLING:
592 		val |= (BIT(d->hwirq % GPIO_PER_REG));
593 		break;
594 	case IRQ_TYPE_EDGE_BOTH: {
595 		u32 in_val, in_reg = INPUT_VAL;
596 
597 		armada_37xx_irq_update_reg(&in_reg, d);
598 		regmap_read(info->regmap, in_reg, &in_val);
599 
600 		/* Set initial polarity based on current input level. */
601 		if (in_val & BIT(d->hwirq % GPIO_PER_REG))
602 			val |= BIT(d->hwirq % GPIO_PER_REG);	/* falling */
603 		else
604 			val &= ~(BIT(d->hwirq % GPIO_PER_REG));	/* rising */
605 		break;
606 	}
607 	default:
608 		spin_unlock_irqrestore(&info->irq_lock, flags);
609 		return -EINVAL;
610 	}
611 	writel(val, info->base + reg);
612 	spin_unlock_irqrestore(&info->irq_lock, flags);
613 
614 	return 0;
615 }
616 
617 static int armada_37xx_edge_both_irq_swap_pol(struct armada_37xx_pinctrl *info,
618 					     u32 pin_idx)
619 {
620 	u32 reg_idx = pin_idx / GPIO_PER_REG;
621 	u32 bit_num = pin_idx % GPIO_PER_REG;
622 	u32 p, l, ret;
623 	unsigned long flags;
624 
625 	regmap_read(info->regmap, INPUT_VAL + 4*reg_idx, &l);
626 
627 	spin_lock_irqsave(&info->irq_lock, flags);
628 	p = readl(info->base + IRQ_POL + 4 * reg_idx);
629 	if ((p ^ l) & (1 << bit_num)) {
630 		/*
631 		 * For the gpios which are used for both-edge irqs, when their
632 		 * interrupts happen, their input levels are changed,
633 		 * yet their interrupt polarities are kept in old values, we
634 		 * should synchronize their interrupt polarities; for example,
635 		 * at first a gpio's input level is low and its interrupt
636 		 * polarity control is "Detect rising edge", then the gpio has
637 		 * a interrupt , its level turns to high, we should change its
638 		 * polarity control to "Detect falling edge" correspondingly.
639 		 */
640 		p ^= 1 << bit_num;
641 		writel(p, info->base + IRQ_POL + 4 * reg_idx);
642 		ret = 0;
643 	} else {
644 		/* Spurious irq */
645 		ret = -1;
646 	}
647 
648 	spin_unlock_irqrestore(&info->irq_lock, flags);
649 	return ret;
650 }
651 
652 static void armada_37xx_irq_handler(struct irq_desc *desc)
653 {
654 	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
655 	struct irq_chip *chip = irq_desc_get_chip(desc);
656 	struct armada_37xx_pinctrl *info = gpiochip_get_data(gc);
657 	struct irq_domain *d = gc->irq.domain;
658 	int i;
659 
660 	chained_irq_enter(chip, desc);
661 	for (i = 0; i <= d->revmap_size / GPIO_PER_REG; i++) {
662 		u32 status;
663 		unsigned long flags;
664 
665 		spin_lock_irqsave(&info->irq_lock, flags);
666 		status = readl_relaxed(info->base + IRQ_STATUS + 4 * i);
667 		/* Manage only the interrupt that was enabled */
668 		status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
669 		spin_unlock_irqrestore(&info->irq_lock, flags);
670 		while (status) {
671 			u32 hwirq = ffs(status) - 1;
672 			u32 virq = irq_find_mapping(d, hwirq +
673 						     i * GPIO_PER_REG);
674 			u32 t = irq_get_trigger_type(virq);
675 
676 			if ((t & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
677 				/* Swap polarity (race with GPIO line) */
678 				if (armada_37xx_edge_both_irq_swap_pol(info,
679 					hwirq + i * GPIO_PER_REG)) {
680 					/*
681 					 * For spurious irq, which gpio level
682 					 * is not as expected after incoming
683 					 * edge, just ack the gpio irq.
684 					 */
685 					writel(1 << hwirq,
686 					       info->base +
687 					       IRQ_STATUS + 4 * i);
688 					goto update_status;
689 				}
690 			}
691 
692 			generic_handle_irq(virq);
693 
694 update_status:
695 			/* Update status in case a new IRQ appears */
696 			spin_lock_irqsave(&info->irq_lock, flags);
697 			status = readl_relaxed(info->base +
698 					       IRQ_STATUS + 4 * i);
699 			/* Manage only the interrupt that was enabled */
700 			status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
701 			spin_unlock_irqrestore(&info->irq_lock, flags);
702 		}
703 	}
704 	chained_irq_exit(chip, desc);
705 }
706 
707 static unsigned int armada_37xx_irq_startup(struct irq_data *d)
708 {
709 	/*
710 	 * The mask field is a "precomputed bitmask for accessing the
711 	 * chip registers" which was introduced for the generic
712 	 * irqchip framework. As we don't use this framework, we can
713 	 * reuse this field for our own usage.
714 	 */
715 	d->mask = BIT(d->hwirq % GPIO_PER_REG);
716 
717 	armada_37xx_irq_unmask(d);
718 
719 	return 0;
720 }
721 
722 static int armada_37xx_irqchip_register(struct platform_device *pdev,
723 					struct armada_37xx_pinctrl *info)
724 {
725 	struct device_node *np = info->dev->of_node;
726 	struct gpio_chip *gc = &info->gpio_chip;
727 	struct irq_chip *irqchip = &info->irq_chip;
728 	struct gpio_irq_chip *girq = &gc->irq;
729 	struct device *dev = &pdev->dev;
730 	struct resource res;
731 	int ret = -ENODEV, i, nr_irq_parent;
732 
733 	/* Check if we have at least one gpio-controller child node */
734 	for_each_child_of_node(info->dev->of_node, np) {
735 		if (of_property_read_bool(np, "gpio-controller")) {
736 			ret = 0;
737 			break;
738 		}
739 	}
740 	if (ret) {
741 		dev_err(dev, "no gpio-controller child node\n");
742 		return ret;
743 	}
744 
745 	nr_irq_parent = of_irq_count(np);
746 	spin_lock_init(&info->irq_lock);
747 
748 	if (!nr_irq_parent) {
749 		dev_err(dev, "invalid or no IRQ\n");
750 		return 0;
751 	}
752 
753 	if (of_address_to_resource(info->dev->of_node, 1, &res)) {
754 		dev_err(dev, "cannot find IO resource\n");
755 		return -ENOENT;
756 	}
757 
758 	info->base = devm_ioremap_resource(info->dev, &res);
759 	if (IS_ERR(info->base))
760 		return PTR_ERR(info->base);
761 
762 	irqchip->irq_ack = armada_37xx_irq_ack;
763 	irqchip->irq_mask = armada_37xx_irq_mask;
764 	irqchip->irq_unmask = armada_37xx_irq_unmask;
765 	irqchip->irq_set_wake = armada_37xx_irq_set_wake;
766 	irqchip->irq_set_type = armada_37xx_irq_set_type;
767 	irqchip->irq_startup = armada_37xx_irq_startup;
768 	irqchip->name = info->data->name;
769 	girq->chip = irqchip;
770 	girq->parent_handler = armada_37xx_irq_handler;
771 	/*
772 	 * Many interrupts are connected to the parent interrupt
773 	 * controller. But we do not take advantage of this and use
774 	 * the chained irq with all of them.
775 	 */
776 	girq->num_parents = nr_irq_parent;
777 	girq->parents = devm_kcalloc(&pdev->dev, nr_irq_parent,
778 				     sizeof(*girq->parents), GFP_KERNEL);
779 	if (!girq->parents)
780 		return -ENOMEM;
781 	for (i = 0; i < nr_irq_parent; i++) {
782 		int irq = irq_of_parse_and_map(np, i);
783 
784 		if (irq < 0)
785 			continue;
786 		girq->parents[i] = irq;
787 	}
788 	girq->default_type = IRQ_TYPE_NONE;
789 	girq->handler = handle_edge_irq;
790 
791 	return 0;
792 }
793 
794 static int armada_37xx_gpiochip_register(struct platform_device *pdev,
795 					struct armada_37xx_pinctrl *info)
796 {
797 	struct device_node *np;
798 	struct gpio_chip *gc;
799 	int ret = -ENODEV;
800 
801 	for_each_child_of_node(info->dev->of_node, np) {
802 		if (of_find_property(np, "gpio-controller", NULL)) {
803 			ret = 0;
804 			break;
805 		}
806 	}
807 	if (ret)
808 		return ret;
809 
810 	info->gpio_chip = armada_37xx_gpiolib_chip;
811 
812 	gc = &info->gpio_chip;
813 	gc->ngpio = info->data->nr_pins;
814 	gc->parent = &pdev->dev;
815 	gc->base = -1;
816 	gc->of_node = np;
817 	gc->label = info->data->name;
818 
819 	ret = armada_37xx_irqchip_register(pdev, info);
820 	if (ret)
821 		return ret;
822 	ret = devm_gpiochip_add_data(&pdev->dev, gc, info);
823 	if (ret)
824 		return ret;
825 
826 	return 0;
827 }
828 
829 /**
830  * armada_37xx_add_function() - Add a new function to the list
831  * @funcs: array of function to add the new one
832  * @funcsize: size of the remaining space for the function
833  * @name: name of the function to add
834  *
835  * If it is a new function then create it by adding its name else
836  * increment the number of group associated to this function.
837  */
838 static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs,
839 				    int *funcsize, const char *name)
840 {
841 	int i = 0;
842 
843 	if (*funcsize <= 0)
844 		return -EOVERFLOW;
845 
846 	while (funcs->ngroups) {
847 		/* function already there */
848 		if (strcmp(funcs->name, name) == 0) {
849 			funcs->ngroups++;
850 
851 			return -EEXIST;
852 		}
853 		funcs++;
854 		i++;
855 	}
856 
857 	/* append new unique function */
858 	funcs->name = name;
859 	funcs->ngroups = 1;
860 	(*funcsize)--;
861 
862 	return 0;
863 }
864 
865 /**
866  * armada_37xx_fill_group() - complete the group array
867  * @info: info driver instance
868  *
869  * Based on the data available from the armada_37xx_pin_group array
870  * completes the last member of the struct for each function: the list
871  * of the groups associated to this function.
872  *
873  */
874 static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
875 {
876 	int n, num = 0, funcsize = info->data->nr_pins;
877 
878 	for (n = 0; n < info->ngroups; n++) {
879 		struct armada_37xx_pin_group *grp = &info->groups[n];
880 		int i, j, f;
881 
882 		grp->pins = devm_kcalloc(info->dev,
883 					 grp->npins + grp->extra_npins,
884 					 sizeof(*grp->pins),
885 					 GFP_KERNEL);
886 		if (!grp->pins)
887 			return -ENOMEM;
888 
889 		for (i = 0; i < grp->npins; i++)
890 			grp->pins[i] = grp->start_pin + i;
891 
892 		for (j = 0; j < grp->extra_npins; j++)
893 			grp->pins[i+j] = grp->extra_pin + j;
894 
895 		for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) {
896 			int ret;
897 			/* check for unique functions and count groups */
898 			ret = armada_37xx_add_function(info->funcs, &funcsize,
899 					    grp->funcs[f]);
900 			if (ret == -EOVERFLOW)
901 				dev_err(info->dev,
902 					"More functions than pins(%d)\n",
903 					info->data->nr_pins);
904 			if (ret < 0)
905 				continue;
906 			num++;
907 		}
908 	}
909 
910 	info->nfuncs = num;
911 
912 	return 0;
913 }
914 
915 /**
916  * armada_37xx_fill_funcs() - complete the funcs array
917  * @info: info driver instance
918  *
919  * Based on the data available from the armada_37xx_pin_group array
920  * completes the last two member of the struct for each group:
921  * - the list of the pins included in the group
922  * - the list of pinmux functions that can be selected for this group
923  *
924  */
925 static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
926 {
927 	struct armada_37xx_pmx_func *funcs = info->funcs;
928 	int n;
929 
930 	for (n = 0; n < info->nfuncs; n++) {
931 		const char *name = funcs[n].name;
932 		const char **groups;
933 		int g;
934 
935 		funcs[n].groups = devm_kcalloc(info->dev,
936 					       funcs[n].ngroups,
937 					       sizeof(*(funcs[n].groups)),
938 					       GFP_KERNEL);
939 		if (!funcs[n].groups)
940 			return -ENOMEM;
941 
942 		groups = funcs[n].groups;
943 
944 		for (g = 0; g < info->ngroups; g++) {
945 			struct armada_37xx_pin_group *gp = &info->groups[g];
946 			int f;
947 
948 			f = match_string(gp->funcs, NB_FUNCS, name);
949 			if (f < 0)
950 				continue;
951 
952 			*groups = gp->name;
953 			groups++;
954 		}
955 	}
956 	return 0;
957 }
958 
959 static int armada_37xx_pinctrl_register(struct platform_device *pdev,
960 					struct armada_37xx_pinctrl *info)
961 {
962 	const struct armada_37xx_pin_data *pin_data = info->data;
963 	struct pinctrl_desc *ctrldesc = &info->pctl;
964 	struct pinctrl_pin_desc *pindesc, *pdesc;
965 	int pin, ret;
966 
967 	info->groups = pin_data->groups;
968 	info->ngroups = pin_data->ngroups;
969 
970 	ctrldesc->name = "armada_37xx-pinctrl";
971 	ctrldesc->owner = THIS_MODULE;
972 	ctrldesc->pctlops = &armada_37xx_pctrl_ops;
973 	ctrldesc->pmxops = &armada_37xx_pmx_ops;
974 	ctrldesc->confops = &armada_37xx_pinconf_ops;
975 
976 	pindesc = devm_kcalloc(&pdev->dev,
977 			       pin_data->nr_pins, sizeof(*pindesc),
978 			       GFP_KERNEL);
979 	if (!pindesc)
980 		return -ENOMEM;
981 
982 	ctrldesc->pins = pindesc;
983 	ctrldesc->npins = pin_data->nr_pins;
984 
985 	pdesc = pindesc;
986 	for (pin = 0; pin < pin_data->nr_pins; pin++) {
987 		pdesc->number = pin;
988 		pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
989 					pin_data->name, pin);
990 		pdesc++;
991 	}
992 
993 	/*
994 	 * we allocate functions for number of pins and hope there are
995 	 * fewer unique functions than pins available
996 	 */
997 	info->funcs = devm_kcalloc(&pdev->dev,
998 				   pin_data->nr_pins,
999 				   sizeof(struct armada_37xx_pmx_func),
1000 				   GFP_KERNEL);
1001 	if (!info->funcs)
1002 		return -ENOMEM;
1003 
1004 
1005 	ret = armada_37xx_fill_group(info);
1006 	if (ret)
1007 		return ret;
1008 
1009 	ret = armada_37xx_fill_func(info);
1010 	if (ret)
1011 		return ret;
1012 
1013 	info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
1014 	if (IS_ERR(info->pctl_dev)) {
1015 		dev_err(&pdev->dev, "could not register pinctrl driver\n");
1016 		return PTR_ERR(info->pctl_dev);
1017 	}
1018 
1019 	return 0;
1020 }
1021 
1022 #if defined(CONFIG_PM)
1023 static int armada_3700_pinctrl_suspend(struct device *dev)
1024 {
1025 	struct armada_37xx_pinctrl *info = dev_get_drvdata(dev);
1026 
1027 	/* Save GPIO state */
1028 	regmap_read(info->regmap, OUTPUT_EN, &info->pm.out_en_l);
1029 	regmap_read(info->regmap, OUTPUT_EN + sizeof(u32), &info->pm.out_en_h);
1030 	regmap_read(info->regmap, OUTPUT_VAL, &info->pm.out_val_l);
1031 	regmap_read(info->regmap, OUTPUT_VAL + sizeof(u32),
1032 		    &info->pm.out_val_h);
1033 
1034 	info->pm.irq_en_l = readl(info->base + IRQ_EN);
1035 	info->pm.irq_en_h = readl(info->base + IRQ_EN + sizeof(u32));
1036 	info->pm.irq_pol_l = readl(info->base + IRQ_POL);
1037 	info->pm.irq_pol_h = readl(info->base + IRQ_POL + sizeof(u32));
1038 
1039 	/* Save pinctrl state */
1040 	regmap_read(info->regmap, SELECTION, &info->pm.selection);
1041 
1042 	return 0;
1043 }
1044 
1045 static int armada_3700_pinctrl_resume(struct device *dev)
1046 {
1047 	struct armada_37xx_pinctrl *info = dev_get_drvdata(dev);
1048 	struct gpio_chip *gc;
1049 	struct irq_domain *d;
1050 	int i;
1051 
1052 	/* Restore GPIO state */
1053 	regmap_write(info->regmap, OUTPUT_EN, info->pm.out_en_l);
1054 	regmap_write(info->regmap, OUTPUT_EN + sizeof(u32),
1055 		     info->pm.out_en_h);
1056 	regmap_write(info->regmap, OUTPUT_VAL, info->pm.out_val_l);
1057 	regmap_write(info->regmap, OUTPUT_VAL + sizeof(u32),
1058 		     info->pm.out_val_h);
1059 
1060 	/*
1061 	 * Input levels may change during suspend, which is not monitored at
1062 	 * that time. GPIOs used for both-edge IRQs may not be synchronized
1063 	 * anymore with their polarities (rising/falling edge) and must be
1064 	 * re-configured manually.
1065 	 */
1066 	gc = &info->gpio_chip;
1067 	d = gc->irq.domain;
1068 	for (i = 0; i < gc->ngpio; i++) {
1069 		u32 irq_bit = BIT(i % GPIO_PER_REG);
1070 		u32 mask, *irq_pol, input_reg, virq, type, level;
1071 
1072 		if (i < GPIO_PER_REG) {
1073 			mask = info->pm.irq_en_l;
1074 			irq_pol = &info->pm.irq_pol_l;
1075 			input_reg = INPUT_VAL;
1076 		} else {
1077 			mask = info->pm.irq_en_h;
1078 			irq_pol = &info->pm.irq_pol_h;
1079 			input_reg = INPUT_VAL + sizeof(u32);
1080 		}
1081 
1082 		if (!(mask & irq_bit))
1083 			continue;
1084 
1085 		virq = irq_find_mapping(d, i);
1086 		type = irq_get_trigger_type(virq);
1087 
1088 		/*
1089 		 * Synchronize level and polarity for both-edge irqs:
1090 		 *     - a high input level expects a falling edge,
1091 		 *     - a low input level exepects a rising edge.
1092 		 */
1093 		if ((type & IRQ_TYPE_SENSE_MASK) ==
1094 		    IRQ_TYPE_EDGE_BOTH) {
1095 			regmap_read(info->regmap, input_reg, &level);
1096 			if ((*irq_pol ^ level) & irq_bit)
1097 				*irq_pol ^= irq_bit;
1098 		}
1099 	}
1100 
1101 	writel(info->pm.irq_en_l, info->base + IRQ_EN);
1102 	writel(info->pm.irq_en_h, info->base + IRQ_EN + sizeof(u32));
1103 	writel(info->pm.irq_pol_l, info->base + IRQ_POL);
1104 	writel(info->pm.irq_pol_h, info->base + IRQ_POL + sizeof(u32));
1105 
1106 	/* Restore pinctrl state */
1107 	regmap_write(info->regmap, SELECTION, info->pm.selection);
1108 
1109 	return 0;
1110 }
1111 
1112 /*
1113  * Since pinctrl is an infrastructure module, its resume should be issued prior
1114  * to other IO drivers.
1115  */
1116 static const struct dev_pm_ops armada_3700_pinctrl_pm_ops = {
1117 	.suspend_noirq = armada_3700_pinctrl_suspend,
1118 	.resume_noirq = armada_3700_pinctrl_resume,
1119 };
1120 
1121 #define PINCTRL_ARMADA_37XX_DEV_PM_OPS (&armada_3700_pinctrl_pm_ops)
1122 #else
1123 #define PINCTRL_ARMADA_37XX_DEV_PM_OPS NULL
1124 #endif /* CONFIG_PM */
1125 
1126 static const struct of_device_id armada_37xx_pinctrl_of_match[] = {
1127 	{
1128 		.compatible = "marvell,armada3710-sb-pinctrl",
1129 		.data = &armada_37xx_pin_sb,
1130 	},
1131 	{
1132 		.compatible = "marvell,armada3710-nb-pinctrl",
1133 		.data = &armada_37xx_pin_nb,
1134 	},
1135 	{ },
1136 };
1137 
1138 static int __init armada_37xx_pinctrl_probe(struct platform_device *pdev)
1139 {
1140 	struct armada_37xx_pinctrl *info;
1141 	struct device *dev = &pdev->dev;
1142 	struct device_node *np = dev->of_node;
1143 	struct regmap *regmap;
1144 	int ret;
1145 
1146 	info = devm_kzalloc(dev, sizeof(struct armada_37xx_pinctrl),
1147 			    GFP_KERNEL);
1148 	if (!info)
1149 		return -ENOMEM;
1150 
1151 	info->dev = dev;
1152 
1153 	regmap = syscon_node_to_regmap(np);
1154 	if (IS_ERR(regmap)) {
1155 		dev_err(&pdev->dev, "cannot get regmap\n");
1156 		return PTR_ERR(regmap);
1157 	}
1158 	info->regmap = regmap;
1159 
1160 	info->data = of_device_get_match_data(dev);
1161 
1162 	ret = armada_37xx_pinctrl_register(pdev, info);
1163 	if (ret)
1164 		return ret;
1165 
1166 	ret = armada_37xx_gpiochip_register(pdev, info);
1167 	if (ret)
1168 		return ret;
1169 
1170 	platform_set_drvdata(pdev, info);
1171 
1172 	return 0;
1173 }
1174 
1175 static struct platform_driver armada_37xx_pinctrl_driver = {
1176 	.driver = {
1177 		.name = "armada-37xx-pinctrl",
1178 		.of_match_table = armada_37xx_pinctrl_of_match,
1179 		.pm = PINCTRL_ARMADA_37XX_DEV_PM_OPS,
1180 	},
1181 };
1182 
1183 builtin_platform_driver_probe(armada_37xx_pinctrl_driver,
1184 			      armada_37xx_pinctrl_probe);
1185