1 /* 2 * Pin controller and GPIO driver for Amlogic Meson SoCs 3 * 4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 as published by the Free Software Foundation. 9 * 10 * You should have received a copy of the GNU General Public License 11 * along with this program. If not, see <http://www.gnu.org/licenses/>. 12 */ 13 14 /* 15 * The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO, 16 * BOOT,CARD for meson6, X,Y,DV,H,Z,AO,BOOT,CARD for meson8 and 17 * X,Y,DV,H,AO,BOOT,CARD,DIF for meson8b) and each bank has a 18 * variable number of pins. 19 * 20 * The AO bank is special because it belongs to the Always-On power 21 * domain which can't be powered off; the bank also uses a set of 22 * registers different from the other banks. 23 * 24 * For each pin controller there are 4 different register ranges that 25 * control the following properties of the pins: 26 * 1) pin muxing 27 * 2) pull enable/disable 28 * 3) pull up/down 29 * 4) GPIO direction, output value, input value 30 * 31 * In some cases the register ranges for pull enable and pull 32 * direction are the same and thus there are only 3 register ranges. 33 * 34 * Every pinmux group can be enabled by a specific bit in the first 35 * register range; when all groups for a given pin are disabled the 36 * pin acts as a GPIO. 37 * 38 * For the pull and GPIO configuration every bank uses a contiguous 39 * set of bits in the register sets described above; the same register 40 * can be shared by more banks with different offsets. 41 * 42 * In addition to this there are some registers shared between all 43 * banks that control the IRQ functionality. This feature is not 44 * supported at the moment by the driver. 45 */ 46 47 #include <linux/device.h> 48 #include <linux/gpio.h> 49 #include <linux/init.h> 50 #include <linux/io.h> 51 #include <linux/of.h> 52 #include <linux/of_address.h> 53 #include <linux/pinctrl/pinconf-generic.h> 54 #include <linux/pinctrl/pinconf.h> 55 #include <linux/pinctrl/pinctrl.h> 56 #include <linux/pinctrl/pinmux.h> 57 #include <linux/platform_device.h> 58 #include <linux/regmap.h> 59 #include <linux/seq_file.h> 60 61 #include "../core.h" 62 #include "../pinctrl-utils.h" 63 #include "pinctrl-meson.h" 64 65 /** 66 * meson_get_bank() - find the bank containing a given pin 67 * 68 * @pc: the pinctrl instance 69 * @pin: the pin number 70 * @bank: the found bank 71 * 72 * Return: 0 on success, a negative value on error 73 */ 74 static int meson_get_bank(struct meson_pinctrl *pc, unsigned int pin, 75 struct meson_bank **bank) 76 { 77 int i; 78 79 for (i = 0; i < pc->data->num_banks; i++) { 80 if (pin >= pc->data->banks[i].first && 81 pin <= pc->data->banks[i].last) { 82 *bank = &pc->data->banks[i]; 83 return 0; 84 } 85 } 86 87 return -EINVAL; 88 } 89 90 /** 91 * meson_calc_reg_and_bit() - calculate register and bit for a pin 92 * 93 * @bank: the bank containing the pin 94 * @pin: the pin number 95 * @reg_type: the type of register needed (pull-enable, pull, etc...) 96 * @reg: the computed register offset 97 * @bit: the computed bit 98 */ 99 static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin, 100 enum meson_reg_type reg_type, 101 unsigned int *reg, unsigned int *bit) 102 { 103 struct meson_reg_desc *desc = &bank->regs[reg_type]; 104 105 *reg = desc->reg * 4; 106 *bit = desc->bit + pin - bank->first; 107 } 108 109 static int meson_get_groups_count(struct pinctrl_dev *pcdev) 110 { 111 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 112 113 return pc->data->num_groups; 114 } 115 116 static const char *meson_get_group_name(struct pinctrl_dev *pcdev, 117 unsigned selector) 118 { 119 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 120 121 return pc->data->groups[selector].name; 122 } 123 124 static int meson_get_group_pins(struct pinctrl_dev *pcdev, unsigned selector, 125 const unsigned **pins, unsigned *num_pins) 126 { 127 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 128 129 *pins = pc->data->groups[selector].pins; 130 *num_pins = pc->data->groups[selector].num_pins; 131 132 return 0; 133 } 134 135 static void meson_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s, 136 unsigned offset) 137 { 138 seq_printf(s, " %s", dev_name(pcdev->dev)); 139 } 140 141 static const struct pinctrl_ops meson_pctrl_ops = { 142 .get_groups_count = meson_get_groups_count, 143 .get_group_name = meson_get_group_name, 144 .get_group_pins = meson_get_group_pins, 145 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 146 .dt_free_map = pinctrl_utils_free_map, 147 .pin_dbg_show = meson_pin_dbg_show, 148 }; 149 150 /** 151 * meson_pmx_disable_other_groups() - disable other groups using a given pin 152 * 153 * @pc: meson pin controller device 154 * @pin: number of the pin 155 * @sel_group: index of the selected group, or -1 if none 156 * 157 * The function disables all pinmux groups using a pin except the 158 * selected one. If @sel_group is -1 all groups are disabled, leaving 159 * the pin in GPIO mode. 160 */ 161 static void meson_pmx_disable_other_groups(struct meson_pinctrl *pc, 162 unsigned int pin, int sel_group) 163 { 164 struct meson_pmx_group *group; 165 int i, j; 166 167 for (i = 0; i < pc->data->num_groups; i++) { 168 group = &pc->data->groups[i]; 169 if (group->is_gpio || i == sel_group) 170 continue; 171 172 for (j = 0; j < group->num_pins; j++) { 173 if (group->pins[j] == pin) { 174 /* We have found a group using the pin */ 175 regmap_update_bits(pc->reg_mux, 176 group->reg * 4, 177 BIT(group->bit), 0); 178 } 179 } 180 } 181 } 182 183 static int meson_pmx_set_mux(struct pinctrl_dev *pcdev, unsigned func_num, 184 unsigned group_num) 185 { 186 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 187 struct meson_pmx_func *func = &pc->data->funcs[func_num]; 188 struct meson_pmx_group *group = &pc->data->groups[group_num]; 189 int i, ret = 0; 190 191 dev_dbg(pc->dev, "enable function %s, group %s\n", func->name, 192 group->name); 193 194 /* 195 * Disable groups using the same pin. 196 * The selected group is not disabled to avoid glitches. 197 */ 198 for (i = 0; i < group->num_pins; i++) 199 meson_pmx_disable_other_groups(pc, group->pins[i], group_num); 200 201 /* Function 0 (GPIO) doesn't need any additional setting */ 202 if (func_num) 203 ret = regmap_update_bits(pc->reg_mux, group->reg * 4, 204 BIT(group->bit), BIT(group->bit)); 205 206 return ret; 207 } 208 209 static int meson_pmx_request_gpio(struct pinctrl_dev *pcdev, 210 struct pinctrl_gpio_range *range, 211 unsigned offset) 212 { 213 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 214 215 meson_pmx_disable_other_groups(pc, offset, -1); 216 217 return 0; 218 } 219 220 static int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev) 221 { 222 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 223 224 return pc->data->num_funcs; 225 } 226 227 static const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev, 228 unsigned selector) 229 { 230 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 231 232 return pc->data->funcs[selector].name; 233 } 234 235 static int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector, 236 const char * const **groups, 237 unsigned * const num_groups) 238 { 239 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 240 241 *groups = pc->data->funcs[selector].groups; 242 *num_groups = pc->data->funcs[selector].num_groups; 243 244 return 0; 245 } 246 247 static const struct pinmux_ops meson_pmx_ops = { 248 .set_mux = meson_pmx_set_mux, 249 .get_functions_count = meson_pmx_get_funcs_count, 250 .get_function_name = meson_pmx_get_func_name, 251 .get_function_groups = meson_pmx_get_groups, 252 .gpio_request_enable = meson_pmx_request_gpio, 253 }; 254 255 static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, 256 unsigned long *configs, unsigned num_configs) 257 { 258 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 259 struct meson_bank *bank; 260 enum pin_config_param param; 261 unsigned int reg, bit; 262 int i, ret; 263 264 ret = meson_get_bank(pc, pin, &bank); 265 if (ret) 266 return ret; 267 268 for (i = 0; i < num_configs; i++) { 269 param = pinconf_to_config_param(configs[i]); 270 271 switch (param) { 272 case PIN_CONFIG_BIAS_DISABLE: 273 dev_dbg(pc->dev, "pin %u: disable bias\n", pin); 274 275 meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); 276 ret = regmap_update_bits(pc->reg_pull, reg, 277 BIT(bit), 0); 278 if (ret) 279 return ret; 280 break; 281 case PIN_CONFIG_BIAS_PULL_UP: 282 dev_dbg(pc->dev, "pin %u: enable pull-up\n", pin); 283 284 meson_calc_reg_and_bit(bank, pin, REG_PULLEN, 285 ®, &bit); 286 ret = regmap_update_bits(pc->reg_pullen, reg, 287 BIT(bit), BIT(bit)); 288 if (ret) 289 return ret; 290 291 meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); 292 ret = regmap_update_bits(pc->reg_pull, reg, 293 BIT(bit), BIT(bit)); 294 if (ret) 295 return ret; 296 break; 297 case PIN_CONFIG_BIAS_PULL_DOWN: 298 dev_dbg(pc->dev, "pin %u: enable pull-down\n", pin); 299 300 meson_calc_reg_and_bit(bank, pin, REG_PULLEN, 301 ®, &bit); 302 ret = regmap_update_bits(pc->reg_pullen, reg, 303 BIT(bit), BIT(bit)); 304 if (ret) 305 return ret; 306 307 meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); 308 ret = regmap_update_bits(pc->reg_pull, reg, 309 BIT(bit), 0); 310 if (ret) 311 return ret; 312 break; 313 default: 314 return -ENOTSUPP; 315 } 316 } 317 318 return 0; 319 } 320 321 static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin) 322 { 323 struct meson_bank *bank; 324 unsigned int reg, bit, val; 325 int ret, conf; 326 327 ret = meson_get_bank(pc, pin, &bank); 328 if (ret) 329 return ret; 330 331 meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); 332 333 ret = regmap_read(pc->reg_pullen, reg, &val); 334 if (ret) 335 return ret; 336 337 if (!(val & BIT(bit))) { 338 conf = PIN_CONFIG_BIAS_DISABLE; 339 } else { 340 meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); 341 342 ret = regmap_read(pc->reg_pull, reg, &val); 343 if (ret) 344 return ret; 345 346 if (val & BIT(bit)) 347 conf = PIN_CONFIG_BIAS_PULL_UP; 348 else 349 conf = PIN_CONFIG_BIAS_PULL_DOWN; 350 } 351 352 return conf; 353 } 354 355 static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin, 356 unsigned long *config) 357 { 358 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 359 enum pin_config_param param = pinconf_to_config_param(*config); 360 u16 arg; 361 362 switch (param) { 363 case PIN_CONFIG_BIAS_DISABLE: 364 case PIN_CONFIG_BIAS_PULL_DOWN: 365 case PIN_CONFIG_BIAS_PULL_UP: 366 if (meson_pinconf_get_pull(pc, pin) == param) 367 arg = 1; 368 else 369 return -EINVAL; 370 break; 371 default: 372 return -ENOTSUPP; 373 } 374 375 *config = pinconf_to_config_packed(param, arg); 376 dev_dbg(pc->dev, "pinconf for pin %u is %lu\n", pin, *config); 377 378 return 0; 379 } 380 381 static int meson_pinconf_group_set(struct pinctrl_dev *pcdev, 382 unsigned int num_group, 383 unsigned long *configs, unsigned num_configs) 384 { 385 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 386 struct meson_pmx_group *group = &pc->data->groups[num_group]; 387 int i; 388 389 dev_dbg(pc->dev, "set pinconf for group %s\n", group->name); 390 391 for (i = 0; i < group->num_pins; i++) { 392 meson_pinconf_set(pcdev, group->pins[i], configs, 393 num_configs); 394 } 395 396 return 0; 397 } 398 399 static int meson_pinconf_group_get(struct pinctrl_dev *pcdev, 400 unsigned int group, unsigned long *config) 401 { 402 return -ENOSYS; 403 } 404 405 static const struct pinconf_ops meson_pinconf_ops = { 406 .pin_config_get = meson_pinconf_get, 407 .pin_config_set = meson_pinconf_set, 408 .pin_config_group_get = meson_pinconf_group_get, 409 .pin_config_group_set = meson_pinconf_group_set, 410 .is_generic = true, 411 }; 412 413 static int meson_gpio_request(struct gpio_chip *chip, unsigned gpio) 414 { 415 return pinctrl_request_gpio(chip->base + gpio); 416 } 417 418 static void meson_gpio_free(struct gpio_chip *chip, unsigned gpio) 419 { 420 struct meson_pinctrl *pc = gpiochip_get_data(chip); 421 422 pinctrl_free_gpio(pc->data->pin_base + gpio); 423 } 424 425 static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) 426 { 427 struct meson_pinctrl *pc = gpiochip_get_data(chip); 428 unsigned int reg, bit, pin; 429 struct meson_bank *bank; 430 int ret; 431 432 pin = pc->data->pin_base + gpio; 433 ret = meson_get_bank(pc, pin, &bank); 434 if (ret) 435 return ret; 436 437 meson_calc_reg_and_bit(bank, pin, REG_DIR, ®, &bit); 438 439 return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), BIT(bit)); 440 } 441 442 static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, 443 int value) 444 { 445 struct meson_pinctrl *pc = gpiochip_get_data(chip); 446 unsigned int reg, bit, pin; 447 struct meson_bank *bank; 448 int ret; 449 450 pin = pc->data->pin_base + gpio; 451 ret = meson_get_bank(pc, pin, &bank); 452 if (ret) 453 return ret; 454 455 meson_calc_reg_and_bit(bank, pin, REG_DIR, ®, &bit); 456 ret = regmap_update_bits(pc->reg_gpio, reg, BIT(bit), 0); 457 if (ret) 458 return ret; 459 460 meson_calc_reg_and_bit(bank, pin, REG_OUT, ®, &bit); 461 return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), 462 value ? BIT(bit) : 0); 463 } 464 465 static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value) 466 { 467 struct meson_pinctrl *pc = gpiochip_get_data(chip); 468 unsigned int reg, bit, pin; 469 struct meson_bank *bank; 470 int ret; 471 472 pin = pc->data->pin_base + gpio; 473 ret = meson_get_bank(pc, pin, &bank); 474 if (ret) 475 return; 476 477 meson_calc_reg_and_bit(bank, pin, REG_OUT, ®, &bit); 478 regmap_update_bits(pc->reg_gpio, reg, BIT(bit), 479 value ? BIT(bit) : 0); 480 } 481 482 static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio) 483 { 484 struct meson_pinctrl *pc = gpiochip_get_data(chip); 485 unsigned int reg, bit, val, pin; 486 struct meson_bank *bank; 487 int ret; 488 489 pin = pc->data->pin_base + gpio; 490 ret = meson_get_bank(pc, pin, &bank); 491 if (ret) 492 return ret; 493 494 meson_calc_reg_and_bit(bank, pin, REG_IN, ®, &bit); 495 regmap_read(pc->reg_gpio, reg, &val); 496 497 return !!(val & BIT(bit)); 498 } 499 500 static const struct of_device_id meson_pinctrl_dt_match[] = { 501 { 502 .compatible = "amlogic,meson8-cbus-pinctrl", 503 .data = &meson8_cbus_pinctrl_data, 504 }, 505 { 506 .compatible = "amlogic,meson8b-cbus-pinctrl", 507 .data = &meson8b_cbus_pinctrl_data, 508 }, 509 { 510 .compatible = "amlogic,meson8-aobus-pinctrl", 511 .data = &meson8_aobus_pinctrl_data, 512 }, 513 { 514 .compatible = "amlogic,meson8b-aobus-pinctrl", 515 .data = &meson8b_aobus_pinctrl_data, 516 }, 517 { 518 .compatible = "amlogic,meson-gxbb-periphs-pinctrl", 519 .data = &meson_gxbb_periphs_pinctrl_data, 520 }, 521 { 522 .compatible = "amlogic,meson-gxbb-aobus-pinctrl", 523 .data = &meson_gxbb_aobus_pinctrl_data, 524 }, 525 { 526 .compatible = "amlogic,meson-gxl-periphs-pinctrl", 527 .data = &meson_gxl_periphs_pinctrl_data, 528 }, 529 { 530 .compatible = "amlogic,meson-gxl-aobus-pinctrl", 531 .data = &meson_gxl_aobus_pinctrl_data, 532 }, 533 { }, 534 }; 535 536 static int meson_gpiolib_register(struct meson_pinctrl *pc) 537 { 538 int ret; 539 540 pc->chip.label = pc->data->name; 541 pc->chip.parent = pc->dev; 542 pc->chip.request = meson_gpio_request; 543 pc->chip.free = meson_gpio_free; 544 pc->chip.direction_input = meson_gpio_direction_input; 545 pc->chip.direction_output = meson_gpio_direction_output; 546 pc->chip.get = meson_gpio_get; 547 pc->chip.set = meson_gpio_set; 548 pc->chip.base = pc->data->pin_base; 549 pc->chip.ngpio = pc->data->num_pins; 550 pc->chip.can_sleep = false; 551 pc->chip.of_node = pc->of_node; 552 pc->chip.of_gpio_n_cells = 2; 553 554 ret = gpiochip_add_data(&pc->chip, pc); 555 if (ret) { 556 dev_err(pc->dev, "can't add gpio chip %s\n", 557 pc->data->name); 558 return ret; 559 } 560 561 return 0; 562 } 563 564 static struct regmap_config meson_regmap_config = { 565 .reg_bits = 32, 566 .val_bits = 32, 567 .reg_stride = 4, 568 }; 569 570 static struct regmap *meson_map_resource(struct meson_pinctrl *pc, 571 struct device_node *node, char *name) 572 { 573 struct resource res; 574 void __iomem *base; 575 int i; 576 577 i = of_property_match_string(node, "reg-names", name); 578 if (of_address_to_resource(node, i, &res)) 579 return ERR_PTR(-ENOENT); 580 581 base = devm_ioremap_resource(pc->dev, &res); 582 if (IS_ERR(base)) 583 return ERR_CAST(base); 584 585 meson_regmap_config.max_register = resource_size(&res) - 4; 586 meson_regmap_config.name = devm_kasprintf(pc->dev, GFP_KERNEL, 587 "%s-%s", node->name, 588 name); 589 if (!meson_regmap_config.name) 590 return ERR_PTR(-ENOMEM); 591 592 return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config); 593 } 594 595 static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc, 596 struct device_node *node) 597 { 598 struct device_node *np, *gpio_np = NULL; 599 600 for_each_child_of_node(node, np) { 601 if (!of_find_property(np, "gpio-controller", NULL)) 602 continue; 603 if (gpio_np) { 604 dev_err(pc->dev, "multiple gpio nodes\n"); 605 return -EINVAL; 606 } 607 gpio_np = np; 608 } 609 610 if (!gpio_np) { 611 dev_err(pc->dev, "no gpio node found\n"); 612 return -EINVAL; 613 } 614 615 pc->of_node = gpio_np; 616 617 pc->reg_mux = meson_map_resource(pc, gpio_np, "mux"); 618 if (IS_ERR(pc->reg_mux)) { 619 dev_err(pc->dev, "mux registers not found\n"); 620 return PTR_ERR(pc->reg_mux); 621 } 622 623 pc->reg_pull = meson_map_resource(pc, gpio_np, "pull"); 624 if (IS_ERR(pc->reg_pull)) { 625 dev_err(pc->dev, "pull registers not found\n"); 626 return PTR_ERR(pc->reg_pull); 627 } 628 629 pc->reg_pullen = meson_map_resource(pc, gpio_np, "pull-enable"); 630 /* Use pull region if pull-enable one is not present */ 631 if (IS_ERR(pc->reg_pullen)) 632 pc->reg_pullen = pc->reg_pull; 633 634 pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio"); 635 if (IS_ERR(pc->reg_gpio)) { 636 dev_err(pc->dev, "gpio registers not found\n"); 637 return PTR_ERR(pc->reg_gpio); 638 } 639 640 return 0; 641 } 642 643 static int meson_pinctrl_probe(struct platform_device *pdev) 644 { 645 const struct of_device_id *match; 646 struct device *dev = &pdev->dev; 647 struct meson_pinctrl *pc; 648 int ret; 649 650 pc = devm_kzalloc(dev, sizeof(struct meson_pinctrl), GFP_KERNEL); 651 if (!pc) 652 return -ENOMEM; 653 654 pc->dev = dev; 655 match = of_match_node(meson_pinctrl_dt_match, pdev->dev.of_node); 656 pc->data = (struct meson_pinctrl_data *) match->data; 657 658 ret = meson_pinctrl_parse_dt(pc, pdev->dev.of_node); 659 if (ret) 660 return ret; 661 662 pc->desc.name = "pinctrl-meson"; 663 pc->desc.owner = THIS_MODULE; 664 pc->desc.pctlops = &meson_pctrl_ops; 665 pc->desc.pmxops = &meson_pmx_ops; 666 pc->desc.confops = &meson_pinconf_ops; 667 pc->desc.pins = pc->data->pins; 668 pc->desc.npins = pc->data->num_pins; 669 670 pc->pcdev = devm_pinctrl_register(pc->dev, &pc->desc, pc); 671 if (IS_ERR(pc->pcdev)) { 672 dev_err(pc->dev, "can't register pinctrl device"); 673 return PTR_ERR(pc->pcdev); 674 } 675 676 return meson_gpiolib_register(pc); 677 } 678 679 static struct platform_driver meson_pinctrl_driver = { 680 .probe = meson_pinctrl_probe, 681 .driver = { 682 .name = "meson-pinctrl", 683 .of_match_table = meson_pinctrl_dt_match, 684 }, 685 }; 686 builtin_platform_driver(meson_pinctrl_driver); 687